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This commit is contained in:
David Haywood 2015-10-29 00:32:00 +00:00
parent 8f2afead9e
commit 81d37e8712
2 changed files with 30 additions and 15 deletions
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41
src/devices/bus/vcs/dpcplus.c
View File

@ -18,17 +18,15 @@ map:
Bankswitching uses addresses $FFF6-$FFFB
* ARM RAM mapped at $40000000 in this area
$0000-$0BFF: DPC+ driver (not accessible by 2600 itself)
$0C00-$1BFF: Bank 0 - ARM code starts here, but 6507 code can also be placed here aswell
$0000-$0BFF: DPC+ driver (not accessible by 2600 itself) (copied to $40000000 - $40000bff on startup by ARM)
$0C00-$1BFF: Bank 0 (each bank can map to 0x1000 - 0x1fff in 6507 space, like other carts)
$1C00-$2BFF: Bank 1
$2C00-$3BFF: Bank 2
$3C00-$4BFF: Bank 3
$4C00-$5BFF: Bank 4
$5C00-$6BFF: Bank 5 - 6507 code
* ARM RAM mapped at $40000C00 in this area
$6C00-$7BFF: Display Data (indirect access)
* ARM RAM mapped at $40001C00 in this area
$7C00-$7FFF: Synth Frequency Data (not accessible by 2600 itself)
$5C00-$6BFF: Bank 5 (default bank is bank 5)
$6C00-$7BFF: Display Data (indirect access) (copied to $40000C00 - $40001bff on startup by ARM)
$7C00-$7FFF: Synth Frequency Data (not accessible by 2600 itself) (copied to $40001C00 - $40001fff on startup by ARM)
***************************************************************************/
@ -61,15 +59,22 @@ void a26_rom_dpcplus_device::device_start()
void a26_rom_dpcplus_device::device_reset()
{
m_base_bank = 0;
m_base_bank = 5;
}
READ8_MEMBER(a26_rom_dpcplus_device::read8_r)
{
return m_rom[offset + (m_base_bank * 0x1000)];
}
READ32_MEMBER(a26_rom_dpcplus_device::armrom_r)
{
UINT32 ret = (a26_rom_f8_device::read_rom(space, offset * 4 + 3) << 24) |
(a26_rom_f8_device::read_rom(space, offset * 4 + 2) << 16) |
(a26_rom_f8_device::read_rom(space, offset * 4 + 1) << 8) |
(a26_rom_f8_device::read_rom(space, offset * 4 + 0) << 0);
UINT32 ret = (m_rom[offset * 4 + 3] << 24) |
(m_rom[offset * 4 + 2] << 16) |
(m_rom[offset * 4 + 1] << 8) |
(m_rom[offset * 4 + 0] << 0);
return ret;
}
@ -78,10 +83,17 @@ WRITE32_MEMBER(a26_rom_dpcplus_device::armrom_w)
}
READ32_MEMBER(a26_rom_dpcplus_device::arm_E01FC088_r)
{
return 0xffffffff;
}
static ADDRESS_MAP_START( dpcplus_arm7_map, AS_PROGRAM, 32, a26_rom_dpcplus_device )
// todo: implement all this correctly
AM_RANGE(0x00000000, 0x00007fff) AM_READWRITE(armrom_r,armrom_w) // flash, 32k
AM_RANGE(0x40000000, 0x40001fff) AM_RAM // sram, 8k
AM_RANGE(0xE01FC088, 0xE01FC08b) AM_READ(arm_E01FC088_r)
ADDRESS_MAP_END
static MACHINE_CONFIG_FRAGMENT( a26_dpcplus )
@ -97,10 +109,11 @@ machine_config_constructor a26_rom_dpcplus_device::device_mconfig_additions() co
READ8_MEMBER(a26_rom_dpcplus_device::read_rom)
{
return a26_rom_f8_device::read_rom(space, offset);
// banks start at 0xc00
return read8_r(space, offset+0xc00);
}
WRITE8_MEMBER(a26_rom_dpcplus_device::write_bank)
{
a26_rom_f8_device::write_bank(space, offset, data);
// a26_rom_f8_device::write_bank(space, offset, data);
}

4
src/devices/bus/vcs/dpcplus.h
View File

@ -26,8 +26,10 @@ public:
DECLARE_READ32_MEMBER(armrom_r);
DECLARE_WRITE32_MEMBER(armrom_w);
DECLARE_READ8_MEMBER(read8_r);
DECLARE_READ32_MEMBER(arm_E01FC088_r);
protected:
};