mirror of
https://github.com/holub/mame
synced 2025-05-20 20:58:51 +03:00
mips1: rework interrupts (nw)
This fixes a bug causing IRIX to crash on 4D/20. Specifically, IRIX doesn't handle the case where the pc is pointing to an unmapped address when an interrupt occurs; presumably on real hardware this doesn't happen because the instruction fetch happens before interrupts are tested (or the pc isn't updated until after), and the fetch exception is prioritised over the incoming interrupt.
This commit is contained in:
Patrick Mackinlay
parent
e1b078da42
commit
8205f140fe
@ -212,9 +212,6 @@ void mips1core_device_base::device_reset()
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void mips1core_device_base::execute_run()
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{
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// check for interrupts
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check_irqs();
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// core execution loop
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while (m_icount-- > 0)
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{
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@ -239,10 +236,17 @@ void mips1core_device_base::execute_run()
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}
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}
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// fetch and execute instruction
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// fetch instruction
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fetch(m_pc, [this](u32 const op)
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{
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// parse the instruction
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// check for interrupts
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if ((CAUSE & SR & SR_IM) && (SR & SR_IEc))
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{
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generate_exception(EXCEPTION_INTERRUPT);
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return;
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}
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// decode and execute instruction
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switch (op >> 26)
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{
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case 0x00: // SPECIAL
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@ -559,31 +563,31 @@ void mips1core_device_base::execute_run()
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break;
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}
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// update pc and branch state
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switch (m_branch_state)
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{
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case NONE:
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m_pc += 4;
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break;
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case DELAY:
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m_branch_state = NONE;
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m_pc = m_branch_target;
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break;
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case BRANCH:
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m_branch_state = DELAY;
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m_pc += 4;
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break;
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case EXCEPTION:
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m_branch_state = NONE;
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break;
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}
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// clear register 0
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m_r[0] = 0;
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});
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// update pc and branch state
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switch (m_branch_state)
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{
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case NONE:
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m_pc += 4;
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break;
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case DELAY:
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m_branch_state = NONE;
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m_pc = m_branch_target;
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break;
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case BRANCH:
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m_branch_state = DELAY;
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m_pc += 4;
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break;
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case EXCEPTION:
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m_branch_state = NONE;
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break;
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}
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}
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}
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@ -599,8 +603,6 @@ void mips1core_device_base::execute_set_input(int irqline, int state)
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}
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else
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CAUSE &= ~(CAUSE_IPEX0 << irqline);
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check_irqs();
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}
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device_memory_interface::space_config_vector mips1core_device_base::memory_space_config() const
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@ -846,12 +848,6 @@ void mips1core_device_base::generate_exception(u32 exception, bool refill)
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debugger_privilege_hook();
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}
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void mips1core_device_base::check_irqs()
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{
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if ((CAUSE & SR & SR_IM) && (SR & SR_IEc))
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generate_exception(EXCEPTION_INTERRUPT);
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}
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void mips1core_device_base::handle_cop0(u32 const op)
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{
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switch (RSREG)
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@ -888,7 +884,7 @@ void mips1core_device_base::handle_cop0(u32 const op)
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switch (op & 31)
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{
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case 0x10: // RFE
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SR = (SR & ~SR_KUIEpc) | ((SR >> 2) & SR_KUIEpc);
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SR = (SR & ~SR_KUIE) | ((SR >> 2) & SR_KUIEpc);
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if (bool(SR & SR_KUc) ^ bool(SR & SR_KUp))
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debugger_privilege_hook();
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break;
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@ -921,10 +917,6 @@ void mips1core_device_base::set_cop0_reg(unsigned const reg, u32 const data)
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// handle cache isolation and swap
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m_data_spacenum = (data & SR_IsC) ? ((data & SR_SwC) ? 1 : 2) : 0;
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// update interrupts
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if (delta & (SR_IEc | SR_IM))
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check_irqs();
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if ((delta & SR_KUc) && (m_branch_state != EXCEPTION))
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debugger_privilege_hook();
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}
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@ -932,9 +924,6 @@ void mips1core_device_base::set_cop0_reg(unsigned const reg, u32 const data)
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case COP0_Cause:
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CAUSE = (CAUSE & CAUSE_IPEX) | (data & ~CAUSE_IPEX);
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// update interrupts -- software ints can occur this way
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check_irqs();
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break;
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case COP0_PRId:
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@ -1241,8 +1230,8 @@ void mips1_device_base::handle_cop0(u32 const op)
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m_tlb[index][0] = m_cop0[COP0_EntryHi];
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m_tlb[index][1] = m_cop0[COP0_EntryLo];
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LOGMASKED(LOG_TLB, "tlb write index %d asid %d vpn 0x%08x pfn 0x%08x %c%c%c%c (%s)\n",
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index, (m_cop0[COP0_EntryHi] & EH_ASID) >> 6, m_cop0[COP0_EntryHi] & EH_VPN, m_cop0[COP0_EntryLo] & EL_PFN,
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LOGMASKED(LOG_TLB, "asid %2d tlb write index %2d vpn 0x%08x pfn 0x%08x %c%c%c%c (%s)\n",
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(m_cop0[COP0_EntryHi] & EH_ASID) >> 6, index, m_cop0[COP0_EntryHi] & EH_VPN, m_cop0[COP0_EntryLo] & EL_PFN,
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m_cop0[COP0_EntryLo] & EL_N ? 'N' : '-',
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m_cop0[COP0_EntryLo] & EL_D ? 'D' : '-',
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m_cop0[COP0_EntryLo] & EL_V ? 'V' : '-',
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@ -1258,8 +1247,8 @@ void mips1_device_base::handle_cop0(u32 const op)
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m_tlb[random][0] = m_cop0[COP0_EntryHi];
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m_tlb[random][1] = m_cop0[COP0_EntryLo];
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LOGMASKED(LOG_TLB, "tlb write random %d asid %d vpn 0x%08x pfn 0x%08x %c%c%c%c (%s)\n",
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random, (m_cop0[COP0_EntryHi] & EH_ASID) >> 6, m_cop0[COP0_EntryHi] & EH_VPN, m_cop0[COP0_EntryLo] & EL_PFN,
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LOGMASKED(LOG_TLB, "asid %2d tlb write random %2d vpn 0x%08x pfn 0x%08x %c%c%c%c (%s)\n",
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(m_cop0[COP0_EntryHi] & EH_ASID) >> 6, random, m_cop0[COP0_EntryHi] & EH_VPN, m_cop0[COP0_EntryLo] & EL_PFN,
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m_cop0[COP0_EntryLo] & EL_N ? 'N' : '-',
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m_cop0[COP0_EntryLo] & EL_D ? 'D' : '-',
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m_cop0[COP0_EntryLo] & EL_V ? 'V' : '-',
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@ -1276,15 +1265,15 @@ void mips1_device_base::handle_cop0(u32 const op)
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u32 const mask = (m_tlb[index][1] & EL_G) ? EH_VPN : EH_VPN | EH_ASID;
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if ((m_tlb[index][0] & mask) == (m_cop0[COP0_EntryHi] & mask))
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{
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LOGMASKED(LOG_TLB, "tlb probe hit vpn 0x%08x index %d (%s)\n",
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m_cop0[COP0_EntryHi] & mask, index, machine().describe_context());
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LOGMASKED(LOG_TLB, "asid %2d tlb probe index %2d vpn 0x%08x (%s)\n",
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(m_cop0[COP0_EntryHi] & EH_ASID) >> 6, index, m_cop0[COP0_EntryHi] & mask, machine().describe_context());
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m_cop0[COP0_Index] = index << 8;
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break;
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}
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}
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if ((VERBOSE & LOG_TLB) && BIT(m_cop0[COP0_Index], 31))
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LOGMASKED(LOG_TLB, "tlb probe miss asid %d vpn 0x%08x(%s)\n",
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LOGMASKED(LOG_TLB, "asid %2d tlb probe miss vpn 0x%08x(%s)\n",
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(m_cop0[COP0_EntryHi] & EH_ASID) >> 6, m_cop0[COP0_EntryHi] & EH_VPN, machine().describe_context());
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break;
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@ -1971,11 +1960,11 @@ bool mips1_device_base::memory_translate(int spacenum, int intention, offs_t &ad
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if (VERBOSE & LOG_TLB)
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{
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if (modify)
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LOGMASKED(LOG_TLB, "tlb modify asid %d address 0x%08x (%s)\n",
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LOGMASKED(LOG_TLB, "asid %2d tlb modify address 0x%08x (%s)\n",
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(m_cop0[COP0_EntryHi] & EH_ASID) >> 6, address, machine().describe_context());
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else
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LOGMASKED(LOG_TLB, "tlb miss %c asid %d address 0x%08x (%s)\n",
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(intention & TRANSLATE_WRITE) ? 'w' : 'r', (m_cop0[COP0_EntryHi] & EH_ASID) >> 6, address, machine().describe_context());
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LOGMASKED(LOG_TLB, "asid %2d tlb miss %c address 0x%08x (%s)\n",
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(m_cop0[COP0_EntryHi] & EH_ASID) >> 6, (intention & TRANSLATE_WRITE) ? 'w' : 'r', address, machine().describe_context());
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}
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// load tlb exception registers
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@ -174,7 +174,6 @@ protected:
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// interrupts
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void generate_exception(u32 exception, bool refill = false);
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void check_irqs();
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// cop0
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virtual void handle_cop0(u32 const op);
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