mirror of
https://github.com/holub/mame
synced 2025-05-06 22:35:43 +03:00
updated Alpha 8302 MCU simulation to match newly dumped internal ROM.
Added the ROM to Champion Baseball 2.
This commit is contained in:
Nicola Salmoria
parent
d6269d15fa
commit
82494e9da3
@ -16,6 +16,7 @@ typedef unsigned char byte;
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#define PTRS_PER_FORMAT 2
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/****************************************************
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8201 CONFIRMED OPCODES:
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opcode mnemonic function flags
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@ -28,11 +29,11 @@ opcode mnemonic function flags
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00000101 INC A A++ ZC
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00000110 DEC A A-- ZC (C=1 means No Borrow: A>=1)
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00000110 CPL A A^=$FF --
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00001aaa LD A,(IX0+i) [IX0+i]->A --
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00010aaa LD A,(IX1+i) [IX1+i]->A --
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00011aaa LD (IX2+i),A A->[IX2+i] --
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00001aaa LD A,(IX0+i) A=[IX0+i] --
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00010aaa LD A,(IX1+i) A=[IX1+i] --
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00011aaa LD (IX2+i),A [IX2+i]=A --
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00111aaa BIT R0.n ZF=R0 bit n Z-
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0100aaa0 LD A,Rn A=Rn Z-
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0100aaa0 LD A,Rn A=Rn Z- [1]
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0100aaa1 LD Rn,A Rn=A --
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0101aaa0 ADD A,Rn A+=Rn ZC
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0101aaa1 SUB A,Rn A-=Rn ZC (C=1 means No Borrow: A>=Rn)
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@ -66,6 +67,64 @@ opcode mnemonic function flags
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1110--xx mirror for the above
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1111--xx mirror for the above
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Bugs:
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[1] the Z flag is not updated correctly after a LD A,Rn instruction. Fixed in 8301.
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8302 CONFIRMED OPCODES:
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----------------------
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all of the 8201 ones, with stricter decoding for the following:
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11010-00 imm JNC imm branch if !C --
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11010-01 imm JZ imm branch if Z --
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11010-1- imm J imm branch --
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and these new opcodes:
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opcode mnemonic function flags
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-------- ------------ --------------- -----
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11011000 imm LD A,(imm) A=MB:[imm] --
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11011001 imm LD (imm),A MB:[imm]=A --
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11011010 imm CMP A,imm temp=A-imm ZC
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11011011 imm XOR A,imm A^=imm Z0
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11011100 imm LD A,R(imm) A=reg(imm) --
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11011101 imm LD R(imm),A reg(imm)=A --
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11011110 imm JC imm branch if C --
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11011111 imm CALL $xx save PC, branch --
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11100000 EXG A,IX0 A<->IX0 --
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11100001 EXG A,IX1 A<->IX1 --
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11100010 EXG A,IX2 A<->IX2 --
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11100011 EXG A,LP1 A<->LP1 --
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11100100 EXG A,LP2 A<->LP2 --
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11100101 EXG A,RXB A<->RXB --
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11100110 EXG A,LP0 A<->LP0 --
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11100111 EXG A,RB A<->RB --
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11101000 LD IX0,A IX0=A --
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11101001 LD IX1,A IX1=A --
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11101010 LD IX2,A IX2=A --
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11101011 LD LP1,A LP1=A --
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11101100 LD LP2,A LP2=A --
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11101101 LD RXB,A RXB=A --
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11101110 LD LP0,A LP0=A --
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11101111 LD RB,A RB=A --
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11110000 EXG IX0,IX1 IX0<->IX1 --
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11110001 EXG IX0,IX2 IX0<->IX2 --
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11110010 REP LD (IX2),(RXB) equivalent to LD (IX2),(RXB); INC RXB; DJNZ LP0
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11110011 REP LD (RXB),(IX0) equivalent to LD (RXB),(IX0); INC RXB; DJNZ LP0
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11110100 SAVE ZC save ZC --
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11110101 REST ZC restore ZC ZC
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11110110 LD (RXB),A reg(RXB)=A --
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11110111 LD A,(RXB) A=reg(RXB) --
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11111000 CMP A,(RXB) temp=A-reg(RXB) ZC
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11111001 XOR A,(RXB) A^=reg(RXB) Z0
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11111010 ADD A,CF if (C) A++ ZC
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11111011 SUB A,!CF if (!C) A-- ZC
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11111100 TST A A==0? Z-
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11111101 CLR A A=0 --
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11111110 LD A,(IX0+A) A=[IX0+A] --
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11111111 RET restore PC --
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****************************************************/
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@ -122,48 +181,48 @@ static const char *const Formats[] = {
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/* -------------- 830x only ------------- */
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FMT("1101_0100 I", "LD A,(R7:$%02X)"), // D4 : exctscc2, bullfgtr; not sure if R7 or R77
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FMT("1101_0101 I", "LD (R7:$%02X),A"), // D5 : exctscc2, bullfgtr, kouyakyu; not sure if R7 or R77
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FMT("1101_0110 I", "LD LP0,(R7:$%02X)"), // D6 : kouyakyu; not sure if R7 or R77
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FMT("1101_0111 I", "LD (R7:$%02X),LP0"), // D7 : hvoltage; not sure if R7 or R77
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FMT("1101_0100 I", "LD A,(R7:$%02X)"), // D4 : 8303+ only? exctscc2, bullfgtr; not sure if R7 or R77
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FMT("1101_0101 I", "LD (R7:$%02X),A"), // D5 : 8303+ only? exctscc2, bullfgtr, kouyakyu; not sure if R7 or R77
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FMT("1101_0110 I", "LD LP0,(R7:$%02X)"), // D6 : 8303+ only? kouyakyu; not sure if R7 or R77
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FMT("1101_0111 I", "LD (R7:$%02X),LP0"), // D7 : 8303+ only? hvoltage; not sure if R7 or R77
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FMT("1101_1000 I", "LD A,($%02X)"), // D8 : equites
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FMT("1101_1001 I", "LD ($%02X),A"), // D9 : equites
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FMT("1101_1010 I", "CMP A,$%02X"), // DA :
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FMT("1101_1011 I", "XOR A,$%02X"), // DB : equites splndrbt
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FMT("1101_1100 I", "unk $%02X"), // DC : not found (LD A,R($%02X) ?)
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FMT("1101_1100 I", "LD A,R($%02X)"), // DC : not found
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FMT("1101_1101 I", "LD R($%02X),A"), // DD : equites, splndrbt
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FMT("1101_1110 I", "unk $%02X"), // DE : not found
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FMT("1101_1110 I", "JC $%02X"), // DE : not found
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FMT("1101_1111 I", "CALL $%02X"), // DF :
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FMT("1110_0000", "DEC IX0"), // E0 :
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FMT("1110_0001", "unknown"), // E1 : not found (DEC IX1?)
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FMT("1110_0010", "unknown"), // E2 : not found (DEC IX2?)
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FMT("1110_0011", "ld a,unk ?"), // E3 : exctsccr in pair with EB
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FMT("1110_0100", "unknown"), // E4 : not found
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FMT("1110_0101", "LD A,B"), // E5 : splndrbt
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FMT("1110_0000", "EXG A,IX0"), // E0 : exctsccr
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FMT("1110_0001", "EXG A,IX1"), // E1 : not found
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FMT("1110_0010", "EXG A,IX2"), // E2 : not found
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FMT("1110_0011", "EXG A,LP1"), // E3 : exctsccr in pair with EB
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FMT("1110_0100", "EXG A,LP2"), // E4 : not found
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FMT("1110_0101", "EXG A,RXB"), // E5 : splndrbt
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FMT("1110_0110", "EXG A,LP0"), // E6 : splndrbt, bullfgtr, kouyakyu. EXG, not LD: see splndrbt $3ba to $3d3
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FMT("1110_0111", "unknown"), // E7 : not found
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FMT("1110_0111", "EXG A,RB"), // E7 : not found
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FMT("1110_1000", "LD IX0,A"), // E8 :
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FMT("1110_1001", "ld ix1,a ?"), // E9 : not found
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FMT("1110_1001", "LD IX1,A"), // E9 : not found
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FMT("1110_1010", "LD IX2,A"), // EA :
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FMT("1110_1011", "ld unk,a ?"), // EB : exctsccr in pair with E3. unk is not LP0, IX0, IX2
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FMT("1110_1100", "unknown"), // EC : not found
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FMT("1110_1101", "LD B,A"), // ED : splndrbt
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FMT("1110_1011", "LD LP1,A"), // EB : exctsccr in pair with E3
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FMT("1110_1100", "LP LP2,A"), // EC : not found
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FMT("1110_1101", "LD RXB,A"), // ED : splndrbt
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FMT("1110_1110", "LD LP0,A"), // EE : splndrbt, bullfgtr
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FMT("1110_1111", "unknown"), // EF : not found
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FMT("1111_0000", "unknown"), // F0 : not found
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FMT("1111_0001", "EXG IX0,IX2"), // F1 : should be EXG, see splndrbt $2e to $38, equites $40 to $4a
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FMT("1111_0010", "LDIR"), // F2 : splndrbt LD (IX2+%X),(RXB); INC B; DJNZ LP0
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FMT("1111_0011", "unknown"), // F3 : not found
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FMT("1111_0100", "unknown"), // F4 : not found
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FMT("1111_0101", "unknown"), // F5 : not found
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FMT("1110_1111", "LD RB,A"), // EF : not found
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FMT("1111_0000", "EXG IX0,IX1"), // F0 : not found
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FMT("1111_0001", "EXG IX0,IX2"), // F1 : splndrbt $2e to $38, equites $40 to $4a
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FMT("1111_0010", "REP LD (IX2),(RXB)"),// F2 : splndrbt LD (IX2),(RXB); INC RXB; DJNZ LP0
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FMT("1111_0011", "REP LD (RXB),(IX0)"),// F3 : not found LD (RXB),(IX0); INC RXB; DJNZ LP0
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FMT("1111_0100", "SAVE ZC"), // F4 : not found
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FMT("1111_0101", "REST ZC"), // F5 : not found
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FMT("1111_0110", "LD (RXB),A"), // F6 : exctsccr
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FMT("1111_0111", "unknown"), // F7 : not found
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FMT("1111_1000", "sub/cmp a,(rxb) ?"), // F8 : exctsccr : ZF check could be CMP instead? see DA/DB
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FMT("1111_0111", "LD A,(RXB)"), // F7 : not found
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FMT("1111_1000", "CMP A,(RXB)"), // F8 : exctsccr
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FMT("1111_1001", "XOR A,(RXB)"), // F9 : exctsccr
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FMT("1111_1010", "ADD A,CF"), // FA :
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FMT("1111_1011", "unknown"), // FB : not found (SUB A,CF ?)
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FMT("1111_1100", "TST A"), // FC : ZF = (A==0) ?
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FMT("1111_1011", "SUB A,!CF"), // FB : not found
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FMT("1111_1100", "TST A"), // FC :
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FMT("1111_1101", "CLR A"), // FD :
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FMT("1111_1110", "LD A,(IX0+A)"), // FE :
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FMT("1111_1111", "RET"), // FF :
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@ -9,7 +9,7 @@ The Alpha8201/830x isn't a real CPU. It is a Hitachi HD44801 4-bit MCU,
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programmed to interpret an external program using a custom instruction set.
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Alpha8301 has an expanded instruction set, backwards compatible with Alpha8201
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The internal ROM hasn't been read (yet), so here we provide a simultaion of
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The internal ROM hasn't been read (yet), so here we provide a simulation of
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the behaviour.
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@ -20,8 +20,8 @@ Shougi 2 1982? 8201 (pcb)
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Talbot 1982 8201?
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Champion Base Ball 1983 8201 (schematics)
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Exciting Soccer 1983 8301?
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Champion Base Ball II 1983 8302?(unofficial schematics)
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Exciting Soccer II 1984 8302?
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Champion Base Ball II 1983 8302 (pcb, unofficial schematics)
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Exciting Soccer II 1984 8303?
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Equites 1984 8303 (post)
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Bull Fighter 1984 8303 (post)
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Splendor Blast 1985 8303 (post)
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@ -29,6 +29,11 @@ Gekisou 1985 8304 (post)
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The Koukouyakyuh 1985 8304 (post)
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High Voltage 1985 8404?(post says 8404, but readme says 8304)
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ALPHA8201: "44801A75" -> HD44801 , ROM code = A75
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ALPHA8302: "44801B35" -> HD44801 , ROM code = B35
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ALPHA8303: "44801B42" -> HD44801 , ROM code = B42
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ALPHA8304: ?
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Notes :
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some unknown instruction are not emulated.
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@ -37,7 +42,6 @@ High Voltage 1985 8404?(post says 8404, but readme says 8304)
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TODO:
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verify with real chip or analyze more.
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-call/ret stack point (8301).
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-A lot of 8301 opcode.
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-memory address 000 specification
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-memory address 001 bit 7-5 specification
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@ -169,12 +173,14 @@ typedef struct
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{
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UINT8 RAM[8*8]; /* internal GP register 8 * 8bank */
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unsigned PREVPC;
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PAIR retptr; /* for 8301, return address stack of CALL */
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PAIR retptr; /* for 8301, return address of CALL */
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PAIR pc; /* 2bit+8bit program counter */
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UINT8 regPtr; /* RB register base */
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UINT8 mb; /* MB memory bank reg. latch after Branch */
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UINT8 cf; /* C flag */
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UINT8 zf; /* Z flag */
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UINT8 savec; /* for 8301, save flags */
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UINT8 savez; /* for 8301, save flags */
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//
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PAIR ix0; /* 8bit memory read index reg. */
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PAIR ix1; /* 8bitmemory read index reg. */
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@ -267,7 +273,7 @@ INLINE void M_XOR(UINT8 dat)
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{
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R.A ^= dat;
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ZF = (R.A==0);
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// CF = 0; unknown whether it's affected or not
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CF = 0;
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}
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INLINE void M_JMP(UINT8 dat)
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@ -305,35 +311,6 @@ INLINE void M_UNDEFINED2(void)
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static void undefined(void) { M_UNDEFINED(); }
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static void undefined2(void) { M_UNDEFINED2(); }
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#if (HAS_ALPHA8301)
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static void need_verify(const char *s)
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{
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UINT8 op = M_RDOP(PC-1);
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logerror("ALPHA8201: PC = %03x, unknown opcode = %02x is '%s' ??\n",PC-1, op,s);
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#if SHOW_MESSAGE_CONSOLE
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mame_printf_debug("ALPHA8201: PC = %03x, unknown opcode = %02x is '%s' ??\n",PC-1, op,s);
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#endif
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#if BREAK_ON_UNCERTAIN_OPCODE
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debugger_break(Machine);
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#endif
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}
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#endif
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#if 0
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static void need_verify2(const char *s)
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{
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UINT8 op1 = M_RDOP(PC-2);
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UINT8 op2 = M_RDOP(PC-1);
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logerror("ALPHA8201: PC = %03x, unknown opcode = %02x %02x is '%s' ??\n",PC-2, op1, op2, s);
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#if SHOW_MESSAGE_CONSOLE
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mame_printf_debug("ALPHA8201: PC = %03x, unknown opcode = %02x %02x is '%s' ??\n",PC-2, op1, op2, s);
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#endif
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#if BREAK_ON_UNCERTAIN_OPCODE
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debugger_break(Machine);
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#endif
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}
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#endif
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static void nop(void) { }
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static void rora(void) { CF = R.A &1; R.A = (R.A>>1) | (R.A<<7); }
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static void rola(void) { CF = (R.A>>7)&1; R.A = (R.A<<1) | (R.A>>7); }
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@ -538,6 +515,7 @@ static void djnz_lp2(void) { UINT8 i=M_RDMEM_OPCODE(); LP2--; if (LP2 != 0) M_JM
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static void jnz(void) { UINT8 i=M_RDMEM_OPCODE(); if (!ZF) M_JMP(i); }
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static void jnc(void) { UINT8 i=M_RDMEM_OPCODE(); if (!CF) M_JMP(i);}
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static void jz(void) { UINT8 i=M_RDMEM_OPCODE(); if ( ZF) M_JMP(i); }
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static void jc(void) { UINT8 i=M_RDMEM_OPCODE(); if ( CF) M_JMP(i);}
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static void jmp(void) { M_JMP( M_RDMEM_OPCODE() ); }
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#if (HAS_ALPHA8201)
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@ -586,19 +564,25 @@ static const s_opcode opcode_8201[256]=
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#if (HAS_ALPHA8301)
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/* ALPHA 8301 : added instruction */
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static void dec_ix0(void) { IX0--; } /* OK */
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static void ld_a_x(void) { R.A = R.B; need_verify("LD A,unk"); }
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static void ld_x_a(void) { R.B = R.A; need_verify("LD unk,A"); }
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static void ld_a_b(void) { R.A = R.B; }
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static void ld_b_a(void) { R.B = R.A; }
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static void exg_a_ix0(void) { UINT8 t=R.A; R.A = IX0; IX0 = t; }
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static void exg_a_ix1(void) { UINT8 t=R.A; R.A = IX1; IX1 = t; }
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static void exg_a_ix2(void) { UINT8 t=R.A; R.A = IX2; IX2 = t; }
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static void exg_a_lp0(void) { UINT8 t=R.A; R.A = LP0; LP0 = t; }
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static void ld_lp0_a(void) { LP0 = R.A; }
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static void exg_a_lp1(void) { UINT8 t=R.A; R.A = LP1; LP1 = t; }
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static void exg_a_lp2(void) { UINT8 t=R.A; R.A = LP2; LP2 = t; }
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static void exg_a_b(void) { UINT8 t=R.A; R.A = R.B; R.B = t; }
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static void exg_a_rb(void) { UINT8 t=R.A; R.A = regPTR; regPTR = t; }
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static void ld_ix0_a(void) { IX0 = R.A; } /* maybe OK */
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static void ld_ix1_a(void) { IX1 = R.A; need_verify("LD IX1,A"); } /* not found */
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static void ld_ix2_a(void) { IX2 = R.A; } /* maybe OK */
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static void ld_ix0_a(void) { IX0 = R.A; }
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static void ld_ix1_a(void) { IX1 = R.A; }
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static void ld_ix2_a(void) { IX2 = R.A; }
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static void ld_lp0_a(void) { LP0 = R.A; }
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static void ld_lp1_a(void) { LP1 = R.A; }
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static void ld_lp2_a(void) { LP2 = R.A; }
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static void ld_b_a(void) { R.B = R.A; }
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static void ld_rb_a(void) { regPTR = R.A; }
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static void exg_ix0_ix1(void) { UINT8 t=IX1; IX1 = IX0; IX0 = t; }
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static void exg_ix0_ix2(void) { UINT8 t=IX2; IX2 = IX0; IX0 = t; }
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static void op_d4(void) { R.A = M_RDMEM( ((RD_REG(7) & 3) << 8) | M_RDMEM_OPCODE() ); }
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@ -608,20 +592,26 @@ static void op_d7(void) { M_WRMEM( ((RD_REG(7) & 3) << 8) | M_RDMEM_OPCODE(), LP
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static void ld_a_abs(void) { R.A = M_RDMEM( ((R.mb & 3) << 8) | M_RDMEM_OPCODE() ); }
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static void ld_abs_a(void) { M_WRMEM( ((R.mb & 3) << 8) | M_RDMEM_OPCODE(), R.A ); }
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static void op_dd(void) { regRAM[(M_RDMEM_OPCODE()>>1)&0x3f] = R.A; }
|
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static void op_ldir(void) { M_WRMEM(BIX2+0, regRAM[(R.B>>1)&0x3f]); IX2++; R.B+=2; LP0--; if (LP0 != 0) PCL--; }
|
||||
static void op_f6(void) { regRAM[(R.B>>1)&0x3f] = R.A; }
|
||||
static void op_f8(void) { M_SUB( regRAM[(R.B>>1)&0x3f] ); need_verify("SUB/CMP A,(RXB)"); }
|
||||
static void op_f9(void) { M_XOR( regRAM[(R.B>>1)&0x3f] ); }
|
||||
static void ld_a_r(void) { R.A = regRAM[(M_RDMEM_OPCODE()>>1)&0x3f]; }
|
||||
static void ld_r_a(void) { regRAM[(M_RDMEM_OPCODE()>>1)&0x3f] = R.A; }
|
||||
static void op_rep_ld_ix2_b(void) { do { M_WRMEM(BIX2, regRAM[(R.B>>1)&0x3f]); IX2++; R.B+=2; LP0--; } while (LP0 != 0); }
|
||||
static void op_rep_ld_b_ix0(void) { do { regRAM[(R.B>>1)&0x3f] = M_RDMEM(BIX0); IX0++; R.B+=2; LP0--; } while (LP0 != 0); }
|
||||
static void ld_rxb_a(void) { regRAM[(R.B>>1)&0x3f] = R.A; }
|
||||
static void ld_a_rxb(void) { R.A = regRAM[(R.B>>1)&0x3f]; }
|
||||
static void cmp_a_rxb(void) { UINT8 i=regRAM[(R.B>>1)&0x3f]; ZF = (R.A==i); CF = (R.A>=i); }
|
||||
static void xor_a_rxb(void) { M_XOR( regRAM[(R.B>>1)&0x3f] ); }
|
||||
|
||||
static void add_a_cf(void) { R.A += CF; CF = 0; ZF = (R.A==0); }
|
||||
static void add_a_cf(void) { if (CF) inc_a(); }
|
||||
static void sub_a_cf(void) { if (CF) dec_a(); }
|
||||
static void tst_a(void) { ZF = (R.A==0); }
|
||||
static void clr_a(void) { R.A = 0; ZF = (R.A==0); }
|
||||
static void cmp_a_n(void) { UINT8 i=M_RDMEM_OPCODE(); ZF = (R.A==i); CF = (R.A>=i); }
|
||||
static void xor_a_n(void) { M_XOR( M_RDMEM_OPCODE() ); }
|
||||
static void call(void) { UINT8 i=M_RDMEM_OPCODE(); R.retptr.w.l = PC; M_JMP(i); }; /* OK , but stack is unknown */
|
||||
static void call(void) { UINT8 i=M_RDMEM_OPCODE(); R.retptr.w.l = PC; M_JMP(i); };
|
||||
static void ld_a_ix0_a(void) { R.A = M_RDMEM(BIX0+R.A); }
|
||||
static void ret(void) { R.mb = R.retptr.b.h; M_JMP( R.retptr.b.l ); }; /* OK , but stack is unknown */
|
||||
static void ret(void) { R.mb = R.retptr.b.h; M_JMP( R.retptr.b.l ); };
|
||||
static void save_zc(void) { R.savez = ZF; R.savec = CF; };
|
||||
static void rest_zc(void) { ZF = R.savez; CF = R.savec; };
|
||||
|
||||
static const s_opcode opcode_8301[256]=
|
||||
{
|
||||
@ -658,12 +648,12 @@ static const s_opcode opcode_8301[256]=
|
||||
{C2, ld_ix0_n },{C2, ld_ix1_n},{C2, ld_ix2_n },{C2, ld_a_n },{C2, ld_lp0_n },{C2, ld_lp1_n },{C2, ld_lp2_n },{C2, ld_b_n },
|
||||
{C2, add_a_n },{C2, sub_a_n },{C2, and_a_n },{C2, or_a_n },{C2, djnz_lp0 },{C2, djnz_lp1 },{C2, djnz_lp2 },{C2, jnz },
|
||||
{C2, jnc },{C2, jz },{C2, jmp },{C2,undefined2},{C2, op_d4 },{C2, op_d5 },{C2, op_d6 },{C2, op_d7 },
|
||||
{C2, ld_a_abs },{C2, ld_abs_a},{C2,cmp_a_n },{C2,xor_a_n },{C2,undefined2},{C2, op_dd },{C2,undefined2},{C2, call},
|
||||
{C2, ld_a_abs },{C2, ld_abs_a},{C2,cmp_a_n },{C2,xor_a_n },{C2, ld_a_r },{C2, ld_r_a },{C2, jc },{C2, call},
|
||||
/* E0 : 8301 */
|
||||
{C1, dec_ix0 },{C1, undefined},{C1, undefined},{C1, ld_a_x },{C1, undefined},{C1, ld_a_b },{C1, exg_a_lp0 },{C1, undefined},
|
||||
{C1, ld_ix0_a },{C1, ld_ix1_a },{C1, ld_ix2_a },{C1, ld_x_a },{C1, undefined},{C1, ld_b_a },{C1, ld_lp0_a },{C1, undefined},
|
||||
{C1, undefined },{C1,exg_ix0_ix2},{C1,op_ldir },{C1, undefined},{C1, undefined},{C1, undefined},{C1, op_f6 },{C1, undefined},
|
||||
{C1, op_f8 },{C1, op_f9 },{C1, add_a_cf },{C1, undefined},{C1, tst_a },{C1, clr_a },{C1,ld_a_ix0_a},{C1, ret }
|
||||
{C1, exg_a_ix0 },{C1, exg_a_ix1},{C1, exg_a_ix2},{C1, exg_a_lp1},{C1, exg_a_lp2},{C1, exg_a_b },{C1, exg_a_lp0},{C1, exg_a_rb },
|
||||
{C1, ld_ix0_a },{C1, ld_ix1_a },{C1, ld_ix2_a },{C1, ld_lp1_a },{C1, ld_lp2_a },{C1, ld_b_a },{C1, ld_lp0_a },{C1, ld_rb_a },
|
||||
{C1,exg_ix0_ix1},{C1,exg_ix0_ix2},{C1,op_rep_ld_ix2_b},{C1, op_rep_ld_b_ix0},{C1, save_zc},{C1, rest_zc},{C1, ld_rxb_a },{C1, ld_a_rxb },
|
||||
{C1, cmp_a_rxb },{C1, xor_a_rxb},{C1, add_a_cf },{C1, sub_a_cf },{C1, tst_a },{C1, clr_a },{C1, ld_a_ix0_a},{C1, ret }
|
||||
};
|
||||
#endif
|
||||
|
||||
@ -690,6 +680,9 @@ static void ALPHA8201_init (int index, int clock, const void *config, int (*irqc
|
||||
state_save_register_item("ALPHA8201", index, LP2);
|
||||
state_save_register_item("ALPHA8201", index, R.A);
|
||||
state_save_register_item("ALPHA8201", index, R.B);
|
||||
state_save_register_item("ALPHA8201", index, R.retptr);
|
||||
state_save_register_item("ALPHA8201", index, R.savec);
|
||||
state_save_register_item("ALPHA8201", index, R.savez);
|
||||
}
|
||||
/****************************************************************************
|
||||
* Reset registers to their initial values
|
||||
|
||||
@ -838,8 +838,9 @@ ROM_START( champbb2 )
|
||||
ROM_LOAD( "epr5934", 0x2000, 0x2000, CRC(7c01715f) SHA1(b15b2001b8c110f2599eee3aeed79f67686ebd7e) )
|
||||
ROM_LOAD( "epr5935", 0x4000, 0x2000, CRC(3c911786) SHA1(eea0c467e213d237b5bb9d04b19a418d6090c2dc) )
|
||||
|
||||
// the pcb has a 8302 on it, though only the 8201 instructions are used
|
||||
ROM_REGION( 0x2000, "MCU", 0 )
|
||||
ROM_LOAD( "8201.bin", 0x0000, 0x2000, CRC(b77931ac) SHA1(405b02585e80d95a2821455538c5c2c31ce262d1) )
|
||||
ROM_LOAD( "8302.bin", 0x0000, 0x2000, CRC(edabac6c) SHA1(eaf1c51b63023256df526b0d3fd53cffc919c901) )
|
||||
|
||||
ROM_REGION( 0x2000, "gfx1", ROMREGION_DISPOSE ) // chars + sprites: rearranged by DRIVER_INIT to leave only chars
|
||||
ROM_LOAD( "epr5936", 0x0000, 0x2000, CRC(c4a4df75) SHA1(7b85dbf405697b0b8881f910c08f6db6c828b19a) )
|
||||
@ -865,8 +866,9 @@ ROM_START( champb2a )
|
||||
ROM_LOAD( "epr5934", 0x2000, 0x2000, CRC(7c01715f) SHA1(b15b2001b8c110f2599eee3aeed79f67686ebd7e) )
|
||||
ROM_LOAD( "epr5935", 0x4000, 0x2000, CRC(3c911786) SHA1(eea0c467e213d237b5bb9d04b19a418d6090c2dc) )
|
||||
|
||||
// the pcb has a 8302 on it, though only the 8201 instructions are used
|
||||
ROM_REGION( 0x2000, "MCU", 0 )
|
||||
ROM_LOAD( "8201.bin", 0x0000, 0x2000, CRC(b77931ac) SHA1(405b02585e80d95a2821455538c5c2c31ce262d1) )
|
||||
ROM_LOAD( "8302.bin", 0x0000, 0x2000, CRC(edabac6c) SHA1(eaf1c51b63023256df526b0d3fd53cffc919c901) )
|
||||
|
||||
ROM_REGION( 0x2000, "gfx1", ROMREGION_DISPOSE ) // chars + sprites: rearranged by DRIVER_INIT to leave only chars
|
||||
ROM_LOAD( "epr5936", 0x0000, 0x2000, CRC(c4a4df75) SHA1(7b85dbf405697b0b8881f910c08f6db6c828b19a) )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user