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m65c02, r65c02: Correct memory access patterns for read-modify-write instructions

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The extra operand cycle in CMOS versions becomes a dummy read rather than a writeback, and page boundaries do not figure into cycle timings for indexed modes.
This commit is contained in:
AJR 2019-08-10 10:33:41 -04:00
parent 5cdfb33855
commit 82c9bfb6bb
4 changed files with 229 additions and 51 deletions
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24
src/devices/cpu/m6502/dm65c02.lst
View File

@ -1,20 +1,20 @@
# license:BSD-3-Clause
# copyright-holders:Olivier Galibert
# m65c02
brk_c_imp ora_idx nop_imm nop_c_imp tsb_zpg ora_zpg asl_zpg nop_c_imp php_imp ora_imm asl_acc nop_c_imp tsb_aba ora_aba asl_aba nop_c_imp
bpl_rel ora_idy ora_zpi nop_c_imp trb_zpg ora_zpx asl_zpx nop_c_imp clc_imp ora_aby inc_acc nop_c_imp trb_aba ora_abx asl_c_abx nop_c_imp
jsr_adr and_idx nop_imm nop_c_imp bit_zpg and_zpg rol_zpg nop_c_imp plp_imp and_imm rol_acc nop_c_imp bit_aba and_aba rol_aba nop_c_imp
bmi_rel and_idy and_zpi nop_c_imp bit_zpx and_zpx rol_zpx nop_c_imp sec_imp and_aby dec_acc nop_c_imp bit_abx and_abx rol_c_abx nop_c_imp
rti_imp eor_idx nop_imm nop_c_imp nop_zpg eor_zpg lsr_zpg nop_c_imp pha_imp eor_imm lsr_acc nop_c_imp jmp_adr eor_aba lsr_aba nop_c_imp
bvc_rel eor_idy eor_zpi nop_c_imp nop_zpx eor_zpx lsr_zpx nop_c_imp cli_imp eor_aby phy_imp nop_c_imp nop_c_aba eor_abx lsr_c_abx nop_c_imp
rts_imp adc_c_idx nop_imm nop_c_imp stz_zpg adc_c_zpg ror_zpg nop_c_imp pla_imp adc_c_imm ror_acc nop_c_imp jmp_c_ind adc_c_aba ror_aba nop_c_imp
bvs_rel adc_c_idy adc_c_zpi nop_c_imp stz_zpx adc_c_zpx ror_zpx nop_c_imp sei_imp adc_c_aby ply_imp nop_c_imp jmp_iax adc_c_abx ror_c_abx nop_c_imp
brk_c_imp ora_idx nop_imm nop_c_imp tsb_zpg ora_zpg asl_c_zpg nop_c_imp php_imp ora_imm asl_acc nop_c_imp tsb_aba ora_aba asl_c_aba nop_c_imp
bpl_rel ora_idy ora_zpi nop_c_imp trb_zpg ora_zpx asl_c_zpx nop_c_imp clc_imp ora_aby inc_acc nop_c_imp trb_aba ora_abx asl_c_abx nop_c_imp
jsr_adr and_idx nop_imm nop_c_imp bit_zpg and_zpg rol_c_zpg nop_c_imp plp_imp and_imm rol_acc nop_c_imp bit_aba and_aba rol_c_aba nop_c_imp
bmi_rel and_idy and_zpi nop_c_imp bit_zpx and_zpx rol_c_zpx nop_c_imp sec_imp and_aby dec_acc nop_c_imp bit_abx and_abx rol_c_abx nop_c_imp
rti_imp eor_idx nop_imm nop_c_imp nop_zpg eor_zpg lsr_c_zpg nop_c_imp pha_imp eor_imm lsr_acc nop_c_imp jmp_adr eor_aba lsr_c_aba nop_c_imp
bvc_rel eor_idy eor_zpi nop_c_imp nop_zpx eor_zpx lsr_c_zpx nop_c_imp cli_imp eor_aby phy_imp nop_c_imp nop_c_aba eor_abx lsr_c_abx nop_c_imp
rts_imp adc_c_idx nop_imm nop_c_imp stz_zpg adc_c_zpg ror_c_zpg nop_c_imp pla_imp adc_c_imm ror_acc nop_c_imp jmp_c_ind adc_c_aba ror_c_aba nop_c_imp
bvs_rel adc_c_idy adc_c_zpi nop_c_imp stz_zpx adc_c_zpx ror_c_zpx nop_c_imp sei_imp adc_c_aby ply_imp nop_c_imp jmp_iax adc_c_abx ror_c_abx nop_c_imp
bra_rel sta_idx nop_imm nop_c_imp sty_zpg sta_zpg stx_zpg nop_c_imp dey_imp bit_imm txa_imp nop_c_imp sty_aba sta_aba stx_aba nop_c_imp
bcc_rel sta_idy sta_zpi nop_c_imp sty_zpx sta_zpx stx_zpy nop_c_imp tya_imp sta_aby txs_imp nop_c_imp stz_aba sta_abx stz_abx nop_c_imp
ldy_imm lda_idx ldx_imm nop_c_imp ldy_zpg lda_zpg ldx_zpg nop_c_imp tay_imp lda_imm tax_imp nop_c_imp ldy_aba lda_aba ldx_aba nop_c_imp
bcs_rel lda_idy lda_zpi nop_c_imp ldy_zpx lda_zpx ldx_zpy nop_c_imp clv_imp lda_aby tsx_imp nop_c_imp ldy_abx lda_abx ldx_aby nop_c_imp
cpy_imm cmp_idx nop_imm nop_c_imp cpy_zpg cmp_zpg dec_zpg nop_c_imp iny_imp cmp_imm dex_imp nop_c_imp cpy_aba cmp_aba dec_aba nop_c_imp
bne_rel cmp_idy cmp_zpi nop_c_imp nop_zpx cmp_zpx dec_zpx nop_c_imp cld_imp cmp_aby phx_imp nop_c_imp nop_c_abx cmp_abx dec_abx nop_c_imp
cpx_imm sbc_c_idx nop_imm nop_c_imp cpx_zpg sbc_c_zpg inc_zpg nop_c_imp inx_imp sbc_c_imm nop_imp nop_c_imp cpx_aba sbc_c_aba inc_aba nop_c_imp
beq_rel sbc_c_idy sbc_c_zpi nop_c_imp nop_zpx sbc_c_zpx inc_zpx nop_c_imp sed_imp sbc_c_aby plx_imp nop_c_imp nop_c_abx sbc_c_abx inc_abx nop_c_imp
cpy_imm cmp_idx nop_imm nop_c_imp cpy_zpg cmp_zpg dec_c_zpg nop_c_imp iny_imp cmp_imm dex_imp nop_c_imp cpy_aba cmp_aba dec_c_aba nop_c_imp
bne_rel cmp_idy cmp_zpi nop_c_imp nop_zpx cmp_zpx dec_c_zpx nop_c_imp cld_imp cmp_aby phx_imp nop_c_imp nop_c_abx cmp_abx dec_c_abx nop_c_imp
cpx_imm sbc_c_idx nop_imm nop_c_imp cpx_zpg sbc_c_zpg inc_c_zpg nop_c_imp inx_imp sbc_c_imm nop_imp nop_c_imp cpx_aba sbc_c_aba inc_c_aba nop_c_imp
beq_rel sbc_c_idy sbc_c_zpi nop_c_imp nop_zpx sbc_c_zpx inc_c_zpx nop_c_imp sed_imp sbc_c_aby plx_imp nop_c_imp nop_c_abx sbc_c_abx inc_c_abx nop_c_imp
reset

24
src/devices/cpu/m6502/dr65c02.lst
View File

@ -1,20 +1,20 @@
# license:BSD-3-Clause
# copyright-holders:Olivier Galibert
# r65c02 - rockwell variant, with the bitwise instructions and stp/wai
brk_c_imp ora_idx nop_imm nop_c_imp tsb_zpg ora_zpg asl_zpg rmb_bzp php_imp ora_imm asl_acc nop_c_imp tsb_aba ora_aba asl_aba bbr_zpb
bpl_rel ora_idy ora_zpi nop_c_imp trb_zpg ora_zpx asl_zpx rmb_bzp clc_imp ora_aby inc_acc nop_c_imp trb_aba ora_abx asl_c_abx bbr_zpb
jsr_adr and_idx nop_imm nop_c_imp bit_zpg and_zpg rol_zpg rmb_bzp plp_imp and_imm rol_acc nop_c_imp bit_aba and_aba rol_aba bbr_zpb
bmi_rel and_idy and_zpi nop_c_imp bit_zpx and_zpx rol_zpx rmb_bzp sec_imp and_aby dec_acc nop_c_imp bit_abx and_abx rol_c_abx bbr_zpb
rti_imp eor_idx nop_imm nop_c_imp nop_zpg eor_zpg lsr_zpg rmb_bzp pha_imp eor_imm lsr_acc nop_c_imp jmp_adr eor_aba lsr_aba bbr_zpb
bvc_rel eor_idy eor_zpi nop_c_imp nop_zpx eor_zpx lsr_zpx rmb_bzp cli_imp eor_aby phy_imp nop_c_imp nop_c_aba eor_abx lsr_c_abx bbr_zpb
rts_imp adc_c_idx nop_imm nop_c_imp stz_zpg adc_c_zpg ror_zpg rmb_bzp pla_imp adc_c_imm ror_acc nop_c_imp jmp_c_ind adc_c_aba ror_aba bbr_zpb
bvs_rel adc_c_idy adc_c_zpi nop_c_imp stz_zpx adc_c_zpx ror_zpx rmb_bzp sei_imp adc_c_aby ply_imp nop_c_imp jmp_iax adc_c_abx ror_c_abx bbr_zpb
brk_c_imp ora_idx nop_imm nop_c_imp tsb_zpg ora_zpg asl_c_zpg rmb_bzp php_imp ora_imm asl_acc nop_c_imp tsb_aba ora_aba asl_c_aba bbr_zpb
bpl_rel ora_idy ora_zpi nop_c_imp trb_zpg ora_zpx asl_c_zpx rmb_bzp clc_imp ora_aby inc_acc nop_c_imp trb_aba ora_abx asl_c_abx bbr_zpb
jsr_adr and_idx nop_imm nop_c_imp bit_zpg and_zpg rol_c_zpg rmb_bzp plp_imp and_imm rol_acc nop_c_imp bit_aba and_aba rol_c_aba bbr_zpb
bmi_rel and_idy and_zpi nop_c_imp bit_zpx and_zpx rol_c_zpx rmb_bzp sec_imp and_aby dec_acc nop_c_imp bit_abx and_abx rol_c_abx bbr_zpb
rti_imp eor_idx nop_imm nop_c_imp nop_zpg eor_zpg lsr_c_zpg rmb_bzp pha_imp eor_imm lsr_acc nop_c_imp jmp_adr eor_aba lsr_c_aba bbr_zpb
bvc_rel eor_idy eor_zpi nop_c_imp nop_zpx eor_zpx lsr_c_zpx rmb_bzp cli_imp eor_aby phy_imp nop_c_imp nop_c_aba eor_abx lsr_c_abx bbr_zpb
rts_imp adc_c_idx nop_imm nop_c_imp stz_zpg adc_c_zpg ror_c_zpg rmb_bzp pla_imp adc_c_imm ror_acc nop_c_imp jmp_c_ind adc_c_aba ror_c_aba bbr_zpb
bvs_rel adc_c_idy adc_c_zpi nop_c_imp stz_zpx adc_c_zpx ror_c_zpx rmb_bzp sei_imp adc_c_aby ply_imp nop_c_imp jmp_iax adc_c_abx ror_c_abx bbr_zpb
bra_rel sta_idx nop_imm nop_c_imp sty_zpg sta_zpg stx_zpg smb_bzp dey_imp bit_imm txa_imp nop_c_imp sty_aba sta_aba stx_aba bbs_zpb
bcc_rel sta_idy sta_zpi nop_c_imp sty_zpx sta_zpx stx_zpy smb_bzp tya_imp sta_aby txs_imp nop_c_imp stz_aba sta_abx stz_abx bbs_zpb
ldy_imm lda_idx ldx_imm nop_c_imp ldy_zpg lda_zpg ldx_zpg smb_bzp tay_imp lda_imm tax_imp nop_c_imp ldy_aba lda_aba ldx_aba bbs_zpb
bcs_rel lda_idy lda_zpi nop_c_imp ldy_zpx lda_zpx ldx_zpy smb_bzp clv_imp lda_aby tsx_imp nop_c_imp ldy_abx lda_abx ldx_aby bbs_zpb
cpy_imm cmp_idx nop_imm nop_c_imp cpy_zpg cmp_zpg dec_zpg smb_bzp iny_imp cmp_imm dex_imp wai_imp cpy_aba cmp_aba dec_aba bbs_zpb
bne_rel cmp_idy cmp_zpi nop_c_imp nop_zpx cmp_zpx dec_zpx smb_bzp cld_imp cmp_aby phx_imp stp_imp nop_c_abx cmp_abx dec_abx bbs_zpb
cpx_imm sbc_c_idx nop_imm nop_c_imp cpx_zpg sbc_c_zpg inc_zpg smb_bzp inx_imp sbc_c_imm nop_imp nop_c_imp cpx_aba sbc_c_aba inc_aba bbs_zpb
beq_rel sbc_c_idy sbc_c_zpi nop_c_imp nop_zpx sbc_c_zpx inc_zpx smb_bzp sed_imp sbc_c_aby plx_imp nop_c_imp nop_c_abx sbc_c_abx inc_abx bbs_zpb
cpy_imm cmp_idx nop_imm nop_c_imp cpy_zpg cmp_zpg dec_c_zpg smb_bzp iny_imp cmp_imm dex_imp wai_imp cpy_aba cmp_aba dec_c_aba bbs_zpb
bne_rel cmp_idy cmp_zpi nop_c_imp nop_zpx cmp_zpx dec_c_zpx smb_bzp cld_imp cmp_aby phx_imp stp_imp nop_c_abx cmp_abx dec_c_abx bbs_zpb
cpx_imm sbc_c_idx nop_imm nop_c_imp cpx_zpg sbc_c_zpg inc_c_zpg smb_bzp inx_imp sbc_c_imm nop_imp nop_c_imp cpx_aba sbc_c_aba inc_c_aba bbs_zpb
beq_rel sbc_c_idy sbc_c_zpi nop_c_imp nop_zpx sbc_c_zpx inc_c_zpx smb_bzp sed_imp sbc_c_aby plx_imp nop_c_imp nop_c_abx sbc_c_abx inc_c_abx bbs_zpb
reset

12
src/devices/cpu/m6502/m65c02.h
View File

@ -31,19 +31,19 @@ protected:
// 65c02 opcodes
O(adc_c_aba); O(adc_c_abx); O(adc_c_aby); O(adc_c_idx); O(adc_c_idy); O(adc_c_imm); O(adc_c_zpg); O(adc_c_zpi); O(adc_c_zpx);
O(and_zpi);
O(asl_c_abx);
O(asl_c_aba); O(asl_c_abx); O(asl_c_zpg); O(asl_c_zpx);
O(bbr_zpb);
O(bbs_zpb);
O(bit_abx); O(bit_imm); O(bit_zpx);
O(bra_rel);
O(brk_c_imp);
O(cmp_zpi);
O(dec_acc);
O(dec_acc); O(dec_c_aba); O(dec_c_abx); O(dec_c_zpg); O(dec_c_zpx);
O(eor_zpi);
O(inc_acc);
O(inc_acc); O(inc_c_aba); O(inc_c_abx); O(inc_c_zpg); O(inc_c_zpx);
O(jmp_c_ind); O(jmp_iax);
O(lda_zpi);
O(lsr_c_abx);
O(lsr_c_aba); O(lsr_c_abx); O(lsr_c_zpg); O(lsr_c_zpx);
O(nop_c_aba); O(nop_c_abx); O(nop_c_imp);
O(ora_zpi);
O(phx_imp);
@ -51,8 +51,8 @@ protected:
O(plx_imp);
O(ply_imp);
O(rmb_bzp);
O(rol_c_abx);
O(ror_c_abx);
O(rol_c_aba); O(rol_c_abx); O(rol_c_zpg); O(rol_c_zpx);
O(ror_c_aba); O(ror_c_abx); O(ror_c_zpg); O(ror_c_zpx);
O(sbc_c_aba); O(sbc_c_abx); O(sbc_c_aby); O(sbc_c_idx); O(sbc_c_idy); O(sbc_c_imm); O(sbc_c_zpg); O(sbc_c_zpi); O(sbc_c_zpx);
O(smb_bzp);
O(stp_imp);

220
src/devices/cpu/m6502/om65c02.lst
View File

@ -119,24 +119,48 @@ and_zpi
set_nz(A);
prefetch();
asl_c_aba
TMP = read_pc();
TMP = set_h(TMP, read_pc());
TMP2 = read(TMP);
read(TMP);
TMP2 = do_asl(TMP2);
write(TMP, TMP2);
prefetch();
asl_c_abx
TMP = read_pc();
TMP = set_h(TMP, read_pc());
if(page_changing(TMP, X)) {
read(set_l(TMP, TMP+X));
}
read(set_l(TMP, TMP+X));
TMP += X;
TMP2 = read(TMP);
read(TMP);
TMP2 = do_asl(TMP2);
write(TMP, TMP2);
prefetch();
asl_c_zpg
TMP = read_pc();
TMP2 = read(TMP);
read(TMP);
TMP2 = do_asl(TMP2);
write(TMP, TMP2);
prefetch();
asl_c_zpx
TMP = read_pc();
read(TMP);
TMP = uint8_t(TMP+X);
TMP2 = read(TMP);
read(TMP);
TMP2 = do_asl(TMP2);
write(TMP, TMP2);
prefetch();
bbr_zpb
// Access pattern uncertain
TMP = read_pc();
TMP2 = read(TMP);
TMP = read_pc();
read(TMP);
read_pc_noinc();
if(!(TMP2 & (1 << ((inst_state >> 4) & 7)))) {
PC += int8_t(TMP);
@ -144,10 +168,9 @@ bbr_zpb
prefetch();
bbs_zpb
// Access pattern uncertain
TMP = read_pc();
TMP2 = read(TMP);
TMP = read_pc();
read(TMP);
read_pc_noinc();
if(TMP2 & (1 << ((inst_state >> 4) & 7))) {
PC += int8_t(TMP);
@ -229,6 +252,48 @@ dec_acc
set_nz(A);
prefetch();
dec_c_aba
TMP = read_pc();
TMP = set_h(TMP, read_pc());
TMP2 = read(TMP);
read(TMP);
TMP2--;
set_nz(TMP2);
write(TMP, TMP2);
prefetch();
dec_c_abx
TMP = read_pc();
TMP = set_h(TMP, read_pc());
read(set_l(TMP, TMP+X));
TMP += X;
TMP2 = read(TMP);
read(TMP);
TMP2--;
set_nz(TMP2);
write(TMP, TMP2);
prefetch();
dec_c_zpg
TMP = read_pc();
TMP2 = read(TMP);
read(TMP);
TMP2--;
set_nz(TMP2);
write(TMP, TMP2);
prefetch();
dec_c_zpx
TMP = read_pc();
read(TMP);
TMP = uint8_t(TMP+X);
TMP2 = read(TMP);
read(TMP);
TMP2--;
set_nz(TMP2);
write(TMP, TMP2);
prefetch();
eor_zpi
TMP2 = read_pc();
TMP = read(TMP2 & 0xff);
@ -243,6 +308,48 @@ inc_acc
set_nz(A);
prefetch();
inc_c_aba
TMP = read_pc();
TMP = set_h(TMP, read_pc());
TMP2 = read(TMP);
read(TMP);
TMP2++;
set_nz(TMP2);
write(TMP, TMP2);
prefetch();
inc_c_abx
TMP = read_pc();
TMP = set_h(TMP, read_pc());
read(set_l(TMP, TMP+X));
TMP += X;
TMP2 = read(TMP);
read(TMP);
TMP2++;
set_nz(TMP2);
write(TMP, TMP2);
prefetch();
inc_c_zpg
TMP = read_pc();
TMP2 = read(TMP);
read(TMP);
TMP2++;
set_nz(TMP2);
write(TMP, TMP2);
prefetch();
inc_c_zpx
TMP = read_pc();
read(TMP);
TMP = uint8_t(TMP+X);
TMP2 = read(TMP);
read(TMP);
TMP2++;
set_nz(TMP2);
write(TMP, TMP2);
prefetch();
jmp_iax
TMP = read_pc();
TMP = set_h(TMP, read_pc());
@ -268,16 +375,40 @@ lda_zpi
set_nz(A);
prefetch();
lsr_c_aba
TMP = read_pc();
TMP = set_h(TMP, read_pc());
TMP2 = read(TMP);
read(TMP);
TMP2 = do_lsr(TMP2);
write(TMP, TMP2);
prefetch();
lsr_c_abx
TMP = read_pc();
TMP = set_h(TMP, read_pc());
if(page_changing(TMP, X)) {
read(set_l(TMP, TMP+X));
}
read(set_l(TMP, TMP+X));
TMP += X;
TMP2 = read(TMP);
read(TMP);
TMP2 = do_lsr(TMP2);
write(TMP, TMP2);
prefetch();
lsr_c_zpg
TMP = read_pc();
TMP2 = read(TMP);
read(TMP);
TMP2 = do_lsr(TMP2);
write(TMP, TMP2);
prefetch();
lsr_c_zpx
TMP = read_pc();
read(TMP);
TMP = uint8_t(TMP+X);
TMP2 = read(TMP);
read(TMP);
TMP2 = do_lsr(TMP2);
write(TMP, TMP2);
prefetch();
@ -338,37 +469,85 @@ ply_imp
prefetch();
rmb_bzp
// Access pattern unknown but probable (built upon inc_zpg)
TMP = read_pc();
TMP2 = read(TMP);
write(TMP, TMP2);
read(TMP);
TMP2 &= ~(1 << ((inst_state >> 4) & 7));
write(TMP, TMP2);
prefetch();
rol_c_aba
TMP = read_pc();
TMP = set_h(TMP, read_pc());
TMP2 = read(TMP);
read(TMP);
TMP2 = do_rol(TMP2);
write(TMP, TMP2);
prefetch();
rol_c_abx
TMP = read_pc();
TMP = set_h(TMP, read_pc());
if(page_changing(TMP, X)) {
read(set_l(TMP, TMP+X));
}
read(set_l(TMP, TMP+X));
TMP += X;
TMP2 = read(TMP);
write(TMP, TMP2);
read(TMP);
TMP2 = do_rol(TMP2);
write(TMP, TMP2);
prefetch();
rol_c_zpg
TMP = read_pc();
TMP2 = read(TMP);
read(TMP);
TMP2 = do_rol(TMP2);
write(TMP, TMP2);
prefetch();
rol_c_zpx
TMP = read_pc();
read(TMP);
TMP = uint8_t(TMP+X);
TMP2 = read(TMP);
read(TMP);
TMP2 = do_rol(TMP2);
write(TMP, TMP2);
prefetch();
ror_c_aba
TMP = read_pc();
TMP = set_h(TMP, read_pc());
TMP2 = read(TMP);
read(TMP);
TMP2 = do_ror(TMP2);
write(TMP, TMP2);
prefetch();
ror_c_abx
TMP = read_pc();
TMP = set_h(TMP, read_pc());
if(page_changing(TMP, X)) {
read(set_l(TMP, TMP+X));
}
read(set_l(TMP, TMP+X));
TMP += X;
TMP2 = read(TMP);
read(TMP);
TMP2 = do_ror(TMP2);
write(TMP, TMP2);
prefetch();
ror_c_zpg
TMP = read_pc();
TMP2 = read(TMP);
read(TMP);
TMP2 = do_ror(TMP2);
write(TMP, TMP2);
prefetch();
ror_c_zpx
TMP = read_pc();
read(TMP);
TMP = uint8_t(TMP+X);
TMP2 = read(TMP);
read(TMP);
TMP2 = do_ror(TMP2);
write(TMP, TMP2);
prefetch();
@ -483,10 +662,9 @@ sbc_c_zpx
prefetch();
smb_bzp
// Access pattern unknown but probable (built upon inc_zpg)
TMP = read_pc();
TMP2 = read(TMP);
write(TMP, TMP2);
read(TMP);
TMP2 |= 1 << ((inst_state >> 4) & 7);
write(TMP, TMP2);
prefetch();