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https://github.com/holub/mame
synced 2025-10-06 17:08:28 +03:00
i386.cpp: athlon xp now supports system management mode (nw)
This commit is contained in:
yz70s
parent
428542508d
commit
8320a30ff3
@ -430,7 +430,9 @@ void athlonxp_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
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m_msr_mtrrfix[2] = data;
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if (m_msr_smm_mask & 1)
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{
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// data = 0x1818181818181818; // when smm is implemented
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if (m_smm)
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data = 0x1818181818181818; // when smm is active
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else
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data = 0; // when smm is not active
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}
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parse_mtrrfix(data, 0xa0000, 16);
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@ -469,12 +471,15 @@ void athlonxp_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
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break;
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case 0xC0010111: // SMM_BASE
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m_msr_smm_base = (offs_t)data;
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m_smbase = m_msr_smm_base;
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break;
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case 0xC0010113: // SMM_MASK
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m_msr_smm_mask = data;
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if (m_msr_smm_mask & 1)
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{
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// data = 0x1818181818181818; // when smm is implemented
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if (m_smm)
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data = 0x1818181818181818; // when smm is active
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else
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data = 0; // when smm is not active
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}
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else
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@ -1542,7 +1542,7 @@ void i386_device::i386_check_irq_line()
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{
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if(!m_smm && m_smi)
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{
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pentium_smi();
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enter_smm();
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return;
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}
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@ -3947,15 +3947,12 @@ void i386_device::device_reset()
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CHANGE_PC(m_eip);
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}
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void i386_device::pentium_smi()
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void i386_device::enter_smm()
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{
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uint32_t smram_state = m_smbase + 0xfe00;
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uint32_t old_cr0 = m_cr[0];
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uint32_t old_flags = get_flags();
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if(m_smm)
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return;
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m_cr[0] &= ~(0x8000000d);
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set_flags(2);
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if(!m_smiact.isnull())
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@ -4037,6 +4034,87 @@ void i386_device::pentium_smi()
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CHANGE_PC(m_eip);
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}
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void i386_device::leave_smm()
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{
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uint32_t smram_state = m_smbase + 0xfe00;
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// load state, no sanity checks anywhere
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m_smbase = READ32(smram_state + SMRAM_SMBASE);
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m_cr[4] = READ32(smram_state + SMRAM_IP5_CR4);
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m_sreg[ES].limit = READ32(smram_state + SMRAM_IP5_ESLIM);
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m_sreg[ES].base = READ32(smram_state + SMRAM_IP5_ESBASE);
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m_sreg[ES].flags = READ32(smram_state + SMRAM_IP5_ESACC);
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m_sreg[CS].limit = READ32(smram_state + SMRAM_IP5_CSLIM);
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m_sreg[CS].base = READ32(smram_state + SMRAM_IP5_CSBASE);
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m_sreg[CS].flags = READ32(smram_state + SMRAM_IP5_CSACC);
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m_sreg[SS].limit = READ32(smram_state + SMRAM_IP5_SSLIM);
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m_sreg[SS].base = READ32(smram_state + SMRAM_IP5_SSBASE);
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m_sreg[SS].flags = READ32(smram_state + SMRAM_IP5_SSACC);
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m_sreg[DS].limit = READ32(smram_state + SMRAM_IP5_DSLIM);
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m_sreg[DS].base = READ32(smram_state + SMRAM_IP5_DSBASE);
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m_sreg[DS].flags = READ32(smram_state + SMRAM_IP5_DSACC);
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m_sreg[FS].limit = READ32(smram_state + SMRAM_IP5_FSLIM);
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m_sreg[FS].base = READ32(smram_state + SMRAM_IP5_FSBASE);
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m_sreg[FS].flags = READ32(smram_state + SMRAM_IP5_FSACC);
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m_sreg[GS].limit = READ32(smram_state + SMRAM_IP5_GSLIM);
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m_sreg[GS].base = READ32(smram_state + SMRAM_IP5_GSBASE);
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m_sreg[GS].flags = READ32(smram_state + SMRAM_IP5_GSACC);
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m_ldtr.flags = READ32(smram_state + SMRAM_IP5_LDTACC);
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m_ldtr.limit = READ32(smram_state + SMRAM_IP5_LDTLIM);
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m_ldtr.base = READ32(smram_state + SMRAM_IP5_LDTBASE);
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m_gdtr.limit = READ32(smram_state + SMRAM_IP5_GDTLIM);
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m_gdtr.base = READ32(smram_state + SMRAM_IP5_GDTBASE);
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m_idtr.limit = READ32(smram_state + SMRAM_IP5_IDTLIM);
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m_idtr.base = READ32(smram_state + SMRAM_IP5_IDTBASE);
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m_task.limit = READ32(smram_state + SMRAM_IP5_TRLIM);
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m_task.base = READ32(smram_state + SMRAM_IP5_TRBASE);
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m_task.flags = READ32(smram_state + SMRAM_IP5_TRACC);
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m_sreg[ES].selector = READ32(smram_state + SMRAM_ES);
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m_sreg[CS].selector = READ32(smram_state + SMRAM_CS);
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m_sreg[SS].selector = READ32(smram_state + SMRAM_SS);
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m_sreg[DS].selector = READ32(smram_state + SMRAM_DS);
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m_sreg[FS].selector = READ32(smram_state + SMRAM_FS);
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m_sreg[GS].selector = READ32(smram_state + SMRAM_GS);
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m_ldtr.segment = READ32(smram_state + SMRAM_LDTR);
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m_task.segment = READ32(smram_state + SMRAM_TR);
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m_dr[7] = READ32(smram_state + SMRAM_DR7);
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m_dr[6] = READ32(smram_state + SMRAM_DR6);
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REG32(EAX) = READ32(smram_state + SMRAM_EAX);
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REG32(ECX) = READ32(smram_state + SMRAM_ECX);
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REG32(EDX) = READ32(smram_state + SMRAM_EDX);
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REG32(EBX) = READ32(smram_state + SMRAM_EBX);
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REG32(ESP) = READ32(smram_state + SMRAM_ESP);
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REG32(EBP) = READ32(smram_state + SMRAM_EBP);
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REG32(ESI) = READ32(smram_state + SMRAM_ESI);
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REG32(EDI) = READ32(smram_state + SMRAM_EDI);
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m_eip = READ32(smram_state + SMRAM_EIP);
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m_eflags = READ32(smram_state + SMRAM_EFLAGS);
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m_cr[3] = READ32(smram_state + SMRAM_CR3);
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m_cr[0] = READ32(smram_state + SMRAM_CR0);
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m_CPL = (m_sreg[SS].flags >> 13) & 3; // cpl == dpl of ss
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for (int i = 0; i <= GS; i++)
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{
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if (PROTECTED_MODE && !V8086_MODE)
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{
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m_sreg[i].valid = m_sreg[i].selector ? true : false;
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m_sreg[i].d = (m_sreg[i].flags & 0x4000) ? 1 : 0;
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}
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else
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m_sreg[i].valid = true;
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}
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if (!m_smiact.isnull())
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m_smiact(false);
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m_smm = false;
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CHANGE_PC(m_eip);
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m_nmi_masked = false;
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}
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void i386_device::execute_set_input(int irqline, int state)
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{
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if ( irqline == INPUT_LINE_A20 )
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@ -4763,7 +4841,7 @@ void athlonxp_device::device_reset()
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m_memory_ranges_1m[n] = 0;
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m_msr_top_mem = 1024 * 1024;
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m_msr_sys_cfg = 0;
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m_msr_smm_base = 0x30000;
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m_msr_smm_base = m_smbase;
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m_msr_smm_mask = 0;
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m_cpuid_max_input_value_eax = 0x01;
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@ -4785,6 +4863,30 @@ device_memory_interface::space_config_vector athlonxp_device::memory_space_confi
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};
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}
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void athlonxp_device::enter_smm()
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{
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u64 data;
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if (m_msr_smm_mask & 1)
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data = 0x1818181818181818; // when smm is active
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else
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data = m_msr_mtrrfix[2];
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parse_mtrrfix(data, 0xa0000, 16);
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i386_device::enter_smm();
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}
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void athlonxp_device::leave_smm()
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{
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u64 data;
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i386_device::leave_smm();
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if (m_msr_smm_mask & 1)
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data = 0; // when smm is not active
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else
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data = m_msr_mtrrfix[2];
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parse_mtrrfix(data, 0xa0000, 16);
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}
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void athlonxp_device::parse_mtrrfix(u64 mtrr, offs_t base, int kblock)
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{
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int nb = kblock / 4;
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@ -72,6 +72,10 @@ protected:
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virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
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virtual int get_mode() const override;
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// cpu-specific system management mode routines
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virtual void enter_smm();
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virtual void leave_smm();
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// routines for opcodes whose operation can vary between cpu models
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// default implementations usually just log an error message
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virtual void opcode_cpuid();
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@ -1504,7 +1508,6 @@ protected:
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void i386_postload();
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void i386_common_init();
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void build_opcode_table(uint32_t features);
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void pentium_smi();
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void zero_state();
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void i386_set_a20_line(int state);
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@ -1644,6 +1647,8 @@ protected:
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virtual void cache_clean() override;
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void enter_smm() override;
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virtual void leave_smm() override;
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virtual u8 mem_pr8(offs_t address) override { return opcode_read_cache<u8, NATIVE_ENDIAN_VALUE_LE_BE(0, 3)>(address); }
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virtual u16 mem_pr16(offs_t address) override { return opcode_read_cache<u16, NATIVE_ENDIAN_VALUE_LE_BE(0, 2)>(address); }
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@ -247,32 +247,38 @@ enum smram_intel_p5
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};
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/* Protected mode exceptions */
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#define FAULT_UD 6 // Invalid Opcode
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#define FAULT_NM 7 // Coprocessor not available
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#define FAULT_DF 8 // Double Fault
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#define FAULT_TS 10 // Invalid TSS
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#define FAULT_NP 11 // Segment or Gate not present
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#define FAULT_SS 12 // Stack fault
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#define FAULT_GP 13 // General Protection Fault
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#define FAULT_PF 14 // Page Fault
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#define FAULT_MF 16 // Match (Coprocessor) Fault
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enum pm_faults
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{
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FAULT_UD = 6, // Invalid Opcode
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FAULT_NM = 7, // Coprocessor not available
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FAULT_DF = 8, // Double Fault
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FAULT_TS = 10, // Invalid TSS
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FAULT_NP = 11, // Segment or Gate not present
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FAULT_SS = 12, // Stack fault
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FAULT_GP = 13, // General Protection Fault
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FAULT_PF = 14, // Page Fault
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FAULT_MF = 16 // Match (Coprocessor) Fault
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};
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/* MXCSR Control and Status Register */
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#define MXCSR_IE (1<<0) // Invalid Operation Flag
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#define MXCSR_DE (1<<1) // Denormal Flag
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#define MXCSR_ZE (1<<2) // Divide-by-Zero Flag
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#define MXCSR_OE (1<<3) // Overflow Flag
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#define MXCSR_UE (1<<4) // Underflow Flag
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#define MXCSR_PE (1<<5) // Precision Flag
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#define MXCSR_DAZ (1<<6) // Denormals Are Zeros
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#define MXCSR_IM (1<<7) // Invalid Operation Mask
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#define MXCSR_DM (1<<8) // Denormal Operation Mask
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#define MXCSR_ZM (1<<9) // Divide-by-Zero Mask
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#define MXCSR_OM (1<<10) // Overflow Mask
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#define MXCSR_UM (1<<11) // Underflow Mask
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#define MXCSR_PM (1<<12) // Precision Mask
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#define MXCSR_RC (3<<13) // Rounding Control
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#define MXCSR_FZ (1<<15) // Flush to Zero
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enum mxcsr_bits
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{
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MXCSR_IE = 1 << 0, // Invalid Operation Flag
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MXCSR_DE = 1 << 1, // Denormal Flag
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MXCSR_ZE = 1 << 2, // Divide-by-Zero Flag
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MXCSR_OE = 1 << 3, // Overflow Flag
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MXCSR_UE = 1 << 4, // Underflow Flag
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MXCSR_PE = 1 << 5, // Precision Flag
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MXCSR_DAZ = 1 << 6, // Denormals Are Zeros
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MXCSR_IM = 1 << 7, // Invalid Operation Mask
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MXCSR_DM = 1 << 8, // Denormal Operation Mask
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MXCSR_ZM = 1 << 9, // Divide-by-Zero Mask
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MXCSR_OM = 1 << 10, // Overflow Mask
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MXCSR_UM = 1 << 11, // Underflow Mask
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MXCSR_PM = 1 << 12, // Precision Mask
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MXCSR_RC = 3 << 13, // Rounding Control
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MXCSR_FZ = 1 << 15 // Flush to Zero
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};
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union MMX_REG {
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uint32_t d[2];
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@ -104,7 +104,6 @@ void i386_device::pentium_ud2() // Opcode 0x0f 0b
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void i386_device::pentium_rsm()
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{
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uint32_t smram_state = m_smbase + 0xfe00;
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if(!m_smm)
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{
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logerror("i386: Invalid RSM outside SMM at %08X\n", m_pc - 1);
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@ -112,84 +111,10 @@ void i386_device::pentium_rsm()
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return;
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}
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// load state, no sanity checks anywhere
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m_smbase = READ32(smram_state+SMRAM_SMBASE);
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m_cr[4] = READ32(smram_state+SMRAM_IP5_CR4);
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m_sreg[ES].limit = READ32(smram_state+SMRAM_IP5_ESLIM);
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m_sreg[ES].base = READ32(smram_state+SMRAM_IP5_ESBASE);
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m_sreg[ES].flags = READ32(smram_state+SMRAM_IP5_ESACC);
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m_sreg[CS].limit = READ32(smram_state+SMRAM_IP5_CSLIM);
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m_sreg[CS].base = READ32(smram_state+SMRAM_IP5_CSBASE);
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m_sreg[CS].flags = READ32(smram_state+SMRAM_IP5_CSACC);
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m_sreg[SS].limit = READ32(smram_state+SMRAM_IP5_SSLIM);
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m_sreg[SS].base = READ32(smram_state+SMRAM_IP5_SSBASE);
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m_sreg[SS].flags = READ32(smram_state+SMRAM_IP5_SSACC);
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m_sreg[DS].limit = READ32(smram_state+SMRAM_IP5_DSLIM);
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m_sreg[DS].base = READ32(smram_state+SMRAM_IP5_DSBASE);
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m_sreg[DS].flags = READ32(smram_state+SMRAM_IP5_DSACC);
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m_sreg[FS].limit = READ32(smram_state+SMRAM_IP5_FSLIM);
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m_sreg[FS].base = READ32(smram_state+SMRAM_IP5_FSBASE);
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m_sreg[FS].flags = READ32(smram_state+SMRAM_IP5_FSACC);
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m_sreg[GS].limit = READ32(smram_state+SMRAM_IP5_GSLIM);
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m_sreg[GS].base = READ32(smram_state+SMRAM_IP5_GSBASE);
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m_sreg[GS].flags = READ32(smram_state+SMRAM_IP5_GSACC);
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m_ldtr.flags = READ32(smram_state+SMRAM_IP5_LDTACC);
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m_ldtr.limit = READ32(smram_state+SMRAM_IP5_LDTLIM);
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m_ldtr.base = READ32(smram_state+SMRAM_IP5_LDTBASE);
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m_gdtr.limit = READ32(smram_state+SMRAM_IP5_GDTLIM);
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m_gdtr.base = READ32(smram_state+SMRAM_IP5_GDTBASE);
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m_idtr.limit = READ32(smram_state+SMRAM_IP5_IDTLIM);
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m_idtr.base = READ32(smram_state+SMRAM_IP5_IDTBASE);
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m_task.limit = READ32(smram_state+SMRAM_IP5_TRLIM);
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m_task.base = READ32(smram_state+SMRAM_IP5_TRBASE);
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m_task.flags = READ32(smram_state+SMRAM_IP5_TRACC);
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m_sreg[ES].selector = READ32(smram_state+SMRAM_ES);
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m_sreg[CS].selector = READ32(smram_state+SMRAM_CS);
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m_sreg[SS].selector = READ32(smram_state+SMRAM_SS);
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m_sreg[DS].selector = READ32(smram_state+SMRAM_DS);
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m_sreg[FS].selector = READ32(smram_state+SMRAM_FS);
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m_sreg[GS].selector = READ32(smram_state+SMRAM_GS);
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m_ldtr.segment = READ32(smram_state+SMRAM_LDTR);
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m_task.segment = READ32(smram_state+SMRAM_TR);
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m_dr[7] = READ32(smram_state+SMRAM_DR7);
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m_dr[6] = READ32(smram_state+SMRAM_DR6);
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REG32(EAX) = READ32(smram_state+SMRAM_EAX);
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REG32(ECX) = READ32(smram_state+SMRAM_ECX);
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REG32(EDX) = READ32(smram_state+SMRAM_EDX);
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REG32(EBX) = READ32(smram_state+SMRAM_EBX);
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REG32(ESP) = READ32(smram_state+SMRAM_ESP);
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REG32(EBP) = READ32(smram_state+SMRAM_EBP);
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REG32(ESI) = READ32(smram_state+SMRAM_ESI);
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REG32(EDI) = READ32(smram_state+SMRAM_EDI);
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m_eip = READ32(smram_state+SMRAM_EIP);
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m_eflags = READ32(smram_state+SMRAM_EFLAGS);
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m_cr[3] = READ32(smram_state+SMRAM_CR3);
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m_cr[0] = READ32(smram_state+SMRAM_CR0);
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m_CPL = (m_sreg[SS].flags >> 13) & 3; // cpl == dpl of ss
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for(int i = 0; i <= GS; i++)
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{
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if(PROTECTED_MODE && !V8086_MODE)
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{
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m_sreg[i].valid = m_sreg[i].selector ? true : false;
|
||||
m_sreg[i].d = (m_sreg[i].flags & 0x4000) ? 1 : 0;
|
||||
}
|
||||
else
|
||||
m_sreg[i].valid = true;
|
||||
}
|
||||
|
||||
if(!m_smiact.isnull())
|
||||
m_smiact(false);
|
||||
m_smm = false;
|
||||
|
||||
CHANGE_PC(m_eip);
|
||||
m_nmi_masked = false;
|
||||
leave_smm();
|
||||
if(m_smi_latched)
|
||||
{
|
||||
pentium_smi();
|
||||
enter_smm();
|
||||
return;
|
||||
}
|
||||
if(m_nmi_latched)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user