diff --git a/src/devices/cpu/tlcs870/tlcs870.cpp b/src/devices/cpu/tlcs870/tlcs870.cpp index 43a167f9427..79af9af88b4 100644 --- a/src/devices/cpu/tlcs870/tlcs870.cpp +++ b/src/devices/cpu/tlcs870/tlcs870.cpp @@ -17,6 +17,8 @@ #include "tlcs870d.h" #include "debugger.h" +//#define VERBOSE 1 +#include "logmacro.h" DEFINE_DEVICE_TYPE(TMP87PH40AN, tmp87ph40an_device, "tmp87ph40an", "Toshiba TMP87PH40AN") @@ -289,15 +291,15 @@ WRITE8_MEMBER(tlcs870_device::tc1cr_w) { m_TC1CR = data; - logerror("%s m_TC1CR (16-bit TC1 Timer Control Register) bits set to\n", machine().describe_context()); - logerror("%d: TFF1 (Timer F/F1 control for PPG mode)\n", (m_TC1CR & 0x80) ? 1 : 0); - logerror("%d: SCAP1/MCAP1/METT1/MPPG1\n", (m_TC1CR & 0x40) ? 1 : 0); - logerror("%d: TC1S-1 (TC1 Start Control)\n", (m_TC1CR & 0x20) ? 1 : 0); - logerror("%d: TC1S-0 (TC1 Start Control)\n", (m_TC1CR & 0x10) ? 1 : 0); - logerror("%d: TC1CK-1 (TC1 Source Clock select)\n", (m_TC1CR & 0x08) ? 1 : 0); - logerror("%d: TC1CK-0 (TC1 Source Clock select)\n", (m_TC1CR & 0x04) ? 1 : 0); - logerror("%d: TC1M-1 (TC1 Mode Select)\n", (m_TC1CR & 0x02) ? 1 : 0); - logerror("%d: TC1M-0 (TC1 Mode Select)\n", (m_TC1CR & 0x01) ? 1 : 0); + LOG("%s m_TC1CR (16-bit TC1 Timer Control Register) bits set to\n", machine().describe_context()); + LOG("%d: TFF1 (Timer F/F1 control for PPG mode)\n", (m_TC1CR & 0x80) ? 1 : 0); + LOG("%d: SCAP1/MCAP1/METT1/MPPG1\n", (m_TC1CR & 0x40) ? 1 : 0); + LOG("%d: TC1S-1 (TC1 Start Control)\n", (m_TC1CR & 0x20) ? 1 : 0); + LOG("%d: TC1S-0 (TC1 Start Control)\n", (m_TC1CR & 0x10) ? 1 : 0); + LOG("%d: TC1CK-1 (TC1 Source Clock select)\n", (m_TC1CR & 0x08) ? 1 : 0); + LOG("%d: TC1CK-0 (TC1 Source Clock select)\n", (m_TC1CR & 0x04) ? 1 : 0); + LOG("%d: TC1M-1 (TC1 Mode Select)\n", (m_TC1CR & 0x02) ? 1 : 0); + LOG("%d: TC1M-0 (TC1 Mode Select)\n", (m_TC1CR & 0x01) ? 1 : 0); } WRITE8_MEMBER(tlcs870_device::treg1a_l_w) @@ -364,15 +366,15 @@ WRITE8_MEMBER(tlcs870_device::tc2cr_w) m_TC2CR = data; - logerror("%s m_TC2CR (16-bit TC2 Timer Control Register) bits set to\n", machine().describe_context()); - logerror("%d: (invalid)\n", (m_TC2CR & 0x80) ? 1 : 0); - logerror("%d: (invalid)\n", (m_TC2CR & 0x40) ? 1 : 0); - logerror("%d: TC2S (TC2 Start Control)\n", (m_TC2CR & 0x20) ? 1 : 0); - logerror("%d: TC2CK-2 (TC2 Source Clock select)\n", (m_TC2CR & 0x10) ? 1 : 0); - logerror("%d: TC2CK-1 (TC2 Source Clock select)\n", (m_TC2CR & 0x08) ? 1 : 0); - logerror("%d: TC2CK-0 (TC2 Source Clock select)\n", (m_TC2CR & 0x04) ? 1 : 0); - logerror("%d: (invalid)\n", (m_TC2CR & 0x02) ? 1 : 0); - logerror("%d: TC2M (TC2 Mode Select)\n", (m_TC2CR & 0x01) ? 1 : 0); + LOG("%s m_TC2CR (16-bit TC2 Timer Control Register) bits set to\n", machine().describe_context()); + LOG("%d: (invalid)\n", (m_TC2CR & 0x80) ? 1 : 0); + LOG("%d: (invalid)\n", (m_TC2CR & 0x40) ? 1 : 0); + LOG("%d: TC2S (TC2 Start Control)\n", (m_TC2CR & 0x20) ? 1 : 0); + LOG("%d: TC2CK-2 (TC2 Source Clock select)\n", (m_TC2CR & 0x10) ? 1 : 0); + LOG("%d: TC2CK-1 (TC2 Source Clock select)\n", (m_TC2CR & 0x08) ? 1 : 0); + LOG("%d: TC2CK-0 (TC2 Source Clock select)\n", (m_TC2CR & 0x04) ? 1 : 0); + LOG("%d: (invalid)\n", (m_TC2CR & 0x02) ? 1 : 0); + LOG("%d: TC2M (TC2 Mode Select)\n", (m_TC2CR & 0x01) ? 1 : 0); } WRITE8_MEMBER(tlcs870_device::treg2_l_w) @@ -396,15 +398,15 @@ WRITE8_MEMBER(tlcs870_device::tc3cr_w) { m_TC3CR = data; - logerror("%s m_TC3CR (8-bit TC3 Timer Control Register) bits set to\n", machine().describe_context()); - logerror("%d: (invalid)\n", (m_TC3CR & 0x80) ? 1 : 0); - logerror("%d: SCAP (Software Capture Control)\n", (m_TC3CR & 0x40) ? 1 : 0); - logerror("%d: (invalid)\n", (m_TC3CR & 0x20) ? 1 : 0); - logerror("%d: TC3S (TC3 Start Control)\n", (m_TC3CR & 0x10) ? 1 : 0); - logerror("%d: TC3CK-1 (TC3 Source Clock select)\n", (m_TC3CR & 0x08) ? 1 : 0); - logerror("%d: TC3CK-0 (TC3 Source Clock select)\n", (m_TC3CR & 0x04) ? 1 : 0); - logerror("%d: (invalid)\n", (m_TC3CR & 0x02) ? 1 : 0); - logerror("%d: TC3M (TC3 Mode Select)\n", (m_TC3CR & 0x01) ? 1 : 0); + LOG("%s m_TC3CR (8-bit TC3 Timer Control Register) bits set to\n", machine().describe_context()); + LOG("%d: (invalid)\n", (m_TC3CR & 0x80) ? 1 : 0); + LOG("%d: SCAP (Software Capture Control)\n", (m_TC3CR & 0x40) ? 1 : 0); + LOG("%d: (invalid)\n", (m_TC3CR & 0x20) ? 1 : 0); + LOG("%d: TC3S (TC3 Start Control)\n", (m_TC3CR & 0x10) ? 1 : 0); + LOG("%d: TC3CK-1 (TC3 Source Clock select)\n", (m_TC3CR & 0x08) ? 1 : 0); + LOG("%d: TC3CK-0 (TC3 Source Clock select)\n", (m_TC3CR & 0x04) ? 1 : 0); + LOG("%d: (invalid)\n", (m_TC3CR & 0x02) ? 1 : 0); + LOG("%d: TC3M (TC3 Mode Select)\n", (m_TC3CR & 0x01) ? 1 : 0); } WRITE8_MEMBER(tlcs870_device::treg3a_w) @@ -433,15 +435,15 @@ WRITE8_MEMBER(tlcs870_device::tc4cr_w) { m_TC4CR = data; - logerror("%s m_TC4CR (8-bit TC4 Timer Control Register) bits set to\n", machine().describe_context()); - logerror("%d: TFF4-1 (Timer F/F 4 Control)\n", (m_TC4CR & 0x80) ? 1 : 0); - logerror("%d: TFF4-0 (Timer F/F 4 Control)\n", (m_TC4CR & 0x40) ? 1 : 0); - logerror("%d: (invalid)\n", (m_TC4CR & 0x20) ? 1 : 0); - logerror("%d: TC4S (TC4 Start Control)\n", (m_TC4CR & 0x10) ? 1 : 0); - logerror("%d: TC4CK-1 (TC4 Source Clock select)\n", (m_TC4CR & 0x08) ? 1 : 0); - logerror("%d: TC4CK-0 (TC4 Source Clock select)\n", (m_TC4CR & 0x04) ? 1 : 0); - logerror("%d: TC4M-1 (TC4 Mode Select)\n", (m_TC4CR & 0x02) ? 1 : 0); - logerror("%d: TC4M-0 (TC4 Mode Select)\n", (m_TC4CR & 0x01) ? 1 : 0); + LOG("%s m_TC4CR (8-bit TC4 Timer Control Register) bits set to\n", machine().describe_context()); + LOG("%d: TFF4-1 (Timer F/F 4 Control)\n", (m_TC4CR & 0x80) ? 1 : 0); + LOG("%d: TFF4-0 (Timer F/F 4 Control)\n", (m_TC4CR & 0x40) ? 1 : 0); + LOG("%d: (invalid)\n", (m_TC4CR & 0x20) ? 1 : 0); + LOG("%d: TC4S (TC4 Start Control)\n", (m_TC4CR & 0x10) ? 1 : 0); + LOG("%d: TC4CK-1 (TC4 Source Clock select)\n", (m_TC4CR & 0x08) ? 1 : 0); + LOG("%d: TC4CK-0 (TC4 Source Clock select)\n", (m_TC4CR & 0x04) ? 1 : 0); + LOG("%d: TC4M-1 (TC4 Mode Select)\n", (m_TC4CR & 0x02) ? 1 : 0); + LOG("%d: TC4M-0 (TC4 Mode Select)\n", (m_TC4CR & 0x01) ? 1 : 0); } WRITE8_MEMBER(tlcs870_device::treg4_w) @@ -457,15 +459,15 @@ WRITE8_MEMBER(tlcs870_device::tbtcr_w) { m_TBTCR = data; - logerror("%s m_TBTCR (Time Base Timer) bits set to\n", machine().describe_context()); - logerror("%d: DV0EN (Divider Output Enable)\n", (m_TBTCR & 0x80) ? 1 : 0); - logerror("%d: DVOCK-1 (Divide Output Frequency Selection)n", (m_TBTCR & 0x40) ? 1 : 0); - logerror("%d: DVOCK-0 (Divide Output Frequency Selection)\n", (m_TBTCR & 0x20) ? 1 : 0); - logerror("%d: DV7CK (?)\n", (m_TBTCR & 0x10) ? 1 : 0); - logerror("%d: TBTEN (Time Base Timer Enable)\n", (m_TBTCR & 0x08) ? 1 : 0); - logerror("%d: TBTCK-2 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x04) ? 1 : 0); - logerror("%d: TBTCK-1 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x02) ? 1 : 0); - logerror("%d: TBTCK-0 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x01) ? 1 : 0); + LOG("%s m_TBTCR (Time Base Timer) bits set to\n", machine().describe_context()); + LOG("%d: DV0EN (Divider Output Enable)\n", (m_TBTCR & 0x80) ? 1 : 0); + LOG("%d: DVOCK-1 (Divide Output Frequency Selection)n", (m_TBTCR & 0x40) ? 1 : 0); + LOG("%d: DVOCK-0 (Divide Output Frequency Selection)\n", (m_TBTCR & 0x20) ? 1 : 0); + LOG("%d: DV7CK (?)\n", (m_TBTCR & 0x10) ? 1 : 0); + LOG("%d: TBTEN (Time Base Timer Enable)\n", (m_TBTCR & 0x08) ? 1 : 0); + LOG("%d: TBTCK-2 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x04) ? 1 : 0); + LOG("%d: TBTCK-1 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x02) ? 1 : 0); + LOG("%d: TBTCK-0 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x01) ? 1 : 0); } READ8_MEMBER(tlcs870_device::tbtcr_r) @@ -482,50 +484,50 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w) { m_SIOCR1[0] = data; - logerror("%s m_SIOCR1[0] (Serial IO Port 1 Control Register 1) bits set to\n", machine().describe_context()); - logerror("%d: SIOS1 (Start/Stop transfer)\n", (m_SIOCR1[0] & 0x80) ? 1 : 0); - logerror("%d: SIOINH1 (Abort/Continue transfer)\n", (m_SIOCR1[0] & 0x40) ? 1 : 0); - logerror("%d: SIOM1-2 (Serial Mode)\n", (m_SIOCR1[0] & 0x20) ? 1 : 0); - logerror("%d: SIOM1-1 (Serial Mode)\n", (m_SIOCR1[0] & 0x10) ? 1 : 0); - logerror("%d: SIOM1-0 (Serial Mode)\n", (m_SIOCR1[0] & 0x08) ? 1 : 0); - logerror("%d: SCK1-2 (Serial Clock)\n", (m_SIOCR1[0] & 0x04) ? 1 : 0); - logerror("%d: SCK1-1 (Serial Clock)\n", (m_SIOCR1[0] & 0x02) ? 1 : 0); - logerror("%d: SCK1-0 (Serial Clock)\n", (m_SIOCR1[0] & 0x01) ? 1 : 0); + LOG("%s m_SIOCR1[0] (Serial IO Port 1 Control Register 1) bits set to\n", machine().describe_context()); + LOG("%d: SIOS1 (Start/Stop transfer)\n", (m_SIOCR1[0] & 0x80) ? 1 : 0); + LOG("%d: SIOINH1 (Abort/Continue transfer)\n", (m_SIOCR1[0] & 0x40) ? 1 : 0); + LOG("%d: SIOM1-2 (Serial Mode)\n", (m_SIOCR1[0] & 0x20) ? 1 : 0); + LOG("%d: SIOM1-1 (Serial Mode)\n", (m_SIOCR1[0] & 0x10) ? 1 : 0); + LOG("%d: SIOM1-0 (Serial Mode)\n", (m_SIOCR1[0] & 0x08) ? 1 : 0); + LOG("%d: SCK1-2 (Serial Clock)\n", (m_SIOCR1[0] & 0x04) ? 1 : 0); + LOG("%d: SCK1-1 (Serial Clock)\n", (m_SIOCR1[0] & 0x02) ? 1 : 0); + LOG("%d: SCK1-0 (Serial Clock)\n", (m_SIOCR1[0] & 0x01) ? 1 : 0); m_transfer_mode[0] = (m_SIOCR1[0] & 0x38) >> 3; switch (m_transfer_mode[0]) { case 0x0: - logerror("(Serial set to 8-bit transmit mode)\n"); + LOG("(Serial set to 8-bit transmit mode)\n"); m_transmit_bits[0] = 8; m_receive_bits[0] = 0; break; case 0x2: - logerror("(Serial set to 4-bit transmit mode)\n"); + LOG("(Serial set to 4-bit transmit mode)\n"); m_transmit_bits[0] = 4; m_receive_bits[0] = 0; break; case 0x4: - logerror("(Serial set to 8-bit transmit/receive mode)\n"); + LOG("(Serial set to 8-bit transmit/receive mode)\n"); m_transmit_bits[0] = 8; m_receive_bits[0] = 8; break; - case 0x5: logerror("(Serial set to 8-bit receive mode)\n"); + case 0x5: LOG("(Serial set to 8-bit receive mode)\n"); m_transmit_bits[0] = 0; m_receive_bits[0] = 8; break; case 0x6: - logerror("(Serial set to 4-bit receive mode)\n"); + LOG("(Serial set to 4-bit receive mode)\n"); m_transmit_bits[0] = 0; m_receive_bits[0] = 4; break; default: - logerror("(Serial set to invalid mode)\n"); + LOG("(Serial set to invalid mode)\n"); m_transmit_bits[0] = 0; m_receive_bits[0] = 0; break; @@ -547,18 +549,18 @@ WRITE8_MEMBER(tlcs870_device::sio1cr2_w) { m_SIOCR2[0] = data; - logerror("%s m_SIOCR2[0] (Serial IO Port 1 Control Register 2) bits set to\n", machine().describe_context()); - logerror("%d: (invalid)\n", (m_SIOCR2[0] & 0x80) ? 1 : 0); - logerror("%d: (invalid)\n", (m_SIOCR2[0] & 0x40) ? 1 : 0); - logerror("%d: (invalid)\n", (m_SIOCR2[0] & 0x20) ? 1 : 0); - logerror("%d: WAIT1-1 (Wait Control\n", (m_SIOCR2[0] & 0x10) ? 1 : 0); - logerror("%d: WAIT1-0 (Wait Control)\n", (m_SIOCR2[0] & 0x08) ? 1 : 0); - logerror("%d: BUF1-2 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x04) ? 1 : 0); - logerror("%d: BUF1-1 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x02) ? 1 : 0); - logerror("%d: BUF1-0 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x01) ? 1 : 0); + LOG("%s m_SIOCR2[0] (Serial IO Port 1 Control Register 2) bits set to\n", machine().describe_context()); + LOG("%d: (invalid)\n", (m_SIOCR2[0] & 0x80) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SIOCR2[0] & 0x40) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SIOCR2[0] & 0x20) ? 1 : 0); + LOG("%d: WAIT1-1 (Wait Control\n", (m_SIOCR2[0] & 0x10) ? 1 : 0); + LOG("%d: WAIT1-0 (Wait Control)\n", (m_SIOCR2[0] & 0x08) ? 1 : 0); + LOG("%d: BUF1-2 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x04) ? 1 : 0); + LOG("%d: BUF1-1 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x02) ? 1 : 0); + LOG("%d: BUF1-0 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x01) ? 1 : 0); m_transfer_numbytes[0] = (m_SIOCR2[0] & 0x7); - logerror("(serial set to transfer %01x bytes)\n", m_transfer_numbytes[0]+1); + LOG("(serial set to transfer %01x bytes)\n", m_transfer_numbytes[0]+1); } @@ -581,7 +583,7 @@ TIMER_CALLBACK_MEMBER(tlcs870_device::sio0_transmit_cb) if (m_transfer_shiftpos[0] == 0) { m_transfer_shiftreg[0] = m_dbr[m_transfer_pos[0]]; - logerror("transmitting byte %02x\n", m_transfer_shiftreg[0]); + LOG("transmitting byte %02x\n", m_transfer_shiftreg[0]); } int dataout = m_transfer_shiftreg[0] & 0x01; @@ -593,14 +595,14 @@ TIMER_CALLBACK_MEMBER(tlcs870_device::sio0_transmit_cb) if (m_transfer_shiftpos[0] == 8) { - logerror("transmitted\n"); + LOG("transmitted\n"); m_transfer_shiftpos[0] = 0; m_transfer_pos[0]++; if (m_transfer_pos[0] > m_transfer_numbytes[0]) { - logerror("end of transmission\n"); + LOG("end of transmission\n"); m_SIOCR1[0] &= ~0x80; // set interrupt latch m_IL |= 1 << (15 - TLCS870_IRQ_INTSIO1); @@ -618,30 +620,30 @@ WRITE8_MEMBER(tlcs870_device::sio2cr1_w) { m_SIOCR1[1] = data; - logerror("%s m_SIOCR1[1] (Serial IO Port 2 Control Register 1) bits set to\n", machine().describe_context()); - logerror("%d: SIOS2 (Start/Stop transfer)\n", (m_SIOCR1[1] & 0x80) ? 1 : 0); - logerror("%d: SIOINH2 (Abort/Continue transfer)\n", (m_SIOCR1[1] & 0x40) ? 1 : 0); - logerror("%d: SIOM2-2 (Serial Mode)\n", (m_SIOCR1[1] & 0x20) ? 1 : 0); - logerror("%d: SIOM2-1 (Serial Mode)\n", (m_SIOCR1[1] & 0x10) ? 1 : 0); - logerror("%d: SIOM2-0 (Serial Mode)\n", (m_SIOCR1[1] & 0x08) ? 1 : 0); - logerror("%d: SCK2-2 (Serial Clock)\n", (m_SIOCR1[1] & 0x04) ? 1 : 0); - logerror("%d: SCK2-1 (Serial Clock)\n", (m_SIOCR1[1] & 0x02) ? 1 : 0); - logerror("%d: SCK2-0 (Serial Clock)\n", (m_SIOCR1[1] & 0x01) ? 1 : 0); + LOG("%s m_SIOCR1[1] (Serial IO Port 2 Control Register 1) bits set to\n", machine().describe_context()); + LOG("%d: SIOS2 (Start/Stop transfer)\n", (m_SIOCR1[1] & 0x80) ? 1 : 0); + LOG("%d: SIOINH2 (Abort/Continue transfer)\n", (m_SIOCR1[1] & 0x40) ? 1 : 0); + LOG("%d: SIOM2-2 (Serial Mode)\n", (m_SIOCR1[1] & 0x20) ? 1 : 0); + LOG("%d: SIOM2-1 (Serial Mode)\n", (m_SIOCR1[1] & 0x10) ? 1 : 0); + LOG("%d: SIOM2-0 (Serial Mode)\n", (m_SIOCR1[1] & 0x08) ? 1 : 0); + LOG("%d: SCK2-2 (Serial Clock)\n", (m_SIOCR1[1] & 0x04) ? 1 : 0); + LOG("%d: SCK2-1 (Serial Clock)\n", (m_SIOCR1[1] & 0x02) ? 1 : 0); + LOG("%d: SCK2-0 (Serial Clock)\n", (m_SIOCR1[1] & 0x01) ? 1 : 0); } WRITE8_MEMBER(tlcs870_device::sio2cr2_w) { m_SIOCR2[1] = data; - logerror("%s m_SIOCR2[1] (Serial IO Port 2 Control Register 2) bits set to\n", machine().describe_context()); - logerror("%d: (invalid)\n", (m_SIOCR2[1] & 0x80) ? 1 : 0); - logerror("%d: (invalid)\n", (m_SIOCR2[1] & 0x40) ? 1 : 0); - logerror("%d: (invalid)\n", (m_SIOCR2[1] & 0x20) ? 1 : 0); - logerror("%d: WAIT2-1 (Wait Control\n", (m_SIOCR2[1] & 0x10) ? 1 : 0); - logerror("%d: WAIT2-0 (Wait Control)\n", (m_SIOCR2[1] & 0x08) ? 1 : 0); - logerror("%d: BUF2-2 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x04) ? 1 : 0); - logerror("%d: BUF2-1 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x02) ? 1 : 0); - logerror("%d: BUF2-0 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x01) ? 1 : 0); + LOG("%s m_SIOCR2[1] (Serial IO Port 2 Control Register 2) bits set to\n", machine().describe_context()); + LOG("%d: (invalid)\n", (m_SIOCR2[1] & 0x80) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SIOCR2[1] & 0x40) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SIOCR2[1] & 0x20) ? 1 : 0); + LOG("%d: WAIT2-1 (Wait Control\n", (m_SIOCR2[1] & 0x10) ? 1 : 0); + LOG("%d: WAIT2-0 (Wait Control)\n", (m_SIOCR2[1] & 0x08) ? 1 : 0); + LOG("%d: BUF2-2 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x04) ? 1 : 0); + LOG("%d: BUF2-1 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x02) ? 1 : 0); + LOG("%d: BUF2-0 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x01) ? 1 : 0); } TIMER_CALLBACK_MEMBER(tlcs870_device::sio1_transmit_cb) @@ -665,15 +667,15 @@ WRITE8_MEMBER(tlcs870_device::wdtcr1_w) { m_WDTCR1 = data; - logerror("%s m_WDTCR1 (Watchdog Timer Control 1) bits set to\n", machine().describe_context()); - logerror("%d: (invalid)\n", (m_WDTCR1 & 0x80) ? 1 : 0); - logerror("%d: (invalid)\n", (m_WDTCR1 & 0x40) ? 1 : 0); - logerror("%d: (invalid)\n", (m_WDTCR1 & 0x20) ? 1 : 0); - logerror("%d: (invalid)\n", (m_WDTCR1 & 0x10) ? 1 : 0); - logerror("%d: WDTEN (Watchdog Timer Enable, also req disable code to WDTCR2)\n", (m_WDTCR1 & 0x08) ? 1 : 0); - logerror("%d: WDTT-1 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x04) ? 1 : 0); - logerror("%d: WDTT-0 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x02) ? 1 : 0); - logerror("%d: WDTOUT (Watchdog Timer Output select, 0 = interrupt, 1 = reset out)\n",(m_WDTCR1 & 0x01) ? 1 : 0); + LOG("%s m_WDTCR1 (Watchdog Timer Control 1) bits set to\n", machine().describe_context()); + LOG("%d: (invalid)\n", (m_WDTCR1 & 0x80) ? 1 : 0); + LOG("%d: (invalid)\n", (m_WDTCR1 & 0x40) ? 1 : 0); + LOG("%d: (invalid)\n", (m_WDTCR1 & 0x20) ? 1 : 0); + LOG("%d: (invalid)\n", (m_WDTCR1 & 0x10) ? 1 : 0); + LOG("%d: WDTEN (Watchdog Timer Enable, also req disable code to WDTCR2)\n", (m_WDTCR1 & 0x08) ? 1 : 0); + LOG("%d: WDTT-1 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x04) ? 1 : 0); + LOG("%d: WDTT-0 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x02) ? 1 : 0); + LOG("%d: WDTOUT (Watchdog Timer Output select, 0 = interrupt, 1 = reset out)\n",(m_WDTCR1 & 0x01) ? 1 : 0); // WDTOUT cannot be set to 1 by software } @@ -689,7 +691,7 @@ WRITE8_MEMBER(tlcs870_device::wdtcr2_w) // disable code if (!(m_WDTCR1 & 0x08)) { - logerror("%s wdtcr2_w - Watchdog disabled\n", machine().describe_context()); + LOG("%s wdtcr2_w - Watchdog disabled\n", machine().describe_context()); } } } @@ -701,30 +703,30 @@ WRITE8_MEMBER(tlcs870_device::syscr1_w) { m_SYSCR1 = data; - logerror("%s m_SYSCR1 (System Control Register 1) bits set to\n", machine().describe_context()); - logerror("%d: STOP (STOP mode start)\n", (m_SYSCR1 & 0x80) ? 1 : 0); - logerror("%d: RELM (release method for STOP, 0 edge, 1 level)\n", (m_SYSCR1 & 0x40) ? 1 : 0); - logerror("%d: RETM (return mode after STOP, 0 normal, 1 slow)\n", (m_SYSCR1 & 0x20) ? 1 : 0); - logerror("%d: OUTEN (port output control during STOP)\n", (m_SYSCR1 & 0x10) ? 1 : 0); - logerror("%d: WUT-1 (warm up time at STOP release)\n", (m_SYSCR1 & 0x08) ? 1 : 0); - logerror("%d: WUT-0 (warm up time at STOP release)\n", (m_SYSCR1 & 0x04) ? 1 : 0); - logerror("%d: (invalid)\n", (m_SYSCR1 & 0x02) ? 1 : 0); - logerror("%d: (invalid)\n", (m_SYSCR1 & 0x01) ? 1 : 0); + LOG("%s m_SYSCR1 (System Control Register 1) bits set to\n", machine().describe_context()); + LOG("%d: STOP (STOP mode start)\n", (m_SYSCR1 & 0x80) ? 1 : 0); + LOG("%d: RELM (release method for STOP, 0 edge, 1 level)\n", (m_SYSCR1 & 0x40) ? 1 : 0); + LOG("%d: RETM (return mode after STOP, 0 normal, 1 slow)\n", (m_SYSCR1 & 0x20) ? 1 : 0); + LOG("%d: OUTEN (port output control during STOP)\n", (m_SYSCR1 & 0x10) ? 1 : 0); + LOG("%d: WUT-1 (warm up time at STOP release)\n", (m_SYSCR1 & 0x08) ? 1 : 0); + LOG("%d: WUT-0 (warm up time at STOP release)\n", (m_SYSCR1 & 0x04) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SYSCR1 & 0x02) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SYSCR1 & 0x01) ? 1 : 0); } WRITE8_MEMBER(tlcs870_device::syscr2_w) { m_SYSCR2 = data; - logerror("%s m_SYSCR2 (System Control Register 2) bits set to\n", machine().describe_context()); - logerror("%d: XEN (High Frequency Oscillator control)\n", (m_SYSCR2 & 0x80) ? 1 : 0); - logerror("%d: XTEN (Low Frequency Oscillator control)\n", (m_SYSCR2 & 0x40) ? 1 : 0); - logerror("%d: SYSCK (system clock select 0 high, 1 low)\n", (m_SYSCR2 & 0x20) ? 1 : 0); - logerror("%d: IDLE (IDLE mode start)\n", (m_SYSCR2 & 0x10) ? 1 : 0); // hng64 sets this in case of ram test failures - logerror("%d: (invalid)\n", (m_SYSCR2 & 0x08) ? 1 : 0); - logerror("%d: (invalid)\n", (m_SYSCR2 & 0x04) ? 1 : 0); - logerror("%d: (invalid)\n", (m_SYSCR2 & 0x02) ? 1 : 0); - logerror("%d: (invalid)\n", (m_SYSCR2 & 0x01) ? 1 : 0); + LOG("%s m_SYSCR2 (System Control Register 2) bits set to\n", machine().describe_context()); + LOG("%d: XEN (High Frequency Oscillator control)\n", (m_SYSCR2 & 0x80) ? 1 : 0); + LOG("%d: XTEN (Low Frequency Oscillator control)\n", (m_SYSCR2 & 0x40) ? 1 : 0); + LOG("%d: SYSCK (system clock select 0 high, 1 low)\n", (m_SYSCR2 & 0x20) ? 1 : 0); + LOG("%d: IDLE (IDLE mode start)\n", (m_SYSCR2 & 0x10) ? 1 : 0); // hng64 sets this in case of ram test failures + LOG("%d: (invalid)\n", (m_SYSCR2 & 0x08) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SYSCR2 & 0x04) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SYSCR2 & 0x02) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SYSCR2 & 0x01) ? 1 : 0); } READ8_MEMBER(tlcs870_device::syscr1_r) @@ -803,15 +805,15 @@ WRITE8_MEMBER(tlcs870_device::eintcr_w) { m_EINTCR = data; - logerror("%s m_EINTCR (External Interrupt Control) bits set to\n", machine().describe_context()); - logerror("%d: INT1NC (Interrupt noise reject)\n", (m_EINTCR & 0x80) ? 1 : 0); - logerror("%d: INT0EN (Interrupt 0 enable)\n", (m_EINTCR & 0x40) ? 1 : 0); - logerror("%d: (invalid)\n", (m_EINTCR & 0x20) ? 1 : 0); - logerror("%d: INT4ES (edge select)\n", (m_EINTCR & 0x10) ? 1 : 0); - logerror("%d: INT3ES (edge select)\n", (m_EINTCR & 0x08) ? 1 : 0); - logerror("%d: INT2ES (edge select)\n", (m_EINTCR & 0x04) ? 1 : 0); - logerror("%d: INT1ES (edge select)\n", (m_EINTCR & 0x02) ? 1 : 0); - logerror("%d: (invalid)\n", (m_EINTCR & 0x01) ? 1 : 0); + LOG("%s m_EINTCR (External Interrupt Control) bits set to\n", machine().describe_context()); + LOG("%d: INT1NC (Interrupt noise reject)\n", (m_EINTCR & 0x80) ? 1 : 0); + LOG("%d: INT0EN (Interrupt 0 enable)\n", (m_EINTCR & 0x40) ? 1 : 0); + LOG("%d: (invalid)\n", (m_EINTCR & 0x20) ? 1 : 0); + LOG("%d: INT4ES (edge select)\n", (m_EINTCR & 0x10) ? 1 : 0); + LOG("%d: INT3ES (edge select)\n", (m_EINTCR & 0x08) ? 1 : 0); + LOG("%d: INT2ES (edge select)\n", (m_EINTCR & 0x04) ? 1 : 0); + LOG("%d: INT1ES (edge select)\n", (m_EINTCR & 0x02) ? 1 : 0); + LOG("%d: (invalid)\n", (m_EINTCR & 0x01) ? 1 : 0); /* For edge select register 0 = rising edge, 1 = falling edge @@ -834,30 +836,30 @@ WRITE8_MEMBER(tlcs870_device::eir_l_w) { m_EIR = (m_EIR & 0xff00) | data; - logerror("%s m_EIR(LSB) (Interrupt Enable) bits set to\n", machine().describe_context()); - logerror("%d: EF7 (External Interrupt 2)\n", (m_EIR & 0x0080) ? 1 : 0); - logerror("%d: EF6 (Time Base Timer Interrupt)\n", (m_EIR & 0x0040) ? 1 : 0); - logerror("%d: EF5 (External Interrupt 1)\n", (m_EIR & 0x0020) ? 1 : 0); - logerror("%d: EF4 (16-bit TC1 Interrupt)\n", (m_EIR & 0x0010) ? 1 : 0); - logerror("%d: (invalid)\n", (m_EIR & 0x0008) ? 1 : 0); // can't be External Int 0 (bit in different register is used) - logerror("%d: (invalid)\n", (m_EIR & 0x0004) ? 1 : 0); // can't be Watchdog interrupt (non-maskable) - logerror("%d: (invalid)\n", (m_EIR & 0x0002) ? 1 : 0); // can't be Software interrupt (non-maskable) - logerror("%d: IMF\n", (m_EIR & 0x0001) ? 1 : 0); // can't be Reset interrupt (non-maskable) + LOG("%s m_EIR(LSB) (Interrupt Enable) bits set to\n", machine().describe_context()); + LOG("%d: EF7 (External Interrupt 2)\n", (m_EIR & 0x0080) ? 1 : 0); + LOG("%d: EF6 (Time Base Timer Interrupt)\n", (m_EIR & 0x0040) ? 1 : 0); + LOG("%d: EF5 (External Interrupt 1)\n", (m_EIR & 0x0020) ? 1 : 0); + LOG("%d: EF4 (16-bit TC1 Interrupt)\n", (m_EIR & 0x0010) ? 1 : 0); + LOG("%d: (invalid)\n", (m_EIR & 0x0008) ? 1 : 0); // can't be External Int 0 (bit in different register is used) + LOG("%d: (invalid)\n", (m_EIR & 0x0004) ? 1 : 0); // can't be Watchdog interrupt (non-maskable) + LOG("%d: (invalid)\n", (m_EIR & 0x0002) ? 1 : 0); // can't be Software interrupt (non-maskable) + LOG("%d: IMF\n", (m_EIR & 0x0001) ? 1 : 0); // can't be Reset interrupt (non-maskable) } WRITE8_MEMBER(tlcs870_device::eir_h_w) { m_EIR = (m_EIR & 0x00ff) | (data << 8); - logerror("%s m_EIR(MSB) (Interrupt Enable) bits set to\n", machine().describe_context()); - logerror("%d: EF15 (External Interrupt 5)\n", (m_EIR & 0x8000) ? 1 : 0); - logerror("%d: EF14 (16-bit TC2 Interrupt)\n", (m_EIR & 0x4000) ? 1 : 0); - logerror("%d: EF13 (Serial Interface 2 Interrupt)\n", (m_EIR & 0x2000) ? 1 : 0); - logerror("%d: EF12 (External Interrupt 4)\n", (m_EIR & 0x1000) ? 1 : 0); - logerror("%d: EF11 (External Interrupt 3)\n", (m_EIR & 0x0800) ? 1 : 0); - logerror("%d: EF10 (8-bit TC4 Interrupt)\n", (m_EIR & 0x0400) ? 1 : 0); - logerror("%d: EF9 (Serial Interface 1 Interrupt)\n", (m_EIR & 0x0200) ? 1 : 0); - logerror("%d: EF8 (8-bit TC3 Interrupt)\n", (m_EIR & 0x0100) ? 1 : 0); + LOG("%s m_EIR(MSB) (Interrupt Enable) bits set to\n", machine().describe_context()); + LOG("%d: EF15 (External Interrupt 5)\n", (m_EIR & 0x8000) ? 1 : 0); + LOG("%d: EF14 (16-bit TC2 Interrupt)\n", (m_EIR & 0x4000) ? 1 : 0); + LOG("%d: EF13 (Serial Interface 2 Interrupt)\n", (m_EIR & 0x2000) ? 1 : 0); + LOG("%d: EF12 (External Interrupt 4)\n", (m_EIR & 0x1000) ? 1 : 0); + LOG("%d: EF11 (External Interrupt 3)\n", (m_EIR & 0x0800) ? 1 : 0); + LOG("%d: EF10 (8-bit TC4 Interrupt)\n", (m_EIR & 0x0400) ? 1 : 0); + LOG("%d: EF9 (Serial Interface 1 Interrupt)\n", (m_EIR & 0x0200) ? 1 : 0); + LOG("%d: EF8 (8-bit TC3 Interrupt)\n", (m_EIR & 0x0100) ? 1 : 0); } /* @@ -928,7 +930,7 @@ void tlcs870_device::execute_set_input(int inputnum, int state) void tlcs870_device::set_irq_line(int irqline, int state) { - //logerror("set_irq_line %d %d\n", irqline, state); + //LOG("set_irq_line %d %d\n", irqline, state); if (!(m_irqstate & (1 << irqline))) { @@ -982,7 +984,7 @@ void tlcs870_device::take_interrupt(int priority) { m_IL &= ~(1< m_ram; }; +// ======================> mb8421_device + +class idt71321_device : public mb8421_device +{ +public: + idt71321_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock = 0); +}; + // ======================> mb8421_mb8431_16_device class mb8421_mb8431_16_device : public mb8421_master_device @@ -145,6 +155,7 @@ private: // device type definition DECLARE_DEVICE_TYPE(MB8421, mb8421_device) +DECLARE_DEVICE_TYPE(IDT71321, idt71321_device) DECLARE_DEVICE_TYPE(MB8421_MB8431_16BIT, mb8421_mb8431_16_device) #endif // MAME_MACHINE_MB8421_H diff --git a/src/mame/drivers/hng64.cpp b/src/mame/drivers/hng64.cpp index 1d51b593080..da62725d74b 100644 --- a/src/mame/drivers/hng64.cpp +++ b/src/mame/drivers/hng64.cpp @@ -30,10 +30,8 @@ Notes: * The Japanese text on the Roads Edge network screen says : "waiting to connect network... please wait without touching machine" * Xrally and Roads Edge have a symbols table at respectively 0xb2f30 and 0xe10c0 - Also, to enter into service mode you need to change value of 0xa2363 / 0xcfb53 to 1 during gameplay (of course, if you put into free play mode games are playable) ToDo: - * Buriki One / Xrally and Roads Edge doesn't coin it up, irq issue? * Sprite garbage in Beast Busters 2nd Nightmare, another irq issue? * Samurai Shodown 64 2 puts "Press 1p & 2p button" msg in gameplay, known to be a MCU simulation issue, i/o port 4 doesn't seem to be just an input port but controls program flow too. @@ -59,11 +57,11 @@ ToDo: Other: * Translate KL5C80 docs and finish up the implementation * Figure out what IO $54 & $72 are on the communications CPU - * Hook up CPU2 (v30 based?) no rom? (maybe its the 'sound driver' the game uploads?) - * Add sound + * Fix sound * Backup ram etc. * Correct cpu speed - * What is ROM1? Data for the KL5C80? There's plenty of physical space to map it to. + * How to use the FPGA data ('ROM1') + */ /* @@ -107,7 +105,7 @@ No. PCB Label IC Markings IC Package 06 ASIC10 NEO64-SCC QFP208 07 CPU1 NEC D30200GD-100 VR4300 QFP120 08 CPU3 KL5C80A12CFP QFP80 -09 DPRAM1 DT7133 LA35J PLCC68 +09 DPRAM1* IDT7133 LA35J PLCC68 10 DSP1 L7A1045 L6028 DSP-A QFP120 11 FPGA1 ALTERA EPF10K10QC208-4 QFP208 12 FROM1 MBM29F400B-12 TSOP48 (archived as FROM1.BIN) @@ -124,6 +122,10 @@ No. PCB Label IC Markings IC Package 23 ROM1 ALTERA EPC1PC8 DIP8 (130817 bytes, archived as ROM1.BIN) 24 SRAM5 TC55257DFL-85L SOP28 + * The IDT 7133 / 7143 lack interrupts and just act as 0x1000 bytes (2x 0x800 16-bit words) of RAM + IDT 7133 - 32K (2K X 16 Bit) MASTER Dual-Port SRAM + IDT 7143 - 32K (2K X 16 Bit) SLAVE Dual-Port SRAM + PCB Layout (Bottom) @@ -188,7 +190,7 @@ LVS-JAM SNK 1999.1.20 No. PCB Label IC Markings IC Package ---------------------------------------------------- -01 DPRAM1 DT 71321 LA55PF QFP64 * +01 DPRAM1 IDT 71321 LA55PF QFP64 * 02 IC1 MC44200FT QFP44 03 IOCTR1 TOSHIBA TMP87CH40N-4828 SDIP64 04 BACKUP EPSON RTC62423 SOP24 @@ -445,6 +447,8 @@ or Fatal Fury for example). #include "cpu/z80/z80.h" #include "machine/nvram.h" +#define VERBOSE 1 +#include "logmacro.h" /* TODO: NOT measured! */ #define PIXEL_CLOCK ((HNG64_MASTER_CLOCK*2)/4) // x 2 is due of the interlaced screen ... @@ -458,28 +462,17 @@ or Fatal Fury for example). #define VBSTART (224*2) -#ifdef UNUSED_FUNCTION -WRITE32_MEMBER(hng64_state::trap_write) -{ - logerror("Remapped write... %08x %08x\n",offset,data); -} - -READ32_MEMBER(hng64_state::hng64_random_read) -{ - return machine().rand()&0xffffffff; -} -#endif READ32_MEMBER(hng64_state::hng64_com_r) { - //logerror("com read (PC=%08x): %08x %08x = %08x\n", m_maincpu->pc(), (offset*4)+0xc0000000, mem_mask, m_com_ram[offset]); - return m_com_ram[offset]; + //LOG("com read (PC=%08x): %08x %08x = %08x\n", m_maincpu->pc(), (offset*4)+0xc0000000, mem_mask, m_idt7133_dpram[offset]); + return m_idt7133_dpram[offset]; } WRITE32_MEMBER(hng64_state::hng64_com_w) { - //logerror("com write (PC=%08x): %08x %08x = %08x\n", m_maincpu->pc(), (offset*4)+0xc0000000, mem_mask, data); - COMBINE_DATA(&m_com_ram[offset]); + //LOG("com write (PC=%08x): %08x %08x = %08x\n", m_maincpu->pc(), (offset*4)+0xc0000000, mem_mask, data); + COMBINE_DATA(&m_idt7133_dpram[offset]); } /* TODO: fully understand this */ @@ -531,11 +524,11 @@ READ32_MEMBER(hng64_state::hng64_sysregs_r) //case 0x106c: //case 0x107c: case 0x1084: - logerror("%s: HNG64 reading MCU status port (%08x)\n", machine().describe_context(), mem_mask); + LOG("%s: HNG64 reading MCU status port (%08x)\n", machine().describe_context(), mem_mask); return 0x00000002; //MCU->MIPS latch port //case 0x108c: case 0x1104: - logerror("%s: irq level READ %04x\n", machine().describe_context(),m_irq_level); + LOG("%s: irq level READ %04x\n", machine().describe_context(),m_irq_level); return m_irq_level; case 0x111c: //printf("Read to IRQ ACK?\n"); @@ -597,7 +590,7 @@ WRITE32_MEMBER(hng64_state::hng64_sysregs_w) { case 0x1084: //MIPS->MCU latch port m_mcu_en = (data & 0xff); //command-based, i.e. doesn't control halt line and such? - logerror("%s: HNG64 writing to MCU control port %08x (%08x)\n", machine().describe_context(), data, mem_mask); + LOG("%s: HNG64 writing to MCU control port %08x (%08x)\n", machine().describe_context(), data, mem_mask); break; //0x110c global irq mask? /* irq ack */ @@ -610,12 +603,12 @@ WRITE32_MEMBER(hng64_state::hng64_sysregs_w) break; case 0x21c4: // guess, written after a write to 0x00 in dpram, which is where the command goes, and the IRQ onthe MCU reads the command - logerror("%s: HNG64 writing to SYSTEM Registers %08x %08x (%08x) (IO MCU IRQ TRIGGER?)\n", machine().describe_context(), offset*4, data, mem_mask); + LOG("%s: HNG64 writing to SYSTEM Registers %08x %08x (%08x) (IO MCU IRQ TRIGGER?)\n", machine().describe_context(), offset*4, data, mem_mask); if (mem_mask & 0xffff0000) m_tempio_irqon_timer->adjust(attotime::zero); break; default: - logerror("%s: HNG64 writing to SYSTEM Registers %08x %08x (%08x)\n", machine().describe_context(), offset*4, data, mem_mask); + LOG("%s: HNG64 writing to SYSTEM Registers %08x %08x (%08x)\n", machine().describe_context(), offset*4, data, mem_mask); } } @@ -627,7 +620,7 @@ WRITE32_MEMBER(hng64_state::hng64_sysregs_w) READ8_MEMBER(hng64_state::hng64_dualport_r) { - logerror("%s: dualport R %04x\n", machine().describe_context(), offset); + LOG("%s: dualport R %04x\n", machine().describe_context(), offset); /* I'm not really convinced these are commands in this sense based on code analysis, probably just a non-standard way of controlling the lines @@ -648,7 +641,7 @@ READ8_MEMBER(hng64_state::hng64_dualport_r) } } - return m_dt7133_dpram->right_r(space, offset); + return m_dt71321_dpram->right_r(space, offset); } /* @@ -679,8 +672,8 @@ Beast Busters 2 outputs (all at offset == 0x1c): WRITE8_MEMBER(hng64_state::hng64_dualport_w) { - m_dt7133_dpram->right_w(space,offset, data); - logerror("%s: dualport WRITE %04x %02x\n", machine().describe_context(), offset, data); + m_dt71321_dpram->right_w(space,offset, data); + LOG("%s: dualport WRITE %04x %02x\n", machine().describe_context(), offset, data); } @@ -891,7 +884,7 @@ void hng64_state::hng_map(address_map &map) // Communications map(0xc0000000, 0xc0000fff).rw(FUNC(hng64_state::hng64_com_r), FUNC(hng64_state::hng64_com_w)).share("com_ram"); - map(0xc0001000, 0xc0001007).rw(FUNC(hng64_state::hng64_com_share_mips_r), FUNC(hng64_state::hng64_com_share_mips_w)); + map(0xc0001000, 0xc0001007).ram().share("comhack");//.rw(FUNC(hng64_state::hng64_com_share_mips_r), FUNC(hng64_state::hng64_com_share_mips_w)); /* 6e000000-6fffffff */ /* 80000000-81ffffff */ @@ -1129,16 +1122,16 @@ static INPUT_PORTS_START( hng64_fight ) PORT_INCLUDE( hng64 ) PORT_MODIFY("IN0") - PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNKNOWN ) + PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_MODIFY("IN1") - PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNKNOWN ) + PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_MODIFY("IN2") - PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNKNOWN ) + PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_MODIFY("IN3") - PORT_BIT( 0xff, IP_ACTIVE_HIGH, IPT_UNKNOWN ) + PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_MODIFY("IN4") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1) @@ -1269,7 +1262,7 @@ static INPUT_PORTS_START( hng64_shoot ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE3 ) PORT_SERVICE_NO_TOGGLE(0x80, IP_ACTIVE_LOW) - PORT_MODIFY("IN3") // Debug Port? + PORT_MODIFY("IN3") // Debug Port? - there are inputs to pause game, bring up a test menu, move the camera around etc. PORT_DIPNAME( 0x01, 0x01, "DEBUG" ) PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) @@ -1778,10 +1771,19 @@ void hng64_state::machine_start() } m_3dfifo_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hng64_state::hng64_3dfifo_processed), this)); + m_comhack_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hng64_state::comhack_callback), this)); init_io(); } +TIMER_CALLBACK_MEMBER(hng64_state::comhack_callback) +{ + printf("comhack_callback %04x\n\n", m_comhack[0]); + + m_comhack[0] = m_comhack[0] | 0x0002; +} + + void hng64_state::machine_reset() { /* For simulate MCU stepping */ @@ -1789,6 +1791,9 @@ void hng64_state::machine_reset() reset_net(); reset_sound(); + + // on real hardware, even with no network, it takes until the counter reaches about 37 (Xtreme Rally) to boot, this kicks in at around 7 + m_comhack_timer->adjust(m_maincpu->cycles_to_attotime(400000000)); } /*********************************************** @@ -1801,7 +1806,7 @@ void hng64_state::machine_reset() WRITE8_MEMBER(hng64_state::ioport1_w) { - logerror("%s: ioport1_w %02x\n", machine().describe_context(), data); + LOG("%s: ioport1_w %02x\n", machine().describe_context(), data); /* Port bits @@ -1824,14 +1829,14 @@ WRITE8_MEMBER(hng64_state::ioport3_w) { int addr = (m_port1&0xe0)>>5; - logerror("%s: ioport3_w %02x (to address %02x) (other bits of m_port1 %02x)\n", machine().describe_context(), data, addr, m_port1 & 0x1f); + LOG("%s: ioport3_w %02x (to address %02x) (other bits of m_port1 %02x)\n", machine().describe_context(), data, addr, m_port1 & 0x1f); } READ8_MEMBER(hng64_state::ioport3_r) { int addr = (m_port1&0xe0)>>5; - //logerror("%s: ioport3_r (from address %02x) (other bits of m_port1 %02x)\n", machine().describe_context(), addr, m_port1 & 0x1f); + //LOG("%s: ioport3_r (from address %02x) (other bits of m_port1 %02x)\n", machine().describe_context(), addr, m_port1 & 0x1f); return m_intest[addr]->read(); } @@ -1861,13 +1866,13 @@ WRITE8_MEMBER(hng64_state::ioport7_w) */ - //logerror("%s: ioport7_w %02x\n", machine().describe_context(), data); + //LOG("%s: ioport7_w %02x\n", machine().describe_context(), data); m_ex_ramaddr_upper = (data & 0x0c) >> 2; if ((!(data & 0x80)) && (m_port7 & 0x80)) { - logerror("%s: MCU request MIPS IRQ?\n", machine().describe_context()); + LOG("%s: MCU request MIPS IRQ?\n", machine().describe_context()); set_irq(0x00020000); } @@ -1888,18 +1893,18 @@ WRITE8_MEMBER(hng64_state::ioport7_w) READ8_MEMBER(hng64_state::ioport0_r) { uint16_t addr = (m_ex_ramaddr | (m_ex_ramaddr_upper<<9)) & 0x7ff; - uint8_t ret = m_dt7133_dpram->left_r(space, addr); + uint8_t ret = m_dt71321_dpram->left_r(space, addr); - logerror("%s: ioport0_r %02x (from address %04x)\n", machine().describe_context(), ret, addr); + LOG("%s: ioport0_r %02x (from address %04x)\n", machine().describe_context(), ret, addr); return ret; } WRITE8_MEMBER(hng64_state::ioport0_w) { uint16_t addr = (m_ex_ramaddr | (m_ex_ramaddr_upper<<9)) & 0x7ff; - m_dt7133_dpram->left_w(space, addr, data); + m_dt71321_dpram->left_w(space, addr, data); - logerror("%s: ioport0_w %02x (to address %04x)\n", machine().describe_context(), data, addr); + LOG("%s: ioport0_w %02x (to address %04x)\n", machine().describe_context(), data, addr); } @@ -1914,7 +1919,7 @@ WRITE8_MEMBER(hng64_state::ioport0_w) */ WRITE8_MEMBER(hng64_state::ioport4_w) { - logerror("%s: ioport4_w %02x\n", machine().describe_context(), data); + LOG("%s: ioport4_w %02x\n", machine().describe_context(), data); } /*********************************************** @@ -1955,17 +1960,18 @@ WRITE_LINE_MEMBER( hng64_state::sio0_w ) TIMER_CALLBACK_MEMBER(hng64_state::tempio_irqon_callback) { - logerror("timer_hack_on\n"); + LOG("timer_hack_on\n"); m_iomcu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE ); m_tempio_irqoff_timer->adjust(m_maincpu->cycles_to_attotime(1000)); } TIMER_CALLBACK_MEMBER(hng64_state::tempio_irqoff_callback) { - logerror("timer_hack_off\n"); + LOG("timer_hack_off\n"); m_iomcu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE ); } + void hng64_state::init_io() { m_tempio_irqon_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hng64_state::tempio_irqon_callback), this)); @@ -2032,7 +2038,7 @@ MACHINE_CONFIG_START(hng64_state::hng64) iomcu.serial0_out_cb().set(FUNC(hng64_state::sio0_w)); //iomcu.serial1_out_cb().set(FUNC(hng64_state::sio1_w)); // not initialized / used - MCFG_DEVICE_ADD("dt7133_dpram", MB8421, 0) + MCFG_DEVICE_ADD("dt71321_dpram", IDT71321, 0) //MCFG_MB8421_INTL_AN0R(INPUTLINE("xxx", 0)) // I don't think the IRQs are connected MACHINE_CONFIG_END diff --git a/src/mame/includes/hng64.h b/src/mame/includes/hng64.h index 777c273ff35..1c3792ec014 100644 --- a/src/mame/includes/hng64.h +++ b/src/mame/includes/hng64.h @@ -136,7 +136,7 @@ public: m_maincpu(*this, "maincpu"), m_audiocpu(*this, "audiocpu"), m_iomcu(*this, "iomcu"), - m_dt7133_dpram(*this, "dt7133_dpram"), + m_dt71321_dpram(*this, "dt71321_dpram"), m_dsp(*this, "l7a1045"), m_comm(*this, "network"), m_rtc(*this, "rtc"), @@ -150,9 +150,10 @@ public: m_videoregs(*this, "videoregs"), m_tcram(*this, "tcram"), m_3dregs(*this, "3dregs"), + m_comhack(*this, "comhack"), m_3d_1(*this, "3d_1"), m_3d_2(*this, "3d_2"), - m_com_ram(*this, "com_ram"), + m_idt7133_dpram(*this, "com_ram"), m_gfxdecode(*this, "gfxdecode"), m_intest(*this, "IN%u", 0U), m_samsho64_3d_hack(0) @@ -174,7 +175,7 @@ private: required_device m_maincpu; required_device m_audiocpu; required_device m_iomcu; - required_device m_dt7133_dpram; + required_device m_dt71321_dpram; required_device m_dsp; required_device m_comm; required_device m_rtc; @@ -191,10 +192,11 @@ private: std::unique_ptr m_dl; required_shared_ptr m_3dregs; + required_shared_ptr m_comhack; required_shared_ptr m_3d_1; required_shared_ptr m_3d_2; - required_shared_ptr m_com_ram; + required_shared_ptr m_idt7133_dpram; //required_shared_ptr m_com_mmu_mem; required_device m_gfxdecode; @@ -340,6 +342,10 @@ private: uint16_t m_mmub[6]; uint8_t read_comm_data(uint32_t offset); void write_comm_data(uint32_t offset,uint8_t data); + TIMER_CALLBACK_MEMBER(comhack_callback); + emu_timer *m_comhack_timer; + + int m_irq_level; TILE_GET_INFO_MEMBER(get_hng64_tile0_8x8_info); TILE_GET_INFO_MEMBER(get_hng64_tile0_16x16_info);