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Convert ADSP21xx core to a modern CPU device.

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This commit is contained in:
Aaron Giles 2010-09-09 08:13:58 +00:00
parent dbd3f07184
commit 83a2fa7ba0
9 changed files with 2768 additions and 2489 deletions
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1384
src/emu/cpu/adsp2100/2100ops.c
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3102
src/emu/cpu/adsp2100/adsp2100.c
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641
src/emu/cpu/adsp2100/adsp2100.h
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@ -1,8 +1,39 @@
/*************************************************************************** /***************************************************************************
ADSP2100.h adsp2100.h
Interface file for the portable Analog ADSP-2100 emulator.
Written by Aaron Giles ADSP-21xx series emulator.
****************************************************************************
Copyright Aaron Giles
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name 'MAME' nor the names of its contributors may be
used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY AARON GILES ''AS IS'' AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL AARON GILES BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
***************************************************************************/ ***************************************************************************/
@ -12,31 +43,502 @@
#define __ADSP2100_H__ #define __ADSP2100_H__
/*************************************************************************** //**************************************************************************
TYPE DEFINITIONS // DEBUGGING
***************************************************************************/ //**************************************************************************
DECLARE_LEGACY_CPU_DEVICE(ADSP2100, adsp2100); #define ADSP_TRACK_HOTSPOTS 0
DECLARE_LEGACY_CPU_DEVICE(ADSP2101, adsp2101);
DECLARE_LEGACY_CPU_DEVICE(ADSP2104, adsp2104);
DECLARE_LEGACY_CPU_DEVICE(ADSP2105, adsp2105);
DECLARE_LEGACY_CPU_DEVICE(ADSP2115, adsp2115);
DECLARE_LEGACY_CPU_DEVICE(ADSP2181, adsp2181);
/* transmit and receive data callbacks types */
typedef INT32 (*adsp21xx_rx_func)(cpu_device &device, int port);
typedef void (*adsp21xx_tx_func)(cpu_device &device, int port, INT32 data); //**************************************************************************
typedef void (*adsp21xx_timer_func)(cpu_device &device, int enable); // INTERFACE CONFIGURATION MACROS
//**************************************************************************
#define MDRV_ADSP21XX_CONFIG(_config) \
adsp21xx_device_config::static_set_config(device, _config); \
//**************************************************************************
// GLOBAL VARIABLES
//**************************************************************************
// device type definition
extern const device_type ADSP2100;
extern const device_type ADSP2101;
extern const device_type ADSP2104;
extern const device_type ADSP2105;
extern const device_type ADSP2115;
extern const device_type ADSP2181;
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
class adsp21xx_device;
class adsp2100_device;
class adsp2101_device;
class adsp2181_device;
// transmit and receive data callbacks types
typedef INT32 (*adsp21xx_rx_func)(adsp21xx_device &device, int port);
typedef void (*adsp21xx_tx_func)(adsp21xx_device &device, int port, INT32 data);
typedef void (*adsp21xx_timer_func)(adsp21xx_device &device, int enable);
// ======================> adsp21xx_config
struct adsp21xx_config struct adsp21xx_config
{ {
adsp21xx_rx_func rx; /* callback for serial receive */ adsp21xx_rx_func m_sport_rx_callback; // callback for serial receive
adsp21xx_tx_func tx; /* callback for serial transmit */ adsp21xx_tx_func m_sport_tx_callback; // callback for serial transmit
adsp21xx_timer_func timer; /* callback for timer fired */ adsp21xx_timer_func m_timer_fired; // callback for timer fired
}; };
// ======================> adsp21xx_device_config
class adsp21xx_device_config : public cpu_device_config,
public adsp21xx_config
{
friend class adsp21xx_device;
protected:
enum
{
CHIP_TYPE_ADSP2100,
CHIP_TYPE_ADSP2101,
CHIP_TYPE_ADSP2104,
CHIP_TYPE_ADSP2105,
CHIP_TYPE_ADSP2115,
CHIP_TYPE_ADSP2181,
};
// construction/destruction
adsp21xx_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 chiptype);
public:
// inline configuration helpers
static void static_set_config(device_config *device, const adsp21xx_config &config);
protected:
// device_config_execute_interface overrides
virtual UINT32 execute_min_cycles() const;
virtual UINT32 execute_max_cycles() const;
// device_config_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const;
virtual UINT32 disasm_max_opcode_bytes() const;
// address spaces
const address_space_config m_program_config;
const address_space_config m_data_config;
// internal state
UINT32 m_chip_type;
};
// ======================> adsp21xx_device
class adsp21xx_device : public cpu_device
{
friend class adsp21xx_device_config;
protected:
// construction/destruction
adsp21xx_device(running_machine &_machine, const adsp21xx_device_config &config);
virtual ~adsp21xx_device();
public:
// public interfaces
void load_boot_data(UINT8 *srcdata, UINT32 *dstdata);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_state_interface overrides
virtual void state_import(const device_state_entry &entry);
virtual void state_string_export(const device_state_entry &entry, astring &string);
// device_disasm_interface overrides
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
// helpers
void create_tables();
inline void update_mstat();
inline UINT32 pc_stack_top();
inline void set_pc_stack_top(UINT32 top);
inline void pc_stack_push();
inline void pc_stack_push_val(UINT32 val);
inline void pc_stack_pop();
inline UINT32 pc_stack_pop_val();
inline UINT32 cntr_stack_top();
inline void cntr_stack_push();
inline void cntr_stack_pop();
inline UINT32 loop_stack_top();
inline void loop_stack_push(UINT32 value);
inline void loop_stack_pop();
inline void stat_stack_push();
inline void stat_stack_pop();
// inline int condition(int c);
int slow_condition();
inline void modify_address(UINT32 ireg, UINT32 mreg);
inline void data_write_dag1(UINT32 op, INT32 val);
inline UINT32 data_read_dag1(UINT32 op);
inline void data_write_dag2(UINT32 op, INT32 val);
inline UINT32 data_read_dag2(UINT32 op);
inline void pgm_write_dag2(UINT32 op, INT32 val);
inline UINT32 pgm_read_dag2(UINT32 op);
void alu_op_ar(int op);
void alu_op_ar_const(int op);
void alu_op_af(int op);
void alu_op_af_const(int op);
void alu_op_none(int op);
void mac_op_mr(int op);
void mac_op_mr_xop(int op);
void mac_op_mf(int op);
void mac_op_mf_xop(int op);
void shift_op(int op);
void shift_op_imm(int op);
// memory access
inline UINT16 data_read(UINT32 addr);
inline void data_write(UINT32 addr, UINT16 data);
inline UINT16 io_read(UINT32 addr);
inline void io_write(UINT32 addr, UINT16 data);
inline UINT32 program_read(UINT32 addr);
inline void program_write(UINT32 addr, UINT32 data);
inline UINT32 opcode_read();
// register read/write
inline void update_i(int which);
inline void update_l(int which);
inline void write_reg0(int regnum, INT32 val);
inline void write_reg1(int regnum, INT32 val);
inline void write_reg2(int regnum, INT32 val);
inline void write_reg3(int regnum, INT32 val);
inline INT32 read_reg0(int regnum);
inline INT32 read_reg1(int regnum);
inline INT32 read_reg2(int regnum);
inline INT32 read_reg3(int regnum);
// interrupts
virtual bool generate_irq(int which, int indx = 0) = 0;
virtual void check_irqs() = 0;
// internal state
static const int PC_STACK_DEPTH = 16;
static const int CNTR_STACK_DEPTH = 4;
static const int STAT_STACK_DEPTH = 4;
static const int LOOP_STACK_DEPTH = 4;
// 16-bit registers that can be loaded signed or unsigned
union adsp_reg16
{
UINT16 u;
INT16 s;
};
// the SHIFT result register is 32 bits
union adsp_shift
{
#ifdef LSB_FIRST
struct { adsp_reg16 sr0, sr1; } srx;
#else
struct { adsp_reg16 sr1, sr0; } srx;
#endif
UINT32 sr;
};
// the MAC result register is 40 bits
union adsp_mac
{
#ifdef LSB_FIRST
struct { adsp_reg16 mr0, mr1, mr2, mrzero; } mrx;
struct { UINT32 mr0, mr1; } mry;
#else
struct { adsp_reg16 mrzero, mr2, mr1, mr0; } mrx;
struct { UINT32 mr1, mr0; } mry;
#endif
UINT64 mr;
};
// core registers which are replicated
struct adsp_core
{
// ALU registers
adsp_reg16 ax0, ax1;
adsp_reg16 ay0, ay1;
adsp_reg16 ar;
adsp_reg16 af;
// MAC registers
adsp_reg16 mx0, mx1;
adsp_reg16 my0, my1;
adsp_mac mr;
adsp_reg16 mf;
// SHIFT registers
adsp_reg16 si;
adsp_reg16 se;
adsp_reg16 sb;
adsp_shift sr;
// dummy registers
adsp_reg16 zero;
};
// configuration
const adsp21xx_device_config &m_config;
// other CPU registers
UINT32 m_pc;
UINT32 m_ppc;
UINT32 m_loop;
UINT32 m_loop_condition;
UINT32 m_cntr;
// status registers
UINT32 m_astat;
UINT32 m_sstat;
UINT32 m_mstat;
UINT32 m_mstat_prev;
UINT32 m_astat_clear;
UINT32 m_idle;
// live set of core registers
adsp_core m_core;
// memory addressing registers
UINT32 m_i[8];
INT32 m_m[8];
UINT32 m_l[8];
UINT32 m_lmask[8];
UINT32 m_base[8];
UINT8 m_px;
// stacks
UINT32 m_loop_stack[LOOP_STACK_DEPTH];
UINT32 m_cntr_stack[CNTR_STACK_DEPTH];
UINT32 m_pc_stack[PC_STACK_DEPTH];
UINT16 m_stat_stack[STAT_STACK_DEPTH][3];
INT32 m_pc_sp;
INT32 m_cntr_sp;
INT32 m_stat_sp;
INT32 m_loop_sp;
// external I/O
UINT8 m_flagout;
UINT8 m_flagin;
UINT8 m_fl0;
UINT8 m_fl1;
UINT8 m_fl2;
UINT16 m_idma_addr;
UINT16 m_idma_cache;
UINT8 m_idma_offs;
// interrupt handling
UINT16 m_imask;
UINT8 m_icntl;
UINT16 m_ifc;
UINT8 m_irq_state[9];
UINT8 m_irq_latch[9];
// other internal states
int m_icount;
int m_mstat_mask;
int m_imask_mask;
// register maps
INT16 * m_read0_ptr[16];
UINT32 * m_read1_ptr[16];
UINT32 * m_read2_ptr[16];
void * m_alu_xregs[8];
void * m_alu_yregs[4];
void * m_mac_xregs[8];
void * m_mac_yregs[4];
void * m_shift_xregs[8];
// alternate core registers (at end for performance)
adsp_core m_alt;
// address spaces
address_space * m_program;
address_space * m_data;
address_space * m_io;
direct_read_data * m_direct;
// tables
UINT8 m_condition_table[0x1000];
UINT16 m_mask_table[0x4000];
UINT16 m_reverse_table[0x4000];
// debugging
#if ADSP_TRACK_HOTSPOTS
UINT32 m_pcbucket[0x4000];
#endif
// flag definitions
static const int SSFLAG = 0x80;
static const int MVFLAG = 0x40;
static const int QFLAG = 0x20;
static const int SFLAG = 0x10;
static const int CFLAG = 0x08;
static const int VFLAG = 0x04;
static const int NFLAG = 0x02;
static const int ZFLAG = 0x01;
};
// ======================> adsp2100_device_config
class adsp2100_device_config : public adsp21xx_device_config
{
friend class adsp2100_device;
// construction/destruction
adsp2100_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock);
public:
// allocators
static device_config *static_alloc_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock);
virtual device_t *alloc_device(running_machine &machine) const;
protected:
// device_config_execute_interface overrides
virtual UINT32 execute_input_lines() const;
// device_config_memory_interface overrides
virtual const address_space_config *memory_space_config(int spacenum = 0) const;
};
// ======================> adsp2100_device
class adsp2100_device : public adsp21xx_device
{
friend class adsp2100_device_config;
// construction/destruction
adsp2100_device(running_machine &_machine, const adsp2100_device_config &config);
// interrupts
virtual bool generate_irq(int which, int indx);
virtual void check_irqs();
};
// ======================> adsp2101_device_config
class adsp2101_device_config : public adsp21xx_device_config
{
friend class adsp2101_device;
protected:
// construction/destruction
adsp2101_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 chiptype);
public:
// allocators
static device_config *static_alloc_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock);
virtual device_t *alloc_device(running_machine &machine) const;
protected:
// device_config_execute_interface overrides
virtual UINT32 execute_input_lines() const;
// device_config_memory_interface overrides
virtual const address_space_config *memory_space_config(int spacenum = 0) const;
};
// ======================> adsp2101_device
class adsp2101_device : public adsp21xx_device
{
friend class adsp2101_device_config;
friend class adsp2104_device_config;
friend class adsp2105_device_config;
friend class adsp2115_device_config;
protected:
// construction/destruction
adsp2101_device(running_machine &_machine, const adsp2101_device_config &config);
// interrupts
virtual bool generate_irq(int which, int indx);
virtual void check_irqs();
};
// ======================> adsp2181_device_config
class adsp2181_device_config : public adsp21xx_device_config
{
friend class adsp2181_device;
// construction/destruction
adsp2181_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock);
public:
// allocators
static device_config *static_alloc_device_config(const machine_config &mconfig, const char *tag, const device_config *owner, UINT32 clock);
virtual device_t *alloc_device(running_machine &machine) const;
protected:
// device_config_execute_interface overrides
virtual UINT32 execute_input_lines() const;
// device_config_memory_interface overrides
virtual const address_space_config *memory_space_config(int spacenum = 0) const;
// address spaces
const address_space_config m_io_config;
};
// ======================> adsp2181_device
class adsp2181_device : public adsp21xx_device
{
friend class adsp2181_device_config;
// construction/destruction
adsp2181_device(running_machine &_machine, const adsp2181_device_config &config);
// interrupts
virtual bool generate_irq(int which, int indx);
virtual void check_irqs();
public:
// public interfaces
void idma_addr_w(UINT16 data);
UINT16 idma_addr_r();
void idma_data_w(UINT16 data);
UINT16 idma_data_r();
};
// ======================> trivial variants
DECLARE_TRIVIAL_DERIVED_DEVICE(adsp2104_device_config, adsp2101_device_config, adsp2104_device, adsp2101_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(adsp2105_device_config, adsp2101_device_config, adsp2105_device, adsp2101_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(adsp2115_device_config, adsp2101_device_config, adsp2115_device, adsp2101_device)
/*************************************************************************** /***************************************************************************
REGISTER ENUMERATION REGISTER ENUMERATION
***************************************************************************/ ***************************************************************************/
@ -69,40 +571,40 @@ enum
PUBLIC FUNCTIONS PUBLIC FUNCTIONS
***************************************************************************/ ***************************************************************************/
#define ADSP2100_IRQ0 0 /* IRQ0 */ #define ADSP2100_IRQ0 0 // IRQ0
#define ADSP2100_SPORT1_RX 0 /* SPORT1 receive IRQ */ #define ADSP2100_SPORT1_RX 0 // SPORT1 receive IRQ
#define ADSP2100_IRQ1 1 /* IRQ1 */ #define ADSP2100_IRQ1 1 // IRQ1
#define ADSP2100_SPORT1_TX 1 /* SPORT1 transmit IRQ */ #define ADSP2100_SPORT1_TX 1 // SPORT1 transmit IRQ
#define ADSP2100_IRQ2 2 /* IRQ2 */ #define ADSP2100_IRQ2 2 // IRQ2
#define ADSP2100_IRQ3 3 /* IRQ3 */ #define ADSP2100_IRQ3 3 // IRQ3
/************************************************************************** /**************************************************************************
* ADSP2101 section * ADSP2101 section
**************************************************************************/ **************************************************************************/
#define ADSP2101_IRQ0 0 /* IRQ0 */ #define ADSP2101_IRQ0 0 // IRQ0
#define ADSP2101_SPORT1_RX 0 /* SPORT1 receive IRQ */ #define ADSP2101_SPORT1_RX 0 // SPORT1 receive IRQ
#define ADSP2101_IRQ1 1 /* IRQ1 */ #define ADSP2101_IRQ1 1 // IRQ1
#define ADSP2101_SPORT1_TX 1 /* SPORT1 transmit IRQ */ #define ADSP2101_SPORT1_TX 1 // SPORT1 transmit IRQ
#define ADSP2101_IRQ2 2 /* IRQ2 */ #define ADSP2101_IRQ2 2 // IRQ2
#define ADSP2101_SPORT0_RX 3 /* SPORT0 receive IRQ */ #define ADSP2101_SPORT0_RX 3 // SPORT0 receive IRQ
#define ADSP2101_SPORT0_TX 4 /* SPORT0 transmit IRQ */ #define ADSP2101_SPORT0_TX 4 // SPORT0 transmit IRQ
#define ADSP2101_TIMER 5 /* internal timer IRQ */ #define ADSP2101_TIMER 5 // internal timer IRQ
/************************************************************************** /**************************************************************************
* ADSP2104 section * ADSP2104 section
**************************************************************************/ **************************************************************************/
#define ADSP2104_IRQ0 0 /* IRQ0 */ #define ADSP2104_IRQ0 0 // IRQ0
#define ADSP2104_SPORT1_RX 0 /* SPORT1 receive IRQ */ #define ADSP2104_SPORT1_RX 0 // SPORT1 receive IRQ
#define ADSP2104_IRQ1 1 /* IRQ1 */ #define ADSP2104_IRQ1 1 // IRQ1
#define ADSP2104_SPORT1_TX 1 /* SPORT1 transmit IRQ */ #define ADSP2104_SPORT1_TX 1 // SPORT1 transmit IRQ
#define ADSP2104_IRQ2 2 /* IRQ2 */ #define ADSP2104_IRQ2 2 // IRQ2
#define ADSP2104_SPORT0_RX 3 /* SPORT0 receive IRQ */ #define ADSP2104_SPORT0_RX 3 // SPORT0 receive IRQ
#define ADSP2104_SPORT0_TX 4 /* SPORT0 transmit IRQ */ #define ADSP2104_SPORT0_TX 4 // SPORT0 transmit IRQ
#define ADSP2104_TIMER 5 /* internal timer IRQ */ #define ADSP2104_TIMER 5 // internal timer IRQ
void adsp2104_load_boot_data(UINT8 *srcdata, UINT32 *dstdata); void adsp2104_load_boot_data(UINT8 *srcdata, UINT32 *dstdata);
@ -111,12 +613,12 @@ void adsp2104_load_boot_data(UINT8 *srcdata, UINT32 *dstdata);
* ADSP2105 section * ADSP2105 section
**************************************************************************/ **************************************************************************/
#define ADSP2105_IRQ0 0 /* IRQ0 */ #define ADSP2105_IRQ0 0 // IRQ0
#define ADSP2105_SPORT1_RX 0 /* SPORT1 receive IRQ */ #define ADSP2105_SPORT1_RX 0 // SPORT1 receive IRQ
#define ADSP2105_IRQ1 1 /* IRQ1 */ #define ADSP2105_IRQ1 1 // IRQ1
#define ADSP2105_SPORT1_TX 1 /* SPORT1 transmit IRQ */ #define ADSP2105_SPORT1_TX 1 // SPORT1 transmit IRQ
#define ADSP2105_IRQ2 2 /* IRQ2 */ #define ADSP2105_IRQ2 2 // IRQ2
#define ADSP2105_TIMER 5 /* internal timer IRQ */ #define ADSP2105_TIMER 5 // internal timer IRQ
void adsp2105_load_boot_data(UINT8 *srcdata, UINT32 *dstdata); void adsp2105_load_boot_data(UINT8 *srcdata, UINT32 *dstdata);
@ -125,14 +627,14 @@ void adsp2105_load_boot_data(UINT8 *srcdata, UINT32 *dstdata);
* ADSP2115 section * ADSP2115 section
**************************************************************************/ **************************************************************************/
#define ADSP2115_IRQ0 0 /* IRQ0 */ #define ADSP2115_IRQ0 0 // IRQ0
#define ADSP2115_SPORT1_RX 0 /* SPORT1 receive IRQ */ #define ADSP2115_SPORT1_RX 0 // SPORT1 receive IRQ
#define ADSP2115_IRQ1 1 /* IRQ1 */ #define ADSP2115_IRQ1 1 // IRQ1
#define ADSP2115_SPORT1_TX 1 /* SPORT1 transmit IRQ */ #define ADSP2115_SPORT1_TX 1 // SPORT1 transmit IRQ
#define ADSP2115_IRQ2 2 /* IRQ2 */ #define ADSP2115_IRQ2 2 // IRQ2
#define ADSP2115_SPORT0_RX 3 /* SPORT0 receive IRQ */ #define ADSP2115_SPORT0_RX 3 // SPORT0 receive IRQ
#define ADSP2115_SPORT0_TX 4 /* SPORT0 transmit IRQ */ #define ADSP2115_SPORT0_TX 4 // SPORT0 transmit IRQ
#define ADSP2115_TIMER 5 /* internal timer IRQ */ #define ADSP2115_TIMER 5 // internal timer IRQ
void adsp2115_load_boot_data(UINT8 *srcdata, UINT32 *dstdata); void adsp2115_load_boot_data(UINT8 *srcdata, UINT32 *dstdata);
@ -141,23 +643,16 @@ void adsp2115_load_boot_data(UINT8 *srcdata, UINT32 *dstdata);
* ADSP2181 section * ADSP2181 section
**************************************************************************/ **************************************************************************/
#define ADSP2181_IRQ0 0 /* IRQ0 */ #define ADSP2181_IRQ0 0 // IRQ0
#define ADSP2181_SPORT1_RX 0 /* SPORT1 receive IRQ */ #define ADSP2181_SPORT1_RX 0 // SPORT1 receive IRQ
#define ADSP2181_IRQ1 1 /* IRQ1 */ #define ADSP2181_IRQ1 1 // IRQ1
#define ADSP2181_SPORT1_TX 1 /* SPORT1 transmit IRQ */ #define ADSP2181_SPORT1_TX 1 // SPORT1 transmit IRQ
#define ADSP2181_IRQ2 2 /* IRQ2 */ #define ADSP2181_IRQ2 2 // IRQ2
#define ADSP2181_SPORT0_RX 3 /* SPORT0 receive IRQ */ #define ADSP2181_SPORT0_RX 3 // SPORT0 receive IRQ
#define ADSP2181_SPORT0_TX 4 /* SPORT0 transmit IRQ */ #define ADSP2181_SPORT0_TX 4 // SPORT0 transmit IRQ
#define ADSP2181_TIMER 5 /* internal timer IRQ */ #define ADSP2181_TIMER 5 // internal timer IRQ
#define ADSP2181_IRQE 6 /* IRQE */ #define ADSP2181_IRQE 6 // IRQE
#define ADSP2181_IRQL1 7 /* IRQL1 */ #define ADSP2181_IRQL1 7 // IRQL1
#define ADSP2181_IRQL2 8 /* IRQL2 */ #define ADSP2181_IRQL2 8 // IRQL2
void adsp2181_load_boot_data(UINT8 *srcdata, UINT32 *dstdata);
void adsp2181_idma_addr_w(running_device *device, UINT16 data);
UINT16 adsp2181_idma_addr_r(running_device *device);
void adsp2181_idma_data_w(running_device *device, UINT16 data);
UINT16 adsp2181_idma_data_r(running_device *device);
#endif /* __ADSP2100_H__ */ #endif /* __ADSP2100_H__ */

62
src/mame/audio/dcs.c
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@ -284,7 +284,7 @@ struct _dsio_denver_state
typedef struct _dcs_state dcs_state; typedef struct _dcs_state dcs_state;
struct _dcs_state struct _dcs_state
{ {
cpu_device *cpu; adsp21xx_device *cpu;
address_space *program; address_space *program;
address_space *data; address_space *data;
UINT8 rev; UINT8 rev;
@ -409,12 +409,12 @@ static WRITE16_HANDLER( output_latch_w );
static READ16_HANDLER( output_control_r ); static READ16_HANDLER( output_control_r );
static WRITE16_HANDLER( output_control_w ); static WRITE16_HANDLER( output_control_w );
static void timer_enable_callback(cpu_device &device, int enable); static void timer_enable_callback(adsp21xx_device &device, int enable);
static TIMER_DEVICE_CALLBACK( internal_timer_callback ); static TIMER_DEVICE_CALLBACK( internal_timer_callback );
static TIMER_DEVICE_CALLBACK( dcs_irq ); static TIMER_DEVICE_CALLBACK( dcs_irq );
static TIMER_DEVICE_CALLBACK( sport0_irq ); static TIMER_DEVICE_CALLBACK( sport0_irq );
static void recompute_sample_rate(running_machine *machine); static void recompute_sample_rate(running_machine *machine);
static void sound_tx_callback(cpu_device &device, int port, INT32 data); static void sound_tx_callback(adsp21xx_device &device, int port, INT32 data);
static READ16_HANDLER( dcs_polling_r ); static READ16_HANDLER( dcs_polling_r );
static WRITE16_HANDLER( dcs_polling_w ); static WRITE16_HANDLER( dcs_polling_w );
@ -610,7 +610,7 @@ static const adsp21xx_config adsp_config =
/* Basic DCS system with ADSP-2105 and 2k of SRAM (T-unit, V-unit, Killer Instinct) */ /* Basic DCS system with ADSP-2105 and 2k of SRAM (T-unit, V-unit, Killer Instinct) */
MACHINE_CONFIG_FRAGMENT( dcs_audio_2k ) MACHINE_CONFIG_FRAGMENT( dcs_audio_2k )
MDRV_CPU_ADD("dcs", ADSP2105, XTAL_10MHz) MDRV_CPU_ADD("dcs", ADSP2105, XTAL_10MHz)
MDRV_CPU_CONFIG(adsp_config) MDRV_ADSP21XX_CONFIG(adsp_config)
MDRV_CPU_PROGRAM_MAP(dcs_2k_program_map) MDRV_CPU_PROGRAM_MAP(dcs_2k_program_map)
MDRV_CPU_DATA_MAP(dcs_2k_data_map) MDRV_CPU_DATA_MAP(dcs_2k_data_map)
@ -650,7 +650,7 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_FRAGMENT( dcs2_audio_2115 ) MACHINE_CONFIG_FRAGMENT( dcs2_audio_2115 )
MDRV_CPU_ADD("dcs2", ADSP2115, XTAL_16MHz) MDRV_CPU_ADD("dcs2", ADSP2115, XTAL_16MHz)
MDRV_CPU_CONFIG(adsp_config) MDRV_ADSP21XX_CONFIG(adsp_config)
MDRV_CPU_PROGRAM_MAP(dcs2_2115_program_map) MDRV_CPU_PROGRAM_MAP(dcs2_2115_program_map)
MDRV_CPU_DATA_MAP(dcs2_2115_data_map) MDRV_CPU_DATA_MAP(dcs2_2115_data_map)
@ -671,7 +671,7 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_DERIVED( dcs2_audio_2104, dcs2_audio_2115 ) MACHINE_CONFIG_DERIVED( dcs2_audio_2104, dcs2_audio_2115 )
MDRV_CPU_REPLACE("dcs2", ADSP2104, XTAL_16MHz) MDRV_CPU_REPLACE("dcs2", ADSP2104, XTAL_16MHz)
MDRV_CPU_CONFIG(adsp_config) MDRV_ADSP21XX_CONFIG(adsp_config)
MDRV_CPU_PROGRAM_MAP(dcs2_2104_program_map) MDRV_CPU_PROGRAM_MAP(dcs2_2104_program_map)
MDRV_CPU_DATA_MAP(dcs2_2104_data_map) MDRV_CPU_DATA_MAP(dcs2_2104_data_map)
MACHINE_CONFIG_END MACHINE_CONFIG_END
@ -686,7 +686,7 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_FRAGMENT( dcs2_audio_dsio ) MACHINE_CONFIG_FRAGMENT( dcs2_audio_dsio )
MDRV_CPU_ADD("dsio", ADSP2181, XTAL_32MHz) MDRV_CPU_ADD("dsio", ADSP2181, XTAL_32MHz)
MDRV_CPU_CONFIG(adsp_config) MDRV_ADSP21XX_CONFIG(adsp_config)
MDRV_CPU_PROGRAM_MAP(dsio_program_map) MDRV_CPU_PROGRAM_MAP(dsio_program_map)
MDRV_CPU_DATA_MAP(dsio_data_map) MDRV_CPU_DATA_MAP(dsio_data_map)
MDRV_CPU_IO_MAP(dsio_io_map) MDRV_CPU_IO_MAP(dsio_io_map)
@ -710,7 +710,7 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_FRAGMENT( dcs2_audio_denver ) MACHINE_CONFIG_FRAGMENT( dcs2_audio_denver )
MDRV_CPU_ADD("denver", ADSP2181, XTAL_33_333MHz) MDRV_CPU_ADD("denver", ADSP2181, XTAL_33_333MHz)
MDRV_CPU_CONFIG(adsp_config) MDRV_ADSP21XX_CONFIG(adsp_config)
MDRV_CPU_PROGRAM_MAP(denver_program_map) MDRV_CPU_PROGRAM_MAP(denver_program_map)
MDRV_CPU_DATA_MAP(denver_data_map) MDRV_CPU_DATA_MAP(denver_data_map)
MDRV_CPU_IO_MAP(denver_io_map) MDRV_CPU_IO_MAP(denver_io_map)
@ -763,7 +763,7 @@ static void dcs_boot(void)
/* convert from 16-bit data to 8-bit data and boot */ /* convert from 16-bit data to 8-bit data and boot */
for (i = 0; i < 0x1000; i++) for (i = 0; i < 0x1000; i++)
buffer[i] = base[i]; buffer[i] = base[i];
adsp2105_load_boot_data(buffer, dcs_internal_program_ram); dcs.cpu->load_boot_data(buffer, dcs_internal_program_ram);
break; break;
/* rev 2: use the ROM page in the SDRC to boot from */ /* rev 2: use the ROM page in the SDRC to boot from */
@ -784,7 +784,7 @@ static void dcs_boot(void)
/* convert from 16-bit data to 8-bit data and boot */ /* convert from 16-bit data to 8-bit data and boot */
for (i = 0; i < 0x1000; i++) for (i = 0; i < 0x1000; i++)
buffer[i] = base[i]; buffer[i] = base[i];
adsp2115_load_boot_data(buffer, dcs_internal_program_ram); dcs.cpu->load_boot_data(buffer, dcs_internal_program_ram);
break; break;
/* rev 3/4: HALT the ADSP-2181 until program is downloaded via IDMA */ /* rev 3/4: HALT the ADSP-2181 until program is downloaded via IDMA */
@ -938,9 +938,9 @@ void dcs_init(running_machine *machine)
dcs_sram = NULL; dcs_sram = NULL;
/* find the DCS CPU and the sound ROMs */ /* find the DCS CPU and the sound ROMs */
dcs.cpu = machine->device<cpu_device>("dcs"); dcs.cpu = machine->device<adsp21xx_device>("dcs");
dcs.program = cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_PROGRAM); dcs.program = dcs.cpu->space(AS_PROGRAM);
dcs.data = cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_DATA); dcs.data = dcs.cpu->space(AS_DATA);
dcs.rev = 1; dcs.rev = 1;
dcs.channels = 1; dcs.channels = 1;
dcs.dmadac[0] = machine->device<dmadac_sound_device>("dac"); dcs.dmadac[0] = machine->device<dmadac_sound_device>("dac");
@ -975,23 +975,23 @@ void dcs2_init(running_machine *machine, int dram_in_mb, offs_t polling_offset)
memset(&dcs, 0, sizeof(dcs)); memset(&dcs, 0, sizeof(dcs));
/* find the DCS CPU and the sound ROMs */ /* find the DCS CPU and the sound ROMs */
dcs.cpu = machine->device<cpu_device>("dcs2"); dcs.cpu = machine->device<adsp21xx_device>("dcs2");
dcs.rev = 2; dcs.rev = 2;
soundbank_words = 0x1000; soundbank_words = 0x1000;
if (dcs.cpu == NULL) if (dcs.cpu == NULL)
{ {
dcs.cpu = machine->device<cpu_device>("dsio"); dcs.cpu = machine->device<adsp21xx_device>("dsio");
dcs.rev = 3; dcs.rev = 3;
soundbank_words = 0x400; soundbank_words = 0x400;
} }
if (dcs.cpu == NULL) if (dcs.cpu == NULL)
{ {
dcs.cpu = machine->device<cpu_device>("denver"); dcs.cpu = machine->device<adsp21xx_device>("denver");
dcs.rev = 4; dcs.rev = 4;
soundbank_words = 0x800; soundbank_words = 0x800;
} }
dcs.program = cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_PROGRAM); dcs.program = dcs.cpu->space(AS_PROGRAM);
dcs.data = cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_DATA); dcs.data = dcs.cpu->space(AS_DATA);
dcs.channels = 2; dcs.channels = 2;
dcs.dmadac[0] = machine->device<dmadac_sound_device>("dac1"); dcs.dmadac[0] = machine->device<dmadac_sound_device>("dac1");
dcs.dmadac[1] = machine->device<dmadac_sound_device>("dac2"); dcs.dmadac[1] = machine->device<dmadac_sound_device>("dac2");
@ -1029,7 +1029,7 @@ void dcs2_init(running_machine *machine, int dram_in_mb, offs_t polling_offset)
/* install the speedup handler */ /* install the speedup handler */
dcs.polling_offset = polling_offset; dcs.polling_offset = polling_offset;
if (polling_offset) if (polling_offset)
dcs_polling_base = memory_install_readwrite16_handler(cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_DATA), polling_offset, polling_offset, 0, 0, dcs_polling_r, dcs_polling_w); dcs_polling_base = memory_install_readwrite16_handler(dcs.cpu->space(AS_DATA), polling_offset, polling_offset, 0, 0, dcs_polling_r, dcs_polling_w);
/* allocate a watchdog timer for HLE transfers */ /* allocate a watchdog timer for HLE transfers */
transfer.hle_enabled = (ENABLE_HLE_TRANSFERS && dram_in_mb != 0); transfer.hle_enabled = (ENABLE_HLE_TRANSFERS && dram_in_mb != 0);
@ -1168,7 +1168,7 @@ static void sdrc_remap_memory(running_machine *machine)
/* reinstall the polling hotspot */ /* reinstall the polling hotspot */
if (dcs.polling_offset) if (dcs.polling_offset)
dcs_polling_base = memory_install_readwrite16_handler(cpu_get_address_space(dcs.cpu, ADDRESS_SPACE_DATA), dcs.polling_offset, dcs.polling_offset, 0, 0, dcs_polling_r, dcs_polling_w); dcs_polling_base = memory_install_readwrite16_handler(dcs.cpu->space(AS_DATA), dcs.polling_offset, dcs.polling_offset, 0, 0, dcs_polling_r, dcs_polling_w);
} }
@ -1440,7 +1440,7 @@ WRITE32_HANDLER( dsio_idma_addr_w )
{ {
if (LOG_DCS_TRANSFERS) if (LOG_DCS_TRANSFERS)
logerror("%08X:IDMA_addr = %04X\n", cpu_get_pc(space->cpu), data); logerror("%08X:IDMA_addr = %04X\n", cpu_get_pc(space->cpu), data);
adsp2181_idma_addr_w(dcs.cpu, data); downcast<adsp2181_device *>(dcs.cpu)->idma_addr_w(data);
if (data == 0) if (data == 0)
dsio.start_on_next_write = 2; dsio.start_on_next_write = 2;
} }
@ -1452,14 +1452,14 @@ WRITE32_HANDLER( dsio_idma_data_w )
if (ACCESSING_BITS_0_15) if (ACCESSING_BITS_0_15)
{ {
if (LOG_DCS_TRANSFERS) if (LOG_DCS_TRANSFERS)
logerror("%08X:IDMA_data_w(%04X) = %04X\n", pc, adsp2181_idma_addr_r(dcs.cpu), data & 0xffff); logerror("%08X:IDMA_data_w(%04X) = %04X\n", pc, downcast<adsp2181_device *>(dcs.cpu)->idma_addr_r(), data & 0xffff);
adsp2181_idma_data_w(dcs.cpu, data & 0xffff); downcast<adsp2181_device *>(dcs.cpu)->idma_data_w(data & 0xffff);
} }
if (ACCESSING_BITS_16_31) if (ACCESSING_BITS_16_31)
{ {
if (LOG_DCS_TRANSFERS) if (LOG_DCS_TRANSFERS)
logerror("%08X:IDMA_data_w(%04X) = %04X\n", pc, adsp2181_idma_addr_r(dcs.cpu), data >> 16); logerror("%08X:IDMA_data_w(%04X) = %04X\n", pc, downcast<adsp2181_device *>(dcs.cpu)->idma_addr_r(), data >> 16);
adsp2181_idma_data_w(dcs.cpu, data >> 16); downcast<adsp2181_device *>(dcs.cpu)->idma_data_w(data >> 16);
} }
if (dsio.start_on_next_write && --dsio.start_on_next_write == 0) if (dsio.start_on_next_write && --dsio.start_on_next_write == 0)
{ {
@ -1472,9 +1472,9 @@ WRITE32_HANDLER( dsio_idma_data_w )
READ32_HANDLER( dsio_idma_data_r ) READ32_HANDLER( dsio_idma_data_r )
{ {
UINT32 result; UINT32 result;
result = adsp2181_idma_data_r(dcs.cpu); result = downcast<adsp2181_device *>(dcs.cpu)->idma_data_r();
if (LOG_DCS_TRANSFERS) if (LOG_DCS_TRANSFERS)
logerror("%08X:IDMA_data_r(%04X) = %04X\n", cpu_get_pc(space->cpu), adsp2181_idma_addr_r(dcs.cpu), result); logerror("%08X:IDMA_data_r(%04X) = %04X\n", cpu_get_pc(space->cpu), downcast<adsp2181_device *>(dcs.cpu)->idma_addr_r(), result);
return result; return result;
} }
@ -1791,7 +1791,7 @@ static void reset_timer(running_machine *machine)
} }
static void timer_enable_callback(cpu_device &device, int enable) static void timer_enable_callback(adsp21xx_device &device, int enable)
{ {
dcs.timer_enable = enable; dcs.timer_enable = enable;
dcs.timer_ignore = 0; dcs.timer_ignore = 0;
@ -1845,7 +1845,7 @@ static READ16_HANDLER( adsp_control_r )
break; break;
case IDMA_CONTROL_REG: case IDMA_CONTROL_REG:
result = adsp2181_idma_addr_r(dcs.cpu); result = downcast<adsp2181_device *>(dcs.cpu)->idma_addr_r();
break; break;
case TIMER_COUNT_REG: case TIMER_COUNT_REG:
@ -1926,7 +1926,7 @@ static WRITE16_HANDLER( adsp_control_w )
break; break;
case IDMA_CONTROL_REG: case IDMA_CONTROL_REG:
adsp2181_idma_addr_w(dcs.cpu, data); downcast<adsp2181_device *>(dcs.cpu)->idma_addr_w(data);
break; break;
} }
} }
@ -2007,7 +2007,7 @@ static void recompute_sample_rate(running_machine *machine)
} }
static void sound_tx_callback(cpu_device &device, int port, INT32 data) static void sound_tx_callback(adsp21xx_device &device, int port, INT32 data)
{ {
/* check if it's for SPORT1 */ /* check if it's for SPORT1 */
if (port != 1) if (port != 1)

6
src/mame/drivers/gaelco3d.c
View File

@ -171,7 +171,7 @@ static UINT8 adsp_ireg;
static offs_t adsp_ireg_base, adsp_incs, adsp_size; static offs_t adsp_ireg_base, adsp_incs, adsp_size;
static dmadac_sound_device *dmadac[SOUND_CHANNELS]; static dmadac_sound_device *dmadac[SOUND_CHANNELS];
static void adsp_tx_callback(cpu_device &device, int port, INT32 data); static void adsp_tx_callback(adsp21xx_device &device, int port, INT32 data);
/************************************* /*************************************
@ -599,7 +599,7 @@ static TIMER_DEVICE_CALLBACK( adsp_autobuffer_irq )
} }
static void adsp_tx_callback(cpu_device &device, int port, INT32 data) static void adsp_tx_callback(adsp21xx_device &device, int port, INT32 data)
{ {
/* check if it's for SPORT1 */ /* check if it's for SPORT1 */
if (port != 1) if (port != 1)
@ -965,7 +965,7 @@ static MACHINE_CONFIG_START( gaelco3d, driver_device )
MDRV_CPU_PROGRAM_MAP(tms_map) MDRV_CPU_PROGRAM_MAP(tms_map)
MDRV_CPU_ADD("adsp", ADSP2115, 16000000) MDRV_CPU_ADD("adsp", ADSP2115, 16000000)
MDRV_CPU_CONFIG(adsp_config) MDRV_ADSP21XX_CONFIG(adsp_config)
MDRV_CPU_PROGRAM_MAP(adsp_program_map) MDRV_CPU_PROGRAM_MAP(adsp_program_map)
MDRV_CPU_DATA_MAP(adsp_data_map) MDRV_CPU_DATA_MAP(adsp_data_map)

17
src/mame/drivers/harddriv.c
View File

@ -320,11 +320,6 @@ Notes:
#include "emu.h" #include "emu.h"
#include "cpu/m68000/m68000.h"
#include "cpu/tms34010/tms34010.h"
#include "cpu/tms32010/tms32010.h"
#include "cpu/adsp2100/adsp2100.h"
#include "cpu/dsp32/dsp32.h"
#include "machine/atarigen.h" #include "machine/atarigen.h"
#include "machine/asic65.h" #include "machine/asic65.h"
#include "audio/atarijsa.h" #include "audio/atarijsa.h"
@ -1235,10 +1230,10 @@ static MACHINE_CONFIG_FRAGMENT( ds4 )
MDRV_CPU_PROGRAM_MAP(ds3_program_map) MDRV_CPU_PROGRAM_MAP(ds3_program_map)
MDRV_CPU_DATA_MAP(ds3_data_map) MDRV_CPU_DATA_MAP(ds3_data_map)
// MDRV_CPU_ADD("soundcpu", ADSP2105, 10000000) // MDRV_CPU_ADD("ds4cpu1", ADSP2105, 10000000)
// MDRV_CPU_PROGRAM_MAP(ds3snd_program_map) // MDRV_CPU_PROGRAM_MAP(ds3snd_program_map)
// MDRV_CPU_ADD("sounddsp", ADSP2105, 10000000) // MDRV_CPU_ADD("ds4cpu2", ADSP2105, 10000000)
// MDRV_CPU_PROGRAM_MAP(ds3snd_program_map) // MDRV_CPU_PROGRAM_MAP(ds3snd_program_map)
MDRV_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MDRV_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
@ -3698,11 +3693,11 @@ static void init_ds3(running_machine *machine)
memory_install_write16_handler(cpu_get_address_space(state->maincpu, ADDRESS_SPACE_PROGRAM), 0x823800, 0x823fff, 0, 0, hd68k_ds3_control_w); memory_install_write16_handler(cpu_get_address_space(state->maincpu, ADDRESS_SPACE_PROGRAM), 0x823800, 0x823fff, 0, 0, hd68k_ds3_control_w);
/* if we have a sound DSP, boot it */ /* if we have a sound DSP, boot it */
if (state->soundcpu != NULL && state->soundcpu->type() == ADSP2105) if (state->ds4cpu1 != NULL)
adsp2105_load_boot_data(state->soundcpu->region()->base() + 0x10000, &state->soundcpu->region()->u32()); state->ds4cpu1->load_boot_data(state->soundcpu->region()->base() + 0x10000, &state->soundcpu->region()->u32());
if (state->sounddsp != NULL && state->sounddsp->type() == ADSP2105) if (state->ds4cpu2 != NULL)
adsp2105_load_boot_data(state->sounddsp->region()->base() + 0x10000, &state->sounddsp->region()->u32()); state->ds4cpu2->load_boot_data(state->sounddsp->region()->base() + 0x10000, &state->sounddsp->region()->u32());
/* /*

11
src/mame/drivers/metalmx.c
View File

@ -255,7 +255,6 @@ Logic:
#include "emu.h" #include "emu.h"
#include "cpu/m68000/m68000.h" #include "cpu/m68000/m68000.h"
#include "cpu/adsp2100/adsp2100.h"
#include "cpu/tms34010/tms34010.h" #include "cpu/tms34010/tms34010.h"
#include "cpu/dsp32/dsp32.h" #include "cpu/dsp32/dsp32.h"
#include "audio/cage.h" #include "audio/cage.h"
@ -746,7 +745,7 @@ static MACHINE_CONFIG_START( metalmx, metalmx_state )
MDRV_CPU_PROGRAM_MAP(main_map) MDRV_CPU_PROGRAM_MAP(main_map)
MDRV_CPU_ADD("adsp", ADSP2105, XTAL_10MHz) MDRV_CPU_ADD("adsp", ADSP2105, XTAL_10MHz)
MDRV_CPU_CONFIG(adsp_config) MDRV_ADSP21XX_CONFIG(adsp_config)
MDRV_CPU_PROGRAM_MAP(adsp_program_map) MDRV_CPU_PROGRAM_MAP(adsp_program_map)
MDRV_CPU_DATA_MAP(adsp_data_map) MDRV_CPU_DATA_MAP(adsp_data_map)
@ -786,13 +785,7 @@ static DRIVER_INIT( metalmx )
UINT8 *adsp_boot = (UINT8*)memory_region(machine, "adsp"); UINT8 *adsp_boot = (UINT8*)memory_region(machine, "adsp");
metalmx_state *state = machine->driver_data<metalmx_state>(); metalmx_state *state = machine->driver_data<metalmx_state>();
state->maincpu = machine->device("maincpu"); state->adsp->load_boot_data(adsp_boot, state->adsp_internal_program_ram);
state->adsp = machine->device("adsp");
state->gsp = machine->device("gsp");
state->dsp32c_1 = machine->device("dsp32c_1");
state->dsp32c_2 = machine->device("dsp32c_2");
adsp2105_load_boot_data(adsp_boot, state->adsp_internal_program_ram);
cage_init(machine, 0); // TODO: speedup address cage_init(machine, 0); // TODO: speedup address
cage_set_irq_handler(cage_irq_callback); cage_set_irq_handler(cage_irq_callback);

15
src/mame/includes/harddriv.h
View File

@ -4,7 +4,11 @@
**************************************************************************/ **************************************************************************/
#include "cpu/m68000/m68000.h"
#include "cpu/tms34010/tms34010.h" #include "cpu/tms34010/tms34010.h"
#include "cpu/tms32010/tms32010.h"
#include "cpu/adsp2100/adsp2100.h"
#include "cpu/dsp32/dsp32.h"
#include "machine/atarigen.h" #include "machine/atarigen.h"
class harddriv_state : public atarigen_state class harddriv_state : public atarigen_state
@ -19,16 +23,21 @@ public:
soundcpu(*this, "soundcpu"), soundcpu(*this, "soundcpu"),
sounddsp(*this, "sounddsp"), sounddsp(*this, "sounddsp"),
jsacpu(*this, "jsacpu"), jsacpu(*this, "jsacpu"),
dsp32(*this, "dsp32") { } dsp32(*this, "dsp32"),
ds4cpu1(*this, "ds4cpu1"),
ds4cpu2(*this, "ds4cpu2"),
duart_timer(*this, "duart_timer") { }
required_device<cpu_device> maincpu; required_device<cpu_device> maincpu;
required_device<tms34010_device> gsp; required_device<tms34010_device> gsp;
optional_device<cpu_device> msp; optional_device<cpu_device> msp;
required_device<cpu_device> adsp; required_device<adsp21xx_device> adsp;
optional_device<cpu_device> soundcpu; optional_device<cpu_device> soundcpu;
optional_device<cpu_device> sounddsp; optional_device<cpu_device> sounddsp;
optional_device<cpu_device> jsacpu; optional_device<cpu_device> jsacpu;
optional_device<cpu_device> dsp32; optional_device<cpu_device> dsp32;
optional_device<adsp2105_device> ds4cpu1;
optional_device<adsp2105_device> ds4cpu2;
UINT8 hd34010_host_access; UINT8 hd34010_host_access;
UINT8 dsk_pio_access; UINT8 dsk_pio_access;
@ -82,7 +91,7 @@ public:
UINT8 duart_read_data[16]; UINT8 duart_read_data[16];
UINT8 duart_write_data[16]; UINT8 duart_write_data[16];
UINT8 duart_output_port; UINT8 duart_output_port;
timer_device * duart_timer; optional_device<timer_device> duart_timer;
UINT8 last_gsp_shiftreg; UINT8 last_gsp_shiftreg;

19
src/mame/includes/metalmx.h
View File

@ -1,14 +1,21 @@
#include "cpu/adsp2100/adsp2100.h"
class metalmx_state : public driver_device class metalmx_state : public driver_device
{ {
public: public:
metalmx_state(running_machine &machine, const driver_device_config_base &config) metalmx_state(running_machine &machine, const driver_device_config_base &config)
: driver_device(machine, config) { } : driver_device(machine, config),
maincpu(*this, "maincpu"),
gsp(*this, "gsp"),
adsp(*this, "adsp"),
dsp32c_1(*this, "dsp32c_1"),
dsp32c_2(*this, "dsp32c_2") { }
running_device *maincpu; required_device<m68ec020_device> maincpu;
running_device *gsp; required_device<tms34010_device> gsp;
running_device *adsp; required_device<adsp2105_device> adsp;
running_device *dsp32c_1; required_device<dsp32c_device> dsp32c_1;
running_device *dsp32c_2; required_device<dsp32c_device> dsp32c_2;
UINT16 *gsp_dram; UINT16 *gsp_dram;
UINT16 *gsp_vram; UINT16 *gsp_vram;