Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-25 09:50:04 +03:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

SCC68070: some minor stuff sorted out

Browse Source
This commit is contained in:
Angelo Salese 2009-07-04 16:37:59 +00:00
parent f07980ccc6
commit 84aa885368
1 changed files with 29 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
src/mame/drivers/magicard.c
View File

@ -384,7 +384,7 @@ static READ16_HANDLER( scc68070_ext_irqc_r ) { return scc68070_ext_irqc_regs[off
static WRITE16_HANDLER( scc68070_ext_irqc_w ){ scc68070_ext_irqc_regs[offset] = data; }
static READ16_HANDLER( scc68070_iic_r )
{
printf("%04x\n",offset*2);
//printf("%04x\n",offset*2);
switch(offset)
{
@ -419,27 +419,36 @@ static WRITE16_HANDLER( scc68070_dma_ch1_w ){ scc68070_dma_ch1_regs[offset] = da
static READ16_HANDLER( scc68070_dma_ch2_r ) { return scc68070_dma_ch2_regs[offset]; }
static WRITE16_HANDLER( scc68070_dma_ch2_w ){ scc68070_dma_ch2_regs[offset] = data; }
static READ16_HANDLER( scc68070_mmu_r ) { return scc68070_mmu_regs[offset]; }
static WRITE16_HANDLER( scc68070_mmu_w ){ scc68070_mmu_regs[offset] = data; }
static WRITE16_HANDLER( scc68070_mmu_w )
{
scc68070_mmu_regs[offset] = data;
switch(offset)
{
case 0x0000/2:
if(data & 0x80) //throw an error if the (unemulated) MMU is enabled
fatalerror("SCC68070: MMU enable bit active");
break;
}
}
static ADDRESS_MAP_START( magicard_mem, ADDRESS_SPACE_PROGRAM, 16 )
// ADDRESS_MAP_GLOBAL_MASK(0x1fffff)
AM_RANGE(0x00000000, 0x000fffff) AM_MIRROR(0x400000) AM_RAM AM_BASE(&magicram) /*only 0-7ffff accessed in Magic Card*/
// AM_RANGE(0x00100000, 0x0017ffff) AM_MIRROR(0x400000) AM_RAM AM_REGION("maincpu", 0)
AM_RANGE(0x00180000, 0x001ffbff) AM_MIRROR(0x400000) AM_ROM AM_REGION("maincpu", 0)
AM_RANGE(0x00000000, 0x0017ffff) AM_MIRROR(0x7fe00000) AM_RAM AM_BASE(&magicram) /*only 0-7ffff accessed in Magic Card*/
AM_RANGE(0x00180000, 0x001ffbff) AM_MIRROR(0x7fe00000) AM_RAM AM_REGION("maincpu", 0)
/* 001ffc00-001ffdff System I/O */
AM_RANGE(0x001ffc00, 0x001ffc01) AM_MIRROR(0x400000) AM_READ(test_r)
AM_RANGE(0x001ffc40, 0x001ffc41) AM_MIRROR(0x400000) AM_READ(test_r)
AM_RANGE(0x001ffd00, 0x001ffd05) AM_MIRROR(0x400000) AM_WRITE(paletteram_io_w) //RAMDAC
AM_RANGE(0x001ffc00, 0x001ffc01) AM_MIRROR(0x7fe00000) AM_READ(test_r)
AM_RANGE(0x001ffc40, 0x001ffc41) AM_MIRROR(0x7fe00000) AM_READ(test_r)
AM_RANGE(0x001ffd00, 0x001ffd05) AM_MIRROR(0x7fe00000) AM_WRITE(paletteram_io_w) //RAMDAC
/*not the right sound chip,unknown type,it should be an ADPCM with 8 channels.*/
AM_RANGE(0x001ffd40, 0x001ffd43) AM_MIRROR(0x400000) AM_DEVWRITE8("ym", ym2413_w, 0x00ff)
AM_RANGE(0x001ffd80, 0x001ffd81) AM_MIRROR(0x400000) AM_READ(test_r)
AM_RANGE(0x001ffd80, 0x001ffd81) AM_MIRROR(0x400000) AM_WRITENOP //?
AM_RANGE(0x001fff80, 0x001fffbf) AM_MIRROR(0x400000) AM_RAM //DRAM I/O, not accessed by this game, CD buffer?
AM_RANGE(0x001fffe0, 0x001fffff) AM_MIRROR(0x400000) AM_READWRITE(philips_66470_r,philips_66470_w) AM_BASE(&pcab_vregs) //video registers
AM_RANGE(0x00200000, 0x002fffff) AM_MIRROR(0x400000) AM_RAM
AM_RANGE(0x80001000, 0x8000100f) AM_READWRITE(scc68070_ext_irqc_r,scc68070_ext_irqc_w) AM_BASE(&scc68070_ext_irqc_regs)
AM_RANGE(0x80002000, 0x8000200f) AM_READWRITE(scc68070_iic_r,scc68070_iic_w) AM_BASE(&scc68070_iic_regs)
AM_RANGE(0x001ffd40, 0x001ffd43) AM_MIRROR(0x7fe00000) AM_DEVWRITE8("ym", ym2413_w, 0x00ff)
AM_RANGE(0x001ffd80, 0x001ffd81) AM_MIRROR(0x7fe00000) AM_READ(test_r)
AM_RANGE(0x001ffd80, 0x001ffd81) AM_MIRROR(0x7fe00000) AM_WRITENOP //?
AM_RANGE(0x001fff80, 0x001fffbf) AM_MIRROR(0x7fe00000) AM_RAM //DRAM I/O, not accessed by this game, CD buffer?
AM_RANGE(0x001fffe0, 0x001fffff) AM_MIRROR(0x7fe00000) AM_READWRITE(philips_66470_r,philips_66470_w) AM_BASE(&pcab_vregs) //video registers
AM_RANGE(0x80001000, 0x8000100f) AM_READWRITE(scc68070_ext_irqc_r,scc68070_ext_irqc_w) AM_BASE(&scc68070_ext_irqc_regs) //lir
AM_RANGE(0x80002000, 0x8000200f) AM_READWRITE(scc68070_iic_r,scc68070_iic_w) AM_BASE(&scc68070_iic_regs) //i2c
AM_RANGE(0x80002010, 0x8000201f) AM_READWRITE(scc68070_uart_r,scc68070_uart_w) AM_BASE(&scc68070_uart_regs)
AM_RANGE(0x80002020, 0x8000202f) AM_READWRITE(scc68070_timer_r,scc68070_timer_w) AM_BASE(&scc68070_timer_regs)
AM_RANGE(0x80002040, 0x8000204f) AM_READWRITE(scc68070_int_irqc_r,scc68070_int_irqc_w) AM_BASE(&scc68070_int_irqc_regs)
@ -472,9 +481,10 @@ static MACHINE_RESET( magicard )
/*Probably there's a mask somewhere if it REALLY uses irqs at all...irq vectors dynamically changes after some time.*/
static INTERRUPT_GEN( magicard_irq )
{
// if(input_code_pressed(KEYCODE_Z))
// cputag_set_input_line(device->machine, "maincpu", 1, HOLD_LINE);
// magicram[0x2004/2]^=0xffff;
if(input_code_pressed(KEYCODE_Z)) //vblank?
cpu_set_input_line_and_vector(device, 1, HOLD_LINE,0xe4/4);
if(input_code_pressed(KEYCODE_X)) //uart irq
cpu_set_input_line_and_vector(device, 1, HOLD_LINE,0xf0/4);
}
static MACHINE_DRIVER_START( magicard )