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https://github.com/holub/mame
synced 2025-04-22 08:22:15 +03:00
r4000: small performance tweak (nw)
Added a primitive mru scheme for tlb searches, resulting in an average of ~1.5 iterations per scan and 2-3% speedup in one test case. Also removed the confusing reverse-endian logic from lwl/lwr and friends because apparently no commercial software implementation has ever used it (and wasn't supported in any of the other instructions anyway).
This commit is contained in:
Patrick Mackinlay
parent
98c7b6f73b
commit
84ae680329
@ -41,6 +41,7 @@
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#define LOG_CACHE (1U << 2)
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#define LOG_EXCEPTION (1U << 3)
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#define LOG_SYSCALL (1U << 4)
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#define LOG_STATS (1U << 5)
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#define VERBOSE (LOG_GENERAL)
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@ -210,15 +211,29 @@ void r4000_base_device::device_reset()
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m_cp0[CP0_WatchLo] = 0;
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m_cp0[CP0_WatchHi] = 0;
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m_icache_hit = 0;
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m_icache_miss = 0;
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// initialize tlb mru index with identity mapping
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for (unsigned i = 0; i < ARRAY_LENGTH(m_tlb); i++)
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{
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m_tlb_mru[TRANSLATE_READ][i] = i;
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m_tlb_mru[TRANSLATE_WRITE][i] = i;
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m_tlb_mru[TRANSLATE_FETCH][i] = i;
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}
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// initialize statistics
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m_tlb_scans = 0;
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m_tlb_loops = 0;
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m_icache_hits = 0;
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m_icache_misses = 0;
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}
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void r4000_base_device::device_stop()
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{
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if (ICACHE)
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LOGMASKED(LOG_CACHE, "icache hit ratio %.3f%% (%d hits %d misses)\n",
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double(m_icache_hit) / double(m_icache_hit + m_icache_miss) * 100.0, m_icache_hit, m_icache_miss);
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if ((m_icache_hits + m_icache_misses) > 0)
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LOGMASKED(LOG_STATS, "icache hit ratio %.3f%% (%d hits %d misses)\n",
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double(m_icache_hits) / double(m_icache_hits + m_icache_misses) * 100.0, m_icache_hits, m_icache_misses);
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if (m_tlb_scans > 0)
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LOGMASKED(LOG_STATS, "tlb scans %d loops %d average %.3f loops per scan\n", m_tlb_scans, m_tlb_loops, double(m_tlb_loops) / double(m_tlb_scans));
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}
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device_memory_interface::space_config_vector r4000_base_device::memory_space_config() const
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@ -1224,8 +1239,7 @@ void r4000_base_device::cpu_exception(u32 exception, u16 const vector)
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void r4000_base_device::cpu_lwl(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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u64 const offset = ADDR(m_r[RSREG], s16(op));
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unsigned const shift = ((offset & 3) ^ R4000_ENDIAN_LE_BE(3, 0)) << 3;
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load<u32>(offset & ~3,
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@ -1237,8 +1251,7 @@ void r4000_base_device::cpu_lwl(u32 const op)
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void r4000_base_device::cpu_lwr(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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u64 const offset = ADDR(m_r[RSREG], s16(op));
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unsigned const shift = ((offset & 0x3) ^ R4000_ENDIAN_LE_BE(0, 3)) << 3;
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load<u32>(offset & ~3,
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@ -1250,8 +1263,7 @@ void r4000_base_device::cpu_lwr(u32 const op)
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void r4000_base_device::cpu_swl(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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u64 const offset = ADDR(m_r[RSREG], s16(op));
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unsigned const shift = ((offset & 3) ^ R4000_ENDIAN_LE_BE(3, 0)) << 3;
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store<u32>(offset & ~3, u32(m_r[RTREG]) >> shift, ~u32(0) >> shift);
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@ -1259,8 +1271,7 @@ void r4000_base_device::cpu_swl(u32 const op)
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void r4000_base_device::cpu_swr(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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u64 const offset = ADDR(m_r[RSREG], s16(op));
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unsigned const shift = ((offset & 3) ^ R4000_ENDIAN_LE_BE(0, 3)) << 3;
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store<u32>(offset & ~3, u32(m_r[RTREG]) << shift, ~u32(0) << shift);
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@ -1268,8 +1279,7 @@ void r4000_base_device::cpu_swr(u32 const op)
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void r4000_base_device::cpu_ldl(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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u64 const offset = ADDR(m_r[RSREG], s16(op));
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unsigned const shift = ((offset & 7) ^ R4000_ENDIAN_LE_BE(7, 0)) << 3;
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load<u64>(offset & ~7,
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@ -1281,8 +1291,7 @@ void r4000_base_device::cpu_ldl(u32 const op)
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void r4000_base_device::cpu_ldr(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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u64 const offset = ADDR(m_r[RSREG], s16(op));
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unsigned const shift = ((offset & 7) ^ R4000_ENDIAN_LE_BE(0, 7)) << 3;
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load<u64>(offset & ~7,
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@ -1294,8 +1303,7 @@ void r4000_base_device::cpu_ldr(u32 const op)
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void r4000_base_device::cpu_sdl(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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u64 const offset = ADDR(m_r[RSREG], s16(op));
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unsigned const shift = ((offset & 7) ^ R4000_ENDIAN_LE_BE(7, 0)) << 3;
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store<u64>(offset & ~7, m_r[RTREG] >> shift, ~u64(0) >> shift);
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@ -1303,8 +1311,7 @@ void r4000_base_device::cpu_sdl(u32 const op)
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void r4000_base_device::cpu_sdr(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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u64 const offset = ADDR(m_r[RSREG], s16(op));
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unsigned const shift = ((offset & 7) ^ R4000_ENDIAN_LE_BE(0, 7)) << 3;
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store<u64>(offset & ~7, m_r[RTREG] << shift, ~u64(0) << shift);
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@ -2712,11 +2719,15 @@ r4000_base_device::translate_t r4000_base_device::translate(int intention, u64 &
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// address needs translation, using a combination of VPN2 and ASID
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u64 const key = (address & (extended ? (EH_R | EH_VPN2_64) : EH_VPN2_32)) | (m_cp0[CP0_EntryHi] & EH_ASID);
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unsigned *mru = m_tlb_mru[intention & TRANSLATE_TYPE_MASK];
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if (LOG_STATS)
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m_tlb_scans++;
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bool invalid = false;
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bool modify = false;
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for (unsigned i = 0; i < ARRAY_LENGTH(m_tlb); i++)
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{
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unsigned const index = (m_last[intention & TRANSLATE_TYPE_MASK] + i) % ARRAY_LENGTH(m_tlb);
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unsigned const index = mru[i];
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tlb_entry_t const &entry = m_tlb[index];
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// test vpn and asid
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@ -2726,6 +2737,9 @@ r4000_base_device::translate_t r4000_base_device::translate(int intention, u64 &
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if ((entry.vpn & mask) != (key & mask))
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continue;
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if (LOG_STATS)
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m_tlb_loops += i + 1;
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u64 const pfn = entry.pfn[BIT(address, entry.low_bit)];
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// test valid
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@ -2746,8 +2760,9 @@ r4000_base_device::translate_t r4000_base_device::translate(int intention, u64 &
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address &= (entry.mask >> 1) | 0xfff;
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address |= ((pfn & EL_PFN) << 6) & ~(entry.mask >> 1);
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// remember the last-used tlb entry
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m_last[intention & TRANSLATE_TYPE_MASK] = index;
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// promote the entry in the mru index
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if (i > 0)
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std::swap(mru[i - 1], mru[i]);
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return ((pfn & EL_C) == C_2) ? UNCACHED : CACHED;
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}
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@ -2979,7 +2994,7 @@ bool r4000_base_device::fetch(u64 address, std::function<void(u32)> &&apply)
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if (!(tag & ICACHE_V) || (tag & ICACHE_PTAG) != (address >> 12))
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{
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// cache miss
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m_icache_miss++;
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m_icache_misses++;
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// reload the cache line
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tag = ICACHE_V | (address >> 12);
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@ -2992,7 +3007,7 @@ bool r4000_base_device::fetch(u64 address, std::function<void(u32)> &&apply)
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}
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}
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else
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m_icache_hit++;
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m_icache_hits++;
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// apply the result
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apply(m_icache_data[cache_address >> 2]);
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@ -401,10 +401,10 @@ protected:
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u64 vpn;
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u64 pfn[2];
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u8 low_bit;
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unsigned low_bit;
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}
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m_tlb[48];
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unsigned m_last[3];
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unsigned m_tlb_mru[3][48];
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bool m_64;
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// cp1 state
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@ -421,9 +421,11 @@ protected:
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std::unique_ptr<u32[]> m_icache_tag;
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std::unique_ptr<u32[]> m_icache_data;
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// experimental icache statistics
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u64 m_icache_hit;
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u64 m_icache_miss;
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// statistics
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u64 m_tlb_scans;
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u64 m_tlb_loops;
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u64 m_icache_hits;
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u64 m_icache_misses;
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};
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class r4000_device : public r4000_base_device
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@ -39,7 +39,7 @@
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#define LOG_COMMANDS (1 << 7)
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#define LOG_ALL (LOG_UNKNOWN | LOG_VC2 | LOG_CMAP0 | LOG_CMAP1 | LOG_XMAP0 | LOG_XMAP1 | LOG_REX3)
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#define VERBOSE (LOG_COMMANDS | LOG_UNKNOWN | LOG_REX3 | LOG_CMAP0 | LOG_CMAP1)
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#define VERBOSE 0
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(NEWPORT_VIDEO, newport_video_device, "newport_video", "SGI Newport graphics board")
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