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https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
dp83932c: refactored, still a skeleton/wip (nw)
This commit is contained in:
Patrick Mackinlay
parent
4ce894b05f
commit
84b57f9658
@ -20,112 +20,99 @@
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#define VERBOSE 0
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(DP83932C_BE, dp83932c_be_device, "dp83932c_be", "National Semiconductor DP83932C SONIC (big)")
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DEFINE_DEVICE_TYPE(DP83932C_LE, dp83932c_le_device, "dp83932c_le", "National Semiconductor DP83932C SONIC (little)")
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DEFINE_DEVICE_TYPE(DP83932C, dp83932c_device, "dp83932c", "National Semiconductor DP83932C SONIC")
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dp83932c_device::dp83932c_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endian)
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: device_t(mconfig, type, tag, owner, clock)
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, device_memory_interface(mconfig, *this)
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dp83932c_device::dp83932c_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: device_t(mconfig, DP83932C, tag, owner, clock)
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, device_network_interface(mconfig, *this, 10.0f)
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, m_space_config("shared", endian, 32, 32)
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, m_ram(*this, finder_base::DUMMY_TAG)
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, m_out_int(*this)
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{
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}
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dp83932c_be_device::dp83932c_be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: dp83932c_device(mconfig, DP83932C_BE, tag, owner, clock, ENDIANNESS_BIG)
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{
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}
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dp83932c_le_device::dp83932c_le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: dp83932c_device(mconfig, DP83932C_LE, tag, owner, clock, ENDIANNESS_LITTLE)
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{
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}
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void dp83932c_device::map(address_map &map)
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{
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/*
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// command and status registers
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map(0x00, 0x03).rw(FUNC(dp83932c_device::cr_r), FUNC(dp83932c_device::cr_w));
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map(0x04, 0x07).rw(FUNC(dp83932c_device::dcr_r), FUNC(dp83932c_device::dcr_w));
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map(0x08, 0x0b).rw(FUNC(dp83932c_device::rcr_r), FUNC(dp83932c_device::rcr_w));
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map(0x0c, 0x0f).rw(FUNC(dp83932c_device::tcr_r), FUNC(dp83932c_device::tcr_w));
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map(0x10, 0x13).rw(FUNC(dp83932c_device::imr_r), FUNC(dp83932c_device::imr_w));
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map(0x14, 0x17).rw(FUNC(dp83932c_device::isr_r), FUNC(dp83932c_device::isr_w));
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// datasheet uses unshifted register addresses
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int const shift = 1;
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// transmit registers
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map(0x18, 0x1b).rw(FUNC(dp83932c_device::utda_r), FUNC(dp83932c_device::utda_w));
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map(0x1c, 0x1f).rw(FUNC(dp83932c_device::ctda_r), FUNC(dp83932c_device::ctda_w));
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// command and status registers
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map(0x00 << shift, (0x00 << shift) | 0x01).rw(FUNC(dp83932c_device::cr_r), FUNC(dp83932c_device::cr_w));
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//map(0x01 << shift, (0x01 << shift) | 0x01).rw(FUNC(dp83932c_device::dcr_r), FUNC(dp83932c_device::dcr_w));
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//map(0x02 << shift, (0x02 << shift) | 0x01).rw(FUNC(dp83932c_device::rcr_r), FUNC(dp83932c_device::rcr_w));
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map(0x03 << shift, (0x03 << shift) | 0x01).rw(FUNC(dp83932c_device::tcr_r), FUNC(dp83932c_device::tcr_w));
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//map(0x04 << shift, (0x04 << shift) | 0x01).rw(FUNC(dp83932c_device::imr_r), FUNC(dp83932c_device::imr_w));
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map(0x05 << shift, (0x05 << shift) | 0x01).rw(FUNC(dp83932c_device::isr_r), FUNC(dp83932c_device::isr_w));
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// tps
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// tfc
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// tsa0
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// tsa1
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// tfs
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// transmit registers
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map(0x06 << shift, (0x06 << shift) | 0x01).rw(FUNC(dp83932c_device::utda_r), FUNC(dp83932c_device::utda_w));
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//map(0x07 << shift, (0x07 << shift) | 0x01).rw(FUNC(dp83932c_device::ctda_r), FUNC(dp83932c_device::ctda_w));
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// receive registers
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map(0x34, 0x37).rw(FUNC(dp83932c_device::urda_r), FUNC(dp83932c_device::urda_w));
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map(0x38, 0x3b).rw(FUNC(dp83932c_device::crda_r), FUNC(dp83932c_device::crda_w));
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// tps
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// tfc
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// tsa0
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// tsa1
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// tfs
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// crba0
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// crba1
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// rbwc0
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// rbwc1
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// eobc
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// urra
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// rsa
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// rea
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// rrp
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// rwp
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// trba0
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// trba1
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// tbwc0
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// tbwc1
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// addr0
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// addr1
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// llfa
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// ttda
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// cep
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// cap2
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// cap1
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// cap0
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// ce
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// cdp
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// cdc
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// sr
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// wt0
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// wt1
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// rsc
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// crct
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// faet
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// mpt
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// mdt
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// receive registers
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//map(0x0d << shift, (0x0d << shift) | 0x01).rw(FUNC(dp83932c_device::urda_r), FUNC(dp83932c_device::urda_w));
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map(0x0e << shift, (0x0e << shift) | 0x01).rw(FUNC(dp83932c_device::crda_r), FUNC(dp83932c_device::crda_w));
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// 30-3e internal use registers
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*/
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// crba0
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// crba1
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// rbwc0
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// rbwc1
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// eobc
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// urra
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// rsa
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// rea
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map(0x17 << shift, (0x17 << shift) | 0x01).rw(FUNC(dp83932c_device::rrp_r), FUNC(dp83932c_device::rrp_w));
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map(0x18 << shift, (0x18 << shift) | 0x01).rw(FUNC(dp83932c_device::rwp_r), FUNC(dp83932c_device::rwp_w));
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// trba0
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// trba1
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// tbwc0
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// tbwc1
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// addr0
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// addr1
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// llfa
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// ttda
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// cep
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// cap2
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// cap1
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// cap0
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map(0x25 << shift, (0x25 << shift) | 0x01).rw(FUNC(dp83932c_device::ce_r), FUNC(dp83932c_device::ce_w));
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// cdp
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// cdc
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// sr
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map(0x29 << shift, (0x29 << shift) | 0x01).rw(FUNC(dp83932c_device::wt0_r), FUNC(dp83932c_device::wt0_w));
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map(0x2a << shift, (0x2a << shift) | 0x01).rw(FUNC(dp83932c_device::wt1_r), FUNC(dp83932c_device::wt1_w));
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map(0x2b << shift, (0x2b << shift) | 0x01).rw(FUNC(dp83932c_device::rsc_r), FUNC(dp83932c_device::rsc_w));
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// crct
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map(0x2d << shift, (0x2d << shift) | 0x01).rw(FUNC(dp83932c_device::faet_r), FUNC(dp83932c_device::faet_w));
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// mpt
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// mdt
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// 30-3e internal use registers
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// dcr2
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}
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void dp83932c_device::device_start()
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{
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m_space = &space(0);
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m_out_int.resolve();
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}
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void dp83932c_device::device_reset()
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{
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m_cr = RST | STP | RXDIS;
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m_tcr = NCRS | PTX;
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m_isr = 0;
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m_ce = 0;
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m_rsc = 0;
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}
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void dp83932c_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
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{
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}
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device_memory_interface::space_config_vector dp83932c_device::memory_space_config() const
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{
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return space_config_vector {
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std::make_pair(0, &m_space_config)
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};
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}
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void dp83932c_device::send_complete_cb(int result)
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{
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}
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@ -6,54 +6,113 @@
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#pragma once
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class dp83932c_device :
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public device_t,
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public device_memory_interface,
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public device_network_interface
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#include "machine/ram.h"
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class dp83932c_device
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: public device_t
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, public device_network_interface
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{
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public:
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// callback configuration
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dp83932c_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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static constexpr feature_type imperfect_features() { return feature::LAN; }
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// configuration
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template <typename T> void set_ram(T &&tag) { m_ram.set_tag(std::forward<T>(tag)); }
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auto out_int_cb() { return m_out_int.bind(); }
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void map(address_map &map);
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protected:
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dp83932c_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endian);
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// device_t overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
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// device_memory_interface overrides
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virtual space_config_vector memory_space_config() const override;
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// device_network_interface overrides
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virtual void send_complete_cb(int result) override;
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virtual int recv_start_cb(u8 *buf, int length) override;
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virtual void recv_complete_cb(int result) override;
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enum cr_mask : u16
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{
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HTX = 0x0001, // halt transmission
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TXP = 0x0002, // transmit packets
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RXDIS = 0x0004, // receiver disable
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RXEN = 0x0008, // receiver enable
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STP = 0x0010, // stop timer
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ST = 0x0020, // start timer
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RST = 0x0080, // software reset
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RRRA = 0x0100, // read rra
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LCAM = 0x0200, // load cam
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CR_WMASK = 0x03bf
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};
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enum tcr_mask : u16
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{
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PTX = 0x0001, // packet transmitted ok
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BCM = 0x0002, // byte count mismatch
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FU = 0x0004, // fifo underrun
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PMB = 0x0008, // packet monitored bad
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OWC = 0x0020, // out of window collision
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EXC = 0x0040, // excessive collisions
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CRSL = 0x0080, // crs lost
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NCRS = 0x0100, // no crs
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DEF = 0x0200, // deferred transmission
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EXD = 0x0400, // excessive deferral
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EXDIS = 0x1000, // disable excessive deferral timer
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CRCI = 0x2000, // crc inhibit
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POWC = 0x4000, // programmed out of window collision timer
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PINT = 0x8000, // programmable interrupt
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TCR_WMASK = 0xf000
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};
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u16 cr_r() { return m_cr; }
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u16 tcr_r() { return m_tcr; }
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u16 utda_r() { return m_utda; }
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u16 crda_r() { return m_crda; }
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u16 rrp_r() { return m_rrp; }
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u16 rwp_r() { return m_rwp; }
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u16 isr_r() { return m_isr; }
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u16 ce_r() { return m_ce; }
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u16 wt0_r() { return m_wt0; }
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u16 wt1_r() { return m_wt1; }
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u16 rsc_r() { return m_rsc; }
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u16 faet_r() { return m_faet; }
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void cr_w(u16 data) { m_cr = (data & CR_WMASK) | (m_cr & ~CR_WMASK); }
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void tcr_w(u16 data) { m_tcr = (data & TCR_WMASK) | (m_tcr & ~TCR_WMASK); }
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void utda_w(u16 data) { m_utda = data; }
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void crda_w(u16 data) { m_crda = data; }
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void rrp_w(u16 data) { m_rrp = data; }
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void rwp_w(u16 data) { m_rwp = data; }
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void isr_w(u16 data) { m_isr = data; }
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void ce_w(u16 data) { m_ce = data; }
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void wt0_w(u16 data) { m_wt0 = data; }
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void wt1_w(u16 data) { m_wt1 = data; }
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void rsc_w(u16 data) { m_rsc = data; }
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void faet_w(u16 data) { m_faet = ~data; }
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private:
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// device_memory_interface members
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const address_space_config m_space_config;
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address_space *m_space;
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required_device<ram_device> m_ram;
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devcb_write_line m_out_int;
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u16 m_cr;
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u16 m_tcr;
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u16 m_utda;
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u16 m_crda;
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u16 m_rrp;
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u16 m_rwp;
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u16 m_isr;
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u16 m_ce;
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u16 m_wt0;
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u16 m_wt1;
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u16 m_rsc;
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u16 m_faet;
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};
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class dp83932c_be_device : public dp83932c_device
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{
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public:
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dp83932c_be_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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};
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class dp83932c_le_device : public dp83932c_device
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{
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public:
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dp83932c_le_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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};
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DECLARE_DEVICE_TYPE(DP83932C_BE, dp83932c_be_device)
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DECLARE_DEVICE_TYPE(DP83932C_LE, dp83932c_le_device)
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DECLARE_DEVICE_TYPE(DP83932C, dp83932c_device)
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#endif // MAME_MACHINE_DP83932C_H
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@ -169,6 +169,8 @@ void jazz_state::jazz(machine_config &config)
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m_kbdc->kbd_data().set(kbdc, FUNC(pc_kbdc_device::data_write_from_mb));
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G364(config, m_ramdac, 0);
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DP83932C(config, m_network, 20_MHz_XTAL);
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}
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void jazz_state::mmr4000be(machine_config &config)
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@ -176,8 +178,6 @@ void jazz_state::mmr4000be(machine_config &config)
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R4000BE(config, m_maincpu, 50_MHz_XTAL);
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jazz(config);
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DP83932C_BE(config, m_network, 20_MHz_XTAL);
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}
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void jazz_state::mmr4000le(machine_config &config)
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@ -185,8 +185,6 @@ void jazz_state::mmr4000le(machine_config &config)
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R4000LE(config, m_maincpu, 50_MHz_XTAL);
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jazz(config);
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DP83932C_LE(config, m_network, 20_MHz_XTAL);
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}
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ROM_START(mmr4000be)
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