diff --git a/scripts/src/bus.lua b/scripts/src/bus.lua index 5e9c9b5ef55..4ff7760533d 100644 --- a/scripts/src/bus.lua +++ b/scripts/src/bus.lua @@ -967,6 +967,21 @@ if (BUSES["GAMATE"]~=null) then end +--------------------------------------------------- +-- +--@src/devices/bus/gio64/gio64.h,BUSES["GIO64"] = true +--------------------------------------------------- + +if (BUSES["GIO64"]~=null) then + files { + MAME_DIR .. "src/devices/bus/gio64/gio64.cpp", + MAME_DIR .. "src/devices/bus/gio64/gio64.h", + MAME_DIR .. "src/devices/bus/gio64/newport.cpp", + MAME_DIR .. "src/devices/bus/gio64/newport.h", + } +end + + --------------------------------------------------- -- --@src/devices/bus/hp_hil/hp_hil.h,BUSES["HPHIL"] = true @@ -3262,6 +3277,30 @@ if (BUSES["SUNMOUSE"]~=null) then } end +--------------------------------------------------- +-- +--@src/devices/bus/sbus/sbus.h,BUSES["SBUS"] = true +--------------------------------------------------- + +if (BUSES["SBUS"]~=null) then + files { + MAME_DIR .. "src/devices/bus/sbus/artecon.cpp", + MAME_DIR .. "src/devices/bus/sbus/artecon.h", + MAME_DIR .. "src/devices/bus/sbus/bwtwo.cpp", + MAME_DIR .. "src/devices/bus/sbus/bwtwo.h", + MAME_DIR .. "src/devices/bus/sbus/cgsix.cpp", + MAME_DIR .. "src/devices/bus/sbus/cgsix.h", + MAME_DIR .. "src/devices/bus/sbus/cgthree.cpp", + MAME_DIR .. "src/devices/bus/sbus/cgthree.h", + MAME_DIR .. "src/devices/bus/sbus/hme.cpp", + MAME_DIR .. "src/devices/bus/sbus/hme.h", + MAME_DIR .. "src/devices/bus/sbus/sunpc.cpp", + MAME_DIR .. "src/devices/bus/sbus/sunpc.h", + MAME_DIR .. "src/devices/bus/sbus/sbus.cpp", + MAME_DIR .. "src/devices/bus/sbus/sbus.h", + } +end + --------------------------------------------------- -- --@src/devices/bus/ql/exp.h,BUSES["QL"] = true diff --git a/scripts/target/mame/mess.lua b/scripts/target/mame/mess.lua index f282cd26ef3..0c5d956db6e 100644 --- a/scripts/target/mame/mess.lua +++ b/scripts/target/mame/mess.lua @@ -758,6 +758,7 @@ BUSES["GAMEBOY"] = true BUSES["GAMEGEAR"] = true BUSES["GBA"] = true BUSES["GENERIC"] = true +BUSES["GIO64"] = true BUSES["HEXBUS"] = true BUSES["HPHIL"] = true BUSES["HPDIO"] = true @@ -809,6 +810,7 @@ BUSES["RS232"] = true BUSES["S100"] = true BUSES["SAT_CTRL"] = true BUSES["SATURN"] = true +BUSES["SBUS"] = true BUSES["SCSI"] = true BUSES["SCV"] = true BUSES["SEGA8"] = true diff --git a/src/devices/bus/gio64/gio64.cpp b/src/devices/bus/gio64/gio64.cpp new file mode 100644 index 00000000000..179debbc658 --- /dev/null +++ b/src/devices/bus/gio64/gio64.cpp @@ -0,0 +1,182 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + gio64.cpp - SGI GIO64 slot bus and GIO64 device emulation + +***************************************************************************/ + +#include "emu.h" + +// Display boards +#include "newport.h" + +#include "gio64.h" + +void gio64_cards(device_slot_interface &device) +{ + device.option_add("xl8", GIO64_XL8); /* SGI 8-bit XL board */ + device.option_add("xl24", GIO64_XL24); /* SGI 24-bit XL board */ +} + +DEFINE_DEVICE_TYPE(GIO64_SLOT, gio64_slot_device, "gio64_slot", "SGI GIO64 Slot") + +gio64_slot_device::gio64_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : gio64_slot_device(mconfig, GIO64_SLOT, tag, owner, clock) +{ +} + +gio64_slot_device::gio64_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, type, tag, owner, clock) + , device_slot_interface(mconfig, *this) + , m_gio64(*this, finder_base::DUMMY_TAG) +{ +} + +void gio64_slot_device::device_validity_check(validity_checker &valid) const +{ + device_t *const card(get_card_device()); + if (card && !dynamic_cast(card)) + osd_printf_error("Card device %s (%s) does not implement device_gio64_card_interface\n", card->tag(), card->name()); +} + +void gio64_slot_device::device_resolve_objects() +{ + device_gio64_card_interface *const gio64_card(dynamic_cast(get_card_device())); + if (gio64_card) + gio64_card->set_gio64(m_gio64, tag()); +} + +void gio64_slot_device::device_start() +{ + device_t *const card(get_card_device()); + if (card && !dynamic_cast(card)) + throw emu_fatalerror("gio64_slot_device: card device %s (%s) does not implement device_gio64_card_interface\n", card->tag(), card->name()); +} + + +DEFINE_DEVICE_TYPE(GIO64, gio64_device, "gio64", "SGI GIO64 Bus") + +device_memory_interface::space_config_vector gio64_device::memory_space_config() const +{ + return space_config_vector { + std::make_pair(0, &m_space_config) + }; +} + +gio64_device::gio64_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : gio64_device(mconfig, GIO64, tag, owner, clock) +{ +} + +gio64_device::gio64_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, type, tag, owner, clock) + , device_memory_interface(mconfig, *this) + , m_space_config("GIO64 Space", ENDIANNESS_BIG, 64, 32, 0, address_map_constructor()) + , m_maincpu(*this, finder_base::DUMMY_TAG) + , m_hpc3(*this, finder_base::DUMMY_TAG) +{ +} + +void gio64_device::device_resolve_objects() +{ +} + +void gio64_device::device_start() +{ + std::fill(std::begin(m_device_list), std::end(m_device_list), nullptr); + + m_space = &space(0); + m_space->install_readwrite_handler(0x00000000, 0x003fffff, read64_delegate(FUNC(gio64_device::no_gfx_r), this), write64_delegate(FUNC(gio64_device::no_gfx_w), this)); + m_space->install_readwrite_handler(0x00400000, 0x005fffff, read64_delegate(FUNC(gio64_device::no_exp0_r), this), write64_delegate(FUNC(gio64_device::no_exp0_w), this)); + m_space->install_readwrite_handler(0x00600000, 0x009fffff, read64_delegate(FUNC(gio64_device::no_exp1_r), this), write64_delegate(FUNC(gio64_device::no_exp1_w), this)); +} + +READ64_MEMBER(gio64_device::no_gfx_r) { return ~0ULL; } +READ64_MEMBER(gio64_device::no_exp0_r) { return ~0ULL; } +READ64_MEMBER(gio64_device::no_exp1_r) { return ~0ULL; } +WRITE64_MEMBER(gio64_device::no_gfx_w) { } +WRITE64_MEMBER(gio64_device::no_exp0_w) { } +WRITE64_MEMBER(gio64_device::no_exp1_w) { } + +READ64_MEMBER(gio64_device::read) +{ + return m_space->read_qword(offset << 3, mem_mask); +} + +WRITE64_MEMBER(gio64_device::write) +{ + m_space->write_qword(offset << 3, data, mem_mask); +} + +device_gio64_card_interface *gio64_device::get_gio64_card(int slot) +{ + if (slot < 0) + { + return nullptr; + } + + if (m_device_list[slot]) + { + return m_device_list[slot]; + } + + return nullptr; +} + +void gio64_device::add_gio64_card(device_gio64_card_interface::gio64_slot_type_t slot_type, device_gio64_card_interface *card) +{ + m_device_list[slot_type] = card; + card->install_device(); +} + + + +device_gio64_card_interface::device_gio64_card_interface(const machine_config &mconfig, device_t &device) + : device_slot_card_interface(mconfig, device) + , m_gio64(nullptr) + , m_gio64_slottag(nullptr) + , m_slot_type(GIO64_SLOT_COUNT) +{ +} + +device_gio64_card_interface::~device_gio64_card_interface() +{ +} + +void device_gio64_card_interface::interface_validity_check(validity_checker &valid) const +{ +} + +void device_gio64_card_interface::interface_pre_start() +{ + device_slot_card_interface::interface_pre_start(); + + if (!m_gio64) + { + fatalerror("Can't find SGI GIO64 device\n"); + } + + if (GIO64_SLOT_COUNT == m_slot_type) + { + if (!m_gio64->started()) + throw device_missing_dependencies(); + + if (strcmp(m_gio64_slottag, ":gio64_gfx") == 0) + m_slot_type = GIO64_SLOT_GFX; + else if (strcmp(m_gio64_slottag, ":gio64_exp0") == 0) + m_slot_type = GIO64_SLOT_EXP0; + else if (strcmp(m_gio64_slottag, ":gio64_exp1") == 0) + m_slot_type = GIO64_SLOT_EXP1; + else + fatalerror("Slot %s incorrectly named for SGI GIO64 graphics slot\n", m_gio64_slottag); + + m_gio64->add_gio64_card(m_slot_type, this); + } +} + +void device_gio64_card_interface::set_gio64(gio64_device *gio64, const char *slottag) +{ + m_gio64 = gio64; + m_gio64_slottag = slottag; +} diff --git a/src/devices/bus/gio64/gio64.h b/src/devices/bus/gio64/gio64.h new file mode 100644 index 00000000000..9cbea5a3ab1 --- /dev/null +++ b/src/devices/bus/gio64/gio64.h @@ -0,0 +1,165 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + gio64.h - SGI GIO64 slot bus and GIO64 device emulation + +***************************************************************************/ + +#ifndef MAME_BUS_GIO64_GIO64_H +#define MAME_BUS_GIO64_GIO64_H + +#pragma once + +#include "cpu/mips/r4000.h" +#include "machine/hpc3.h" + +class gio64_device; + +class gio64_slot_device : public device_t, public device_slot_interface +{ +public: + // construction/destruction + template + gio64_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&gio64_tag, U &&opts, const char *dflt) + : gio64_slot_device(mconfig, tag, owner, (uint32_t)0) + { + option_reset(); + opts(*this); + set_default_option(dflt); + set_fixed(false); + m_gio64.set_tag(std::forward(gio64_tag)); + } + gio64_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + gio64_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); + + // device-level overrides + virtual void device_validity_check(validity_checker &valid) const override; + virtual void device_resolve_objects() override; + virtual void device_start() override; + + // configuration + required_device m_gio64; + + DECLARE_READ32_MEMBER(timeout_r); + DECLARE_WRITE32_MEMBER(timeout_w); +}; + +DECLARE_DEVICE_TYPE(GIO64_SLOT, gio64_slot_device) + + +// class representing interface-specific live GIO64 card +class device_gio64_card_interface : public device_slot_card_interface +{ + friend class gio64_device; +public: + // construction/destruction + virtual ~device_gio64_card_interface(); + + // inline configuration + void set_gio64(gio64_device *gio64, const char *slottag); + + virtual void mem_map(address_map &map) = 0; + +protected: + device_gio64_card_interface(const machine_config &mconfig, device_t &device); + + enum gio64_slot_type_t : uint32_t + { + GIO64_SLOT_GFX, + GIO64_SLOT_EXP0, + GIO64_SLOT_EXP1, + + GIO64_SLOT_COUNT + }; + + virtual void interface_validity_check(validity_checker &valid) const override; + virtual void interface_pre_start() override; + virtual void install_device() = 0; + + gio64_device &gio64() { assert(m_gio64); return *m_gio64; } + + gio64_device *m_gio64; + const char *m_gio64_slottag; + gio64_slot_type_t m_slot_type; +}; + + +class gio64_device : public device_t, + public device_memory_interface +{ + friend class device_gio64_card_interface; +public: + // construction/destruction + template + gio64_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag, U &&hpc3_tag) + : gio64_device(mconfig, tag, owner, (uint32_t)0) + { + set_cpu_tag(std::forward(cpu_tag)); + set_hpc3_tag(std::forward(hpc3_tag)); + } + + gio64_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + // inline configuration + template void set_cpu_tag(T &&tag) { m_maincpu.set_tag(std::forward(tag)); } + template void set_hpc3_tag(T &&tag) { m_hpc3.set_tag(std::forward(tag)); } + + virtual space_config_vector memory_space_config() const override; + + const address_space_config m_space_config; + + void add_gio64_card(device_gio64_card_interface::gio64_slot_type_t slot_type, device_gio64_card_interface *card); + device_gio64_card_interface *get_gio64_card(int slot); + + template void install_graphics(T &device, void (T::*map)(class address_map &map), uint64_t unitmask = ~u64(0)) + { + m_space->install_device(0x000000, 0x3fffff, device, map, unitmask); + } + + template void install_expansion(int index, T &device, void (T::*map)(class address_map &map), uint64_t unitmask = ~u64(0)) + { + if (index == 0) + m_space->install_device(0x400000, 0x5fffff, device, map, unitmask); + else if (index == 1) + m_space->install_device(0x600000, 0x9fffff, device, map, unitmask); + else + fatalerror("Invalid SGI GIO64 expansion slot index: %d\n", index); + } + + hpc3_base_device* get_hpc3() { return m_hpc3.target(); } + + DECLARE_READ64_MEMBER(read); + DECLARE_WRITE64_MEMBER(write); + +protected: + gio64_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); + + // device-level overrides + virtual void device_resolve_objects() override; + virtual void device_start() override; + + // internal state + required_device m_maincpu; + required_device m_hpc3; + address_space *m_space; + + device_gio64_card_interface *m_device_list[3]; + +private: + DECLARE_READ64_MEMBER(no_gfx_r); + DECLARE_READ64_MEMBER(no_exp0_r); + DECLARE_READ64_MEMBER(no_exp1_r); + DECLARE_WRITE64_MEMBER(no_gfx_w); + DECLARE_WRITE64_MEMBER(no_exp0_w); + DECLARE_WRITE64_MEMBER(no_exp1_w); +}; + +DECLARE_DEVICE_TYPE(GIO64, gio64_device) + + +void gio64_cards(device_slot_interface &device); + +#endif // MAME_BUS_GIO_GIO_H diff --git a/src/devices/bus/gio64/newport.cpp b/src/devices/bus/gio64/newport.cpp new file mode 100644 index 00000000000..6a564fb11cd --- /dev/null +++ b/src/devices/bus/gio64/newport.cpp @@ -0,0 +1,3986 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/* + SGI "Newport" graphics board used in the Indy and some Indigo2s + + Newport is modular, consisting of the following custom chips: + - REX3: Raster Engine, which is basically a blitter which can also draw antialiased lines. + REX also acts as the interface to the rest of the system - all the other chips on + a Newport board are accessed through it. + - RB2: Frame buffer input controller + - RO1: Frame buffer output controller + - XMAP9: Final display generator + - CMAP: Palette mapper + - VC2: Video timing controller / CRTC + + Taken from the Linux Newport driver, slave addresses for Newport devices are: + VC2 0 + Both CMAPs 1 + CMAP 0 2 + CMAP 1 3 + Both XMAPs 4 + XMAP 0 5 + XMAP 1 6 + RAMDAC 7 + VIDEO (CC1) 8 + VIDEO (AB1) 9 +*/ + +#include "emu.h" +#include "newport.h" + +#define LOG_UNKNOWN (1 << 0) +#define LOG_VC2 (1 << 1) +#define LOG_CMAP0 (1 << 2) +#define LOG_CMAP1 (1 << 3) +#define LOG_XMAP0 (1 << 4) +#define LOG_XMAP1 (1 << 5) +#define LOG_REX3 (1 << 6) +#define LOG_COMMANDS (1 << 7) +#define LOG_REJECTS (1 << 8) +#define LOG_ALL (LOG_UNKNOWN | LOG_VC2 | LOG_CMAP0 | LOG_CMAP1 | LOG_XMAP0 | LOG_XMAP1 | LOG_REX3 | LOG_COMMANDS | LOG_REJECTS) + +#define VERBOSE (0)//(LOG_REX3 | LOG_COMMANDS) +#include "logmacro.h" + +DEFINE_DEVICE_TYPE(GIO64_XL8, gio64_xl8_device, "gio64_xl8", "SGI 8-bit XL board") +DEFINE_DEVICE_TYPE(GIO64_XL24, gio64_xl24_device, "gio64_xl24", "SGI 24-bit XL board") + +/*static*/ const uint32_t newport_base_device::s_host_shifts[4] = { 8, 8, 16, 32 }; + +newport_base_device::newport_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t global_mask) + : device_t(mconfig, type, tag, owner, clock) + , device_palette_interface(mconfig, *this) + , device_gio64_card_interface(mconfig, *this) + , m_screen(*this, "screen") + , m_global_mask(global_mask) +{ +} + +gio64_xl8_device::gio64_xl8_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : newport_base_device(mconfig, GIO64_XL8, tag, owner, clock, 0x000000ff) +{ +} + +gio64_xl24_device::gio64_xl24_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : newport_base_device(mconfig, GIO64_XL24, tag, owner, clock, 0xffffffff) +{ +} + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void newport_base_device::device_start() +{ + m_rgbci = make_unique_clear((1280+64) * (1024+64)); + m_olay = make_unique_clear((1280+64) * (1024+64)); + m_pup = make_unique_clear((1280+64) * (1024+64)); + m_cid = make_unique_clear((1280+64) * (1024+64)); + m_vt_table = make_unique_clear(2048 * 2048); + + m_dcb_timeout_timer = timer_alloc(DCB_TIMEOUT); + + save_pointer(NAME(m_rgbci), (1280+64) * (1024+64)); + save_pointer(NAME(m_olay), (1280+64) * (1024+64)); + save_pointer(NAME(m_pup), (1280+64) * (1024+64)); + save_pointer(NAME(m_cid), (1280+64) * (1024+64)); + save_item(NAME(m_vc2.m_vid_entry)); + save_item(NAME(m_vc2.m_cursor_entry)); + save_item(NAME(m_vc2.m_cursor_x)); + save_item(NAME(m_vc2.m_cursor_y)); + save_item(NAME(m_vc2.m_cur_cursor_x)); + save_item(NAME(m_vc2.m_did_entry)); + save_item(NAME(m_vc2.m_scanline_len)); + save_item(NAME(m_vc2.m_ram_addr)); + save_item(NAME(m_vc2.m_vt_frame_ptr)); + save_item(NAME(m_vc2.m_vt_line_ptr)); + save_item(NAME(m_vc2.m_vt_line_run)); + save_item(NAME(m_vc2.m_vt_line_count)); + save_item(NAME(m_vc2.m_cursor_table_ptr)); + save_item(NAME(m_vc2.m_work_cursor_y)); + save_item(NAME(m_vc2.m_did_frame_ptr)); + save_item(NAME(m_vc2.m_did_line_ptr)); + save_item(NAME(m_vc2.m_display_ctrl)); + save_item(NAME(m_vc2.m_config)); + save_item(NAME(m_vc2.m_ram)); + save_item(NAME(m_vc2.m_reg_idx)); + save_item(NAME(m_vc2.m_reg_data)); + + save_item(NAME(m_xmap0.m_config)); + save_item(NAME(m_xmap0.m_revision)); + save_item(NAME(m_xmap0.m_entries)); + save_item(NAME(m_xmap0.m_cursor_cmap)); + save_item(NAME(m_xmap0.m_popup_cmap)); + save_item(NAME(m_xmap0.m_mode_table_idx)); + save_item(NAME(m_xmap0.m_mode_table)); + save_item(NAME(m_xmap1.m_config)); + save_item(NAME(m_xmap1.m_revision)); + save_item(NAME(m_xmap1.m_entries)); + save_item(NAME(m_xmap1.m_cursor_cmap)); + save_item(NAME(m_xmap1.m_popup_cmap)); + save_item(NAME(m_xmap1.m_mode_table_idx)); + save_item(NAME(m_xmap1.m_mode_table)); + + save_item(NAME(m_rex3.m_draw_mode0)); + save_item(NAME(m_rex3.m_color_host)); + save_item(NAME(m_rex3.m_draw_mode1)); + save_item(NAME(m_rex3.m_plane_enable)); + save_item(NAME(m_rex3.m_plane_depth)); + save_item(NAME(m_rex3.m_rwpacked)); + save_item(NAME(m_rex3.m_hostdepth)); + save_item(NAME(m_rex3.m_rwdouble)); + save_item(NAME(m_rex3.m_sfactor)); + save_item(NAME(m_rex3.m_dfactor)); + save_item(NAME(m_rex3.m_logicop)); + save_item(NAME(m_rex3.m_store_shift)); + save_item(NAME(m_rex3.m_write_width)); + save_item(NAME(m_rex3.m_ls_mode)); + save_item(NAME(m_rex3.m_ls_pattern)); + save_item(NAME(m_rex3.m_ls_pattern_saved)); + save_item(NAME(m_rex3.m_z_pattern)); + save_item(NAME(m_rex3.m_color_back)); + save_item(NAME(m_rex3.m_color_vram)); + save_item(NAME(m_rex3.m_alpha_ref)); + save_item(NAME(m_rex3.m_smask_x)); + save_item(NAME(m_rex3.m_smask_y)); + save_item(NAME(m_rex3.m_setup)); + save_item(NAME(m_rex3.m_step_z)); + save_item(NAME(m_rex3.m_x_start)); + save_item(NAME(m_rex3.m_y_start)); + save_item(NAME(m_rex3.m_x_end)); + save_item(NAME(m_rex3.m_y_end)); + save_item(NAME(m_rex3.m_x_start_frac)); + save_item(NAME(m_rex3.m_y_start_frac)); + save_item(NAME(m_rex3.m_x_end_frac)); + save_item(NAME(m_rex3.m_y_end_frac)); + + save_item(NAME(m_rex3.m_x_save)); + save_item(NAME(m_rex3.m_xy_move)); + save_item(NAME(m_rex3.m_x_move)); + save_item(NAME(m_rex3.m_y_move)); + save_item(NAME(m_rex3.m_bres_d)); + save_item(NAME(m_rex3.m_bres_s1)); + save_item(NAME(m_rex3.m_bres_octant_inc1)); + save_item(NAME(m_rex3.m_bres_round_inc2)); + save_item(NAME(m_rex3.m_bres_e1)); + save_item(NAME(m_rex3.m_bres_s2)); + save_item(NAME(m_rex3.m_a_weight0)); + save_item(NAME(m_rex3.m_a_weight1)); + save_item(NAME(m_rex3.m_x_start_f)); + save_item(NAME(m_rex3.m_y_start_f)); + save_item(NAME(m_rex3.m_x_end_f)); + save_item(NAME(m_rex3.m_y_end_f)); + save_item(NAME(m_rex3.m_x_start_i)); + save_item(NAME(m_rex3.m_y_start_i)); + save_item(NAME(m_rex3.m_x_end_i)); + save_item(NAME(m_rex3.m_y_end_i)); + save_item(NAME(m_rex3.m_xy_start_i)); + save_item(NAME(m_rex3.m_xy_end_i)); + save_item(NAME(m_rex3.m_x_start_end_i)); + save_item(NAME(m_rex3.m_color_red)); + save_item(NAME(m_rex3.m_color_alpha)); + save_item(NAME(m_rex3.m_color_green)); + save_item(NAME(m_rex3.m_color_blue)); + save_item(NAME(m_rex3.m_slope_red)); + save_item(NAME(m_rex3.m_slope_alpha)); + save_item(NAME(m_rex3.m_slope_green)); + save_item(NAME(m_rex3.m_slope_blue)); + save_item(NAME(m_rex3.m_write_mask)); + save_item(NAME(m_rex3.m_color_i)); + save_item(NAME(m_rex3.m_zero_overflow)); + save_item(NAME(m_rex3.m_host_dataport)); + save_item(NAME(m_rex3.m_dcb_mode)); + save_item(NAME(m_rex3.m_dcb_reg_select)); + save_item(NAME(m_rex3.m_dcb_slave_select)); + save_item(NAME(m_rex3.m_dcb_data_msw)); + save_item(NAME(m_rex3.m_dcb_data_lsw)); + save_item(NAME(m_rex3.m_top_scanline)); + save_item(NAME(m_rex3.m_xy_window)); + save_item(NAME(m_rex3.m_x_window)); + save_item(NAME(m_rex3.m_y_window)); + save_item(NAME(m_rex3.m_clip_mode)); + save_item(NAME(m_rex3.m_config)); + save_item(NAME(m_rex3.m_status)); + save_item(NAME(m_rex3.m_xfer_width)); + + save_item(NAME(m_cmap0.m_palette_idx)); + save_item(NAME(m_cmap0.m_palette)); + + save_item(NAME(m_readout_x0)); + save_item(NAME(m_readout_y0)); + save_item(NAME(m_readout_x1)); + save_item(NAME(m_readout_y1)); + + save_item(NAME(m_ramdac_lut_r)); + save_item(NAME(m_ramdac_lut_g)); + save_item(NAME(m_ramdac_lut_b)); + save_item(NAME(m_ramdac_lut_index)); +} + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void newport_base_device::device_reset() +{ + memset(&m_vc2, 0, sizeof(vc2_t)); + memset(&m_xmap0, 0, sizeof(xmap_t)); + memset(&m_xmap1, 0, sizeof(xmap_t)); + memset(&m_rex3, 0, sizeof(rex3_t)); + memset(&m_cmap0, 0, sizeof(cmap_t)); + memset(m_ramdac_lut_r, 0, sizeof(uint32_t) * 256); + memset(m_ramdac_lut_g, 0, sizeof(uint32_t) * 256); + memset(m_ramdac_lut_b, 0, sizeof(uint32_t) * 256); + + m_rex3.m_draw_mode0 = 0x00000000; + m_rex3.m_draw_mode1 = 0x3002f001; + m_rex3.m_dcb_mode = 0x00000780; + m_rex3.m_x_window = 0x1000; + m_rex3.m_y_window = 0x1000; + + m_xmap0.m_entries = 0x2; + m_xmap1.m_entries = 0x2; + + m_readout_x0 = 0; + m_readout_y0 = 0; + m_readout_x1 = 0; + m_readout_y1 = 0; + +#if ENABLE_NEWVIEW_LOG + m_newview_log = nullptr; +#endif +} + +void newport_base_device::mem_map(address_map &map) +{ + map(0x000f0000, 0x000f1fff).rw(FUNC(newport_base_device::rex3_r), FUNC(newport_base_device::rex3_w)); +} + +#if ENABLE_NEWVIEW_LOG +void newport_base_device::start_logging() +{ + uint16_t log_index = 0xffff; + char log_name_buf[128]; + FILE *log_test = nullptr; + do + { + log_index++; + snprintf(log_name_buf, 128, "newview%04d.log", log_index); + log_test = fopen(log_name_buf, "rb"); + } while(log_test != nullptr); + + m_newview_log = fopen(log_name_buf, "wb"); + + popmessage("Recording Newport to %s", log_name_buf); + + fwrite(&m_vc2, sizeof(vc2_t), 1, m_newview_log); + fwrite(&m_xmap0, sizeof(xmap_t), 1, m_newview_log); + fwrite(&m_xmap1, sizeof(xmap_t), 1, m_newview_log); + fwrite(&m_rex3, sizeof(rex3_t), 1, m_newview_log); + fwrite(&m_cmap0, sizeof(cmap_t), 1, m_newview_log); + fwrite(&m_rgbci[0], sizeof(uint32_t), (1280+64)*(1024+64), m_newview_log); + fwrite(&m_olay[0], sizeof(uint32_t), (1280+64)*(1024+64), m_newview_log); + fwrite(&m_pup[0], sizeof(uint32_t), (1280+64)*(1024+64), m_newview_log); + fwrite(&m_cid[0], sizeof(uint32_t), (1280+64)*(1024+64), m_newview_log); +} + +void newport_base_device::stop_logging() +{ + popmessage("Newport recording stopped."); + fclose(m_newview_log); + m_newview_log = nullptr; +} +#endif + +void newport_base_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) +{ + if (id == DCB_TIMEOUT) + { + m_rex3.m_status &= ~STATUS_BACKBUSY; + } +} + +uint8_t newport_base_device::get_cursor_pixel(int x, int y) +{ + if (x < 0 || y < 0) + return 0; + + bool monochrome_cursor = BIT(m_vc2.m_display_ctrl, DCR_CURSOR_SIZE_BIT) == DCR_CURSOR_SIZE_64; + + int size = monochrome_cursor ? 64 : 32; + if (x >= size || y >= size) + return 0; + + const int shift = 15 - (x % 16); + + if (monochrome_cursor) + { + const int address = y * 4 + (x / 16); + const uint16_t word = m_vc2.m_ram[m_vc2.m_cursor_entry + address]; + return BIT(word, shift); + } + else + { + const int address = y * 2 + (x / 16); + const uint16_t word0 = m_vc2.m_ram[m_vc2.m_cursor_entry + address]; + const uint16_t word1 = m_vc2.m_ram[m_vc2.m_cursor_entry + address + 64]; + return BIT(word0, shift) | (BIT(word1, shift) << 1); + } +} + +uint32_t newport_base_device::screen_update(screen_device &device, bitmap_rgb32 &bitmap, const rectangle &cliprect) +{ + bool enable_cursor = BIT(m_vc2.m_display_ctrl, DCR_CURSOR_FUNC_ENABLE_BIT) != 0 + && BIT(m_vc2.m_display_ctrl, DCR_CURSOR_ENABLE_BIT) != 0 + && BIT(m_vc2.m_display_ctrl, DCR_CURSOR_MODE_BIT) == DCR_CURSOR_MODE_GLYPH; + + const uint16_t cursor_msb = (uint16_t)m_xmap0.m_cursor_cmap << 5; + const uint16_t popup_msb = (uint16_t)m_xmap0.m_popup_cmap << 5; + + /* loop over rows and copy to the destination */ + for (int y = cliprect.min_y, sy = m_readout_y0; y <= cliprect.max_y && sy < m_readout_y1; y++, sy++) + //for (int y = cliprect.min_y; y <= cliprect.max_y; y++) + { + uint32_t *dest = &bitmap.pix32(y, cliprect.min_x); + //uint32_t *src = &m_vt_table[y * 2048]; + uint32_t *src_ci = &m_rgbci[1344 * y]; + uint32_t *src_pup = &m_pup[1344 * y]; + uint32_t *src_olay = &m_pup[1344 * y]; + + m_vc2.m_did_frame_ptr = m_vc2.m_did_entry + (uint16_t)y; + m_vc2.m_did_line_ptr = m_vc2.m_ram[m_vc2.m_did_frame_ptr]; + + // Fetch the initial DID entry + uint16_t curr_did_entry = m_vc2.m_ram[m_vc2.m_did_line_ptr]; + uint32_t table_entry = m_xmap0.m_mode_table[curr_did_entry & 0x1f]; + uint8_t pix_mode = (table_entry >> 8) & 3; + uint8_t pix_size = (table_entry >> 10) & 3; + uint8_t aux_pix_mode = (table_entry >> 16) & 7; + uint16_t aux_msb = (table_entry >> 11) & 0x1f00; + uint16_t ci_msb = 0; + switch ((table_entry >> 8) & 3) + { + case 0: ci_msb = (m_xmap0.m_mode_table[curr_did_entry & 0x1f] & 0xf8) << 5; break; + case 1: ci_msb = 0x1d00; break; + case 2: ci_msb = 0x1e00; break; + case 3: ci_msb = 0x1f00; break; + } + + // Prepare for the next DID entry + m_vc2.m_did_line_ptr++; + curr_did_entry = m_vc2.m_ram[m_vc2.m_did_line_ptr]; + + // loop over columns + for (int x = cliprect.min_x; x < cliprect.max_x; x++) + { + //*dest++ = *src++; + if ((uint16_t)x == (curr_did_entry >> 5)) + { + table_entry = m_xmap0.m_mode_table[curr_did_entry & 0x1f]; + pix_mode = (table_entry >> 8) & 3; + pix_size = (table_entry >> 10) & 3; + aux_pix_mode = (table_entry >> 16) & 7; + aux_msb = (table_entry >> 11) & 0x1f00; + switch ((table_entry >> 8) & 3) + { + case 0: ci_msb = (m_xmap0.m_mode_table[curr_did_entry & 0x1f] & 0xf8) << 5; break; + case 1: ci_msb = 0x1d00; break; + case 2: ci_msb = 0x1e00; break; + case 3: ci_msb = 0x1f00; break; + } + m_vc2.m_did_line_ptr++; + curr_did_entry = m_vc2.m_ram[m_vc2.m_did_line_ptr]; + } + uint8_t cursor_pixel = 0; + if (x >= (m_vc2.m_cursor_x - 31) && x <= m_vc2.m_cursor_x && y >= (m_vc2.m_cursor_y - 31) && y <= m_vc2.m_cursor_y && enable_cursor) + { + cursor_pixel = get_cursor_pixel(x - ((int)m_vc2.m_cursor_x - 31), y - ((int)m_vc2.m_cursor_y - 31)); + } + + bool pixel_replaced = false; + if (cursor_pixel) + { + *dest++ = m_cmap0.m_palette[cursor_msb | cursor_pixel]; + pixel_replaced = true; + } + else if (*src_pup) + { + const uint32_t src = (*src_pup >> 2) & 3; + *dest++ = m_cmap0.m_palette[popup_msb | src]; + pixel_replaced = true; + } + else if (aux_pix_mode != 0) + { + if (BIT(m_xmap0.m_config, 2)) + { + switch (aux_pix_mode) + { + case 1: // 2-Bit Underlay + *dest++ = m_cmap0.m_palette[aux_msb | ((*src_olay >> 8) & 3)]; + pixel_replaced = true; + continue; + case 2: // 2-Bit Overlay + { + const uint32_t pix_in = (*src_olay >> 8) & 3; + if (pix_in) + { + *dest++ = m_cmap0.m_palette[aux_msb | pix_in]; + pixel_replaced = true; + } + break; + } + case 6: // 1-Bit Overlay + { + const uint32_t shift = BIT(table_entry, 1) ? 9 : 8; + const uint32_t pix_in = (*src_olay >> shift) & 1; + if (pix_in) + { + *dest++ = m_cmap0.m_palette[aux_msb | pix_in]; + pixel_replaced = true; + } + break; + } + case 7: // 1-Bit Overlay, 1-Bit Underlay + { + const uint32_t pix_in = (*src_olay >> 8) & 1; + if (pix_in) + *dest++ = m_cmap0.m_palette[aux_msb | pix_in]; + else + *dest++ = m_cmap0.m_palette[aux_msb | ((*src_olay >> 9) & 1)]; + pixel_replaced = true; + break; + } + default: + break; + } + } + else + { + switch (aux_pix_mode) + { + case 1: // 8-Bit Underlay + *dest++ = m_cmap0.m_palette[aux_msb | ((*src_olay >> 8) & 0xff)]; + pixel_replaced = true; + break; + case 2: // 8-Bit Overlay + { + const uint32_t pix_in = (*src_olay >> 8) & 0xff; + if (pix_in) + { + *dest++ = m_cmap0.m_palette[aux_msb | pix_in]; + pixel_replaced = true; + } + break; + } + case 6: // 4-Bit Overlay + { + const uint32_t shift = BIT(table_entry, 1) ? 12 : 8; + const uint32_t pix_in = (*src_olay >> shift) & 0xf; + if (pix_in) + { + *dest++ = m_cmap0.m_palette[aux_msb | pix_in]; + pixel_replaced = true; + } + break; + } + case 7: // 4-Bit Overlay, 4-Bit Underlay + { + const uint32_t pix_in = (*src_pup >> 8) & 0xf; + if (pix_in) + *dest++ = m_cmap0.m_palette[aux_msb | pix_in]; + else + *dest++ = m_cmap0.m_palette[aux_msb | ((*src_pup >> 12) & 0xf)]; + pixel_replaced = true; + break; + } + default: + break; + } + } + } + + if (!pixel_replaced) + { + switch (pix_mode) + { + case 0: // CI + switch (pix_size) + { + case 0: // 4bpp + { + const uint8_t shift = BIT(table_entry, 0) ? 4 : 0; + const uint32_t pix_in = *src_ci; + *dest++ = m_cmap0.m_palette[ci_msb | ((pix_in >> shift) & 0x0f)]; + break; + } + case 1: // 8bpp + *dest++ = m_cmap0.m_palette[ci_msb | (uint8_t)*src_ci]; + break; + case 2: // 12bpp + { + const uint8_t shift = BIT(table_entry, 0) ? 12 : 0; + const uint32_t pix_in = (*src_ci >> shift) & 0x00000fff; + *dest++ = m_cmap0.m_palette[(ci_msb & 0x1000) | pix_in]; + break; + } + case 3: // 24bpp (not yet supported) + dest++; + break; + } + break; + case 1: // RGB Map0 + switch (pix_size) + { + case 0: // 4bpp + { + const uint8_t shift = BIT(table_entry, 0) ? 4 : 0; + const uint8_t pix_in = (uint8_t)(*src_ci >> shift); + *dest++ = convert_4bpp_bgr_to_24bpp_rgb(pix_in); + break; + } + case 1: // 8bpp + { + const uint8_t shift = BIT(table_entry, 0) ? 8 : 0; + const uint8_t pix_in = (uint8_t)(*src_ci >> shift); + *dest++ = convert_8bpp_bgr_to_24bpp_rgb(pix_in); + break; + } + case 2: // 12bpp + { + const uint8_t shift = BIT(table_entry, 0) ? 12 : 0; + const uint16_t pix_in = (uint16_t)(*src_ci >> shift); + *dest++ = convert_12bpp_bgr_to_24bpp_rgb(pix_in); + break; + } + case 3: // 24bpp + { + const uint32_t pix_in = (uint32_t)*src_ci; + const uint8_t r = (uint8_t)(pix_in >> 0); + const uint8_t g = (uint8_t)(pix_in >> 8); + const uint8_t b = (uint8_t)(pix_in >> 16); + *dest++ = (r << 16) | (g << 8) | b; + break; + } + } + break; + case 2: // RGB Map1 (not yet supported) + *dest++ = 0xff00ff; + break; + case 3: // RGB Map2 (not yet supported) + *dest++ = 0x00ff00; + break; + } + } + + ramdac_remap(dest - 1); + + src_ci++; + src_pup++; + src_olay++; + } + } + +#if ENABLE_NEWVIEW_LOG + if (machine().input().code_pressed_once(KEYCODE_TILDE)) + { + if (m_newview_log == nullptr) + start_logging(); + else + stop_logging(); + } +#endif + + return 0; +} + +void newport_base_device::ramdac_remap(uint32_t *dest) +{ + uint32_t out = 0xff000000; + out |= m_ramdac_lut_r[(uint8_t)(*dest >> 16)]; + out |= m_ramdac_lut_g[(uint8_t)(*dest >> 8)]; + out |= m_ramdac_lut_b[(uint8_t)(*dest >> 0)]; + *dest = out; +} + +uint32_t newport_base_device::convert_4bpp_bgr_to_8bpp(uint8_t pix_in) +{ + const uint8_t r = 0xff * BIT(pix_in, 0); + const uint8_t g = (0xaa * BIT(pix_in, 2)) | (0x55 * BIT(pix_in, 1)); + const uint8_t b = 0xff * BIT(pix_in, 3); + return (b & 0xc0) | ((g & 0xe0) >> 2) | ((r & 0xe0) >> 5); +} + +uint32_t newport_base_device::convert_4bpp_bgr_to_12bpp(uint8_t pix_in) +{ + const uint32_t r = 0xff * BIT(pix_in, 0); + const uint32_t g = (0xaa * BIT(pix_in, 2)) | (0x55 * BIT(pix_in, 1)); + const uint32_t b = 0xff * BIT(pix_in, 3); + return ((b & 0xf0) << 4) | (g & 0xf0) | ((r & 0xf0) >> 4); +} + +uint32_t newport_base_device::convert_4bpp_bgr_to_24bpp(uint8_t pix_in) +{ + const uint8_t r = 0xff * BIT(pix_in, 0); + const uint8_t g = (0xaa * BIT(pix_in, 2)) | (0x55 * BIT(pix_in, 1)); + const uint8_t b = 0xff * BIT(pix_in, 3); + return (b << 16) | (g << 8) | r; +} + +uint32_t newport_base_device::convert_8bpp_bgr_to_4bpp(uint8_t pix_in) +{ + const uint8_t r = (0x92 * BIT(pix_in, 2)) | (0x49 * BIT(pix_in, 1)) | (0x24 * BIT(pix_in, 0)); + const uint8_t g = (0x92 * BIT(pix_in, 5)) | (0x49 * BIT(pix_in, 4)) | (0x24 * BIT(pix_in, 3)); + const uint8_t b = (0xaa * BIT(pix_in, 7)) | (0x55 * BIT(pix_in, 6)); + return (BIT(b, 7) << 3) | ((g & 0xc0) >> 5) | BIT(r, 7); +} + +uint32_t newport_base_device::convert_8bpp_bgr_to_12bpp(uint8_t pix_in) +{ + const uint8_t r = (0x92 * BIT(pix_in, 2)) | (0x49 * BIT(pix_in, 1)) | (0x24 * BIT(pix_in, 0)); + const uint8_t g = (0x92 * BIT(pix_in, 5)) | (0x49 * BIT(pix_in, 4)) | (0x24 * BIT(pix_in, 3)); + const uint8_t b = (0xaa * BIT(pix_in, 7)) | (0x55 * BIT(pix_in, 6)); + return ((b & 0xf0) << 4) | (g & 0xf0) | ((r & 0xf0) >> 4); +} + +uint32_t newport_base_device::convert_8bpp_bgr_to_24bpp(uint8_t pix_in) +{ + const uint8_t r = (0x92 * BIT(pix_in, 2)) | (0x49 * BIT(pix_in, 1)) | (0x24 * BIT(pix_in, 0)); + const uint8_t g = (0x92 * BIT(pix_in, 5)) | (0x49 * BIT(pix_in, 4)) | (0x24 * BIT(pix_in, 3)); + const uint8_t b = (0xaa * BIT(pix_in, 7)) | (0x55 * BIT(pix_in, 6)); + return (b << 16) | (g << 8) | r; +} + +uint32_t newport_base_device::convert_12bpp_bgr_to_4bpp(uint16_t pix_in) +{ + const uint8_t r = 0x11 * ((pix_in >> 0) & 0xf); + const uint8_t g = 0x11 * ((pix_in >> 4) & 0xf); + const uint8_t b = 0x11 * ((pix_in >> 8) & 0xf); + return (BIT(b, 7) << 3) | ((g & 0xc0) >> 5) | BIT(r, 7); +} + +uint32_t newport_base_device::convert_12bpp_bgr_to_8bpp(uint16_t pix_in) +{ + const uint8_t r = 0x11 * ((pix_in >> 0) & 0xf); + const uint8_t g = 0x11 * ((pix_in >> 4) & 0xf); + const uint8_t b = 0x11 * ((pix_in >> 8) & 0xf); + return (b & 0xc0) | ((g & 0xe0) >> 2) | ((r & 0xe0) >> 5); +} + +uint32_t newport_base_device::convert_12bpp_bgr_to_24bpp(uint16_t pix_in) +{ + const uint8_t r = 0x11 * ((pix_in >> 0) & 0xf); + const uint8_t g = 0x11 * ((pix_in >> 4) & 0xf); + const uint8_t b = 0x11 * ((pix_in >> 8) & 0xf); + return (b << 16) | (g << 8) | r; +} + +uint32_t newport_base_device::convert_24bpp_bgr_to_4bpp(uint32_t pix_in) +{ + const uint8_t r = (uint8_t)(pix_in >> 0); + const uint8_t g = (uint8_t)(pix_in >> 8); + const uint8_t b = (uint8_t)(pix_in >> 16); + return (BIT(b, 7) << 3) | ((g & 0xc0) >> 5) | BIT(r, 7); +} + +uint32_t newport_base_device::convert_24bpp_bgr_to_8bpp(uint32_t pix_in) +{ + const uint8_t r = (uint8_t)(pix_in >> 0); + const uint8_t g = (uint8_t)(pix_in >> 8); + const uint8_t b = (uint8_t)(pix_in >> 16); + return (b & 0xc0) | ((g & 0xe0) >> 2) | ((r & 0xe0) >> 5); +} + +uint32_t newport_base_device::convert_24bpp_bgr_to_12bpp(uint32_t pix_in) +{ + const uint8_t r = (uint8_t)(pix_in >> 0); + const uint8_t g = (uint8_t)(pix_in >> 8); + const uint8_t b = (uint8_t)(pix_in >> 16); + return ((b & 0xf0) << 4) | (g & 0xf0) | ((r & 0xf0) >> 4); +} + +uint32_t newport_base_device::convert_4bpp_bgr_to_24bpp_rgb(uint8_t pix_in) +{ + const uint8_t r = 0xff * BIT(pix_in, 0); + const uint8_t g = (0xaa * BIT(pix_in, 2)) | (0x55 * BIT(pix_in, 1)); + const uint8_t b = 0xff * BIT(pix_in, 3); + return (r << 16) | (g << 8) | b; +} + +uint32_t newport_base_device::convert_8bpp_bgr_to_24bpp_rgb(uint8_t pix_in) +{ + const uint8_t r = (0x92 * BIT(pix_in, 2)) | (0x49 * BIT(pix_in, 1)) | (0x24 * BIT(pix_in, 0)); + const uint8_t g = (0x92 * BIT(pix_in, 5)) | (0x49 * BIT(pix_in, 4)) | (0x24 * BIT(pix_in, 3)); + const uint8_t b = (0xaa * BIT(pix_in, 7)) | (0x55 * BIT(pix_in, 6)); + return (r << 16) | (g << 8) | b; +} + +uint32_t newport_base_device::convert_12bpp_bgr_to_24bpp_rgb(uint16_t pix_in) +{ + const uint8_t r = 0x11 * ((pix_in >> 0) & 0xf); + const uint8_t g = 0x11 * ((pix_in >> 4) & 0xf); + const uint8_t b = 0x11 * ((pix_in >> 8) & 0xf); + return (r << 16) | (g << 8) | b; +} + +void newport_base_device::ramdac_write(uint32_t data) +{ + switch (m_rex3.m_dcb_reg_select) + { + case 0: + m_ramdac_lut_index = (uint8_t)data; + break; + case 1: + m_ramdac_lut_r[m_ramdac_lut_index] = (uint8_t)(data >> 8) << 16; + m_ramdac_lut_g[m_ramdac_lut_index] = (uint8_t)(data >> 16) << 8; + m_ramdac_lut_b[m_ramdac_lut_index] = (uint8_t)(data >> 24) << 0; + m_ramdac_lut_index++; + break; + } +} + +void newport_base_device::cmap0_write(uint32_t data) +{ + switch (m_rex3.m_dcb_reg_select) + { + case 0x00: + LOGMASKED(LOG_CMAP0, "CMAP0 Palette Index Write: %04x\n", data & 0xffff); + m_cmap0.m_palette_idx = (uint16_t)data; + break; + case 0x02: + m_cmap0.m_palette[m_cmap0.m_palette_idx] = data >> 8; + if (m_cmap0.m_palette_idx < 0x2000) + set_pen_color(m_cmap0.m_palette_idx, rgb_t((uint8_t)(data >> 24), (uint8_t)(data >> 16), (uint8_t)(data >> 8))); + LOGMASKED(LOG_CMAP0, "CMAP0 Palette Entry %04x Write: %08x\n", m_cmap0.m_palette_idx, data >> 8); + break; + default: + LOGMASKED(LOG_CMAP0 | LOG_UNKNOWN, "Unknown CMAP0 Register %d Write: %08x\n", m_rex3.m_dcb_reg_select, data); + break; + } +} + +uint32_t newport_base_device::cmap0_read() +{ + switch (m_rex3.m_dcb_reg_select) + { + case 0x04: + LOGMASKED(LOG_CMAP0, "CMAP0 Status Read: %08x\n", 0x8); + return 0x8; + case 0x06: /* Revision */ + { + const uint32_t ret = get_cmap_revision();; + LOGMASKED(LOG_CMAP0, "CMAP0 Revision Read: %08x\n", ret); + return ret; + } + default: + LOGMASKED(LOG_CMAP0 | LOG_UNKNOWN, "Unknown CMAP0 Register %d Read\n", m_rex3.m_dcb_reg_select); + return 0; + } +} + +uint32_t newport_base_device::cmap1_read() +{ + switch (m_rex3.m_dcb_reg_select) + { + case 0x04: + LOGMASKED(LOG_CMAP1, "CMAP1 Status Read: %08x\n", 0x8); + return 0x8; + case 0x06: /* Revision */ + { + const uint32_t ret = get_cmap_revision();; + LOGMASKED(LOG_CMAP1, "CMAP1 Revision Read: %08x\n", ret); + return ret; + } + default: + LOGMASKED(LOG_CMAP1 | LOG_UNKNOWN, "Unknown CMAP0 Register %d Read\n", m_rex3.m_dcb_reg_select); + return 0; + } +} + +uint32_t gio64_xl8_device::get_cmap_revision() +{ + return 0xa1; +} + +uint32_t gio64_xl24_device::get_cmap_revision() +{ + return 0x02; +} + +uint32_t newport_base_device::xmap0_read() +{ + switch (m_rex3.m_dcb_reg_select) + { + case 0: + LOGMASKED(LOG_XMAP0, "XMAP0 Config Read: %08x\n", m_xmap0.m_config); + return m_xmap0.m_config; + case 1: + { + const uint32_t ret = get_xmap_revision(); + LOGMASKED(LOG_XMAP0, "XMAP0 Revision Read: %08x\n", ret); + return ret; + } + case 2: + LOGMASKED(LOG_XMAP0, "XMAP0 FIFO Availability Read: %08x\n", 0x2); + return 0x2; + case 3: + LOGMASKED(LOG_XMAP0, "XMAP0 Cursor CMAP MSB Read: %08x\n", m_xmap0.m_cursor_cmap); + return m_xmap0.m_cursor_cmap; + case 4: + LOGMASKED(LOG_XMAP0, "XMAP0 Pop Up CMAP MSB Read: %08x\n", m_xmap0.m_popup_cmap); + return m_xmap0.m_popup_cmap; + case 5: + { + uint8_t mode_idx = (m_xmap0.m_mode_table_idx & 0x7c) >> 2; + switch (m_xmap0.m_mode_table_idx & 3) + { + case 0: + { + uint8_t ret = (uint8_t)(m_xmap0.m_mode_table[mode_idx] >> 16); + LOGMASKED(LOG_XMAP0, "XMAP0 Mode Register Read: %02x (Byte 0): %08x\n", mode_idx, ret); + return ret; + } + case 1: + { + uint8_t ret = (uint8_t)(m_xmap0.m_mode_table[mode_idx] >> 8); + LOGMASKED(LOG_XMAP0, "XMAP0 Mode Register Read: %02x (Byte 1): %08x\n", mode_idx, ret); + return ret; + } + case 2: + { + uint8_t ret = (uint8_t)m_xmap0.m_mode_table[mode_idx]; + LOGMASKED(LOG_XMAP0, "XMAP0 Mode Register Read: %02x (Byte 2): %08x\n", mode_idx, ret); + return ret; + } + } + break; + } + case 6: + LOGMASKED(LOG_XMAP0, "XMAP0 Unused Read: %08x\n", 0); + return 0; + case 7: + LOGMASKED(LOG_XMAP0, "XMAP0 Mode Table Address Read: %08x\n", m_xmap0.m_mode_table_idx); + return m_xmap0.m_mode_table_idx; + default: + LOGMASKED(LOG_XMAP0 | LOG_UNKNOWN, "XMAP0 Unknown DCB Register Select Value: %02x, returning 0\n", m_rex3.m_dcb_reg_select); + return 0; + } + return 0; +} + +void newport_base_device::xmap0_write(uint32_t data) +{ + switch (m_rex3.m_dcb_reg_select) + { + case 0: + LOGMASKED(LOG_XMAP0, "XMAP0 Config Write: %02x\n", (uint8_t)data); + m_xmap0.m_config = (uint8_t)data; + break; + case 1: + LOGMASKED(LOG_XMAP0, "XMAP0 Revision Write (Ignored): %02x\n", (uint8_t)data); + break; + case 2: + LOGMASKED(LOG_XMAP0, "XMAP0 FIFO Availability Write (Ignored): %02x\n", (uint8_t)data); + break; + case 3: + LOGMASKED(LOG_XMAP0, "XMAP0 Cursor CMAP MSB Write: %02x\n", (uint8_t)data); + m_xmap0.m_cursor_cmap = (uint8_t)data; + break; + case 4: + LOGMASKED(LOG_XMAP0, "XMAP0 Pop Up CMAP MSB Write: %02x\n", (uint8_t)data); + m_xmap0.m_popup_cmap = (uint8_t)data; + break; + case 5: + LOGMASKED(LOG_XMAP0, "XMAP0 Mode Register Write: %02x = %06x\n", data >> 24, data & 0xffffff); + m_xmap0.m_mode_table[data >> 24] = data & 0xffffff; + break; + case 6: + LOGMASKED(LOG_XMAP0, "XMAP0 Unused Write (Ignored): %08x\n", data); + break; + case 7: + LOGMASKED(LOG_XMAP0, "XMAP0 Mode Table Address Write: %02x\n", (uint8_t)data); + m_xmap0.m_mode_table_idx = (uint8_t)data; + break; + default: + LOGMASKED(LOG_XMAP0 | LOG_UNKNOWN, "XMAP0 Unknown DCB Register Select Value: %02x = %08x\n", m_rex3.m_dcb_reg_select, data); + break; + } +} + +uint32_t newport_base_device::xmap1_read() +{ + switch (m_rex3.m_dcb_reg_select) + { + case 0: + LOGMASKED(LOG_XMAP1, "XMAP1 Config Read: %08x\n", m_xmap1.m_config); + return m_xmap1.m_config; + case 1: + { + const uint32_t ret = get_xmap_revision(); + LOGMASKED(LOG_XMAP1, "XMAP1 Revision Read: %08x\n", ret); + return ret; + } + case 2: + LOGMASKED(LOG_XMAP1, "XMAP1 FIFO Availability Read: %08x\n", 0x02); + return 0x2; + case 3: + LOGMASKED(LOG_XMAP1, "XMAP1 Cursor CMAP MSB Read: %08x\n", m_xmap1.m_cursor_cmap); + return m_xmap1.m_cursor_cmap; + case 4: + LOGMASKED(LOG_XMAP1, "XMAP1 Pop Up CMAP MSB Read: %08x\n", m_xmap1.m_popup_cmap); + return m_xmap1.m_popup_cmap; + case 5: + { + const uint8_t mode_idx = (m_xmap1.m_mode_table_idx & 0x7c) >> 2; + switch (m_xmap1.m_mode_table_idx & 3) + { + case 0: + { + uint8_t ret = (uint8_t)(m_xmap1.m_mode_table[mode_idx] >> 16); + LOGMASKED(LOG_XMAP1, "XMAP1 Mode Register Read: %02x (Byte 0): %08x\n", mode_idx, ret); + return ret; + } + case 1: + { + uint8_t ret = (uint8_t)(m_xmap1.m_mode_table[mode_idx] >> 8); + LOGMASKED(LOG_XMAP1, "XMAP1 Mode Register Read: %02x (Byte 1): %08x\n", mode_idx, ret); + return ret; + } + case 2: + { + uint8_t ret = (uint8_t)m_xmap1.m_mode_table[mode_idx]; + LOGMASKED(LOG_XMAP1, "XMAP1 Mode Register Read: %02x (Byte 2): %08x\n", mode_idx, ret); + return ret; + } + } + break; + } + case 6: + LOGMASKED(LOG_XMAP1, "XMAP1 Unused Read: %08x\n", 0); + return 0; + case 7: + LOGMASKED(LOG_XMAP1, "XMAP1 Mode Table Address Read: %08x\n", m_xmap0.m_mode_table_idx); + return m_xmap1.m_mode_table_idx; + default: + LOGMASKED(LOG_XMAP1 | LOG_UNKNOWN, "XMAP1 Unknown DCB Register Select Value: %02x, returning 0\n", m_rex3.m_dcb_reg_select); + return 0; + } + return 0; +} + +void newport_base_device::xmap1_write(uint32_t data) +{ + switch (m_rex3.m_dcb_reg_select) + { + case 0: + LOGMASKED(LOG_XMAP1, "XMAP1 Config Write: %02x\n", (uint8_t)data); + m_xmap1.m_config = (uint8_t)data; + break; + case 1: + LOGMASKED(LOG_XMAP1, "XMAP1 Revision Write (Ignored): %02x\n", (uint8_t)data); + break; + case 2: + LOGMASKED(LOG_XMAP1, "XMAP1 FIFO Availability Write (Ignored): %02x\n", (uint8_t)data); + break; + case 3: + LOGMASKED(LOG_XMAP1, "XMAP1 Cursor CMAP MSB Write: %02x\n", (uint8_t)data); + m_xmap1.m_cursor_cmap = (uint8_t)data; + break; + case 4: + LOGMASKED(LOG_XMAP1, "XMAP1 Pop Up CMAP MSB Write: %02x\n", (uint8_t)data); + m_xmap1.m_popup_cmap = (uint8_t)data; + break; + case 5: + LOGMASKED(LOG_XMAP1, "XMAP1 Mode Register Write: %02x = %06x\n", data >> 24, data & 0xffffff); + m_xmap1.m_mode_table[data >> 24] = data & 0xffffff; + break; + case 6: + LOGMASKED(LOG_XMAP1, "XMAP1 Unused Write (Ignored): %08x\n", data); + break; + case 7: + LOGMASKED(LOG_XMAP1, "XMAP1 Mode Table Address Write: %02x\n", (uint8_t)data); + m_xmap1.m_mode_table_idx = (uint8_t)data; + break; + default: + LOGMASKED(LOG_XMAP0 | LOG_UNKNOWN, "XMAP0 Unknown DCB Register Select Value: %02x = %08x\n", m_rex3.m_dcb_reg_select, data); + break; + } +} + +uint32_t gio64_xl8_device::get_xmap_revision() +{ + return 1; +} + +uint32_t gio64_xl24_device::get_xmap_revision() +{ + return 3; +} + +uint32_t newport_base_device::vc2_read() +{ + switch (m_rex3.m_dcb_reg_select) + { + case 0x01: /* Register Read */ + switch (m_vc2.m_reg_idx) + { + case 0x00: + LOGMASKED(LOG_VC2, "VC2 Register Read: Video Entry Pointer, %08x\n", m_vc2.m_vid_entry); + return m_vc2.m_vid_entry; + case 0x01: + LOGMASKED(LOG_VC2, "VC2 Register Read: Cursor Entry Pointer, %08x\n", m_vc2.m_cursor_entry); + return m_vc2.m_cursor_entry; + case 0x02: + LOGMASKED(LOG_VC2, "VC2 Register Read: Cursor X, %08x\n", m_vc2.m_cursor_x); + return m_vc2.m_cursor_x; + case 0x03: + LOGMASKED(LOG_VC2, "VC2 Register Read: Cursor Y, %08x\n", m_vc2.m_cursor_y); + return m_vc2.m_cursor_y; + case 0x04: + LOGMASKED(LOG_VC2, "VC2 Register Read: Current Cursor X, %08x\n", m_vc2.m_cur_cursor_x); + return m_vc2.m_cur_cursor_x; + case 0x05: + LOGMASKED(LOG_VC2, "VC2 Register Read: DID Entry, %08x\n", m_vc2.m_did_entry); + return m_vc2.m_did_entry; + case 0x06: + LOGMASKED(LOG_VC2, "VC2 Register Read: Scanline Length, %08x\n", m_vc2.m_scanline_len); + return m_vc2.m_scanline_len; + case 0x07: + LOGMASKED(LOG_VC2, "VC2 Register Read: RAM Address, %08x\n", m_vc2.m_ram_addr); + return m_vc2.m_ram_addr; + case 0x08: + LOGMASKED(LOG_VC2, "VC2 Register Read: VT Frame Pointer, %08x\n", m_vc2.m_vt_frame_ptr); + return m_vc2.m_vt_frame_ptr; + case 0x09: + LOGMASKED(LOG_VC2, "VC2 Register Read: VT Line Sequence Pointer, %08x\n", m_vc2.m_vt_line_ptr); + return m_vc2.m_vt_line_ptr; + case 0x0a: + LOGMASKED(LOG_VC2, "VC2 Register Read: VT Lines in Run, %08x\n", m_vc2.m_vt_line_run); + return m_vc2.m_vt_line_run; + case 0x0b: + LOGMASKED(LOG_VC2, "VC2 Register Read: Vertical Line Count, %08x\n", m_vc2.m_vt_line_count); + return m_vc2.m_vt_line_count; + case 0x0c: + LOGMASKED(LOG_VC2, "VC2 Register Read: Cursor Table Pointer, %08x\n", m_vc2.m_cursor_table_ptr); + return m_vc2.m_cursor_table_ptr; + case 0x0d: + LOGMASKED(LOG_VC2, "VC2 Register Read: Working Cursor Y, %08x\n", m_vc2.m_work_cursor_y); + return m_vc2.m_work_cursor_y; + case 0x0e: + LOGMASKED(LOG_VC2, "VC2 Register Read: DID Frame Pointer, %08x\n", m_vc2.m_did_frame_ptr); + return m_vc2.m_did_frame_ptr; + case 0x0f: + LOGMASKED(LOG_VC2, "VC2 Register Read: DID Line Pointer, %08x\n", m_vc2.m_did_line_ptr); + return m_vc2.m_did_line_ptr; + case 0x10: + LOGMASKED(LOG_VC2, "VC2 Register Read: Display Control, %08x\n", m_vc2.m_display_ctrl); + return m_vc2.m_display_ctrl; + case 0x1f: + LOGMASKED(LOG_VC2, "VC2 Register Read: Configuration, %08x\n", m_vc2.m_config); + return m_vc2.m_config; + default: + return 0; + } + break; + case 0x03: /* RAM Read */ + { + LOGMASKED(LOG_VC2, "VC2 RAM Read: %04x = %08x\n", m_vc2.m_ram_addr, m_vc2.m_ram[m_vc2.m_ram_addr]); + uint16_t ret = m_vc2.m_ram[m_vc2.m_ram_addr]; + m_vc2.m_ram_addr++; + if (m_vc2.m_ram_addr == 0x8000) + { + m_vc2.m_ram_addr = 0x0000; + } + return ret; + } + default: + LOGMASKED(LOG_VC2 | LOG_UNKNOWN, "Unknown VC2 Register Read: %02x\n", m_rex3.m_dcb_reg_select); + return 0; + } +} + +void newport_base_device::decode_vt_line(uint32_t line, uint32_t line_seq_ptr) +{ + bool eol_sa = false; + bool eol_sb = false; + uint32_t vt_entry = 0; + uint32_t i = 0; + do + { + vt_entry &= ~(0x7f << 14); + vt_entry |= (m_vc2.m_ram[line_seq_ptr] & 0x7f) << 14; + eol_sa = BIT(m_vc2.m_ram[line_seq_ptr], 15); + if (!BIT(m_vc2.m_ram[line_seq_ptr], 7)) + { + eol_sb = BIT(m_vc2.m_ram[line_seq_ptr + 1], 15); + vt_entry &= (0x7f << 14); + vt_entry |= (m_vc2.m_ram[line_seq_ptr + 1] & 0x7f00) >> 1; + vt_entry |= m_vc2.m_ram[line_seq_ptr + 1] & 0x7f; + line_seq_ptr += 2; + } + else + { + eol_sb = true; + line_seq_ptr++; + } + for (uint32_t j = 0; j < ((m_vc2.m_ram[line_seq_ptr] & 0x7f00) >> 7); i++, j++) + { + const uint8_t sa = ((vt_entry >> 14) & 0x7f) << 1; + const uint8_t sb = ((vt_entry >> 7) & 0x7f) << 1; + const uint8_t sc = ((vt_entry >> 0) & 0x7f) << 1; + //m_vt_table[line * 2048 + i] = vt_entry; + m_vt_table[line * 2048 + i] = 0xff000000 | (sa << 16) | (sb << 8) | sc; + } + } while (!(eol_sa && eol_sb)); +} + +void newport_base_device::decode_vt_table() +{ + memset(&m_vt_table[0], 0, sizeof(uint32_t) * 2048 * 2048); + uint32_t curr_vt_entry = m_vc2.m_vid_entry; + uint32_t line_counter = 0; + uint32_t line_seq_len = 0; + do + { + const uint32_t line_seq_ptr = m_vc2.m_ram[curr_vt_entry]; + line_seq_len = m_vc2.m_ram[curr_vt_entry + 1]; + if (line_seq_len) + { + for (uint32_t i = 0; i < line_seq_len; i++, line_counter++) + { + decode_vt_line(line_counter, line_seq_ptr); + } + } + curr_vt_entry += 2; + } while (line_seq_len != 0); +} + +void newport_base_device::update_screen_size() +{ + decode_vt_table(); + + bool x_started = false; + bool y_started = false; + bool x_done = false; + bool y_done = false; + bool done = false; + m_readout_x0 = 0; + m_readout_y0 = 0; + m_readout_x1 = 0; + m_readout_y1 = 0; + + for (int y = 0; y < 2048 && !done; y++) + { + uint32_t *src = &m_vt_table[y * 2048]; + for (int x = 0; x < 2048 && !done; x++) + { + if (BIT(*src, 7)) + { + if (!x_started) + { + x_started = true; + m_readout_x0 = x; + } + if (!y_started) + { + y_started = true; + m_readout_y0 = y; + } + } + else + { + if (x_started && !x_done) + { + m_readout_x1 = x; + x_done = true; + } + if (y_started && !y_done && x == m_readout_x0) + { + m_readout_y1 = y; + y_done = true; + } + } + done = x_done && y_done; + src++; + } + } + + m_screen->set_size((uint16_t)(m_readout_x1 - m_readout_x0), (uint16_t)(m_readout_y1 - m_readout_y0)); + m_screen->set_visarea_full(); +} + +void newport_base_device::vc2_write(uint32_t data) +{ + switch (m_rex3.m_xfer_width) + { + case 0x01: /* Register Select */ + switch (m_rex3.m_dcb_reg_select) + { + case 0x00: + m_vc2.m_reg_idx = (uint8_t)data; + LOGMASKED(LOG_VC2, "VC2 Register Select: %02x\n", m_vc2.m_reg_idx); + break; + default: + LOGMASKED(LOG_VC2 | LOG_UNKNOWN, "Unknown VC2 Register Select: DCB Register %02x, data = %08x\n", m_rex3.m_dcb_reg_select, data); + break; + } + break; + case 0x02: /* RAM Write */ + switch (m_rex3.m_dcb_reg_select) + { + case 0x03: + LOGMASKED(LOG_VC2, "VC2 RAM Write: %04x = %08x\n", m_vc2.m_ram_addr, (uint16_t)data); + m_vc2.m_ram[m_vc2.m_ram_addr] = (uint16_t)data; + m_vc2.m_ram_addr++; + if (m_vc2.m_ram_addr >= 0x8000) + { + m_vc2.m_ram_addr = 0x0000; + } + break; + default: + LOGMASKED(LOG_VC2 | LOG_UNKNOWN, "Unknown Word Write: DCB Register %02x, data = %08x\n", m_rex3.m_dcb_reg_select, data); + break; + } + break; + case 0x03: /* Register Write */ + switch (m_rex3.m_dcb_reg_select) + { + case 0x00: + LOGMASKED(LOG_VC2, "VC2 Register Setup:\n"); + m_vc2.m_reg_idx = data >> 24; + m_vc2.m_reg_data = (uint16_t)(data >> 8); + switch (m_vc2.m_reg_idx) + { + case 0x00: + m_vc2.m_vid_entry = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Video Entry Pointer, %04x\n", m_vc2.m_vid_entry); + update_screen_size(); + break; + case 0x01: + m_vc2.m_cursor_entry = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Cursor Entry Pointer, %04x\n", m_vc2.m_cursor_entry); + break; + case 0x02: + m_vc2.m_cursor_x = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Cursor X, %04x\n", m_vc2.m_cursor_x); + break; + case 0x03: + m_vc2.m_cursor_y = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Cursor Y, %04x\n", m_vc2.m_cursor_y); + m_vc2.m_cur_cursor_x = m_vc2.m_cursor_x; + break; + case 0x04: + m_vc2.m_cur_cursor_x = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Current Cursor X, %04x\n", m_vc2.m_cur_cursor_x); + break; + case 0x05: + m_vc2.m_did_entry = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: DID Entry Pointer, %04x\n", m_vc2.m_did_entry); + break; + case 0x06: + m_vc2.m_scanline_len = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Scanline Length, %04x\n", m_vc2.m_scanline_len); + break; + case 0x07: + m_vc2.m_ram_addr = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: RAM Address, %04x\n", m_vc2.m_ram_addr); + break; + case 0x08: + m_vc2.m_vt_frame_ptr = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: VT Frame Table Ptr, %04x\n", m_vc2.m_vt_frame_ptr); + break; + case 0x09: + m_vc2.m_vt_line_ptr = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: VT Line Sequence Pointer, %04x\n", m_vc2.m_vt_line_ptr); + break; + case 0x0a: + m_vc2.m_vt_line_run = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: VT Lines in Run, %04x\n", m_vc2.m_vt_line_run); + break; + case 0x0b: + m_vc2.m_vt_line_count = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Vertical Line Count, %04x\n", m_vc2.m_vt_line_count); + break; + case 0x0c: + m_vc2.m_cursor_table_ptr = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Cursor Table Pointer, %04x\n", m_vc2.m_cursor_table_ptr); + break; + case 0x0d: + m_vc2.m_work_cursor_y = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Working Cursor Y, %04x\n", m_vc2.m_work_cursor_y); + break; + case 0x0e: + m_vc2.m_did_frame_ptr = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: DID Frame Table Pointer, %04x\n", m_vc2.m_did_frame_ptr); + break; + case 0x0f: + m_vc2.m_did_line_ptr = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: DID Line Table Pointer, %04x\n", m_vc2.m_did_line_ptr); + break; + case 0x10: + m_vc2.m_display_ctrl = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Display Control, %04x\n", m_vc2.m_display_ctrl); + break; + case 0x1f: + m_vc2.m_config = m_vc2.m_reg_data; + LOGMASKED(LOG_VC2, "VC2 Register Write: Configuration, %04x\n", m_vc2.m_config); + break; + default: + LOGMASKED(LOG_VC2 | LOG_UNKNOWN, "VC2 Register Write: Unknown VC2 Register: %02x = %04x\n", m_vc2.m_reg_idx, m_vc2.m_reg_data); + break; + } + break; + default: + LOGMASKED(LOG_VC2 | LOG_UNKNOWN, "Unknown VC2 Register Write: %02x = %08x\n", m_rex3.m_dcb_reg_select, data); + break; + } + break; + default: + LOGMASKED(LOG_VC2 | LOG_UNKNOWN, "Unknown VC2 Transfer Width: Width %02x, DCB Register %02x, Value %08x\n", m_rex3.m_xfer_width, m_rex3.m_dcb_reg_select, data); + break; + } +} + +WRITE_LINE_MEMBER(newport_base_device::vblank_w) +{ + if (state) + { + if (BIT(m_vc2.m_display_ctrl, 0)) + { + m_rex3.m_status |= STATUS_VRINT; + m_gio64->get_hpc3()->raise_local_irq(1, ioc2_device::INT3_LOCAL1_RETRACE); + } + } +} + +READ64_MEMBER(newport_base_device::rex3_r) +{ + uint64_t ret = 0; + switch (offset & ~(0x800/8)) + { + case 0x0000/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Draw Mode 1 Read: %08x\n", m_rex3.m_draw_mode1); + ret |= (uint64_t)m_rex3.m_draw_mode1 << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Draw Mode 0 Read: %08x\n", m_rex3.m_draw_mode0); + ret |= m_rex3.m_draw_mode0; + } + break; + case 0x0008/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Line Stipple Mode Read: %08x\n", m_rex3.m_ls_mode); + ret |= (uint64_t)m_rex3.m_ls_mode << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Line Stipple Pattern Read: %08x\n", m_rex3.m_ls_pattern); + ret |= m_rex3.m_ls_pattern; + } + break; + case 0x0010/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Line Stipple Pattern (Save) Read: %08x\n", m_rex3.m_ls_pattern_saved); + ret |= (uint64_t)m_rex3.m_ls_pattern_saved << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Pattern Register Read: %08x\n", m_rex3.m_z_pattern); + ret |= m_rex3.m_z_pattern; + } + break; + case 0x0018/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Opaque Pattern / Blendfunc Dest Color Read: %08x\n", m_rex3.m_color_back); + ret |= (uint64_t)m_rex3.m_color_back << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 VRAM Fastclear Color Read: %08x\n", m_rex3.m_color_vram); + ret |= m_rex3.m_color_vram; + } + break; + case 0x0020/8: + LOGMASKED(LOG_REX3, "REX3 AFUNCTION Reference Alpha Read: %08x\n", m_rex3.m_alpha_ref); + ret |= (uint64_t)m_rex3.m_alpha_ref << 32; + break; + case 0x0028/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 0 X Min/Max Read: %08x\n", m_rex3.m_smask_x[0]); + ret |= (uint64_t)m_rex3.m_smask_x[0] << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 0 Y Min/Max Read: %08x\n", m_rex3.m_smask_y[0]); + ret |= m_rex3.m_smask_y[0]; + } + break; + case 0x0030/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Line/Span Setup Read: %08x\n", m_rex3.m_setup); + ret |= (uint64_t)m_rex3.m_setup << 32; + } + break; + case 0x0100/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "%s: REX3 X Start Read: %08x\n", machine().describe_context(), m_rex3.m_x_start); + ret |= (uint64_t)m_rex3.m_x_start << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 YStart Read: %08x\n", m_rex3.m_y_start); + ret |= m_rex3.m_y_start; + } + break; + case 0x0108/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 XEnd Read: %08x\n", m_rex3.m_x_end); + ret |= (uint64_t)m_rex3.m_x_end << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 YEnd Read: %08x\n", m_rex3.m_y_end); + ret |= m_rex3.m_y_end; + } + break; + case 0x0110/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 XSave Read: %08x\n", m_rex3.m_x_save); + ret |= (uint64_t)(uint16_t)m_rex3.m_x_save << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 XYMove Read: %08x\n", m_rex3.m_xy_move); + ret |= m_rex3.m_xy_move; + } + break; + case 0x0118/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham D Read: %08x\n", m_rex3.m_bres_d); + ret |= (uint64_t)m_rex3.m_bres_d << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham S1 Read: %08x\n", m_rex3.m_bres_s1); + ret |= m_rex3.m_bres_s1; + } + break; + case 0x0120/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham Octant & Incr1 Read: %08x\n", m_rex3.m_bres_octant_inc1); + ret |= (uint64_t)m_rex3.m_bres_octant_inc1 << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham Octant Rounding Mode & Incr2 Read: %08x\n", m_rex3.m_bres_round_inc2); + ret |= m_rex3.m_bres_round_inc2; + } + break; + case 0x0128/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham E1 Read: %08x\n", m_rex3.m_bres_e1); + ret |= (uint64_t)m_rex3.m_bres_e1 << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham S2 Read: %08x\n", m_rex3.m_bres_s2); + ret |= m_rex3.m_bres_s2; + } + break; + case 0x0130/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 AA Line Weight Table 1/2 Read: %08x\n", m_rex3.m_a_weight0); + ret |= (uint64_t)m_rex3.m_a_weight0 << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 AA Line Weight Table 2/2 Read: %08x\n", m_rex3.m_a_weight1); + ret |= m_rex3.m_a_weight1; + } + break; + case 0x0138/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 GL XStart Read: %08x\n", m_rex3.m_x_start_f); + ret |= (uint64_t)m_rex3.m_x_start_f << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 GL YStart Read: %08x\n", m_rex3.m_y_start_f); + ret |= m_rex3.m_y_start_f; + } + break; + case 0x0140/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 GL XEnd Read: %08x\n", m_rex3.m_x_end_f); + ret |= (uint64_t)m_rex3.m_x_end_f << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 GL YEnd Read: %08x\n", m_rex3.m_y_end_f); + ret |= m_rex3.m_y_end_f; + } + break; + case 0x0148/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 XStart (integer) Read: %08x\n", m_rex3.m_x_start_i); + ret |= (uint64_t)m_rex3.m_x_start_i << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 GL XEnd (copy) Read: %08x\n", m_rex3.m_x_end_f); + ret |= m_rex3.m_x_end_f; + } + break; + case 0x0150/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 XYStart (integer) Read: %08x\n", m_rex3.m_xy_start_i); + ret |= (uint64_t)m_rex3.m_xy_start_i << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 XYEnd (integer) Read: %08x\n", m_rex3.m_xy_end_i); + ret |= m_rex3.m_xy_end_i; + } + break; + case 0x0158/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 XStartEnd (integer) Read: %08x\n", m_rex3.m_x_start_end_i); + ret |= (uint64_t)m_rex3.m_x_start_end_i << 32; + } + break; + case 0x0200/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Red/CI Full State Read: %08x\n", m_rex3.m_color_red); + ret |= (uint64_t)m_rex3.m_color_red << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Alpha Full State Read: %08x\n", m_rex3.m_color_alpha); + ret |= m_rex3.m_color_alpha; + } + break; + case 0x0208/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Green Full State Read: %08x\n", m_rex3.m_color_green); + ret |= (uint64_t)m_rex3.m_color_green << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Blue Full State Read: %08x\n", m_rex3.m_color_blue); + ret |= m_rex3.m_color_blue; + } + break; + case 0x0210/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Red/CI Slope Read: %08x\n", m_rex3.m_slope_red); + ret |= (uint64_t)m_rex3.m_slope_red << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Alpha Slope Read: %08x\n", m_rex3.m_slope_alpha); + ret |= m_rex3.m_slope_alpha; + } + break; + case 0x0218/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Green Slope Read: %08x\n", m_rex3.m_slope_green); + ret |= (uint64_t)m_rex3.m_slope_green << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Blue Slope Read: %08x\n", m_rex3.m_slope_blue); + ret |= m_rex3.m_slope_blue; + } + break; + case 0x0220/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Write Mask Read: %08x\n", m_rex3.m_write_mask); + ret |= (uint64_t)m_rex3.m_write_mask << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Packed Color Fractions Read: %08x\n", m_rex3.m_color_i); + ret |= m_rex3.m_color_i; + } + break; + case 0x0228/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Color Index Zeros Overflow Read: %08x\n", m_rex3.m_zero_overflow); + ret |= (uint64_t)m_rex3.m_zero_overflow << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Red/CI Slope (copy) Read: %08x\n", m_rex3.m_slope_red); + ret |= m_rex3.m_slope_red; + } + break; + case 0x0230/8: + LOGMASKED(LOG_REX3, "%s: REX3 Host Data Port Read: %08x%08x\n", machine().describe_context(), (uint32_t)(m_rex3.m_host_dataport >> 32), + (uint32_t)m_rex3.m_host_dataport); + ret = m_rex3.m_host_dataport; + break; + case 0x0238/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Mode Read: %08x\n", m_rex3.m_dcb_mode); + ret |= (uint64_t)m_rex3.m_dcb_mode << 32; + } + break; + case 0x0240/8: + if (ACCESSING_BITS_32_63) + { + switch (m_rex3.m_dcb_slave_select) + { + case DCB_ADDR_VC2: + ret |= (uint64_t)vc2_read() << 32; + break; + case DCB_ADDR_CMAP0: + ret |= (uint64_t)cmap0_read() << 32; + break; + case DCB_ADDR_CMAP1: + ret |= (uint64_t)cmap1_read() << 32; + break; + case DCB_ADDR_XMAP0: + ret |= (uint64_t)xmap0_read() << 32; + break; + case DCB_ADDR_XMAP1: + ret |= (uint64_t)xmap1_read() << 32; + break; + case DCB_ADDR_RAMDAC: + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Read from RAMDAC (not yet implemented)\n"); + break; + case DCB_ADDR_CC1: + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Read from CC1 (not yet implemented)\n"); + break; + case DCB_ADDR_AB1: + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Read from AB1 (not yet implemented)\n"); + break; + case DCB_ADDR_PCD: + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Read from PCD (not yet implemented)\n"); + // Presenter not connected; simulate a bus timeout + m_rex3.m_status |= STATUS_BACKBUSY; + m_dcb_timeout_timer->adjust(attotime::from_msec(1)); + break; + default: + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Read: %08x\n", m_rex3.m_dcb_data_msw); + ret |= (uint64_t)m_rex3.m_dcb_data_msw << 32; + break; + } + if (BIT(m_rex3.m_dcb_mode, 3)) + { + m_rex3.m_dcb_reg_select++; + m_rex3.m_dcb_reg_select &= 7; + } + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data LSW Read: %08x\n", m_rex3.m_dcb_data_lsw); + ret |= m_rex3.m_dcb_data_lsw; + } + break; + case 0x1300/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 1 X Min/Max Read: %08x\n", m_rex3.m_smask_x[1]); + ret |= (uint64_t)m_rex3.m_smask_x[1] << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 1 Y Min/Max Read: %08x\n", m_rex3.m_smask_y[1]); + ret |= m_rex3.m_smask_y[1]; + } + break; + case 0x1308/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 2 X Min/Max Read: %08x\n", m_rex3.m_smask_x[2]); + ret |= (uint64_t)m_rex3.m_smask_x[2] << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 2 Y Min/Max Read: %08x\n", m_rex3.m_smask_y[2]); + ret |= m_rex3.m_smask_y[2]; + } + break; + case 0x1310/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 3 X Min/Max Read: %08x\n", m_rex3.m_smask_x[3]); + ret |= (uint64_t)m_rex3.m_smask_x[3] << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 3 Y Min/Max Read: %08x\n", m_rex3.m_smask_y[3]); + ret |= m_rex3.m_smask_y[3]; + } + break; + case 0x1318/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 4 X Min/Max Read: %08x\n", m_rex3.m_smask_x[4]); + ret |= (uint64_t)m_rex3.m_smask_x[4] << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 4 Y Min/Max Read: %08x\n", m_rex3.m_smask_y[4]); + ret |= m_rex3.m_smask_y[4]; + } + break; + case 0x1320/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Top of Screen Scanline Read: %08x\n", m_rex3.m_top_scanline); + ret |= (uint64_t)m_rex3.m_top_scanline << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 XY Window Read: %08x\n", m_rex3.m_xy_window); + ret |= m_rex3.m_xy_window; + } + break; + case 0x1328/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Clipping Mode Read: %08x\n", m_rex3.m_clip_mode); + ret |= (uint64_t)m_rex3.m_clip_mode << 32; + } + break; + case 0x1330/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Config Read: %08x\n", m_rex3.m_config); + ret |= (uint64_t)m_rex3.m_config << 32; + } + break; + case 0x1338/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Status Read: %08x\n", m_rex3.m_status); + uint32_t old_status = m_rex3.m_status; + m_rex3.m_status &= ~STATUS_VRINT; + m_gio64->get_hpc3()->lower_local_irq(1, ioc2_device::INT3_LOCAL1_RETRACE); + ret |= (uint64_t)(old_status | 3) << 32; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 User Status Read: %08x\n", m_rex3.m_status); + ret |= m_rex3.m_status; + } + break; + default: + LOGMASKED(LOG_REX3 | LOG_UNKNOWN, "Unknown REX3 Read: %08x (%08x%08x)\n", 0x1f0f0000 + (offset << 2), (uint32_t)(mem_mask >> 32), (uint32_t)mem_mask); + return 0; + } + + if (offset & 0x00000100) + { + do_rex3_command(); + } + + return ret; +} + +uint32_t newport_base_device::get_host_color() +{ + static const uint32_t s_color_masks[4] = { 0xf, 0xff, 0xfff, 0xffffff }; + const uint32_t color = (uint32_t)(m_rex3.m_host_dataport >> m_rex3.m_host_shift) & s_color_masks[m_rex3.m_hostdepth]; + if (m_rex3.m_rwpacked) + { + if ((m_rex3.m_rwdouble && m_rex3.m_host_shift > 0) || m_rex3.m_host_shift > 32) + m_rex3.m_host_shift -= s_host_shifts[m_rex3.m_hostdepth]; + else + m_rex3.m_host_shift = 64 - s_host_shifts[m_rex3.m_hostdepth]; + } + uint8_t convert_index = (m_rex3.m_hostdepth << 2) | m_rex3.m_plane_depth; + switch (convert_index & 15) + { + default: + // No conversion needed + return color; + case 1: // 4bpp -> 8bpp + return convert_4bpp_bgr_to_8bpp((uint8_t)color); + case 2: // 4bpp -> 12bpp + return convert_4bpp_bgr_to_12bpp((uint8_t)color); + case 3: // 4bpp -> 24bpp + return convert_4bpp_bgr_to_24bpp((uint8_t)color); + case 4: // 8bpp -> 4bpp + return convert_8bpp_bgr_to_4bpp((uint8_t)color); + case 6: // 8bpp -> 12bpp + return convert_8bpp_bgr_to_12bpp((uint8_t)color); + case 7: // 8bpp -> 24bpp + return convert_8bpp_bgr_to_24bpp((uint8_t)color); + case 8: // 12bpp -> 4bpp + return convert_12bpp_bgr_to_4bpp((uint16_t)color); + case 9: // 12bpp -> 8bpp + return convert_12bpp_bgr_to_8bpp((uint16_t)color); + case 11: // 12bpp -> 24bpp + return convert_12bpp_bgr_to_24bpp((uint16_t)color); + case 12: // 32bpp -> 4bpp + return convert_24bpp_bgr_to_4bpp(color); + case 13: // 32bpp -> 8bpp + return convert_24bpp_bgr_to_8bpp(color); + case 14: // 32bpp -> 12bpp + return convert_24bpp_bgr_to_12bpp(color); + } + return color; +} + +void newport_base_device::write_pixel(uint32_t color) +{ + const bool shade = BIT(m_rex3.m_draw_mode0, 18); + const bool rgbmode = BIT(m_rex3.m_draw_mode1, 15); + if (m_rex3.m_color_host) + write_pixel(m_rex3.m_x_start_i, m_rex3.m_y_start_i, get_host_color()); + else if (shade || rgbmode) + write_pixel(m_rex3.m_x_start_i, m_rex3.m_y_start_i, get_rgb_color(m_rex3.m_x_start_i, m_rex3.m_y_start_i)); + else + write_pixel(m_rex3.m_x_start_i, m_rex3.m_y_start_i, color); +} + +bool newport_base_device::pixel_clip_pass(int16_t x, int16_t y) +{ + bool mask0_pass = true; + if (BIT(m_rex3.m_clip_mode, 0)) + { + const int16_t min_x = (int16_t)(m_rex3.m_smask_x[0] >> 16); + const int16_t min_y = (int16_t)(m_rex3.m_smask_y[0] >> 16); + const int16_t max_x = (int16_t)m_rex3.m_smask_x[0]; + const int16_t max_y = (int16_t)m_rex3.m_smask_y[0]; + + if (x < min_x) + mask0_pass = false; + else if (y < min_y) + mask0_pass = false; + else if (x > max_x) + mask0_pass = false; + else if (y > max_y) + mask0_pass = false; + } + + if (!mask0_pass) + { + LOGMASKED(LOG_REJECTS, "Rejecting pixel at %d,%d due to Mask 0 clipping (%d,%d - %d,%d)\n", x, y, + (int16_t)(m_rex3.m_smask_x[0] >> 16), (int16_t)(m_rex3.m_smask_y[0] >> 16), (int16_t)m_rex3.m_smask_x[0], (int16_t)m_rex3.m_smask_y[0]); + return false; + } + + x += m_rex3.m_x_window; + y += m_rex3.m_y_window; + x -= 0x1000; + y -= 0x1000; + + if (m_rex3.m_clip_mode & 0x1e) + { + uint8_t bit = 1; + for (; bit < 5; bit++) + { + if (!BIT(m_rex3.m_clip_mode, bit)) + continue; + + int16_t min_x = (int16_t)(m_rex3.m_smask_x[bit] >> 16) - 0x1000; + int16_t min_y = (int16_t)(m_rex3.m_smask_y[bit] >> 16) - 0x1000; + int16_t max_x = (int16_t)m_rex3.m_smask_x[bit] - 0x1000; + int16_t max_y = (int16_t)m_rex3.m_smask_y[bit] - 0x1000; + + if (x < min_x) + { + LOGMASKED(LOG_REJECTS, "Skipping Mask %d because %04x,%04x is outside %04x,%04x to %04x,%04x (MinX)\n", bit, x, y, min_x, min_y, max_x, max_y); + continue; + } + if (x > max_x) + { + LOGMASKED(LOG_REJECTS, "Skipping Mask %d because %04x,%04x is outside %04x,%04x to %04x,%04x (MaxX)\n", bit, x, y, min_x, min_y, max_x, max_y); + continue; + } + if (y < min_y) + { + LOGMASKED(LOG_REJECTS, "Skipping Mask %d because %04x,%04x is outside %04x,%04x to %04x,%04x (MinY)\n", bit, x, y, min_x, min_y, max_x, max_y); + continue; + } + if (y > max_y) + { + LOGMASKED(LOG_REJECTS, "Skipping Mask %d because %04x,%04x is outside %04x,%04x to %04x,%04x (MaxY)\n", bit, x, y, min_x, min_y, max_x, max_y); + continue; + } + break; + } + if (bit == 5) + { + LOGMASKED(LOG_REJECTS, "Rejecting pixel at %d,%d due to Mask 1-4 clipping\n", x, y); + return false; + } + } + + if (x < 0 || y < 0 || x >= (1280+64) || y >= 1024) + { + LOGMASKED(LOG_REJECTS, "Rejecting pixel at %d,%d due to VRAM clipping\n", x, y); + return false; + } + + return true; +} + +void newport_base_device::blend_pixel(uint32_t *dest_buf, uint32_t src) +{ + const uint32_t dst = *dest_buf >> m_rex3.m_store_shift; + + float sa = 0.0f; + float sb = 0.0f; + float sg = 0.0f; + float sr = 0.0f; + + float db = 0.0f; + float dg = 0.0f; + float dr = 0.0f; + + float sbb = 0.0f; + float sgb = 0.0f; + float srb = 0.0f; + + float dbb = 0.0f; + float dgb = 0.0f; + float drb = 0.0f; + + switch (m_rex3.m_plane_depth) + { + case 0: // 4bpp (not supported) + case 1: // 8bpp (not supported) + break; + case 2: // 12bpp + sa = (((src >> 12) & 15) * 0x11) / 255.0f; + sr = (((src >> 8) & 15) * 0x11) / 255.0f; + sg = (((src >> 4) & 15) * 0x11) / 255.0f; + sb = (((src >> 0) & 15) * 0x11) / 255.0f; + + if (BIT(m_rex3.m_draw_mode1, 25)) + { + db = (uint8_t)(m_rex3.m_color_back >> 16) / 255.0f; + dg = (uint8_t)(m_rex3.m_color_back >> 8) / 255.0f; + dr = (uint8_t)(m_rex3.m_color_back >> 0) / 255.0f; + } + else + { + const uint32_t dstc = dst & 0xfff; + dr = (((dstc >> 8) & 15) * 0x11) / 255.0f; + dg = (((dstc >> 4) & 15) * 0x11) / 255.0f; + db = (((dstc >> 0) & 15) * 0x11) / 255.0f; + } + break; + case 3: // 24bpp + sa = (uint8_t)(src >> 24) / 255.0f; + sr = (uint8_t)(src >> 16) / 255.0f; + sg = (uint8_t)(src >> 8) / 255.0f; + sb = (uint8_t)(src >> 0) / 255.0f; + + if (BIT(m_rex3.m_draw_mode1, 25)) + { + db = (uint8_t)(m_rex3.m_color_back >> 16) / 255.0f; + dg = (uint8_t)(m_rex3.m_color_back >> 8) / 255.0f; + dr = (uint8_t)(m_rex3.m_color_back >> 0) / 255.0f; + } + else + { + const uint32_t dstc = dst; + dr = (uint8_t)(dstc >> 16) / 255.0f; + dg = (uint8_t)(dstc >> 8) / 255.0f; + db = (uint8_t)(dstc >> 0) / 255.0f; + } + break; + } + + switch (m_rex3.m_sfactor) + { + case 0: // 0 + default: + break; + case 1: // 1 + sbb = sb; + sgb = sg; + srb = sr; + break; + case 2: // dstc + sbb = sb * db; + sgb = sg * dg; + srb = sr * dr; + break; + case 3: // 1 - dstc + sbb = sb * (1.0f - db); + sgb = sg * (1.0f - dg); + srb = sr * (1.0f - dr); + break; + case 4: // srca + if (BIT(m_rex3.m_draw_mode1, 27)) + { + sbb = sb * sa; + sgb = sg * sa; + srb = sr * sa; + } + else + { + sbb = sb; + sgb = sg; + srb = sr; + } + break; + case 5: // 1 - srca + if (BIT(m_rex3.m_draw_mode1, 27)) + { + sbb = sb * (1.0f - sa); + sgb = sg * (1.0f - sa); + srb = sr * (1.0f - sa); + } + break; + } + + switch (m_rex3.m_dfactor) + { + case 0: // 0 + default: + break; + case 1: // 1 + dbb = db; + dgb = dg; + drb = dr; + break; + case 2: // srcc + dbb = db * sb; + dgb = dg * sg; + drb = dr * sr; + break; + case 3: // 1 - srcc + dbb = db * (1.0f - sb); + dgb = dg * (1.0f - sg); + drb = dr * (1.0f - sr); + break; + case 4: // srca + dbb = db * sa; + dgb = dg * sa; + drb = dr * sa; + break; + case 5: // 1 - srca + dbb = db * (1.0f - sa); + dgb = dg * (1.0f - sa); + drb = dr * (1.0f - sa); + break; + } + + const float b_blend = sbb + dbb; + const float g_blend = sgb + dgb; + const float r_blend = srb + drb; + + const uint8_t b_blend_i = b_blend > 1.0f ? 255 : (b_blend < 0.0f ? 0 : (uint8_t)(b_blend * 255.0f)); + const uint8_t g_blend_i = g_blend > 1.0f ? 255 : (g_blend < 0.0f ? 0 : (uint8_t)(g_blend * 255.0f)); + const uint8_t r_blend_i = r_blend > 1.0f ? 255 : (r_blend < 0.0f ? 0 : (uint8_t)(r_blend * 255.0f)); + + switch (m_rex3.m_plane_depth) + { + case 0: // 4bpp (not supported) + case 1: // 8bpp (not supported) + break; + case 2: // 12bpp + store_pixel(dest_buf, ((r_blend_i & 0xf0) << 4) | (g_blend_i & 0xf0) | ((b_blend_i & 0xf0) >> 4)); + break; + case 3: // 24bpp + store_pixel(dest_buf, (r_blend_i << 16) | (g_blend_i << 8) | b_blend_i); + break; + } +} + +void newport_base_device::logic_pixel(uint32_t *dest_buf, uint32_t src) +{ + const uint32_t dst = *dest_buf >> m_rex3.m_store_shift; + + switch (m_rex3.m_logicop) + { + case 0: store_pixel(dest_buf, 0x000000); break; + case 1: store_pixel(dest_buf, src & dst); break; + case 2: store_pixel(dest_buf, src & ~dst); break; + case 3: store_pixel(dest_buf, src); break; + case 4: store_pixel(dest_buf, ~src & dst); break; + case 5: store_pixel(dest_buf, dst); break; + case 6: store_pixel(dest_buf, src ^ dst); break; + case 7: store_pixel(dest_buf, src | dst); break; + case 8: store_pixel(dest_buf, ~(src | dst)); break; + case 9: store_pixel(dest_buf, ~(src ^ dst)); break; + case 10: store_pixel(dest_buf, ~dst); break; + case 11: store_pixel(dest_buf, src | ~dst); break; + case 12: store_pixel(dest_buf, ~src); break; + case 13: store_pixel(dest_buf, ~src | dst); break; + case 14: store_pixel(dest_buf, ~(src & dst)); break; + case 15: store_pixel(dest_buf, 0xffffff); break; + } +} + +void newport_base_device::store_pixel(uint32_t *dest_buf, uint32_t value) +{ + const uint32_t write_mask = m_rex3.m_write_mask & m_global_mask; + *dest_buf &= ~write_mask; + *dest_buf |= (value << m_rex3.m_store_shift) & write_mask; +} + +void newport_base_device::write_pixel(int16_t x, int16_t y, uint32_t color) +{ + if (!pixel_clip_pass(x, y)) + { + return; + } + + x += m_rex3.m_x_window; + y += m_rex3.m_y_window; + x -= 0x1000; + y -= 0x1000; + + uint32_t *dest_buf = nullptr; + switch (m_rex3.m_plane_enable) + { + case 1: // RGB/CI planes + dest_buf = &m_rgbci[y * (1280 + 64) + x]; + break; + case 2: // RGBA planes + // Not yet handled + break; + case 4: // Overlay planes + dest_buf = &m_olay[y * (1280 + 64) + x]; + break; + case 5: // Popup planes + dest_buf = &m_pup[y * (1280 + 64) + x]; + color = (color << 2) | (color << 6); + break; + case 6: // CID planes + dest_buf = &m_cid[y * (1280 + 64) + x]; + break; + } + + if (BIT(m_rex3.m_draw_mode1, 18)) + blend_pixel(dest_buf, color); + else + logic_pixel(dest_buf, color); +} + +uint32_t newport_base_device::get_rgb_color(int16_t x, int16_t y) +{ + static const uint8_t s_bayer[4][4] = { { 0, 12, 3, 15 },{ 8, 4, 11, 7 },{ 2, 14, 1, 13 },{ 10, 6, 9, 5 } }; + + const uint32_t red = (uint8_t)(m_rex3.m_color_red >> 11); + const uint32_t green = (uint8_t)(m_rex3.m_color_green >> 11); + const uint32_t blue = (uint8_t)(m_rex3.m_color_blue >> 11); + + if (!BIT(m_rex3.m_draw_mode1, 15)) // RGB + { + switch (m_rex3.m_plane_depth) + { + case 0: // 4bpp + return (m_rex3.m_color_red >> 11) & 0x0000000f; + case 1: // 8bpp + return (m_rex3.m_color_red >> 11) & 0x000000ff; + case 2: // 12bpp + return (m_rex3.m_color_red >> 9) & 0x00000fff; + case 3: // 24bpp + // Not supported + return 0; + } + } + + if (BIT(m_rex3.m_draw_mode1, 16)) // Dithering + { + switch (m_rex3.m_plane_depth) + { + case 0: // 4bpp + { + const uint8_t sr = (red >> 3) - (red >> 4); + const uint8_t sg = (green >> 2) - (green >> 4); + const uint8_t sb = (blue >> 3) - (blue >> 4); + + uint8_t dr = BIT(sr, 4); + uint8_t dg = (sg >> 4) & 3; + uint8_t db = BIT(sb, 4); + + if ((sr & 0xf) > s_bayer[x & 3][y & 3]) dr++; + if ((sg & 0xf) > s_bayer[x & 3][y & 3]) dg++; + if ((sb & 0xf) > s_bayer[x & 3][y & 3]) db++; + + if (dr > 1) dr = 1; + if (dg > 3) dg = 3; + if (db > 1) db = 1; + + uint32_t color = (db << 3) | (dg << 1) | dr; + return (color << 4) | color; + } + + case 1: // 8bpp + { + const uint8_t sr = (red >> 1) - (red >> 4); + const uint8_t sg = (green >> 1) - (green >> 4); + const uint8_t sb = (blue >> 2) - (blue >> 4); + + uint8_t dr = (sr >> 4) & 7; + uint8_t dg = (sg >> 4) & 7; + uint8_t db = (sb >> 4) & 3; + + if ((sr & 0xf) > s_bayer[x & 3][y & 3]) dr++; + if ((sg & 0xf) > s_bayer[x & 3][y & 3]) dg++; + if ((sb & 0xf) > s_bayer[x & 3][y & 3]) db++; + + if (dr > 7) dr = 7; + if (dg > 7) dg = 7; + if (db > 3) db = 3; + + return (db << 6) | (dg << 3) | dr; + } + + case 2: // 12bpp + { + const uint32_t sr = red - (red >> 4); + const uint32_t sg = green - (green >> 4); + const uint32_t sb = blue - (blue >> 4); + + uint32_t dr = (sr >> 4) & 15; + uint32_t dg = (sg >> 4) & 15; + uint32_t db = (sb >> 4) & 15; + + if ((sr & 0xf) > s_bayer[x & 3][y & 3]) dr++; + if ((sg & 0xf) > s_bayer[x & 3][y & 3]) dg++; + if ((sb & 0xf) > s_bayer[x & 3][y & 3]) db++; + + if (dr > 15) dr = 15; + if (dg > 15) dg = 15; + if (db > 15) db = 15; + + uint32_t color = (db << 8) | (dg << 4) | dr; + return (color << 12) | color; + } + + case 3: // 24bpp + return (blue << 16) | (green << 8) | red; + + default: + return 0; + } + } + else + { + switch (m_rex3.m_plane_depth) + { + case 0: // 4bpp + return (BIT(blue, 7) << 3) | ((green & 0xc0) >> 5) | BIT(red, 7); + case 1: // 8bpp + return (blue & 0xc0) | ((green & 0xe0) >> 2) | ((red & 0xe0) >> 5); + case 2: // 12bpp + return ((blue & 0xf0) << 4) | (green & 0xf0) | ((red & 0xf0) >> 4); + case 3: // 24bpp + return (blue << 16) | (green << 8) | red; + default: + return 0; + } + } +} + +uint8_t newport_base_device::get_octant(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t dx, uint16_t dy) +{ + if (x1 < x2) + { + if (y2 < y1) + return (dx > dy) ? 0 : 1; + else + return (dx > dy) ? 7 : 6; + } + else + { + if (y2 < y1) + return (dx > dy) ? 3 : 2; + else + return (dx > dy) ? 4 : 5; + } +} + +void newport_base_device::do_fline(uint32_t color) +{ + const uint32_t x1 = m_rex3.m_x_start >> 7; + const uint32_t y1 = m_rex3.m_y_start >> 7; + const uint32_t x2 = m_rex3.m_x_end >> 7; + const uint32_t y2 = m_rex3.m_y_end >> 7; + + const uint16_t x10 = x1 & ~0xf; + const uint16_t y10 = y1 & ~0xf; + const uint16_t x20 = x2 & ~0xf; + const uint16_t y20 = y2 & ~0xf; + + const bool iterate_one = (m_rex3.m_draw_mode0 & 0x300) == 0; + const bool skip_first = BIT(m_rex3.m_draw_mode0, 10); + const bool skip_last = BIT(m_rex3.m_draw_mode0, 11); + const bool shade = BIT(m_rex3.m_draw_mode0, 18); + const bool rgbmode = BIT(m_rex3.m_draw_mode1, 15); + + uint16_t x = x10; + uint16_t y = y10; + + uint16_t x1_fract = m_rex3.m_x_start_frac; + uint16_t y1_fract = m_rex3.m_y_start_frac; + + int32_t dx = abs((int32_t)x1 - (int32_t)x2); + int32_t dy = abs((int32_t)y1 - (int32_t)y2); + + const int16_t dx_i = abs(x10 - x20) - 1; + const int16_t dy_i = abs(y10 - y20) - 1; + + static const bresenham_octant_info_t s_bresenham_infos[8] = + { + { 1, 1, 0, 1, 0 }, + { 0, 1, 1, 1, 1 }, + { 0, -1, 1, 1, 1 }, + { -1, -1, 0, 1, 0 }, + { -1, -1, 0, -1, 0 }, + { 0, -1, -1, -1, 1 }, + { 0, 1, -1, -1, 1 }, + { 1, 1, 0, -1, 0 } + }; + + const uint8_t octant = get_octant(x1, y1, x2, y2, dx, dy); + const int16_t incrx1 = s_bresenham_infos[octant].incrx1; + const int16_t incrx2 = s_bresenham_infos[octant].incrx2; + const int16_t incry1 = s_bresenham_infos[octant].incry1; + const int16_t incry2 = s_bresenham_infos[octant].incry2; + int16_t loop = s_bresenham_infos[octant].loop ? dy_i : dx_i; + if (BIT(m_rex3.m_draw_mode0, 15) && loop > 32) + loop = 32; + const int16_t x_major = 1 - s_bresenham_infos[octant].loop; + + const int32_t incr1 = s_bresenham_infos[octant].loop ? (2 * dx) : (2 * dy); + const int32_t incr2 = s_bresenham_infos[octant].loop ? (2 * (dx - dy)) : (2 * (dy - dx)); + int32_t d = s_bresenham_infos[octant].loop ? (3 * dx - 2 * dy) : (3 * dy - 2 * dx); + + switch (octant) + { + case 0: + // Nothing special needed + break; + case 1: + { + const int16_t temp_fract = x1_fract; + x1_fract = y1_fract; + y1_fract = temp_fract; + const int32_t temp_d = dx; + dx = dy; + dy = temp_d; + break; + } + case 2: + { + const int16_t temp_fract = 0x10 - x1_fract; + x1_fract = y1_fract; + y1_fract = temp_fract; + const int32_t temp_d = dx; + dx = dy; + dy = temp_d; + break; + } + case 3: + x1_fract = 0x10 - x1_fract; + break; + case 4: + x1_fract = 0x10 - x1_fract; + y1_fract = 0x10 - y1_fract; + break; + case 5: + { + const int16_t temp_fract = 0x10 - x1_fract; + x1_fract = 0x10 - y1_fract; + y1_fract = temp_fract; + const int32_t temp_d = dx; + dx = dy; + dy = temp_d; + break; + } + case 6: + { + const int16_t temp_fract = 0x10 - y1_fract; + y1_fract = x1_fract; + x1_fract = temp_fract; + const int32_t temp_d = dx; + dx = dy; + dy = temp_d; + break; + } + case 7: + y1_fract = 0x10 - y1_fract; + break; + } + + d += 2 * (((dx * y1_fract) >> 4) - ((dy * x1_fract) >> 4)); // Adjust d due to fractional endpoints + const int32_t E = d - 2 * dx; // Variable used for adjusting the start point up one pixel + if (E > 0) + { + d = E; + x += incrx2 * (1 - x_major); + y += incry2 * x_major; + } + + if (!skip_first || iterate_one) + { + if (shade || rgbmode) + write_pixel(x >> 4, y >> 4, get_rgb_color(x >> 4, y >> 4)); + else + write_pixel(x >> 4, y >> 4, color); + + if (shade) + iterate_shade(); + + if (d < 0) + { + x += incrx1; + y -= incry1; + d += incr1; + } + else + { + x += incrx2; + y -= incry2; + d += incr2; + } + + if (iterate_one) + { + write_x_start(x << 7); + write_y_start(y << 7); + return; + } + } + + for (int16_t i = 1; i < loop; i++) + { + if (shade || rgbmode) + write_pixel(x >> 4, y >> 4, get_rgb_color(x >> 4, y >> 4)); + else + write_pixel(x >> 4, y >> 4, color); + + if (shade) + iterate_shade(); + + if (d < 0) + { + x += incrx1; + y -= incry1; + d += incr1; + } + else + { + x += incrx2; + y -= incry2; + d += incr2; + } + } + + if (!skip_last) + { + if (shade || rgbmode) + write_pixel(x2 >> 4, y2 >> 4, get_rgb_color(x2 >> 4, y2 >> 4)); + else + write_pixel(x2 >> 4, y2 >> 4, color); + + if (shade) + iterate_shade(); + + write_x_start(x2); + write_y_start(y2); + } + else + { + write_x_start(x << 7); + write_y_start(y << 7); + } +} + +void newport_base_device::do_iline(uint32_t color) +{ + uint16_t x1 = m_rex3.m_x_start_i; + uint16_t y1 = m_rex3.m_y_start_i; + uint16_t x2 = m_rex3.m_x_end_i; + uint16_t y2 = m_rex3.m_y_end_i; + + const bool iterate_one = (m_rex3.m_draw_mode0 & 0x300) == 0; + const bool skip_first = BIT(m_rex3.m_draw_mode0, 10); + const bool skip_last = BIT(m_rex3.m_draw_mode0, 11); + const bool shade = BIT(m_rex3.m_draw_mode0, 18); + const bool rgbmode = BIT(m_rex3.m_draw_mode1, 15); + + uint16_t x = x1; + uint16_t y = y1; + uint16_t dx = abs(x1 - x2); + uint16_t dy = abs(y1 - y2); + + static const bresenham_octant_info_t s_bresenham_infos[8] = + { + { 1, 1, 0, 1, 0 }, + { 0, 1, 1, 1, 1 }, + { 0, -1, 1, 1, 1 }, + { -1, -1, 0, 1, 0 }, + { -1, -1, 0, -1, 0 }, + { 0, -1, -1, -1, 1 }, + { 0, 1, -1, -1, 1 }, + { 1, 1, 0, -1, 0 } + }; + + const uint8_t octant = get_octant(x1, y1, x2, y2, dx, dy); + const int16_t incrx1 = s_bresenham_infos[octant].incrx1; + const int16_t incrx2 = s_bresenham_infos[octant].incrx2; + const int16_t incry1 = s_bresenham_infos[octant].incry1; + const int16_t incry2 = s_bresenham_infos[octant].incry2; + uint16_t loop = s_bresenham_infos[octant].loop ? dy : dx; + if (BIT(m_rex3.m_draw_mode0, 15) && loop > 32) + loop = 32; + + const int16_t incr1 = 2 * (s_bresenham_infos[octant].loop ? dx : dy); + const int16_t incr2 = 2 * (s_bresenham_infos[octant].loop ? (dx - dy) : (dy - dx)); + int16_t d = incr1 - (s_bresenham_infos[octant].loop ? dy : dx); + + if (!skip_first || iterate_one) + { + if (shade || rgbmode) + write_pixel(x, y, get_rgb_color(x, y)); + else + write_pixel(x, y, color); + + if (shade) + iterate_shade(); + + if (d < 0) + { + x += incrx1; + y -= incry1; + d += incr1; + } + else + { + x += incrx2; + y -= incry2; + d += incr2; + } + + if (iterate_one) + { + write_x_start(x << 11); + write_y_start(y << 11); + return; + } + } + + for (int16_t i = 1; i < loop; i++) + { + if (shade || rgbmode) + write_pixel(x, y, get_rgb_color(x, y)); + else + write_pixel(x, y, color); + + if (shade) + iterate_shade(); + + if (d < 0) + { + x += incrx1; + y -= incry1; + d += incr1; + } + else + { + x += incrx2; + y -= incry2; + d += incr2; + } + } + + if (!skip_last) + { + if (shade || rgbmode) + write_pixel(x2, y2, get_rgb_color(x2, y2)); + else + write_pixel(x2, y2, color); + + if (shade) + iterate_shade(); + + write_x_start(x2 << 11); + write_y_start(y2 << 11); + } + else + { + write_x_start(x << 11); + write_y_start(y << 11); + } +} + +uint32_t newport_base_device::do_pixel_read() +{ + m_rex3.m_bres_octant_inc1 = 0; + const int16_t src_x = m_rex3.m_x_start_i + m_rex3.m_x_window - 0x1000; + const int16_t src_y = m_rex3.m_y_start_i + m_rex3.m_y_window - 0x1000; + const uint32_t src_addr = src_y * (1280 + 64) + src_x; + uint32_t ret = 0; + switch (m_rex3.m_plane_enable) + { + case 1: // RGB/CI planes + case 2: // RGBA planes + { + ret = m_rgbci[src_addr]; + uint8_t convert_index = (m_rex3.m_plane_depth << 2) | m_rex3.m_hostdepth; + switch (convert_index & 15) + { + default: + // No conversion needed + break; + case 1: // 4bpp -> 8bpp + ret = convert_4bpp_bgr_to_8bpp((uint8_t)ret); + break; + case 2: // 4bpp -> 12bpp + ret = convert_4bpp_bgr_to_12bpp((uint8_t)ret); + break; + case 3: // 4bpp -> 24bpp + ret = convert_4bpp_bgr_to_24bpp((uint8_t)ret); + break; + case 4: // 8bpp -> 4bpp + ret = convert_8bpp_bgr_to_4bpp((uint8_t)ret); + break; + case 6: // 8bpp -> 12bpp + ret = convert_8bpp_bgr_to_12bpp((uint8_t)ret); + break; + case 7: // 8bpp -> 24bpp + ret = convert_8bpp_bgr_to_24bpp((uint8_t)ret); + break; + case 8: // 12bpp -> 4bpp + ret = convert_12bpp_bgr_to_4bpp((uint16_t)ret); + break; + case 9: // 12bpp -> 8bpp + ret = convert_12bpp_bgr_to_8bpp((uint16_t)ret); + break; + case 11: // 12bpp -> 24bpp + ret = convert_12bpp_bgr_to_24bpp((uint16_t)ret); + break; + case 12: // 32bpp -> 4bpp + ret = convert_24bpp_bgr_to_4bpp(ret); + break; + case 13: // 32bpp -> 8bpp + ret = convert_24bpp_bgr_to_8bpp(ret); + break; + case 14: // 32bpp -> 12bpp + ret = convert_24bpp_bgr_to_12bpp(ret); + break; + } + break; + } + case 4: // Overlay planes + ret = m_olay[src_addr]; + break; + case 5: // Popup planes + ret = m_pup[src_addr]; + break; + case 6: // CID planes + ret = m_cid[src_addr]; + break; + } + LOGMASKED(LOG_COMMANDS, "Read %08x (%08x) from %04x, %04x\n", ret, m_rgbci[src_addr], src_x, src_y); + m_rex3.m_x_start_i++; + if (m_rex3.m_x_start_i > m_rex3.m_x_end_i) + { + m_rex3.m_y_start_i++; + m_rex3.m_x_start_i = m_rex3.m_x_save; + } + + write_x_start(m_rex3.m_x_start_i << 11); + write_y_start(m_rex3.m_y_start_i << 11); + return ret; +} + +uint64_t newport_base_device::do_pixel_word_read() +{ + const uint16_t x_start = (uint16_t)(m_rex3.m_xy_start_i >> 16); + const uint16_t x_end = (uint16_t)(m_rex3.m_xy_end_i >> 16); + const bool doubleword = BIT(m_rex3.m_draw_mode1, 10); + + uint16_t width = (x_end - x_start) + 1; + uint64_t ret = 0; + uint64_t shift = 0; + switch ((m_rex3.m_draw_mode1 >> 8) & 3) + { + case 0: // 4bpp + { + const uint16_t max_width = doubleword ? 16 : 8; + if (width > max_width) + width = max_width; + + shift = 60; + for (uint16_t i = 0; i < width; i++) + { + ret |= (uint64_t)(do_pixel_read() & 0x0000000f) << shift; + shift -= 4; + } + break; + } + + case 1: // 8bpp + { + const uint16_t max_width = doubleword ? 8 : 4; + if (width > max_width) + width = max_width; + + shift = 56; + for (uint16_t i = 0; i < width; i++) + { + ret |= (uint64_t)(do_pixel_read() & 0x000000ff) << shift; + shift -= 8; + } + break; + } + + case 2: // 12bpp + { + const uint16_t max_width = doubleword ? 4 : 2; + if (width > max_width) + width = max_width; + + shift = 48; + for (uint16_t i = 0; i < width; i++) + { + ret |= (uint64_t)(do_pixel_read() & 0x00000fff) << shift; + shift -= 16; + } + break; + } + + case 3: // 32bpp + { + const uint16_t max_width = doubleword ? 2 : 1; + if (width > max_width) + width = max_width; + + shift = 32; + for (uint16_t i = 0; i < width; i++) + { + ret |= (uint64_t)do_pixel_read() << shift; + shift -= 32; + } + break; + } + } + return ret; +} + +void newport_base_device::iterate_shade() +{ + m_rex3.m_color_red += m_rex3.m_slope_red; + m_rex3.m_color_green += m_rex3.m_slope_green; + m_rex3.m_color_blue += m_rex3.m_slope_blue; +} + +void newport_base_device::do_rex3_command() +{ + static const char* const s_opcode_str[4] = { "Noop", "Read", "Draw", "Scr2Scr" }; + static const char* const s_adrmode_str[8] = { + "Span", "Block", "IntLine", "FracLine", "AALine", "Unk5", "Unk6", "Unk7" + }; + + const uint32_t mode0 = m_rex3.m_draw_mode0; + const uint32_t mode1 = m_rex3.m_draw_mode1; + + int16_t start_x = m_rex3.m_x_start_i; + int16_t start_y = m_rex3.m_y_start_i; + int16_t end_x = m_rex3.m_x_end_i; + int16_t end_y = m_rex3.m_y_end_i; + int16_t dx = start_x > end_x ? -1 : 1; + int16_t dy = start_y > end_y ? -1 : 1; + + LOGMASKED(LOG_COMMANDS, "REX3 Command: %08x|%08x - %s %s\n", mode0, mode1, s_opcode_str[mode0 & 3], s_adrmode_str[(mode0 >> 2) & 7]); + + const uint8_t opcode = mode0 & 3; + const uint8_t adrmode = (mode0 >> 2) & 7; + + switch (opcode) + { + case 0: // NoOp + break; + case 1: // Read + m_rex3.m_host_dataport = do_pixel_word_read(); + break; + case 2: // Draw + switch (adrmode) + { + case 0: // Span + { + if (BIT(mode0, 19) && dx < 0) // LROnly + break; + + end_x += dx; + + int16_t prim_end_x = end_x; + bool stop_on_x = BIT(mode0, 8); + + if (BIT(mode0, 15) && abs(end_x - start_x) > 32) + prim_end_x = start_x + 32 * dx; + + if (m_rex3.m_color_host && m_rex3.m_rwpacked) + { + stop_on_x = true; + static const int16_t s_max_host_lengths[2][4] = { { 4, 4, 2, 1 }, { 8, 8, 4, 2 } }; + const int16_t max_length = s_max_host_lengths[m_rex3.m_rwdouble ? 1 : 0][m_rex3.m_hostdepth]; + int16_t length = abs(prim_end_x - start_x); + if (length > max_length) + prim_end_x = start_x + dx * max_length; + } + + const bool shade = BIT(mode0, 18); + const bool rgbmode = BIT(mode1, 15); + const bool opaque = BIT(mode0, 16) || BIT(mode0, 17); + const bool fastclear = BIT(mode1, 17); + const uint32_t pattern = BIT(mode0, 12) ? m_rex3.m_z_pattern : (BIT(mode0, 13) ? m_rex3.m_ls_pattern : 0xffffffff); + + LOGMASKED(LOG_COMMANDS, "%04x, %04x to %04x, %04x = %08x\n", start_x, start_y, end_x, end_y, pattern); + + uint32_t color = m_rex3.m_color_i; + if (fastclear) + { + if (rgbmode) + { + switch (m_rex3.m_plane_depth) + { + case 0: // 4bpp + color = m_rex3.m_color_vram & 0xf; + color |= color << 4; + break; + case 1: // 8bpp + color = m_rex3.m_color_vram & 0xff; + break; + case 2: // 12bpp + color = ((m_rex3.m_color_vram & 0xf00000) >> 12) | ((m_rex3.m_color_vram & 0xf000) >> 8) | ((m_rex3.m_color_vram & 0xf0) >> 4); + color |= color << 12; + break; + case 3: // 24bpp + color = m_rex3.m_color_vram & 0xffffff; + break; + } + } + else + { + color = m_rex3.m_color_vram; + } + } + + uint32_t bit = 31; + do + { + if (BIT(pattern, bit)) + { + if (m_rex3.m_color_host) + write_pixel(start_x, start_y, get_host_color()); + else if ((shade || rgbmode) && !fastclear) + write_pixel(start_x, start_y, get_rgb_color(start_x, start_y)); + else + write_pixel(start_x, start_y, color); + } + else if (opaque) + { + write_pixel(start_x, start_y, m_rex3.m_color_back); + } + + if (shade) + iterate_shade(); + + bit = (bit - 1) & 0x1f; + start_x += dx; + } while (start_x != prim_end_x && start_x != end_x && stop_on_x); + + write_x_start(start_x << 11); + break; + } + + case 1: // Block + { + if (BIT(mode0, 19) && dx < 0) // LROnly + break; + + end_x += dx; + end_y += dy; + + int16_t prim_end_x = end_x; + bool stop_on_x = BIT(mode0, 8); + const bool stop_on_y = BIT(mode0, 9); + + if (BIT(mode0, 15) && (end_x - start_x) >= 32) + prim_end_x = start_x + 32 * dx; + + if (m_rex3.m_color_host && m_rex3.m_rwpacked) + { + stop_on_x = true; + static const int16_t s_max_host_lengths[2][4] = { { 4, 4, 2, 1 }, { 8, 8, 4, 2 } }; + const int16_t max_length = s_max_host_lengths[m_rex3.m_rwdouble ? 1 : 0][m_rex3.m_hostdepth]; + int16_t length = abs(prim_end_x - start_x); + if (length > max_length) + prim_end_x = start_x + dx * max_length; + } + + const bool shade = BIT(mode0, 18); + const bool rgbmode = BIT(mode1, 15); + const bool opaque = BIT(mode0, 16) || BIT(mode0, 17); + const bool fastclear = BIT(mode1, 17); + const uint32_t pattern = BIT(mode0, 12) ? m_rex3.m_z_pattern : (BIT(mode0, 13) ? m_rex3.m_ls_pattern : 0xffffffff); + + uint32_t color = m_rex3.m_color_i; + if (fastclear) + { + if (rgbmode) + { + switch (m_rex3.m_plane_depth) + { + case 0: // 4bpp + color = m_rex3.m_color_vram & 0xf; + color |= color << 4; + break; + case 1: // 8bpp + color = m_rex3.m_color_vram & 0xff; + break; + case 2: // 12bpp + color = ((m_rex3.m_color_vram & 0xf00000) >> 12) | ((m_rex3.m_color_vram & 0xf000) >> 8) | ((m_rex3.m_color_vram & 0xf0) >> 4); + color |= color << 12; + break; + case 3: // 24bpp + color = m_rex3.m_color_vram & 0xffffff; + break; + } + } + else + { + color = m_rex3.m_color_vram; + } + } + + do + { + uint32_t bit = 31; + do + { + if (BIT(pattern, bit)) + { + if (m_rex3.m_color_host) + write_pixel(start_x, start_y, get_host_color()); + else if ((shade || rgbmode) && !fastclear) + write_pixel(start_x, start_y, get_rgb_color(start_x, start_y)); + else + write_pixel(start_x, start_y, color); + } + else if (opaque) + { + write_pixel(start_x, start_y, m_rex3.m_color_back); + } + + if (shade) + iterate_shade(); + + bit = (bit - 1) & 0x1f; + start_x += dx; + } while (start_x != prim_end_x && start_x != end_x && stop_on_x); + + if (start_x == end_x) + { + start_x = m_rex3.m_x_save; + start_y += dy; + } + } while (start_y != end_y && stop_on_y); + + write_x_start(start_x << 11); + write_y_start(start_y << 11); + break; + } + + case 2: // I_Line + do_iline(m_rex3.m_color_i); + break; + + case 3: // F_Line + do_fline(m_rex3.m_color_i); + break; + + case 4: // A_Line + do_iline(m_rex3.m_color_i); // FIXME + break; + + default: // Invalid + break; + } + break; + case 3: // Scr2Scr + if (adrmode < 2) + { + const bool stop_on_x = BIT(mode0, 8); + const bool stop_on_y = BIT(mode0, 9); + + end_x += dx; + end_y += dy; + + LOGMASKED(LOG_COMMANDS, "%04x, %04x - %04x, %04x to %04x, %04x\n", start_x, start_y, end_x, end_y, start_x + m_rex3.m_x_move, start_y + m_rex3.m_y_move); + do + { + do + { + const uint32_t src_addr = (start_y + m_rex3.m_y_window - 0x1000) * (1280 + 64) + (start_x + m_rex3.m_x_window - 0x1000); + uint32_t src = 0; + switch (mode1 & 7) + { + case 1: // RGB/CI planes + src = m_rgbci[src_addr]; + break; + case 2: // RGBA planes (not yet implemented) + break; + case 4: // Overlay planes + src = m_olay[src_addr]; + break; + case 5: // Popup planes + src = m_pup[src_addr] >> 2; + break; + case 6: // CID planes + src = m_cid[src_addr]; + break; + default: + break; + } + src >>= m_rex3.m_store_shift; + + write_pixel(start_x + m_rex3.m_x_move, start_y + m_rex3.m_y_move, src); + + start_x += dx; + } while (start_x != end_x && stop_on_x); + + if (start_x == end_x) + { + start_x = m_rex3.m_x_save; + start_y += dy; + } + } while (start_y != end_y && stop_on_y); + + write_x_start(start_x << 11); + write_y_start(start_y << 11); + } + break; + } +} + +void newport_base_device::write_x_start(int32_t val) +{ + m_rex3.m_x_start = val & 0x07ffff80; + m_rex3.m_x_start_frac = (val >> 7) & 0xf; + m_rex3.m_x_start_i = (int16_t)(val >> 11); + m_rex3.m_x_start_f = (uint32_t)val & 0x007fff80; + m_rex3.m_xy_start_i = (m_rex3.m_xy_start_i & 0x0000ffff) | (m_rex3.m_x_start_i << 16); +} + +void newport_base_device::write_y_start(int32_t val) +{ + m_rex3.m_y_start = val & 0x07ffff80; + m_rex3.m_y_start_frac = (val >> 7) & 0xf; + m_rex3.m_y_start_i = (int16_t)(val >> 11); + m_rex3.m_y_start_f = (uint32_t)val & 0x007fff80; + m_rex3.m_xy_start_i = (m_rex3.m_xy_start_i & 0xffff0000) | (uint16_t)m_rex3.m_y_start_i; +} + +void newport_base_device::write_x_end(int32_t val) +{ + m_rex3.m_x_end = val & 0x07ffff80; + m_rex3.m_x_end_frac = (val >> 7) & 0xf; + m_rex3.m_x_end_i = (int16_t)(val >> 11); + m_rex3.m_x_end_f = (uint32_t)val & 0x007fff80; + m_rex3.m_xy_end_i = (m_rex3.m_xy_end_i & 0x0000ffff) | (m_rex3.m_x_end_i << 16); +} + +void newport_base_device::write_y_end(int32_t val) +{ + m_rex3.m_y_end = val & 0x07ffff80; + m_rex3.m_y_end_frac = (val >> 7) & 0xf; + m_rex3.m_y_end_i = (int16_t)(val >> 11); + m_rex3.m_y_end_f = (uint32_t)val & 0x007fff80; + m_rex3.m_xy_end_i = (m_rex3.m_xy_end_i & 0xffff0000) | (uint16_t)m_rex3.m_y_end_i; +} + +WRITE64_MEMBER(newport_base_device::rex3_w) +{ +#if ENABLE_NEWVIEW_LOG + if (m_newview_log != nullptr) + { + uint32_t offset_lo = (uint32_t)offset; + uint32_t data_hi = (uint32_t)(data >> 32); + uint32_t data_lo = (uint32_t)data; + uint32_t mem_mask_hi = (uint32_t)(mem_mask >> 32); + uint32_t mem_mask_lo = (uint32_t)mem_mask; + + fwrite(&offset_lo, sizeof(uint32_t), 1, m_newview_log); + fwrite(&data_hi, sizeof(uint32_t), 1, m_newview_log); + fwrite(&data_lo, sizeof(uint32_t), 1, m_newview_log); + fwrite(&mem_mask_hi, sizeof(uint32_t), 1, m_newview_log); + fwrite(&mem_mask_lo, sizeof(uint32_t), 1, m_newview_log); + } +#endif + + switch (offset & ~(0x800/8)) + { + case 0x0000/8: + if (ACCESSING_BITS_32_63) + { + const uint32_t data32 = (uint32_t)(data >> 32); + LOGMASKED(LOG_REX3, "REX3 Draw Mode 1 Write: %08x\n", data32); + switch (data32 & 7) + { + case 0x00: + LOGMASKED(LOG_REX3, " Planes Enabled: None\n"); + break; + case 0x01: + LOGMASKED(LOG_REX3, " Planes Enabled: R/W RGB/CI\n"); + break; + case 0x02: + LOGMASKED(LOG_REX3, " Planes Enabled: R/W RGBA\n"); + break; + case 0x04: + LOGMASKED(LOG_REX3, " Planes Enabled: R/W OLAY\n"); + break; + case 0x05: + LOGMASKED(LOG_REX3, " Planes Enabled: R/W PUP\n"); + break; + case 0x06: + LOGMASKED(LOG_REX3, " Planes Enabled: R/W CID\n"); + break; + default: + LOGMASKED(LOG_REX3 | LOG_UNKNOWN, " Unknown Plane Enable Value\n"); + break; + } + switch ((data32 & 0x00000018) >> 3) + { + case 0x00: + LOGMASKED(LOG_REX3, " Plane Draw Depth: 4 bits\n"); + m_rex3.m_write_width = 0x0000000f; + break; + case 0x01: + LOGMASKED(LOG_REX3, " Plane Draw Depth: 8 bits\n"); + m_rex3.m_write_width = 0x000000ff; + break; + case 0x02: + LOGMASKED(LOG_REX3, " Plane Draw Depth: 12 bits\n"); + m_rex3.m_write_width = 0x000000ff; // TODO: 24-bit + break; + case 0x03: + LOGMASKED(LOG_REX3, " Plane Draw Depth: 32 bits\n"); + m_rex3.m_write_width = 0x000000ff; // TODO: 24-bit + break; + } + LOGMASKED(LOG_REX3, " DBuf Source Buffer: %d\n", BIT(data32, 5)); + LOGMASKED(LOG_REX3, " GL Y Coordinates: %d\n", BIT(data32, 6)); + LOGMASKED(LOG_REX3, " Enable Pxl Packing: %d\n", BIT(data32, 7)); + switch ((data32 & 0x00000300) >> 8) + { + case 0x00: + LOGMASKED(LOG_REX3, " HOSTRW Depth: 4 bits\n"); + break; + case 0x01: + LOGMASKED(LOG_REX3, " HOSTRW Depth: 8 bits\n"); + break; + case 0x02: + LOGMASKED(LOG_REX3, " HOSTRW Depth: 12 bits\n"); + break; + case 0x03: + LOGMASKED(LOG_REX3, " HOSTRW Depth: 32 bits\n"); + break; + } + LOGMASKED(LOG_REX3, " DWord Transfers: %d\n", BIT(data32, 10)); + LOGMASKED(LOG_REX3, " Swap Endianness: %d\n", BIT(data32, 11)); + LOGMASKED(LOG_REX3, " Compare Src > Dest: %d\n", BIT(data32, 12)); + LOGMASKED(LOG_REX3, " Compare Src = Dest: %d\n", BIT(data32, 13)); + LOGMASKED(LOG_REX3, " Compare Src < Dest: %d\n", BIT(data32, 14)); + LOGMASKED(LOG_REX3, " RGB Mode Select: %d\n", BIT(data32, 15)); + LOGMASKED(LOG_REX3, " Enable Dithering: %d\n", BIT(data32, 16)); + LOGMASKED(LOG_REX3, " Enable Fast Clear: %d\n", BIT(data32, 17)); + LOGMASKED(LOG_REX3, " Enable Blending: %d\n", BIT(data32, 18)); + switch ((data32 >> 19) & 7) + { + case 0x00: + LOGMASKED(LOG_REX3, " Src Blend Factor: 0\n"); + break; + case 0x01: + LOGMASKED(LOG_REX3, " Src Blend Factor: 1\n"); + break; + case 0x02: + LOGMASKED(LOG_REX3, " Src Blend Factor: Normalized Dest Color (or COLORBACK)\n"); + break; + case 0x03: + LOGMASKED(LOG_REX3, " Src Blend Factor: 1 - Normalized Dest Color (or COLORBACK)\n"); + break; + case 0x04: + LOGMASKED(LOG_REX3, " Src Blend Factor: Normalized Src Alpha\n"); + break; + case 0x05: + LOGMASKED(LOG_REX3, " Src Blend Factor: 1 - Normalized Src Alpha\n"); + break; + default: + LOGMASKED(LOG_REX3 | LOG_UNKNOWN, " Unknown Src Blend Factor: %02x\n", (data32 >> 19) & 7); + break; + } + switch ((data32 >> 22) & 7) + { + case 0x00: + LOGMASKED(LOG_REX3, " Dest Blend Factor: 0\n"); + break; + case 0x01: + LOGMASKED(LOG_REX3, " Dest Blend Factor: 1\n"); + break; + case 0x02: + LOGMASKED(LOG_REX3, " Dest Blend Factor: Normalized Src Color\n"); + break; + case 0x03: + LOGMASKED(LOG_REX3, " Dest Blend Factor: 1 - Normalized Src Color\n"); + break; + case 0x04: + LOGMASKED(LOG_REX3, " Dest Blend Factor: Normalized Src Alpha\n"); + break; + case 0x05: + LOGMASKED(LOG_REX3, " Dest Blend Factor: 1 - Normalized Src Alpha\n"); + break; + default: + LOGMASKED(LOG_REX3 | LOG_UNKNOWN, " Unknown Src Blend Factor: %02x\n", (data32 & 0x00380000) >> 19); + break; + } + LOGMASKED(LOG_REX3, " COLORBACK Dest Blend: %d\n", BIT(data32, 25)); + LOGMASKED(LOG_REX3, " Enable Pxl Prefetch: %d\n", BIT(data32, 26)); + LOGMASKED(LOG_REX3, " SFACTOR Src Alpha: %d\n", BIT(data32, 27)); + switch ((data32 >> 28) & 15) + { + case 0x00: + LOGMASKED(LOG_REX3, " Logical Op. Type: 0\n"); + break; + case 0x01: + LOGMASKED(LOG_REX3, " Logical Op. Type: Src & Dst\n"); + break; + case 0x02: + LOGMASKED(LOG_REX3, " Logical Op. Type: Src & ~Dst\n"); + break; + case 0x03: + LOGMASKED(LOG_REX3, " Logical Op. Type: Src\n"); + break; + case 0x04: + LOGMASKED(LOG_REX3, " Logical Op. Type: ~Src & Dst\n"); + break; + case 0x05: + LOGMASKED(LOG_REX3, " Logical Op. Type: Dst\n"); + break; + case 0x06: + LOGMASKED(LOG_REX3, " Logical Op. Type: Src ^ Dst\n"); + break; + case 0x07: + LOGMASKED(LOG_REX3, " Logical Op. Type: Src | Dst\n"); + break; + case 0x08: + LOGMASKED(LOG_REX3, " Logical Op. Type: ~(Src | Dst)\n"); + break; + case 0x09: + LOGMASKED(LOG_REX3, " Logical Op. Type: ~(Src ^ Dst)\n"); + break; + case 0x0a: + LOGMASKED(LOG_REX3, " Logical Op. Type: ~Dst\n"); + break; + case 0x0b: + LOGMASKED(LOG_REX3, " Logical Op. Type: Src | ~Dst\n"); + break; + case 0x0c: + LOGMASKED(LOG_REX3, " Logical Op. Type: ~Src\n"); + break; + case 0x0d: + LOGMASKED(LOG_REX3, " Logical Op. Type: ~Src | Dst\n"); + break; + case 0x0e: + LOGMASKED(LOG_REX3, " Logical Op. Type: ~(Src & Dst)\n"); + break; + case 0x0f: + LOGMASKED(LOG_REX3, " Logical Op. Type: 1\n"); + break; + } + m_rex3.m_draw_mode1 = data32; + + static const uint32_t s_store_shift[4] = { 4, 0, 12, 0 }; + m_rex3.m_plane_enable = m_rex3.m_draw_mode1 & 7; + m_rex3.m_plane_depth = (m_rex3.m_draw_mode1 >> 3) & 3; + m_rex3.m_rwpacked = BIT(m_rex3.m_draw_mode1, 7); + m_rex3.m_hostdepth = (m_rex3.m_draw_mode1 >> 8) & 3; + m_rex3.m_rwdouble = BIT(m_rex3.m_draw_mode1, 10); + m_rex3.m_sfactor = (m_rex3.m_draw_mode1 >> 19) & 7; + m_rex3.m_dfactor = (m_rex3.m_draw_mode1 >> 22) & 7; + m_rex3.m_logicop = (m_rex3.m_draw_mode1 >> 28) & 15; + + m_rex3.m_store_shift = BIT(m_rex3.m_draw_mode1, 5) ? s_store_shift[m_rex3.m_plane_depth] : 0; + + m_rex3.m_host_shift = 64 - s_host_shifts[m_rex3.m_hostdepth]; + } + if (ACCESSING_BITS_0_31) + { + const uint32_t data32 = (uint32_t)data; + LOGMASKED(LOG_REX3, "REX3 Draw Mode 0 Write: %08x\n", data32); + switch (data32 & 3) + { + case 0x00: + LOGMASKED(LOG_REX3, " Primitive Function: No Op\n"); + break; + case 0x01: + LOGMASKED(LOG_REX3, " Primitive Function: Read From FB\n"); + break; + case 0x02: + LOGMASKED(LOG_REX3, " Primitive Function: Draw To FB\n"); + break; + case 0x03: + LOGMASKED(LOG_REX3, " Primitive Function: Copy FB To FB\n"); + break; + } + switch ((data32 & 0x0000001c) >> 2) + { + case 0x00: + LOGMASKED(LOG_REX3, " Addressing Mode: Span/Point\n"); + break; + case 0x01: + LOGMASKED(LOG_REX3, " Addressing Mode: Block\n"); + break; + case 0x02: + LOGMASKED(LOG_REX3, " Addressing Mode: Bresenham Line, Integer Endpoints\n"); + break; + case 0x03: + LOGMASKED(LOG_REX3, " Addressing Mode: Bresenham Line, Fractional Endpoints\n"); + break; + case 0x04: + LOGMASKED(LOG_REX3, " Addressing Mode: AA Bresenham Line\n"); + break; + default: + LOGMASKED(LOG_REX3 | LOG_UNKNOWN, " Unknown Addressing Mode: %02x\n", (data32 & 0x0000001c) >> 2); + break; + } + LOGMASKED(LOG_REX3, " Iterator Setup: %d\n", BIT(data32, 5)); + LOGMASKED(LOG_REX3, " RGB/CI Draw Source: %d\n", BIT(data32, 6)); + LOGMASKED(LOG_REX3, " Alpha Draw Source: %d\n", BIT(data32, 7)); + LOGMASKED(LOG_REX3, " Stop On X: %d\n", BIT(data32, 8)); + LOGMASKED(LOG_REX3, " Stop On Y: %d\n", BIT(data32, 9)); + LOGMASKED(LOG_REX3, " Skip Start Point: %d\n", BIT(data32, 10)); + LOGMASKED(LOG_REX3, " Skip End Point: %d\n", BIT(data32, 11)); + LOGMASKED(LOG_REX3, " Enable Patterning: %d\n", BIT(data32, 12)); + LOGMASKED(LOG_REX3, " Enable Stippling: %d\n", BIT(data32, 13)); + LOGMASKED(LOG_REX3, " Stipple Advance: %d\n", BIT(data32, 14)); + LOGMASKED(LOG_REX3, " Limit Draw To 32px: %d\n", BIT(data32, 15)); + LOGMASKED(LOG_REX3, " Z Opaque Stipple %d\n", BIT(data32, 16)); + LOGMASKED(LOG_REX3, " LS Opaque Stipple: %d\n", BIT(data32, 17)); + LOGMASKED(LOG_REX3, " Enable Lin. Shade: %d\n", BIT(data32, 18)); + LOGMASKED(LOG_REX3, " Left-Right Only: %d\n", BIT(data32, 19)); + LOGMASKED(LOG_REX3, " Offset by XYMove: %d\n", BIT(data32, 20)); + LOGMASKED(LOG_REX3, " Enable CI Clamping: %d\n", BIT(data32, 21)); + LOGMASKED(LOG_REX3, " Enable End Filter: %d\n", BIT(data32, 22)); + LOGMASKED(LOG_REX3, " Enable Y+2 Stride: %d\n", BIT(data32, 23)); + m_rex3.m_draw_mode0 = data32; + + m_rex3.m_color_host = BIT(m_rex3.m_draw_mode0, 6); + } + break; + case 0x0008/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Line Stipple Mode Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_ls_mode = (uint32_t)(data >> 32) & 0xfffffff; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Line Stipple Pattern Write: %08x\n", (uint32_t)data); + m_rex3.m_ls_pattern = (uint32_t)data; + } + break; + case 0x0010/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Line Stipple Pattern (Save) Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_ls_pattern_saved = (uint32_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Pattern Register Write: %08x\n", (uint32_t)data); + m_rex3.m_z_pattern = (uint32_t)data; + } + break; + case 0x0018/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Opaque Pattern / Blendfunc Dest Color Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_color_back = (uint32_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 VRAM Fastclear Color Write: %08x\n", (uint32_t)data); + m_rex3.m_color_vram = (uint32_t)data; + } + break; + case 0x0020/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 AFUNCTION Reference Alpha Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_alpha_ref = (uint8_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Stall GFIFO Write: %08x\n", data); + break; + } + break; + case 0x0028/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 0 X Min/Max Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_smask_x[0] = (uint32_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 0 Y Min/Max Write: %08x\n", (uint32_t)data); + m_rex3.m_smask_y[0] = (uint32_t)data; + } + break; + case 0x0030/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Line/Span Setup Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_setup = (uint32_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 ZPattern Enable Write\n"); + m_rex3.m_step_z = 1; + } + break; + case 0x0038/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Update LSPATTERN/LSRCOUNT\n"); + m_rex3.m_ls_pattern = m_rex3.m_ls_pattern_saved; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Update LSPATSAVE/LSRCNTSAVE\n"); + m_rex3.m_ls_pattern_saved = m_rex3.m_ls_pattern; + } + break; + case 0x0100/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 XStart Write: %08x\n", (uint32_t)(data >> 32)); + write_x_start((int32_t)(data >> 32)); + m_rex3.m_x_save = m_rex3.m_x_start_i; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 YStart Write: %08x\n", (uint32_t)data); + write_y_start((int32_t)data); + } + break; + case 0x0108/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 XEnd Write: %08x\n", (uint32_t)(data >> 32)); + write_x_end((int32_t)(data >> 32)); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 YEnd Write: %08x\n", (uint32_t)data); + write_y_end((int32_t)data); + } + break; + case 0x0110/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 XSave Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_x_save = (int16_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 XYMove Write: %08x\n", (uint32_t)data); + m_rex3.m_xy_move = (uint32_t)data; + m_rex3.m_x_move = (int16_t)(m_rex3.m_xy_move >> 16); + m_rex3.m_y_move = (int16_t)m_rex3.m_xy_move; + } + break; + case 0x0118/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham D Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_bres_d = (uint32_t)(data >> 32) & 0x7ffffff; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham S1 Write: %08x\n", (uint32_t)data); + m_rex3.m_bres_s1 = (uint32_t)data & 0x1ffff; + } + break; + case 0x0120/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham Octant & Incr1 Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_bres_octant_inc1 = (uint32_t)(data >> 32) & 0x70fffff; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham Octant Rounding Mode & Incr2 Write: %08x\n", (uint32_t)data); + m_rex3.m_bres_round_inc2 = data & 0xff1fffff; + } + break; + case 0x0128/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham E1 Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_bres_e1 = (uint16_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Bresenham S2 Write: %08x\n", (uint32_t)data); + m_rex3.m_bres_s2 = (uint32_t)data & 0x3ffffff; + } + break; + case 0x0130/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 AA Line Weight Table 1/2 Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_a_weight0 = (uint32_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 AA Line Weight Table 2/2 Write: %08x\n", (uint32_t)data); + m_rex3.m_a_weight1 = (uint32_t)data; + } + break; + case 0x0138/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 GL XStart Write: %08x\n", (uint32_t)(data >> 32)); + write_x_start((int32_t)(data >> 32) & 0x007fff80); + m_rex3.m_x_save = m_rex3.m_x_start_i; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 GL YStart Write: %08x\n", (uint32_t)data); + write_y_start((int32_t)data & 0x007fff80); + } + break; + case 0x0140/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 GL XEnd Write: %08x\n", (uint32_t)(data >> 32)); + write_x_end((int32_t)(data >> 32) & 0x007fff80); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 GL YEnd Write: %08x\n", (uint32_t)data); + write_y_end((int32_t)data & 0x007fff80); + } + break; + case 0x0148/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 XStart (integer) Write: %08x\n", (uint32_t)(data >> 32)); + write_x_start(((int32_t)(int16_t)(data >> 32)) << 11); + m_rex3.m_x_save = m_rex3.m_x_start_i; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 GL XEnd (copy) Write: %08x\n", (uint32_t)data); + write_x_end((int32_t)data & 0x007fff80); + } + break; + case 0x0150/8: + if (ACCESSING_BITS_32_63) + { + const uint32_t data32 = (uint32_t)(data >> 32); + LOGMASKED(LOG_REX3, "REX3 XYStart (integer) Write: %08x\n", data32); + write_x_start(((int32_t)(int16_t)(data >> 48)) << 11); + write_y_start(((int32_t)(int16_t)(data >> 32)) << 11); + m_rex3.m_x_save = m_rex3.m_x_start_i; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 XYEnd (integer) Write: %08x\n", (uint32_t)data); + write_x_end(((int32_t)(int16_t)(data >> 16)) << 11); + write_y_end(((int32_t)(int16_t)(data >> 0)) << 11); + } + break; + case 0x0158/8: + if (ACCESSING_BITS_32_63) + { + const uint32_t data32 = (uint32_t)(data >> 32); + LOGMASKED(LOG_REX3, "REX3 XStartEnd (integer) Write: %08x\n", data32); + write_x_start(((int32_t)(int16_t)(data >> 48)) << 11); + write_x_end(((int32_t)(int16_t)(data >> 32)) << 11); + m_rex3.m_x_save = m_rex3.m_x_start_i; + } + break; + case 0x0200/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Red/CI Full State Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_color_red = (int32_t)((data >> 32) & 0xffffff); + if (m_rex3.m_plane_depth == 2 && !BIT(m_rex3.m_draw_mode1, 15)) + { + m_rex3.m_color_i = m_rex3.m_color_red >> 9; + } + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Alpha Full State Write: %08x\n", (uint32_t)data); + m_rex3.m_color_alpha = (int32_t)(data & 0xfffff); + } + break; + case 0x0208/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Green Full State Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_color_green = (int32_t)((data >> 32) & 0xfffff); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Blue Full State Write: %08x\n", (uint32_t)data); + m_rex3.m_color_blue = (int32_t)(data & 0xfffff); + } + break; + case 0x0210/8: + { + if (ACCESSING_BITS_32_63) + { + uint32_t data32 = (uint32_t)(data >> 32); + LOGMASKED(LOG_REX3, "REX3 Red/CI Slope Write: %08x\n", data32); + data32 &= 0x807fffff; + int32_t temp = 0; + if (BIT(data32, 31)) + { + temp = 0x00800000 - (data32 & 0x7fffff); + temp |= 0x00800000; + } + else + { + temp = data32 & 0x7fffff; + } + m_rex3.m_slope_red = temp; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Alpha Slope Write: %08x\n", (uint32_t)data); + data &= 0x8007ffff; + int32_t temp = 0; + if (BIT(data, 31)) + { + temp = 0x00080000 - (data & 0x7ffff); + temp |= 0x00080000; + } + else + { + temp = data & 0x7ffff; + } + m_rex3.m_slope_alpha = temp; + } + break; + } + case 0x0218/8: + { + if (ACCESSING_BITS_32_63) + { + uint32_t data32 = (uint32_t)(data >> 32); + LOGMASKED(LOG_REX3, "REX3 Green Slope Write: %08x\n", data32); + data32 &= 0x8007ffff; + int32_t temp = 0; + if (BIT(data32, 31)) + { + temp = 0x00080000 - (data32 & 0x7ffff); + temp |= 0x00080000; + } + else + { + temp = data32 & 0x7ffff; + } + m_rex3.m_slope_green = temp; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Blue Slope Write: %08x\n", (uint32_t)data); + data &= 0x8007ffff; + int32_t temp = 0; + if (BIT(data, 31)) + { + temp = 0x00080000 - (data & 0x7ffff); + temp |= 0x00080000; + } + else + { + temp = data & 0x7ffff; + } + m_rex3.m_slope_blue = temp; + } + break; + } + case 0x0220/8: + if (ACCESSING_BITS_32_63) + { + const uint32_t data32 = (uint32_t)(data >> 32); + LOGMASKED(LOG_REX3, "REX3 Write Mask Write: %08x\n", data32); + m_rex3.m_write_mask = data32 & 0xffffff; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Packed Color Fractions Write: %08x\n", (uint32_t)data); + m_rex3.m_color_i = (uint32_t)data; + } + break; + case 0x0228/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Color Index Zeros Overflow Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_zero_overflow = (uint32_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Red/CI Slope (copy) Write: %08x\n", (uint32_t)data); + m_rex3.m_slope_red = (uint32_t)data; + } + break; + case 0x0230/8: + LOGMASKED(LOG_REX3, "REX3 Host Data Port Write: %08x%08x & %08x%08x\n", (uint32_t)(data >> 32), (uint32_t)data, (uint64_t)(mem_mask >> 32), (uint32_t)mem_mask); + COMBINE_DATA(&m_rex3.m_host_dataport); + m_rex3.m_host_shift = 64 - s_host_shifts[m_rex3.m_hostdepth]; + break; + case 0x0238/8: + if (ACCESSING_BITS_32_63) + { + data >>= 32; + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Mode Write: %08x\n", (uint32_t)data); + switch (data & 3) + { + case 0x00: + LOGMASKED(LOG_REX3, " Transfer Width: 4 bytes\n"); + m_rex3.m_xfer_width = 4; + break; + case 0x01: + LOGMASKED(LOG_REX3, " Transfer Width: 1 bytes\n"); + m_rex3.m_xfer_width = 1; + break; + case 0x02: + LOGMASKED(LOG_REX3, " Transfer Width: 2 bytes\n"); + m_rex3.m_xfer_width = 2; + break; + case 0x03: + LOGMASKED(LOG_REX3, " Transfer Width: 3 bytes\n"); + m_rex3.m_xfer_width = 3; + break; + } + LOGMASKED(LOG_REX3, " Enable Data Packing: %d\n", BIT(data, 2)); + LOGMASKED(LOG_REX3, " Enable Auto-Increment: %d\n", BIT(data, 3)); + LOGMASKED(LOG_REX3, " DCB Reg Select Adr: %d\n", (data & 0x00000070 ) >> 4); + LOGMASKED(LOG_REX3, " DCB Slave Address: %d\n", (data & 0x00000780 ) >> 7); + LOGMASKED(LOG_REX3, " Use Sync XFer ACK: %d\n", (data & 0x00000800 ) >> 11); + LOGMASKED(LOG_REX3, " Use Async XFer ACK: %d\n", (data & 0x00001000 ) >> 12); + LOGMASKED(LOG_REX3, " GIO CLK Cycle Width: %d\n", (data & 0x0003e000 ) >> 13); + LOGMASKED(LOG_REX3, " GIO CLK Cycle Hold: %d\n", (data & 0x007c0000 ) >> 18); + LOGMASKED(LOG_REX3, " GIO CLK Cycle Setup: %d\n", (data & 0x0f800000 ) >> 23); + LOGMASKED(LOG_REX3, " Swap Byte Ordering: %d\n", (data & 0x10000000 ) >> 28); + m_rex3.m_dcb_reg_select = (data & 0x00000070) >> 4; + m_rex3.m_dcb_slave_select = (data & 0x00000780) >> 7; + m_rex3.m_dcb_mode = data & 0x1fffffff; + } + break; + case 0x0240/8: + if (ACCESSING_BITS_32_63) + { + const uint32_t data32 = (uint32_t)(data >> 32); + m_rex3.m_dcb_data_msw = data32; + switch (m_rex3.m_dcb_slave_select) + { + case DCB_ADDR_VC2: + vc2_write(data32); + break; + case DCB_ADDR_CMAP01: + cmap0_write(data32); + //cmap1_write(data32); + break; + case DCB_ADDR_CMAP0: + cmap0_write(data32); + break; + case DCB_ADDR_CMAP1: + //cmap1_write(data32); + break; + case DCB_ADDR_XMAP01: + xmap0_write(data32); + xmap1_write(data32); + break; + case DCB_ADDR_XMAP0: + xmap0_write(data32); + break; + case DCB_ADDR_XMAP1: + xmap1_write(data32); + break; + case DCB_ADDR_RAMDAC: + ramdac_write(data32); + break; + case DCB_ADDR_CC1: + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Write to CC1 (not yet implemented): %08x\n", data32); + break; + case DCB_ADDR_AB1: + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Write to AB1 (not yet implemented): %08x\n", data32); + break; + case DCB_ADDR_PCD: + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data MSW Write to PCD (not yet implemented): %08x\n", data32); + // Presenter not connected; simulate a bus timeout + m_rex3.m_status |= STATUS_BACKBUSY; + m_dcb_timeout_timer->adjust(attotime::from_msec(1)); + break; + default: + LOGMASKED(LOG_REX3 | LOG_UNKNOWN, "REX3 Display Control Bus Data MSW Write: %08x\n", data32); + break; + } + if (BIT(m_rex3.m_dcb_mode, 3)) + { + m_rex3.m_dcb_reg_select++; + m_rex3.m_dcb_reg_select &= 7; + } + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Display Control Bus Data LSW Write: %08x\n", (uint32_t)data); + m_rex3.m_dcb_data_lsw = (uint32_t)data; + } + break; + case 0x1300/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 1 X Min/Max Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_smask_x[1] = (uint32_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 1 Y Min/Max Write: %08x\n", (uint32_t)data); + m_rex3.m_smask_y[1] = (uint32_t)data; + } + break; + case 0x1308/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 2 X Min/Max Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_smask_x[2] = (uint32_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 2 Y Min/Max Write: %08x\n", (uint32_t)data); + m_rex3.m_smask_y[2] = (uint32_t)data; + } + break; + case 0x1310/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 3 X Min/Max Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_smask_x[3] = (uint32_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 3 Y Min/Max Write: %08x\n", (uint32_t)data); + m_rex3.m_smask_y[3] = (uint32_t)data; + } + break; + case 0x1318/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 4 X Min/Max Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_smask_x[4] = (uint32_t)(data >> 32); + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 Screenmask 4 Y Min/Max Write: %08x\n", (uint32_t)data); + m_rex3.m_smask_y[4] = (uint32_t)data; + } + break; + case 0x1320/8: + if (ACCESSING_BITS_32_63) + { + const uint32_t data32 = (uint32_t)(data >> 32); + LOGMASKED(LOG_REX3, "REX3 Top of Screen Scanline Write: %08x\n", data32); + m_rex3.m_top_scanline = data32 & 0x3ff; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "REX3 XY Window Write: %08x\n", (uint32_t)data); + m_rex3.m_xy_window = (uint32_t)data; + m_rex3.m_x_window = (int16_t)(m_rex3.m_xy_window >> 16); + m_rex3.m_y_window = (int16_t)m_rex3.m_xy_window; + } + break; + case 0x1328/8: + if (ACCESSING_BITS_32_63) + { + const uint32_t data32 = (uint32_t)(data >> 32); + LOGMASKED(LOG_REX3, "REX3 Clipping Mode Write: %08x\n", data32); + m_rex3.m_clip_mode = data32 & 0x1fff; + } + if (ACCESSING_BITS_0_31) + { + LOGMASKED(LOG_REX3, "Request GFIFO Stall\n"); + } + break; + case 0x1330/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "REX3 Config Write: %08x\n", (uint32_t)(data >> 32)); + m_rex3.m_config = (data >> 32) & 0x1fffff; + } + break; + case 0x1340/8: + if (ACCESSING_BITS_32_63) + { + LOGMASKED(LOG_REX3, "Reset DCB Bus and Flush BFIFO\n"); + } + break; + default: + LOGMASKED(LOG_REX3 | LOG_UNKNOWN, "Unknown REX3 Write: %08x (%08x): %08x\n", 0xbf0f0000 + (offset << 2), mem_mask, data); + break; + } + + if (offset & 0x00000100) + { + do_rex3_command(); + } +} + +void newport_base_device::install_device() +{ + m_gio64->install_graphics(*this, &newport_base_device::mem_map); +} + +void newport_base_device::device_add_mconfig(machine_config &config) +{ + /* video hardware */ + SCREEN(config, m_screen, SCREEN_TYPE_RASTER); + m_screen->set_refresh_hz(60); + m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(2500)); /* not accurate */ + //m_screen->set_size(2048, 2048); + //m_screen->set_visarea(0, 2047, 0, 2047); + m_screen->set_size(1280+64, 1024+64); + m_screen->set_visarea(0, 1279, 0, 1023); + m_screen->set_screen_update(FUNC(newport_base_device::screen_update)); + m_screen->screen_vblank().set(FUNC(newport_base_device::vblank_w)); +} diff --git a/src/devices/bus/gio64/newport.h b/src/devices/bus/gio64/newport.h new file mode 100644 index 00000000000..b9738328e26 --- /dev/null +++ b/src/devices/bus/gio64/newport.h @@ -0,0 +1,351 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/* + SGI "Newport" graphics board used in the Indy and some Indigo2s +*/ + +#ifndef MAME_BUS_GIO_NEWPORT_H +#define MAME_BUS_GIO_NEWPORT_H + +#pragma once + +#include "gio64.h" +#include "screen.h" + +#define ENABLE_NEWVIEW_LOG (0) + +class newport_base_device : public device_t + , public device_palette_interface + , public device_gio64_card_interface +{ +public: + newport_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t global_mask); + + // device_gio_slot_interface overrides + virtual void install_device() override; + + DECLARE_READ64_MEMBER(rex3_r); + DECLARE_WRITE64_MEMBER(rex3_w); + + uint32_t screen_update(screen_device &device, bitmap_rgb32 &bitmap, const rectangle &cliprect); + + DECLARE_WRITE_LINE_MEMBER(vblank_w); + +protected: + virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; + virtual void device_add_mconfig(machine_config &config) override; + virtual uint32_t palette_entries() const override { return 0x2000; } + virtual void device_start() override; + virtual void device_reset() override; + + void mem_map(address_map &map) override; + + static constexpr device_timer_id DCB_TIMEOUT = 0; + + enum + { + DCR_CURSOR_FUNC_ENABLE_BIT = 4, + DCR_CURSOR_ENABLE_BIT = 7, + + DCR_CURSOR_MODE_BIT = 8, + DCR_CURSOR_MODE_GLYPH = 0, + DCR_CURSOR_MODE_CROSSHAIR = 1, + + DCR_CURSOR_SIZE_BIT = 9, + DCR_CURSOR_SIZE_32 = 0, + DCR_CURSOR_SIZE_64 = 1 + }; + + enum + { + DCB_ADDR_VC2, + DCB_ADDR_CMAP01, + DCB_ADDR_CMAP0, + DCB_ADDR_CMAP1, + DCB_ADDR_XMAP01, + DCB_ADDR_XMAP0, + DCB_ADDR_XMAP1, + DCB_ADDR_RAMDAC, + DCB_ADDR_CC1, + DCB_ADDR_AB1, + DCB_ADDR_PCD = 12 + }; + + enum + { + STATUS_GFXBUSY = (1 << 3), + STATUS_BACKBUSY = (1 << 4), + STATUS_VRINT = (1 << 5), + STATUS_VIDEOINT = (1 << 6), + STATUS_GFIFOLEVEL_SHIFT = 7, + STATUS_GFIFOLEVEL_MASK = (0x3f << STATUS_GFIFOLEVEL_SHIFT), + STATUS_BFIFOLEVEL_SHIFT = 13, + STATUS_BFIFOLEVEL_MASK = (0x1f << STATUS_BFIFOLEVEL_SHIFT), + STATUS_BFIFO_INT = 18, + STATUS_GFIFO_INT = 19 + }; + + struct vc2_t + { + uint16_t m_vid_entry; + uint16_t m_cursor_entry; + uint16_t m_cursor_x; + uint16_t m_cursor_y; + uint16_t m_cur_cursor_x; + uint16_t m_did_entry; + uint16_t m_scanline_len; + uint16_t m_ram_addr; + uint16_t m_vt_frame_ptr; + uint16_t m_vt_line_ptr; + uint16_t m_vt_line_run; + uint16_t m_vt_line_count; + uint16_t m_cursor_table_ptr; + uint16_t m_work_cursor_y; + uint16_t m_did_frame_ptr; + uint16_t m_did_line_ptr; + uint16_t m_display_ctrl; + uint16_t m_config; + uint16_t m_ram[0x8000]; + uint8_t m_reg_idx; + uint16_t m_reg_data; + }; + + + struct xmap_t + { + uint32_t m_config; + uint32_t m_revision; + uint32_t m_entries; + uint32_t m_cursor_cmap; + uint32_t m_popup_cmap; + uint32_t m_mode_table_idx; + uint32_t m_mode_table[0x20]; + }; + + struct rex3_t + { + uint32_t m_draw_mode0; + bool m_color_host; + uint32_t m_draw_mode1; + uint8_t m_plane_enable; + uint8_t m_plane_depth; + bool m_rwpacked; + bool m_rwdouble; + uint8_t m_hostdepth; + uint8_t m_sfactor; + uint8_t m_dfactor; + uint8_t m_logicop; + + uint32_t m_store_shift; + uint32_t m_host_shift; + + uint32_t m_write_width; + uint32_t m_ls_mode; + uint32_t m_ls_pattern; + uint32_t m_ls_pattern_saved; + uint32_t m_z_pattern; + uint32_t m_color_back; + uint32_t m_color_vram; + uint32_t m_alpha_ref; + uint32_t m_setup; + uint32_t m_step_z; + int32_t m_x_start; + int32_t m_y_start; + int32_t m_x_end; + int32_t m_y_end; + int16_t m_x_start_frac; + int16_t m_y_start_frac; + int16_t m_x_end_frac; + int16_t m_y_end_frac; + int16_t m_x_save; + uint32_t m_xy_move; + int16_t m_x_move; + int16_t m_y_move; + uint32_t m_bres_d; + uint32_t m_bres_s1; + uint32_t m_bres_octant_inc1; + uint32_t m_bres_round_inc2; + uint32_t m_bres_e1; + uint32_t m_bres_s2; + uint32_t m_a_weight0; + uint32_t m_a_weight1; + uint32_t m_x_start_f; + uint32_t m_y_start_f; + uint32_t m_x_end_f; + uint32_t m_y_end_f; + int16_t m_x_start_i; + uint32_t m_xy_start_i; + int16_t m_y_start_i; + uint32_t m_xy_end_i; + int16_t m_x_end_i; + int16_t m_y_end_i; + uint32_t m_x_start_end_i; + uint32_t m_color_red; + uint32_t m_color_alpha; + uint32_t m_color_green; + uint32_t m_color_blue; + uint32_t m_slope_red; + uint32_t m_slope_alpha; + uint32_t m_slope_green; + uint32_t m_slope_blue; + uint32_t m_write_mask; + uint32_t m_color_i; + uint32_t m_zero_overflow; + uint64_t m_host_dataport; + uint32_t m_dcb_mode; + uint32_t m_dcb_reg_select; + uint32_t m_dcb_slave_select; + uint32_t m_dcb_data_msw; + uint32_t m_dcb_data_lsw; + uint32_t m_smask_x[5]; + uint32_t m_smask_y[5]; + uint32_t m_top_scanline; + uint32_t m_xy_window; + int16_t m_x_window; + int16_t m_y_window; + uint32_t m_clip_mode; + uint32_t m_config; + uint32_t m_status; + uint8_t m_xfer_width; + }; + + struct cmap_t + { + uint16_t m_palette_idx; + uint32_t m_palette[0x10000]; + }; + + uint8_t get_cursor_pixel(int x, int y); + + // internal state + + uint32_t cmap0_read(); + void cmap0_write(uint32_t data); + uint32_t cmap1_read(); + uint32_t xmap0_read(); + void xmap0_write(uint32_t data); + uint32_t xmap1_read(); + void xmap1_write(uint32_t data); + uint32_t vc2_read(); + void vc2_write(uint32_t data); + void ramdac_write(uint32_t data); + + void write_x_start(int32_t val); + void write_y_start(int32_t val); + void write_x_end(int32_t val); + void write_y_end(int32_t val); + + bool pixel_clip_pass(int16_t x, int16_t y); + void write_pixel(uint32_t color); + void write_pixel(int16_t x, int16_t y, uint32_t color); + void blend_pixel(uint32_t *dest_buf, uint32_t src); + void logic_pixel(uint32_t *dest_buf, uint32_t src); + void store_pixel(uint32_t *dest_buf, uint32_t src); + + void iterate_shade(); + + virtual uint32_t get_cmap_revision() = 0; + virtual uint32_t get_xmap_revision() = 0; + + uint32_t get_host_color(); + uint32_t get_rgb_color(int16_t x, int16_t y); + + uint32_t convert_4bpp_bgr_to_8bpp(uint8_t pix_in); + uint32_t convert_4bpp_bgr_to_12bpp(uint8_t pix_in); + uint32_t convert_4bpp_bgr_to_24bpp(uint8_t pix_in); + uint32_t convert_8bpp_bgr_to_4bpp(uint8_t pix_in); + uint32_t convert_8bpp_bgr_to_12bpp(uint8_t pix_in); + uint32_t convert_8bpp_bgr_to_24bpp(uint8_t pix_in); + uint32_t convert_12bpp_bgr_to_4bpp(uint16_t pix_in); + uint32_t convert_12bpp_bgr_to_8bpp(uint16_t pix_in); + uint32_t convert_12bpp_bgr_to_24bpp(uint16_t pix_in); + uint32_t convert_24bpp_bgr_to_4bpp(uint32_t pix_in); + uint32_t convert_24bpp_bgr_to_8bpp(uint32_t pix_in); + uint32_t convert_24bpp_bgr_to_12bpp(uint32_t pix_in); + + uint32_t convert_4bpp_bgr_to_24bpp_rgb(uint8_t pix_in); + uint32_t convert_8bpp_bgr_to_24bpp_rgb(uint8_t pix_in); + uint32_t convert_12bpp_bgr_to_24bpp_rgb(uint16_t pix_in); + + struct bresenham_octant_info_t + { + int16_t incrx1; + int16_t incrx2; + int16_t incry1; + int16_t incry2; + uint8_t loop; + }; + uint8_t get_octant(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t dx, uint16_t dy); + void do_fline(uint32_t color); + void do_iline(uint32_t color); + + uint32_t do_pixel_read(); + uint64_t do_pixel_word_read(); + + void do_rex3_command(); + + void decode_vt_line(uint32_t line, uint32_t line_seq_ptr); + void decode_vt_table(); + void update_screen_size(); + + void ramdac_remap(uint32_t *dest); + + required_device m_screen; + + uint32_t m_ramdac_lut_r[256]; + uint32_t m_ramdac_lut_g[256]; + uint32_t m_ramdac_lut_b[256]; + uint8_t m_ramdac_lut_index; + + vc2_t m_vc2; + xmap_t m_xmap0; + xmap_t m_xmap1; + rex3_t m_rex3; + std::unique_ptr m_rgbci; + std::unique_ptr m_olay; + std::unique_ptr m_pup; + std::unique_ptr m_cid; + std::unique_ptr m_vt_table; + cmap_t m_cmap0; + uint32_t m_global_mask; + emu_timer *m_dcb_timeout_timer; + + int m_readout_x0; + int m_readout_y0; + int m_readout_x1; + int m_readout_y1; + +#if ENABLE_NEWVIEW_LOG + void start_logging(); + void stop_logging(); + + FILE *m_newview_log; +#endif + + static const uint32_t s_host_shifts[4]; +}; + +class gio64_xl8_device : public newport_base_device +{ +public: + gio64_xl8_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0U); + +protected: + virtual uint32_t get_cmap_revision() override; + virtual uint32_t get_xmap_revision() override; +}; + +class gio64_xl24_device : public newport_base_device +{ +public: + gio64_xl24_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0U); + +protected: + virtual uint32_t get_cmap_revision() override; + virtual uint32_t get_xmap_revision() override; +}; + +DECLARE_DEVICE_TYPE(GIO64_XL8, gio64_xl8_device) +DECLARE_DEVICE_TYPE(GIO64_XL24, gio64_xl24_device) + +#endif // MAME_BUS_GIO_NEWPORT_H diff --git a/src/devices/bus/sbus/artecon.cpp b/src/devices/bus/sbus/artecon.cpp new file mode 100644 index 00000000000..f306494035b --- /dev/null +++ b/src/devices/bus/sbus/artecon.cpp @@ -0,0 +1,72 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Artecon SB-300P 3-serial 1-parallel SBus card skeleton + + The Artecon SB series of SBus cards uses up to 4 Cirrus Logic + CL-CD1400 Four-Channel Serial/Parallel Communications Engines. + + Each chip supports up to four full-duplex serial channels, or three + full-duplex serial channels and one high-speed bidirectional parallel + channel. + +***************************************************************************/ + +#include "emu.h" +#include "artecon.h" + +DEFINE_DEVICE_TYPE(SBUS_SB300P, sbus_artecon_device, "sb300p", "Artecon SB-300P 3S/1P controller") + +void sbus_artecon_device::mem_map(address_map &map) +{ + map(0x00000000, 0x01ffffff).rw(FUNC(sbus_artecon_device::unknown_r), FUNC(sbus_artecon_device::unknown_w)); + map(0x00000000, 0x00003fff).r(FUNC(sbus_artecon_device::rom_r)); +} + +ROM_START( sbus_artecon ) + ROM_REGION32_BE(0x8000, "prom", ROMREGION_ERASEFF) + ROM_LOAD( "artecon_sbus_port.bin", 0x0000, 0x4000, CRC(bced6981) SHA1(1c6006fb8cb555eff0cb7c2783c776d05c6797f8)) +ROM_END + +const tiny_rom_entry *sbus_artecon_device::device_rom_region() const +{ + return ROM_NAME( sbus_artecon ); +} + +void sbus_artecon_device::device_add_mconfig(machine_config &config) +{ +} + + +sbus_artecon_device::sbus_artecon_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, SBUS_SB300P, tag, owner, clock) + , device_sbus_card_interface(mconfig, *this) + , m_rom(*this, "prom") +{ +} + +void sbus_artecon_device::device_start() +{ +} + +void sbus_artecon_device::install_device() +{ + m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_artecon_device::mem_map); +} + +READ32_MEMBER(sbus_artecon_device::unknown_r) +{ + logerror("%s: unknown_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask); + return 0; +} + +WRITE32_MEMBER(sbus_artecon_device::unknown_w) +{ + logerror("%s: unknown_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask); +} + +READ32_MEMBER(sbus_artecon_device::rom_r) +{ + return ((uint32_t*)m_rom->base())[offset]; +} diff --git a/src/devices/bus/sbus/artecon.h b/src/devices/bus/sbus/artecon.h new file mode 100644 index 00000000000..ce414cf51b9 --- /dev/null +++ b/src/devices/bus/sbus/artecon.h @@ -0,0 +1,45 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Artecon SB-300P 3-serial 1-parallel SBus card skeleton + +***************************************************************************/ + +#ifndef MAME_BUS_SBUS_ARTECON_H +#define MAME_BUS_SBUS_ARTECON_H + +#pragma once + +#include "sbus.h" + + +class sbus_artecon_device : public device_t, public device_sbus_card_interface +{ +public: + // construction/destruction + sbus_artecon_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + // device_t overrides + virtual const tiny_rom_entry *device_rom_region() const override; + virtual void device_add_mconfig(machine_config &config) override; + virtual void device_start() override; + + // device_sbus_slot_interface overrides + virtual void install_device() override; + + DECLARE_READ32_MEMBER(unknown_r); + DECLARE_WRITE32_MEMBER(unknown_w); + DECLARE_READ32_MEMBER(rom_r); + +private: + void mem_map(address_map &map) override; + + required_memory_region m_rom; +}; + + +DECLARE_DEVICE_TYPE(SBUS_SB300P, sbus_artecon_device) + +#endif // MAME_BUS_SBUS_ARTECON_H diff --git a/src/devices/bus/sbus/bwtwo.cpp b/src/devices/bus/sbus/bwtwo.cpp new file mode 100644 index 00000000000..65f40df715c --- /dev/null +++ b/src/devices/bus/sbus/bwtwo.cpp @@ -0,0 +1,115 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Sun bwtwo monochrome video controller + +***************************************************************************/ + +#include "emu.h" +#include "bwtwo.h" +#include "screen.h" + +DEFINE_DEVICE_TYPE(SBUS_BWTWO, sbus_bwtwo_device, "bwtwo", "Sun bwtwo SBus Video") + +void sbus_bwtwo_device::mem_map(address_map &map) +{ + map(0x00000000, 0x00007fff).r(FUNC(sbus_bwtwo_device::rom_r)); + map(0x00400000, 0x0040001f).rw(FUNC(sbus_bwtwo_device::regs_r), FUNC(sbus_bwtwo_device::regs_w)); + map(0x00800000, 0x008fffff).rw(FUNC(sbus_bwtwo_device::vram_r), FUNC(sbus_bwtwo_device::vram_w)); +} + +ROM_START( sbus_bwtwo ) + ROM_REGION32_BE(0x8000, "prom", ROMREGION_ERASEFF) + + ROM_SYSTEM_BIOS(0, "1081", "P/N 525-1081-01") + ROMX_LOAD( "bw2_525-1081-01.bin", 0x0000, 0x8000, CRC(8b70c8c7) SHA1(fd750ad2fd6efdde957f8b0f9abf962e14fe221a), ROM_BIOS(0) ) + ROM_SYSTEM_BIOS(1, "1124", "P/N 525-1124-01") + ROMX_LOAD( "bw2_525-1124-01.bin", 0x0000, 0x0800, CRC(e37a3314) SHA1(78761bd2369cb0c58ef1344c697a47d3a659d4bc), ROM_BIOS(1) ) +ROM_END + +const tiny_rom_entry *sbus_bwtwo_device::device_rom_region() const +{ + return ROM_NAME( sbus_bwtwo ); +} + +void sbus_bwtwo_device::device_add_mconfig(machine_config &config) +{ + screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); + screen.set_screen_update(FUNC(sbus_bwtwo_device::screen_update)); + screen.set_size(1152, 900); + screen.set_visarea(0, 1152-1, 0, 900-1); + screen.set_refresh_hz(72); +} + + +sbus_bwtwo_device::sbus_bwtwo_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, SBUS_BWTWO, tag, owner, clock) + , device_sbus_card_interface(mconfig, *this) + , m_rom(*this, "prom") + , m_screen(*this, "screen") +{ +} + +void sbus_bwtwo_device::device_start() +{ + m_vram = std::make_unique(0x100000); + save_pointer(NAME(m_vram), 0x100000); + + for (int i = 0; i < 0x100; i++) + { + for (int bit = 7; bit >= 0; bit--) + { + m_mono_lut[i][7 - bit] = BIT(i, bit) ? 0 : ~0; + } + } +} + +void sbus_bwtwo_device::install_device() +{ + m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_bwtwo_device::mem_map); +} + +uint32_t sbus_bwtwo_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) +{ + uint8_t *line = &m_vram[0]; + + for (int y = 0; y < 900; y++) + { + uint32_t *scanline = &bitmap.pix32(y); + for (int x = 0; x < 1152/8; x++) + { + memcpy(scanline, m_mono_lut[*line], sizeof(uint32_t) * 8); + line++; + scanline += 8; + } + } + + return 0; +} + +READ8_MEMBER(sbus_bwtwo_device::regs_r) +{ + logerror("%s: regs_r (unimplemented): %08x\n", machine().describe_context(), 0x400000 + offset); + return 0; +} + +WRITE8_MEMBER(sbus_bwtwo_device::regs_w) +{ + logerror("%s: regs_w (unimplemented): %08x = %02x\n", machine().describe_context(), 0x400000 + offset, data); +} + +READ32_MEMBER(sbus_bwtwo_device::rom_r) +{ + return ((uint32_t*)m_rom->base())[offset]; +} + +READ8_MEMBER(sbus_bwtwo_device::vram_r) +{ + return m_vram[offset]; +} + +WRITE8_MEMBER(sbus_bwtwo_device::vram_w) +{ + m_vram[offset] = data; +} diff --git a/src/devices/bus/sbus/bwtwo.h b/src/devices/bus/sbus/bwtwo.h new file mode 100644 index 00000000000..fb3408db7d4 --- /dev/null +++ b/src/devices/bus/sbus/bwtwo.h @@ -0,0 +1,52 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Sun bwtwo monochrome video controller + +***************************************************************************/ + +#ifndef MAME_BUS_SBUS_BWTWO_H +#define MAME_BUS_SBUS_BWTWO_H + +#pragma once + +#include "sbus.h" + + +class sbus_bwtwo_device : public device_t, public device_sbus_card_interface +{ +public: + // construction/destruction + sbus_bwtwo_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + // device_t overrides + virtual const tiny_rom_entry *device_rom_region() const override; + virtual void device_add_mconfig(machine_config &config) override; + virtual void device_start() override; + + // device_sbus_slot_interface overrides + virtual void install_device() override; + + DECLARE_READ8_MEMBER(regs_r); + DECLARE_WRITE8_MEMBER(regs_w); + DECLARE_READ32_MEMBER(rom_r); + DECLARE_READ8_MEMBER(vram_r); + DECLARE_WRITE8_MEMBER(vram_w); + +private: + uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); + + void mem_map(address_map &map) override; + + required_memory_region m_rom; + std::unique_ptr m_vram; + required_device m_screen; + uint32_t m_mono_lut[256][8]; +}; + + +DECLARE_DEVICE_TYPE(SBUS_BWTWO, sbus_bwtwo_device) + +#endif // MAME_BUS_SBUS_BWTWO_H diff --git a/src/devices/bus/sbus/cgsix.cpp b/src/devices/bus/sbus/cgsix.cpp new file mode 100644 index 00000000000..beebe3dadd9 --- /dev/null +++ b/src/devices/bus/sbus/cgsix.cpp @@ -0,0 +1,1188 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Sun cgsix-series accelerated 8-bit color video controller + +***************************************************************************/ + +#include "emu.h" +#include "cgsix.h" + +DEFINE_DEVICE_TYPE(SBUS_TURBOGX, sbus_turbogx_device, "turbogx", "Sun TurboGX SBus Video") +DEFINE_DEVICE_TYPE(SBUS_TURBOGXP, sbus_turbogxp_device, "turbogxp", "Sun TurboGX+ SBus Video") + +//------------------------------------------------- +// base cgsix device +//------------------------------------------------- + +void sbus_cgsix_device::base_map(address_map &map) +{ + map(0x00000000, 0x01ffffff).rw(FUNC(sbus_cgsix_device::unknown_r), FUNC(sbus_cgsix_device::unknown_w)); + map(0x00000000, 0x00007fff).r(FUNC(sbus_cgsix_device::rom_r)); + map(0x00200000, 0x0020000f).m(m_ramdac, FUNC(bt458_device::map)).umask32(0xff000000); + map(0x00700000, 0x00700fff).rw(FUNC(sbus_cgsix_device::fbc_r), FUNC(sbus_cgsix_device::fbc_w)); +} + +sbus_cgsix_device::sbus_cgsix_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, type, tag, owner, clock) + , device_sbus_card_interface(mconfig, *this) + , m_rom(*this, "prom") + , m_screen(*this, "screen") + , m_ramdac(*this, "ramdac") +{ +} + +void sbus_cgsix_device::device_start() +{ + m_vram = std::make_unique(m_vram_size / 4); + + save_pointer(NAME(m_vram), m_vram_size / 4); + save_item(NAME(m_vram_size)); + + save_item(NAME(m_fbc.m_clip_check)); + save_item(NAME(m_fbc.m_status)); + save_item(NAME(m_fbc.m_draw_status)); + save_item(NAME(m_fbc.m_blit_status)); + save_item(NAME(m_fbc.m_font)); + + save_item(NAME(m_fbc.m_x0)); + save_item(NAME(m_fbc.m_y0)); + save_item(NAME(m_fbc.m_z0)); + save_item(NAME(m_fbc.m_color0)); + save_item(NAME(m_fbc.m_x1)); + save_item(NAME(m_fbc.m_y1)); + save_item(NAME(m_fbc.m_z1)); + save_item(NAME(m_fbc.m_color1)); + save_item(NAME(m_fbc.m_x2)); + save_item(NAME(m_fbc.m_y2)); + save_item(NAME(m_fbc.m_z2)); + save_item(NAME(m_fbc.m_color2)); + save_item(NAME(m_fbc.m_x3)); + save_item(NAME(m_fbc.m_y3)); + save_item(NAME(m_fbc.m_z3)); + save_item(NAME(m_fbc.m_color3)); + + save_item(NAME(m_fbc.m_raster_offx)); + save_item(NAME(m_fbc.m_raster_offy)); + + save_item(NAME(m_fbc.m_autoincx)); + save_item(NAME(m_fbc.m_autoincy)); + + save_item(NAME(m_fbc.m_clip_minx)); + save_item(NAME(m_fbc.m_clip_miny)); + + save_item(NAME(m_fbc.m_clip_maxx)); + save_item(NAME(m_fbc.m_clip_maxy)); + + save_item(NAME(m_fbc.m_fcolor)); + save_item(NAME(m_fbc.m_bcolor)); + + save_item(NAME(m_fbc.m_rasterop)); + + save_item(NAME(m_fbc.m_plane_mask)); + save_item(NAME(m_fbc.m_pixel_mask)); + + save_item(NAME(m_fbc.m_patt_align)); + save_item(NAME(m_fbc.m_pattern)); + + save_item(NAME(m_fbc.m_ipoint_absx)); + save_item(NAME(m_fbc.m_ipoint_absy)); + save_item(NAME(m_fbc.m_ipoint_absz)); + save_item(NAME(m_fbc.m_ipoint_relx)); + save_item(NAME(m_fbc.m_ipoint_rely)); + save_item(NAME(m_fbc.m_ipoint_relz)); + save_item(NAME(m_fbc.m_ipoint_r)); + save_item(NAME(m_fbc.m_ipoint_g)); + save_item(NAME(m_fbc.m_ipoint_b)); + save_item(NAME(m_fbc.m_ipoint_a)); + + save_item(NAME(m_fbc.m_iline_absx)); + save_item(NAME(m_fbc.m_iline_absy)); + save_item(NAME(m_fbc.m_iline_absz)); + save_item(NAME(m_fbc.m_iline_relx)); + save_item(NAME(m_fbc.m_iline_rely)); + save_item(NAME(m_fbc.m_iline_relz)); + save_item(NAME(m_fbc.m_iline_r)); + save_item(NAME(m_fbc.m_iline_g)); + save_item(NAME(m_fbc.m_iline_b)); + save_item(NAME(m_fbc.m_iline_a)); + + save_item(NAME(m_fbc.m_itri_absx)); + save_item(NAME(m_fbc.m_itri_absy)); + save_item(NAME(m_fbc.m_itri_absz)); + save_item(NAME(m_fbc.m_itri_relx)); + save_item(NAME(m_fbc.m_itri_rely)); + save_item(NAME(m_fbc.m_itri_relz)); + save_item(NAME(m_fbc.m_itri_r)); + save_item(NAME(m_fbc.m_itri_g)); + save_item(NAME(m_fbc.m_itri_b)); + save_item(NAME(m_fbc.m_itri_a)); + + save_item(NAME(m_fbc.m_iquad_absx)); + save_item(NAME(m_fbc.m_iquad_absy)); + save_item(NAME(m_fbc.m_iquad_absz)); + save_item(NAME(m_fbc.m_iquad_relx)); + save_item(NAME(m_fbc.m_iquad_rely)); + save_item(NAME(m_fbc.m_iquad_relz)); + save_item(NAME(m_fbc.m_iquad_r)); + save_item(NAME(m_fbc.m_iquad_g)); + save_item(NAME(m_fbc.m_iquad_b)); + save_item(NAME(m_fbc.m_iquad_a)); + + save_item(NAME(m_fbc.m_irect_absx)); + save_item(NAME(m_fbc.m_irect_absy)); + save_item(NAME(m_fbc.m_irect_absz)); + save_item(NAME(m_fbc.m_irect_relx)); + save_item(NAME(m_fbc.m_irect_rely)); + save_item(NAME(m_fbc.m_irect_relz)); + save_item(NAME(m_fbc.m_irect_r)); + save_item(NAME(m_fbc.m_irect_g)); + save_item(NAME(m_fbc.m_irect_b)); + save_item(NAME(m_fbc.m_irect_a)); + + save_item(NAME(m_fbc.m_vertex_count)); + + for (int i = 0; i < 0x1000; i++) + { + save_item(NAME(m_fbc.m_prim_buf[i].m_absx), i); + save_item(NAME(m_fbc.m_prim_buf[i].m_absy), i); + save_item(NAME(m_fbc.m_prim_buf[i].m_absz), i); + save_item(NAME(m_fbc.m_prim_buf[i].m_relx), i); + save_item(NAME(m_fbc.m_prim_buf[i].m_rely), i); + save_item(NAME(m_fbc.m_prim_buf[i].m_relz), i); + save_item(NAME(m_fbc.m_prim_buf[i].m_r), i); + save_item(NAME(m_fbc.m_prim_buf[i].m_g), i); + save_item(NAME(m_fbc.m_prim_buf[i].m_b), i); + save_item(NAME(m_fbc.m_prim_buf[i].m_a), i); + } + + save_item(NAME(m_fbc.m_curr_prim_type)); +} + +void sbus_cgsix_device::device_reset() +{ + memset(&m_fbc, 0, sizeof(m_fbc)); +} + +uint32_t sbus_cgsix_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) +{ + const pen_t *pens = m_ramdac->pens(); + uint8_t *vram = (uint8_t *)&m_vram[0]; + + for (int y = 0; y < 900; y++) + { + uint32_t *scanline = &bitmap.pix32(y); + for (int x = 0; x < 1152; x++) + { + const uint8_t pixel = vram[y * 1152 + BYTE4_XOR_BE(x)]; + *scanline++ = pens[pixel]; + } + } + + return 0; +} + +READ32_MEMBER(sbus_cgsix_device::rom_r) +{ + return ((uint32_t*)m_rom->base())[offset]; +} + +READ32_MEMBER(sbus_cgsix_device::unknown_r) +{ + logerror("%s: unknown_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask); + return 0; +} + +WRITE32_MEMBER(sbus_cgsix_device::unknown_w) +{ + logerror("%s: unknown_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask); +} + +READ32_MEMBER(sbus_cgsix_device::vram_r) +{ + return m_vram[offset]; +} + +WRITE32_MEMBER(sbus_cgsix_device::vram_w) +{ + COMBINE_DATA(&m_vram[offset]); +} + +uint8_t sbus_cgsix_device::perform_rasterop(uint8_t src, uint8_t dst) +{ + const uint32_t rops[4] = { fbc_rasterop_rop00(), fbc_rasterop_rop01(), fbc_rasterop_rop10(), fbc_rasterop_rop11() }; + + uint8_t result = 0; + //logerror("src:%02x dst:%02x\n", src, dst); + for (int bit = 0; bit < 8; bit++) + { + const uint8_t mask = (1 << bit); + const uint8_t f = BIT(m_fbc.m_fcolor, bit) << 1; + const uint8_t b = BIT(m_fbc.m_bcolor, bit); + const uint8_t s = src & mask; + const uint8_t d = dst & mask; + const uint32_t rop = rops[f | b]; + //logerror("f:%d b:%d s:%02x d:%02x rop:%d\n", f >> 1, b, s, d, rop); + + uint8_t value = 0; + switch (rop) + { + case ROP_CLR: break; + case ROP_SRC_NOR_DST: value = ~(s | d); break; + case ROP_NSRC_AND_DST: value = ~s & d; break; + case ROP_NOT_SRC: value = ~s; break; + case ROP_SRC_AND_NDST: value = s & ~d; break; + case ROP_NOT_DST: value = ~d; break; + case ROP_SRC_XOR_DST: value = s ^ d; break; + case ROP_SRC_NAND_DST: value = ~(s & d); break; + case ROP_SRC_AND_DST: value = s & d; break; + case ROP_SRC_XNOR_DST: value = ~(s ^ d); break; + case ROP_DST: value = d; break; + case ROP_NSRC_OR_DST: value = ~s | d; break; + case ROP_SRC: value = s; break; + case ROP_SRC_OR_NDST: value = s | ~d; break; + case ROP_SRC_OR_DST: value = s | d; break; + case ROP_SET: value = 0xff; break; + default: value = 0; break; + } + result |= value & mask; + } + return result; +} + +void sbus_cgsix_device::handle_font_poke() +{ + if (fbc_misc_draw() != FBC_MISC_DRAW_RENDER) + { + logerror("handle_font_poke: Unsupported font draw mode %d, abandoning draw\n", fbc_misc_draw()); + return; + } + + const uint32_t daddr = m_fbc.m_y0 * 1152; + uint8_t *vram = (uint8_t*)&m_vram[0]; + vram += daddr; + const int width = (int)m_fbc.m_x1 - (int)m_fbc.m_x0; + const uint32_t font = m_fbc.m_font; + uint32_t x = m_fbc.m_x0; + logerror("Width: %d, bits %d to %d\n", width, 31, 31 - width); + for (int bit = 31; bit >= (31 - width); bit--) + { + const uint8_t src = BIT(font, bit) ? 0xff : 0x00; + const uint8_t dst = vram[BYTE4_XOR_BE(x)]; + vram[BYTE4_XOR_BE(x)]= perform_rasterop(src, dst); + x++; + if (x >= 1152) break; + } + m_fbc.m_x0 += m_fbc.m_autoincx; + m_fbc.m_x1 += m_fbc.m_autoincx; + m_fbc.m_y0 += m_fbc.m_autoincy; + m_fbc.m_y1 += m_fbc.m_autoincy; +} + +// NOTE: This is basically untested, and probably full of bugs! +void sbus_cgsix_device::handle_draw_command() +{ + if (fbc_misc_draw() != FBC_MISC_DRAW_RENDER) + { + logerror("handle_draw_command: Unsupported draw mode %d, abandoning draw\n", fbc_misc_draw()); + return; + } + + if (m_fbc.m_curr_prim_type != PRIM_RECT) + { + logerror("handle_draw_command: Unsupported prim type %d, abandoning draw\n", m_fbc.m_curr_prim_type); + return; + } + + if (m_fbc.m_vertex_count < 2) + { + logerror("handle_draw_command: Insufficient number of vertices queued, abandoning draw\n"); + return; + } + + uint8_t *vram = (uint8_t*)&m_vram[0]; + + uint32_t vindex = 0; + while (vindex < m_fbc.m_vertex_count) + { + vertex_t &v0 = m_fbc.m_prim_buf[vindex++]; + vertex_t &v1 = m_fbc.m_prim_buf[vindex++]; + + for (uint32_t y = v0.m_absy; y <= v1.m_absy; y++) + { + uint8_t *line = &vram[y * 1152]; + for (uint32_t x = v0.m_absx; x <= v1.m_absx; x++) + { + const uint32_t native_x = BYTE4_XOR_BE(x); + const uint8_t src = line[native_x]; + const uint8_t dst = src; + line[native_x] = perform_rasterop(src, dst); + } + } + } + m_fbc.m_vertex_count = 0; +} + +// NOTE: This is basically untested, and probably full of bugs! +void sbus_cgsix_device::handle_blit_command() +{ + uint8_t *vram = (uint8_t*)&m_vram[0]; + const uint32_t fbw = 1152;//(m_fbc.m_clip_maxx + 1); + logerror("Copying from %d,%d-%d,%d to %d,%d-%d,%d, width %d, height %d\n" + , m_fbc.m_x0, m_fbc.m_y0 + , m_fbc.m_x1, m_fbc.m_y1 + , m_fbc.m_x2, m_fbc.m_y2 + , m_fbc.m_x3, m_fbc.m_y3 + , m_fbc.m_clip_maxx, m_fbc.m_clip_maxy); + uint32_t srcy = m_fbc.m_y0; + uint32_t dsty = m_fbc.m_y2; + for (; srcy < m_fbc.m_y1; srcy++, dsty++) + { + uint8_t *srcline = &vram[srcy * fbw]; + uint8_t *dstline = &vram[dsty * fbw]; + uint32_t srcx = m_fbc.m_x0; + uint32_t dstx = m_fbc.m_x2; + for (; srcx < m_fbc.m_x1; srcx++, dstx++) + { + const uint32_t native_dstx = BYTE4_XOR_BE(dstx); + const uint8_t src = srcline[BYTE4_XOR_BE(srcx)]; + const uint8_t dst = dstline[native_dstx]; + const uint8_t result = perform_rasterop(src, dst); + //logerror("vram[%d] = %02x\n", result); + dstline[native_dstx] = result; + } + } +} + +READ32_MEMBER(sbus_cgsix_device::fbc_r) +{ + uint32_t ret = 0; + switch (offset) + { + case FBC_MISC: + logerror("fbc_r: MISC (%08x & %08x)\n", m_fbc.m_misc, mem_mask); + return m_fbc.m_misc; + case FBC_CLIP_CHECK: + logerror("fbc_r: CLIP_CHECK (%08x & %08x)\n", m_fbc.m_clip_check, mem_mask); + return m_fbc.m_clip_check; + + case FBC_STATUS: + logerror("fbc_r: STATUS (%08x & %08x)\n", m_fbc.m_status, mem_mask); + return m_fbc.m_status; + case FBC_DRAW_STATUS: + logerror("fbc_r: DRAW_STATUS (%08x & %08x)\n", m_fbc.m_draw_status, mem_mask); + handle_draw_command(); + return m_fbc.m_draw_status; + case FBC_BLIT_STATUS: + logerror("fbc_r: BLIT_STATUS (%08x & %08x)\n", m_fbc.m_blit_status, mem_mask); + handle_blit_command(); + return m_fbc.m_blit_status; + case FBC_FONT: + logerror("fbc_r: FONT (%08x & %08x)\n", m_fbc.m_font, mem_mask); + return m_fbc.m_font; + + case FBC_X0: + logerror("fbc_r: X0 (%08x & %08x)\n", m_fbc.m_x0, mem_mask); + return m_fbc.m_x0; + case FBC_Y0: + logerror("fbc_r: Y0 (%08x & %08x)\n", m_fbc.m_y0, mem_mask); + return m_fbc.m_y0; + case FBC_Z0: + logerror("fbc_r: Z0 (%08x & %08x)\n", m_fbc.m_z0, mem_mask); + return m_fbc.m_z0; + case FBC_COLOR0: + logerror("fbc_r: COLOR0 (%08x & %08x)\n", m_fbc.m_color0, mem_mask); + return m_fbc.m_color0; + case FBC_X1: + logerror("fbc_r: X1 (%08x & %08x)\n", m_fbc.m_x1, mem_mask); + return m_fbc.m_x1; + case FBC_Y1: + logerror("fbc_r: Y1 (%08x & %08x)\n", m_fbc.m_y1, mem_mask); + return m_fbc.m_y1; + case FBC_Z1: + logerror("fbc_r: Z1 (%08x & %08x)\n", m_fbc.m_z1, mem_mask); + return m_fbc.m_z1; + case FBC_COLOR1: + logerror("fbc_r: COLOR1 (%08x & %08x)\n", m_fbc.m_color1, mem_mask); + return m_fbc.m_color1; + case FBC_X2: + logerror("fbc_r: X2 (%08x & %08x)\n", m_fbc.m_x2, mem_mask); + return m_fbc.m_x2; + case FBC_Y2: + logerror("fbc_r: Y2 (%08x & %08x)\n", m_fbc.m_y2, mem_mask); + return m_fbc.m_y2; + case FBC_Z2: + logerror("fbc_r: Z2 (%08x & %08x)\n", m_fbc.m_z2, mem_mask); + return m_fbc.m_z2; + case FBC_COLOR2: + logerror("fbc_r: COLOR2 (%08x & %08x)\n", m_fbc.m_color2, mem_mask); + return m_fbc.m_color2; + case FBC_X3: + logerror("fbc_r: X3 (%08x & %08x)\n", m_fbc.m_x3, mem_mask); + return m_fbc.m_x3; + case FBC_Y3: + logerror("fbc_r: Y3 (%08x & %08x)\n", m_fbc.m_y3, mem_mask); + return m_fbc.m_y3; + case FBC_Z3: + logerror("fbc_r: Z3 (%08x & %08x)\n", m_fbc.m_z3, mem_mask); + return m_fbc.m_z3; + case FBC_COLOR3: + logerror("fbc_r: COLOR3 (%08x & %08x)\n", m_fbc.m_color3, mem_mask); + return m_fbc.m_color3; + + case FBC_RASTER_OFFX: + logerror("fbc_r: RASTER_OFFX (%08x & %08x)\n", m_fbc.m_raster_offx, mem_mask); + return m_fbc.m_raster_offx; + case FBC_RASTER_OFFY: + logerror("fbc_r: RASTER_OFFY (%08x & %08x)\n", m_fbc.m_raster_offy, mem_mask); + return m_fbc.m_raster_offy; + case FBC_AUTOINCX: + logerror("fbc_r: AUTOINCX (%08x & %08x)\n", m_fbc.m_autoincx, mem_mask); + return m_fbc.m_autoincx; + case FBC_AUTOINCY: + logerror("fbc_r: AUTOINCY (%08x & %08x)\n", m_fbc.m_autoincy, mem_mask); + return m_fbc.m_autoincy; + case FBC_CLIP_MINX: + logerror("fbc_r: CLIP_MINX (%08x & %08x)\n", m_fbc.m_clip_minx, mem_mask); + return m_fbc.m_clip_minx; + case FBC_CLIP_MINY: + logerror("fbc_r: CLIP_MINY (%08x & %08x)\n", m_fbc.m_clip_miny, mem_mask); + return m_fbc.m_clip_miny; + case FBC_CLIP_MAXX: + logerror("fbc_r: CLIP_MAXX (%08x & %08x)\n", m_fbc.m_clip_maxx, mem_mask); + return m_fbc.m_clip_maxx; + case FBC_CLIP_MAXY: + logerror("fbc_r: CLIP_MAXY (%08x & %08x)\n", m_fbc.m_clip_maxy, mem_mask); + return m_fbc.m_clip_maxy; + + case FBC_FCOLOR: + logerror("fbc_r: FCOLOR (%08x & %08x)\n", m_fbc.m_fcolor, mem_mask); + return m_fbc.m_fcolor; + case FBC_BCOLOR: + logerror("fbc_r: BCOLOR (%08x & %08x)\n", m_fbc.m_bcolor, mem_mask); + return m_fbc.m_bcolor; + case FBC_RASTEROP: + logerror("fbc_r: RASTEROP (%08x & %08x)\n", m_fbc.m_rasterop, mem_mask); + return m_fbc.m_rasterop; + case FBC_PLANE_MASK: + logerror("fbc_r: PLANE_MASK (%08x & %08x)\n", m_fbc.m_plane_mask, mem_mask); + return m_fbc.m_plane_mask; + case FBC_PIXEL_MASK: + logerror("fbc_r: PIXEL_MASK (%08x & %08x)\n", m_fbc.m_pixel_mask, mem_mask); + return m_fbc.m_pixel_mask; + + case FBC_PATT_ALIGN: + logerror("fbc_r: PATT_ALIGN (%08x & %08x)\n", m_fbc.m_patt_align, mem_mask); + return m_fbc.m_patt_align; + case FBC_PATTERN0: + logerror("fbc_r: PATTERN0 (%08x & %08x)\n", m_fbc.m_pattern[0], mem_mask); + return m_fbc.m_pattern[0]; + case FBC_PATTERN1: + logerror("fbc_r: PATTERN1 (%08x & %08x)\n", m_fbc.m_pattern[1], mem_mask); + return m_fbc.m_pattern[1]; + case FBC_PATTERN2: + logerror("fbc_r: PATTERN2 (%08x & %08x)\n", m_fbc.m_pattern[2], mem_mask); + return m_fbc.m_pattern[2]; + case FBC_PATTERN3: + logerror("fbc_r: PATTERN3 (%08x & %08x)\n", m_fbc.m_pattern[3], mem_mask); + return m_fbc.m_pattern[3]; + case FBC_PATTERN4: + logerror("fbc_r: PATTERN4 (%08x & %08x)\n", m_fbc.m_pattern[4], mem_mask); + return m_fbc.m_pattern[4]; + case FBC_PATTERN5: + logerror("fbc_r: PATTERN5 (%08x & %08x)\n", m_fbc.m_pattern[5], mem_mask); + return m_fbc.m_pattern[5]; + case FBC_PATTERN6: + logerror("fbc_r: PATTERN6 (%08x & %08x)\n", m_fbc.m_pattern[6], mem_mask); + return m_fbc.m_pattern[6]; + case FBC_PATTERN7: + logerror("fbc_r: PATTERN7 (%08x & %08x)\n", m_fbc.m_pattern[7], mem_mask); + return m_fbc.m_pattern[7]; + + case FBC_IPOINT_ABSX: + logerror("fbc_r: IPOINT_ABSX (%08x & %08x)\n", m_fbc.m_ipoint_absx, mem_mask); + return m_fbc.m_ipoint_absx; + case FBC_IPOINT_ABSY: + logerror("fbc_r: IPOINT_ABSY (%08x & %08x)\n", m_fbc.m_ipoint_absy, mem_mask); + return m_fbc.m_ipoint_absy; + case FBC_IPOINT_ABSZ: + logerror("fbc_r: IPOINT_ABSZ (%08x & %08x)\n", m_fbc.m_ipoint_absz, mem_mask); + return m_fbc.m_ipoint_absz; + case FBC_IPOINT_RELX: + logerror("fbc_r: IPOINT_RELX (%08x & %08x)\n", m_fbc.m_ipoint_relx, mem_mask); + return m_fbc.m_ipoint_relx; + case FBC_IPOINT_RELY: + logerror("fbc_r: IPOINT_RELY (%08x & %08x)\n", m_fbc.m_ipoint_rely, mem_mask); + return m_fbc.m_ipoint_rely; + case FBC_IPOINT_RELZ: + logerror("fbc_r: IPOINT_RELZ (%08x & %08x)\n", m_fbc.m_ipoint_relz, mem_mask); + return m_fbc.m_ipoint_relz; + case FBC_IPOINT_R: + logerror("fbc_r: IPOINT_R (%08x & %08x)\n", m_fbc.m_ipoint_r, mem_mask); + return m_fbc.m_ipoint_r; + case FBC_IPOINT_G: + logerror("fbc_r: IPOINT_G (%08x & %08x)\n", m_fbc.m_ipoint_g, mem_mask); + return m_fbc.m_ipoint_g; + case FBC_IPOINT_B: + logerror("fbc_r: IPOINT_B (%08x & %08x)\n", m_fbc.m_ipoint_b, mem_mask); + return m_fbc.m_ipoint_b; + case FBC_IPOINT_A: + logerror("fbc_r: IPOINT_A (%08x & %08x)\n", m_fbc.m_ipoint_a, mem_mask); + return m_fbc.m_ipoint_a; + + case FBC_ILINE_ABSX: + logerror("fbc_r: ILINE_ABSX (%08x & %08x)\n", m_fbc.m_iline_absx, mem_mask); + return m_fbc.m_iline_absx; + case FBC_ILINE_ABSY: + logerror("fbc_r: ILINE_ABSY (%08x & %08x)\n", m_fbc.m_iline_absy, mem_mask); + return m_fbc.m_iline_absy; + case FBC_ILINE_ABSZ: + logerror("fbc_r: ILINE_ABSZ (%08x & %08x)\n", m_fbc.m_iline_absz, mem_mask); + return m_fbc.m_iline_absz; + case FBC_ILINE_RELX: + logerror("fbc_r: ILINE_RELX (%08x & %08x)\n", m_fbc.m_iline_relx, mem_mask); + return m_fbc.m_iline_relx; + case FBC_ILINE_RELY: + logerror("fbc_r: ILINE_RELY (%08x & %08x)\n", m_fbc.m_iline_rely, mem_mask); + return m_fbc.m_iline_rely; + case FBC_ILINE_RELZ: + logerror("fbc_r: ILINE_RELZ (%08x & %08x)\n", m_fbc.m_iline_relz, mem_mask); + return m_fbc.m_iline_relz; + case FBC_ILINE_R: + logerror("fbc_r: ILINE_R (%08x & %08x)\n", m_fbc.m_iline_r, mem_mask); + return m_fbc.m_iline_r; + case FBC_ILINE_G: + logerror("fbc_r: ILINE_G (%08x & %08x)\n", m_fbc.m_iline_g, mem_mask); + return m_fbc.m_iline_g; + case FBC_ILINE_B: + logerror("fbc_r: ILINE_B (%08x & %08x)\n", m_fbc.m_iline_b, mem_mask); + return m_fbc.m_iline_b; + case FBC_ILINE_A: + logerror("fbc_r: ILINE_A (%08x & %08x)\n", m_fbc.m_iline_a, mem_mask); + return m_fbc.m_iline_a; + + case FBC_ITRI_ABSX: + logerror("fbc_r: ITRI_ABSX (%08x & %08x)\n", m_fbc.m_itri_absx, mem_mask); + return m_fbc.m_itri_absx; + case FBC_ITRI_ABSY: + logerror("fbc_r: ITRI_ABSY (%08x & %08x)\n", m_fbc.m_itri_absy, mem_mask); + return m_fbc.m_itri_absy; + case FBC_ITRI_ABSZ: + logerror("fbc_r: ITRI_ABSZ (%08x & %08x)\n", m_fbc.m_itri_absz, mem_mask); + return m_fbc.m_itri_absz; + case FBC_ITRI_RELX: + logerror("fbc_r: ITRI_RELX (%08x & %08x)\n", m_fbc.m_itri_relx, mem_mask); + return m_fbc.m_itri_relx; + case FBC_ITRI_RELY: + logerror("fbc_r: ITRI_RELY (%08x & %08x)\n", m_fbc.m_itri_rely, mem_mask); + return m_fbc.m_itri_rely; + case FBC_ITRI_RELZ: + logerror("fbc_r: ITRI_RELZ (%08x & %08x)\n", m_fbc.m_itri_relz, mem_mask); + return m_fbc.m_itri_relz; + case FBC_ITRI_R: + logerror("fbc_r: ITRI_R (%08x & %08x)\n", m_fbc.m_itri_r, mem_mask); + return m_fbc.m_itri_r; + case FBC_ITRI_G: + logerror("fbc_r: ITRI_G (%08x & %08x)\n", m_fbc.m_itri_g, mem_mask); + return m_fbc.m_itri_g; + case FBC_ITRI_B: + logerror("fbc_r: ITRI_B (%08x & %08x)\n", m_fbc.m_itri_b, mem_mask); + return m_fbc.m_itri_b; + case FBC_ITRI_A: + logerror("fbc_r: ITRI_A (%08x & %08x)\n", m_fbc.m_itri_a, mem_mask); + return m_fbc.m_itri_a; + + case FBC_IQUAD_ABSX: + logerror("fbc_r: IQUAD_ABSX (%08x & %08x)\n", m_fbc.m_iquad_absx, mem_mask); + return m_fbc.m_iquad_absx; + case FBC_IQUAD_ABSY: + logerror("fbc_r: IQUAD_ABSY (%08x & %08x)\n", m_fbc.m_iquad_absy, mem_mask); + return m_fbc.m_iquad_absy; + case FBC_IQUAD_ABSZ: + logerror("fbc_r: IQUAD_ABSZ (%08x & %08x)\n", m_fbc.m_iquad_absz, mem_mask); + return m_fbc.m_iquad_absz; + case FBC_IQUAD_RELX: + logerror("fbc_r: IQUAD_RELX (%08x & %08x)\n", m_fbc.m_iquad_relx, mem_mask); + return m_fbc.m_iquad_relx; + case FBC_IQUAD_RELY: + logerror("fbc_r: IQUAD_RELY (%08x & %08x)\n", m_fbc.m_iquad_rely, mem_mask); + return m_fbc.m_iquad_rely; + case FBC_IQUAD_RELZ: + logerror("fbc_r: IQUAD_RELZ (%08x & %08x)\n", m_fbc.m_iquad_relz, mem_mask); + return m_fbc.m_iquad_relz; + case FBC_IQUAD_R: + logerror("fbc_r: IQUAD_R (%08x & %08x)\n", m_fbc.m_iquad_r, mem_mask); + return m_fbc.m_iquad_r; + case FBC_IQUAD_G: + logerror("fbc_r: IQUAD_G (%08x & %08x)\n", m_fbc.m_iquad_g, mem_mask); + return m_fbc.m_iquad_g; + case FBC_IQUAD_B: + logerror("fbc_r: IQUAD_B (%08x & %08x)\n", m_fbc.m_iquad_b, mem_mask); + return m_fbc.m_iquad_b; + case FBC_IQUAD_A: + logerror("fbc_r: IQUAD_A (%08x & %08x)\n", m_fbc.m_iquad_a, mem_mask); + return m_fbc.m_iquad_a; + + case FBC_IRECT_ABSX: + logerror("fbc_r: IRECT_ABSX (%08x & %08x)\n", m_fbc.m_irect_absx, mem_mask); + return m_fbc.m_irect_absx; + case FBC_IRECT_ABSY: + logerror("fbc_r: IRECT_ABSY (%08x & %08x)\n", m_fbc.m_irect_absy, mem_mask); + return m_fbc.m_irect_absy; + case FBC_IRECT_ABSZ: + logerror("fbc_r: IRECT_ABSZ (%08x & %08x)\n", m_fbc.m_irect_absz, mem_mask); + return m_fbc.m_irect_absz; + case FBC_IRECT_RELX: + logerror("fbc_r: IRECT_RELX (%08x & %08x)\n", m_fbc.m_irect_relx, mem_mask); + return m_fbc.m_irect_relx; + case FBC_IRECT_RELY: + logerror("fbc_r: IRECT_RELY (%08x & %08x)\n", m_fbc.m_irect_rely, mem_mask); + return m_fbc.m_irect_rely; + case FBC_IRECT_RELZ: + logerror("fbc_r: IRECT_RELZ (%08x & %08x)\n", m_fbc.m_irect_relz, mem_mask); + return m_fbc.m_irect_relz; + case FBC_IRECT_R: + logerror("fbc_r: IRECT_R (%08x & %08x)\n", m_fbc.m_irect_r, mem_mask); + return m_fbc.m_irect_r; + case FBC_IRECT_G: + logerror("fbc_r: IRECT_G (%08x & %08x)\n", m_fbc.m_irect_g, mem_mask); + return m_fbc.m_irect_g; + case FBC_IRECT_B: + logerror("fbc_r: IRECT_B (%08x & %08x)\n", m_fbc.m_irect_b, mem_mask); + return m_fbc.m_irect_b; + case FBC_IRECT_A: + logerror("fbc_r: IRECT_A (%08x & %08x)\n", m_fbc.m_irect_a, mem_mask); + return m_fbc.m_irect_a; + + default: + logerror("fbc_r: Unknown register %08x & %08x\n", 0x00700000 | (offset << 2), mem_mask); + break; + } + return ret; +} + +WRITE32_MEMBER(sbus_cgsix_device::fbc_w) +{ + static char const *const misc_bdisp_name[4] = { "IGNORE", "0", "1", "ILLEGAL" }; + static char const *const misc_bread_name[4] = { "IGNORE", "0", "1", "ILLEGAL" }; + static char const *const misc_bwrite1_name[4] = { "IGNORE", "ENABLE", "DISABLE", "ILLEGAL" }; + static char const *const misc_bwrite0_name[4] = { "IGNORE", "ENABLE", "DISABLE", "ILLEGAL" }; + static char const *const misc_draw_name[4] = { "IGNORE", "RENDER", "PICK", "ILLEGAL" }; + static char const *const misc_data_name[4] = { "IGNORE", "COLOR8", "COLOR1", "HRMONO" }; + static char const *const misc_blit_name[4] = { "IGNORE", "NOSRC", "SRC", "ILLEGAL" }; + static char const *const rasterop_rop_name[16] = + { + "CLR", "SRC_NOR_DST", "NSRC_AND_DST", "NOT_SRC", "SRC_AND_NDST", "NOT_DST", "SRC_XOR_DST", "SRC_NAND_DST", + "SRC_AND_DST", "SRC_XNOR_DST", "DST", "NSRC_OR_DST", "SRC", "SRC_OR_NDST", "SRC_OR_DST", "SET" + }; + static char const *const rasterop_plot_name[2] = { "PLOT", "UNPLOT" }; + static char const *const rasterop_rast_name[2] = { "BOOL", "LINEAR" }; + static char const *const rasterop_attr_name[4] = { "IGNORE", "UNSUPP", "SUPP", "ILLEGAL" }; + static char const *const rasterop_polyg_name[4] = { "IGNORE", "OVERLAP", "NONOVERLAP", "ILLEGAL" }; + static char const *const rasterop_pattern_name[4] = { "IGNORE", "ZEROES", "ONES", "MASK" }; + static char const *const rasterop_pixel_name[4] = { "IGNORE", "ZEROES", "ONES", "MASK" }; + static char const *const rasterop_plane_name[4] = { "IGNORE", "ZEROES", "ONES", "MASK" }; + + switch (offset) + { + case FBC_MISC: + COMBINE_DATA(&m_fbc.m_misc); + logerror("fbc_w: MISC = %08x & %08x\n", data, mem_mask); + logerror(" MISC_INDEX = %d\n", fbc_misc_index()); + logerror(" MISC_INDEX_MOD = %d\n", fbc_misc_index_mod()); + logerror(" MISC_BDISP = %d (%s)\n", fbc_misc_bdisp(), misc_bdisp_name[fbc_misc_bdisp()]); + logerror(" MISC_BREAD = %d (%s)\n", fbc_misc_bread(), misc_bread_name[fbc_misc_bread()]); + logerror(" MISC_BWRITE1 = %d (%s)\n", fbc_misc_bwrite1(), misc_bwrite1_name[fbc_misc_bwrite1()]); + logerror(" MISC_BWRITE0 = %d (%s)\n", fbc_misc_bwrite0(), misc_bwrite0_name[fbc_misc_bwrite0()]); + logerror(" MISC_DRAW = %d (%s)\n", fbc_misc_draw(), misc_draw_name[fbc_misc_draw()]); + logerror(" MISC_DATA = %d (%s)\n", fbc_misc_data(), misc_data_name[fbc_misc_data()]); + logerror(" MISC_BLIT = %d (%s)\n", fbc_misc_blit(), misc_blit_name[fbc_misc_blit()]); + break; + case FBC_CLIP_CHECK: + logerror("fbc_w: CLIP_CHECK = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_clip_check); + break; + + case FBC_STATUS: + logerror("fbc_w: STATUS = %08x & %08x\n", data, mem_mask); + //COMBINE_DATA(&m_fbc.m_status); + break; + case FBC_DRAW_STATUS: + logerror("fbc_w: DRAW_STATUS = %08x & %08x\n", data, mem_mask); + //COMBINE_DATA(&m_fbc.m_draw_status); + break; + case FBC_BLIT_STATUS: + logerror("fbc_w: BLIT_STATUS = %08x & %08x\n", data, mem_mask); + //COMBINE_DATA(&m_fbc.m_blit_status); + break; + case FBC_FONT: + { + logerror("fbc_w: FONT = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_font); + handle_font_poke(); + break; + } + + case FBC_X0: + logerror("fbc_w: X0 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_x0); + break; + case FBC_Y0: + logerror("fbc_w: Y0 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_y0); + break; + case FBC_Z0: + logerror("fbc_w: Z0 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_z0); + break; + case FBC_COLOR0: + logerror("fbc_w: COLOR0 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_color0); + break; + case FBC_X1: + logerror("fbc_w: X1 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_x1); + break; + case FBC_Y1: + logerror("fbc_w: Y1 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_y1); + break; + case FBC_Z1: + logerror("fbc_w: Z1 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_z1); + break; + case FBC_COLOR1: + logerror("fbc_w: COLOR1 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_color1); + break; + case FBC_X2: + logerror("fbc_w: X2 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_x2); + break; + case FBC_Y2: + logerror("fbc_w: Y2 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_y2); + break; + case FBC_Z2: + logerror("fbc_w: Z2 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_z2); + break; + case FBC_COLOR2: + logerror("fbc_w: COLOR2 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_color2); + break; + case FBC_X3: + logerror("fbc_w: X3 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_x3); + break; + case FBC_Y3: + logerror("fbc_w: Y3 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_y3); + break; + case FBC_Z3: + logerror("fbc_w: Z3 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_z3); + break; + case FBC_COLOR3: + logerror("fbc_w: COLOR3 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_color3); + break; + + case FBC_RASTER_OFFX: + logerror("fbc_w: RASTER_OFFX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_raster_offx); + break; + case FBC_RASTER_OFFY: + logerror("fbc_w: RASTER_OFFY = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_raster_offy); + break; + case FBC_AUTOINCX: + logerror("fbc_w: AUTOINCX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_autoincx); + break; + case FBC_AUTOINCY: + logerror("fbc_w: AUTOINCY = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_autoincy); + break; + case FBC_CLIP_MINX: + logerror("fbc_w: CLIP_MINX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_clip_minx); + break; + case FBC_CLIP_MINY: + logerror("fbc_w: CLIP_MINY = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_clip_miny); + break; + case FBC_CLIP_MAXX: + logerror("fbc_w: CLIP_MAXX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_clip_maxx); + break; + case FBC_CLIP_MAXY: + logerror("fbc_w: CLIP_MAXY (%08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_clip_maxy); + break; + + case FBC_FCOLOR: + logerror("fbc_w: FCOLOR = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_fcolor); + break; + case FBC_BCOLOR: + logerror("fbc_w: BCOLOR = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_bcolor); + break; + case FBC_RASTEROP: + COMBINE_DATA(&m_fbc.m_rasterop); + logerror("fbc_w: RASTEROP = %08x & %08x\n", data, mem_mask); + logerror(" RASTEROP_ROP00 = %d (%s)\n", fbc_rasterop_rop00(), rasterop_rop_name[fbc_rasterop_rop00()]); + logerror(" RASTEROP_ROP01 = %d (%s)\n", fbc_rasterop_rop01(), rasterop_rop_name[fbc_rasterop_rop01()]); + logerror(" RASTEROP_ROP10 = %d (%s)\n", fbc_rasterop_rop10(), rasterop_rop_name[fbc_rasterop_rop10()]); + logerror(" RASTEROP_ROP11 = %d (%s)\n", fbc_rasterop_rop11(), rasterop_rop_name[fbc_rasterop_rop11()]); + logerror(" RASTEROP_PLOT = %d (%s)\n", fbc_rasterop_plot(), rasterop_plot_name[fbc_rasterop_plot()]); + logerror(" RASTEROP_RAST = %d (%s)\n", fbc_rasterop_rast(), rasterop_rast_name[fbc_rasterop_rast()]); + logerror(" RASTEROP_ATTR = %d (%s)\n", fbc_rasterop_attr(), rasterop_attr_name[fbc_rasterop_attr()]); + logerror(" RASTEROP_POLYG = %d (%s)\n", fbc_rasterop_polyg(), rasterop_polyg_name[fbc_rasterop_polyg()]); + logerror(" RASTEROP_PATT = %d (%s)\n", fbc_rasterop_pattern(), rasterop_pattern_name[fbc_rasterop_pattern()]); + logerror(" RASTEROP_PIXEL = %d (%s)\n", fbc_rasterop_pixel(), rasterop_pixel_name[fbc_rasterop_pixel()]); + logerror(" RASTEROP_PLANE = %d (%s)\n", fbc_rasterop_plane(), rasterop_plane_name[fbc_rasterop_plane()]); + break; + case FBC_PLANE_MASK: + logerror("fbc_w: PLANE_MASK = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_plane_mask); + break; + case FBC_PIXEL_MASK: + logerror("fbc_w: PIXEL_MASK = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_pixel_mask); + break; + + case FBC_PATT_ALIGN: + logerror("fbc_w: PATT_ALIGN = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_patt_align); + break; + case FBC_PATTERN0: + logerror("fbc_w: PATTERN0 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_pattern[0]); + break; + case FBC_PATTERN1: + logerror("fbc_w: PATTERN1 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_pattern[1]); + break; + case FBC_PATTERN2: + logerror("fbc_w: PATTERN2 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_pattern[2]); + break; + case FBC_PATTERN3: + logerror("fbc_w: PATTERN3 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_pattern[3]); + break; + case FBC_PATTERN4: + logerror("fbc_w: PATTERN4 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_pattern[4]); + break; + case FBC_PATTERN5: + logerror("fbc_w: PATTERN5 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_pattern[5]); + break; + case FBC_PATTERN6: + logerror("fbc_w: PATTERN6 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_pattern[6]); + break; + case FBC_PATTERN7: + logerror("fbc_w: PATTERN7 = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_pattern[7]); + break; + + case FBC_IPOINT_ABSX: + logerror("fbc_w: IPOINT_ABSX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_ipoint_absx); + break; + case FBC_IPOINT_ABSY: + logerror("fbc_w: IPOINT_ABSY = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_ipoint_absy); + break; + case FBC_IPOINT_ABSZ: + logerror("fbc_w: IPOINT_ABSZ = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_ipoint_absz); + break; + case FBC_IPOINT_RELX: + logerror("fbc_w: IPOINT_RELX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_ipoint_relx); + break; + case FBC_IPOINT_RELY: + logerror("fbc_w: IPOINT_RELY = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_ipoint_rely); + break; + case FBC_IPOINT_RELZ: + logerror("fbc_w: IPOINT_RELZ = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_ipoint_relz); + break; + case FBC_IPOINT_R: + logerror("fbc_w: IPOINT_R = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_ipoint_r); + break; + case FBC_IPOINT_G: + logerror("fbc_w: IPOINT_G = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_ipoint_g); + break; + case FBC_IPOINT_B: + logerror("fbc_w: IPOINT_B = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_ipoint_b); + break; + case FBC_IPOINT_A: + logerror("fbc_w: IPOINT_A = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_ipoint_a); + break; + + case FBC_ILINE_ABSX: + logerror("fbc_w: ILINE_ABSX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iline_absx); + break; + case FBC_ILINE_ABSY: + logerror("fbc_w: ILINE_ABSY = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iline_absy); + break; + case FBC_ILINE_ABSZ: + logerror("fbc_w: ILINE_ABSZ = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iline_absz); + break; + case FBC_ILINE_RELX: + logerror("fbc_w: ILINE_RELX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iline_relx); + break; + case FBC_ILINE_RELY: + logerror("fbc_w: ILINE_RELY = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iline_rely); + break; + case FBC_ILINE_RELZ: + logerror("fbc_w: ILINE_RELZ = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iline_relz); + break; + case FBC_ILINE_R: + logerror("fbc_w: ILINE_R = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iline_r); + break; + case FBC_ILINE_G: + logerror("fbc_w: ILINE_G = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iline_g); + break; + case FBC_ILINE_B: + logerror("fbc_w: ILINE_B = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iline_b); + break; + case FBC_ILINE_A: + logerror("fbc_w: ILINE_A = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iline_a); + break; + + case FBC_ITRI_ABSX: + logerror("fbc_w: ITRI_ABSX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_itri_absx); + break; + case FBC_ITRI_ABSY: + COMBINE_DATA(&m_fbc.m_itri_absy); + logerror("fbc_w: ITRI_ABSY = %08x & %08x\n", data, mem_mask); + break; + case FBC_ITRI_ABSZ: + logerror("fbc_w: ITRI_ABSZ = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_itri_absz); + break; + case FBC_ITRI_RELX: + logerror("fbc_w: ITRI_RELX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_itri_relx); + break; + case FBC_ITRI_RELY: + logerror("fbc_w: ITRI_RELY = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_itri_rely); + break; + case FBC_ITRI_RELZ: + logerror("fbc_w: ITRI_RELZ = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_itri_relz); + break; + case FBC_ITRI_R: + logerror("fbc_w: ITRI_R = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_itri_r); + break; + case FBC_ITRI_G: + logerror("fbc_w: ITRI_G = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_itri_g); + break; + case FBC_ITRI_B: + logerror("fbc_w: ITRI_B = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_itri_b); + break; + case FBC_ITRI_A: + logerror("fbc_w: ITRI_A = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_itri_a); + break; + + case FBC_IQUAD_ABSX: + logerror("fbc_w: IQUAD_ABSX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iquad_absx); + break; + case FBC_IQUAD_ABSY: + logerror("fbc_w: IQUAD_ABSY = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iquad_absy); + break; + case FBC_IQUAD_ABSZ: + logerror("fbc_w: IQUAD_ABSZ = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iquad_absz); + break; + case FBC_IQUAD_RELX: + logerror("fbc_w: IQUAD_RELX = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iquad_relx); + break; + case FBC_IQUAD_RELY: + logerror("fbc_w: IQUAD_RELY = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iquad_rely); + break; + case FBC_IQUAD_RELZ: + logerror("fbc_w: IQUAD_RELZ = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iquad_relz); + break; + case FBC_IQUAD_R: + logerror("fbc_w: IQUAD_R = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iquad_r); + break; + case FBC_IQUAD_G: + logerror("fbc_w: IQUAD_G = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iquad_g); + break; + case FBC_IQUAD_B: + logerror("fbc_w: IQUAD_B = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iquad_b); + break; + case FBC_IQUAD_A: + logerror("fbc_w: IQUAD_A = %08x & %08x\n", data, mem_mask); + COMBINE_DATA(&m_fbc.m_iquad_a); + break; + + case FBC_IRECT_ABSX: + logerror("fbc_w: IRECT_ABSX = %08x & %08x\n", data, mem_mask); + m_fbc.m_prim_buf[m_fbc.m_vertex_count].m_absx = data; + m_fbc.m_vertex_count++; + m_fbc.m_curr_prim_type = PRIM_RECT; + break; + case FBC_IRECT_ABSY: + logerror("fbc_w: IRECT_ABSY = %08x & %08x\n", data, mem_mask); + m_fbc.m_prim_buf[m_fbc.m_vertex_count].m_absy = data; + break; + case FBC_IRECT_ABSZ: + logerror("fbc_w: IRECT_ABSZ = %08x & %08x\n", data, mem_mask); + m_fbc.m_prim_buf[m_fbc.m_vertex_count].m_absz = data; + break; + case FBC_IRECT_RELX: + logerror("fbc_w: IRECT_RELX = %08x & %08x\n", data, mem_mask); + m_fbc.m_prim_buf[m_fbc.m_vertex_count].m_relx = data; + break; + case FBC_IRECT_RELY: + logerror("fbc_w: IRECT_RELY = %08x & %08x\n", data, mem_mask); + m_fbc.m_prim_buf[m_fbc.m_vertex_count].m_rely = data; + break; + case FBC_IRECT_RELZ: + logerror("fbc_w: IRECT_RELZ = %08x & %08x\n", data, mem_mask); + m_fbc.m_prim_buf[m_fbc.m_vertex_count].m_relz = data; + break; + case FBC_IRECT_R: + logerror("fbc_w: IRECT_R = %08x & %08x\n", data, mem_mask); + m_fbc.m_prim_buf[m_fbc.m_vertex_count].m_r = data; + break; + case FBC_IRECT_G: + logerror("fbc_w: IRECT_G = %08x & %08x\n", data, mem_mask); + m_fbc.m_prim_buf[m_fbc.m_vertex_count].m_g = data; + break; + case FBC_IRECT_B: + logerror("fbc_w: IRECT_B = %08x & %08x\n", data, mem_mask); + m_fbc.m_prim_buf[m_fbc.m_vertex_count].m_b = data; + break; + case FBC_IRECT_A: + logerror("fbc_w: IRECT_A = %08x & %08x\n", data, mem_mask); + m_fbc.m_prim_buf[m_fbc.m_vertex_count].m_a = data; + break; + + default: + logerror("fbc_w: Unknown register %08x = %08x & %08x\n", 0x00700000 | (offset << 2), data, mem_mask); + break; + } +} + +//------------------------------------------------- +// TurboGX implementation +//------------------------------------------------- + +void sbus_turbogx_device::mem_map(address_map &map) +{ + base_map(map); + map(0x00800000, 0x008fffff).rw(FUNC(sbus_turbogx_device::vram_r), FUNC(sbus_turbogx_device::vram_w)); +} + +ROM_START( sbus_turbogx ) + ROM_REGION32_BE(0x8000, "prom", ROMREGION_ERASEFF) + ROM_LOAD( "sunw,501-2325.bin", 0x0000, 0x8000, CRC(bbdc45f8) SHA1(e4a51d78e199cd57f2fcb9d45b25dfae2bd537e4)) +ROM_END + +const tiny_rom_entry *sbus_turbogx_device::device_rom_region() const +{ + return ROM_NAME( sbus_turbogx ); +} + +void sbus_turbogx_device::device_add_mconfig(machine_config &config) +{ + SCREEN(config, m_screen, SCREEN_TYPE_RASTER); + m_screen->set_screen_update(FUNC(sbus_turbogx_device::screen_update)); + m_screen->set_size(1152, 900); + m_screen->set_visarea(0, 1152-1, 0, 900-1); + m_screen->set_refresh_hz(72); + + BT458(config, m_ramdac, 0); +} + +sbus_turbogx_device::sbus_turbogx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : sbus_cgsix_device(mconfig, SBUS_TURBOGX, tag, owner, clock, 0x100000) +{ +} + +void sbus_turbogx_device::install_device() +{ + m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_turbogx_device::mem_map); +} + +//------------------------------------------------- +// TurboGX+ implementation +//------------------------------------------------- + +void sbus_turbogxp_device::mem_map(address_map &map) +{ + base_map(map); + map(0x00800000, 0x00bfffff).rw(FUNC(sbus_turbogxp_device::vram_r), FUNC(sbus_turbogxp_device::vram_w)); +} + +ROM_START( sbus_turbogxp ) + ROM_REGION32_BE(0x8000, "prom", ROMREGION_ERASEFF) + ROM_LOAD( "sunw,501-2253.bin", 0x0000, 0x8000, CRC(525a58db) SHA1(721fc378d4b952b5cbb271e16bd67bc02439efdc)) +ROM_END + +const tiny_rom_entry *sbus_turbogxp_device::device_rom_region() const +{ + return ROM_NAME( sbus_turbogxp ); +} + +void sbus_turbogxp_device::device_add_mconfig(machine_config &config) +{ + SCREEN(config, m_screen, SCREEN_TYPE_RASTER); + m_screen->set_screen_update(FUNC(sbus_turbogxp_device::screen_update)); + m_screen->set_size(1152, 900); + m_screen->set_visarea(0, 1152-1, 0, 900-1); + m_screen->set_refresh_hz(72); + + BT467(config, m_ramdac, 0); +} + +sbus_turbogxp_device::sbus_turbogxp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : sbus_cgsix_device(mconfig, SBUS_TURBOGXP, tag, owner, clock, 0x400000) +{ +} + +void sbus_turbogxp_device::install_device() +{ + m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_turbogxp_device::mem_map); +} + diff --git a/src/devices/bus/sbus/cgsix.h b/src/devices/bus/sbus/cgsix.h new file mode 100644 index 00000000000..3bee124d229 --- /dev/null +++ b/src/devices/bus/sbus/cgsix.h @@ -0,0 +1,515 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Sun cgsix-series accelerated 8-bit color video controller + +***************************************************************************/ + +#ifndef MAME_BUS_SBUS_CGSIX_H +#define MAME_BUS_SBUS_CGSIX_H + +#pragma once + +#include "sbus.h" +#include "video/bt45x.h" +#include "screen.h" + +class sbus_cgsix_device : public device_t, public device_sbus_card_interface +{ +public: + static constexpr feature_type imperfect_features() { return feature::GRAPHICS; } + +protected: + // construction/destruction + sbus_cgsix_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, const uint32_t vram_size) + : sbus_cgsix_device(mconfig, type, tag, owner, clock) + { + set_vram_size(vram_size); + } + + sbus_cgsix_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); + + // configuration + void set_vram_size(uint32_t vram_size) { m_vram_size = vram_size; } + + // device_t overrides + virtual void device_start() override; + virtual void device_reset() override; + + DECLARE_READ32_MEMBER(rom_r); + DECLARE_READ32_MEMBER(unknown_r); + DECLARE_WRITE32_MEMBER(unknown_w); + DECLARE_READ32_MEMBER(vram_r); + DECLARE_WRITE32_MEMBER(vram_w); + DECLARE_READ32_MEMBER(fbc_r); + DECLARE_WRITE32_MEMBER(fbc_w); + + uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); + uint8_t perform_rasterop(uint8_t src, uint8_t dst); + void handle_font_poke(); + void handle_draw_command(); + void handle_blit_command(); + + void base_map(address_map &map); + + enum + { + ROP_CLR = 0x00, + ROP_SRC_NOR_DST = 0x01, + ROP_NSRC_AND_DST = 0x02, + ROP_NOT_SRC = 0x03, + ROP_SRC_AND_NDST = 0x04, + ROP_NOT_DST = 0x05, + ROP_SRC_XOR_DST = 0x06, + ROP_SRC_NAND_DST = 0x07, + ROP_SRC_AND_DST = 0x08, + ROP_SRC_XNOR_DST = 0x09, + ROP_DST = 0x0a, + ROP_NSRC_OR_DST = 0x0b, + ROP_SRC = 0x0c, + ROP_SRC_OR_NDST = 0x0d, + ROP_SRC_OR_DST = 0x0e, + ROP_SET = 0x0f + }; + + enum + { + FBC_MISC_INDEX_SHIFT = 4, + FBC_MISC_INDEX_MOD_SHIFT = 6, + FBC_MISC_BDISP_SHIFT = 7, + FBC_MISC_BREAD_SHIFT = 9, + FBC_MISC_BWRITE1_SHIFT = 11, + FBC_MISC_BWRITE0_SHIFT = 13, + FBC_MISC_DRAW_SHIFT = 15, + FBC_MISC_DATA_SHIFT = 17, + FBC_MISC_VBLANK_SHIFT = 19, + FBC_MISC_BLIT_SHIFT = 20 + }; + + enum + { + FBC_MISC_INDEX_MASK = 0x3, + FBC_MISC_INDEX_MOD_MASK = 0x1, + FBC_MISC_BDISP_MASK = 0x3, + FBC_MISC_BREAD_MASK = 0x3, + FBC_MISC_BWRITE1_MASK = 0x3, + FBC_MISC_BWRITE0_MASK = 0x3, + FBC_MISC_DRAW_MASK = 0x3, + FBC_MISC_DATA_MASK = 0x3, + FBC_MISC_VBLANK_MASK = 0x1, + FBC_MISC_BLIT_MASK = 0x3 + }; + + enum + { + FBC_MISC_BDISP_IGNORE = 0, + FBC_MISC_BDISP_0 = 1, + FBC_MISC_BDISP_1 = 2, + FBC_MISC_BDISP_ILLEGAL = 3, + + FBC_MISC_BREAD_IGNORE = 0, + FBC_MISC_BREAD_0 = 1, + FBC_MISC_BREAD_1 = 2, + FBC_MISC_BREAD_ILLEGAL = 3, + + FBC_MISC_BWRITE1_IGNORE = 0, + FBC_MISC_BWRITE1_ENABLE = 1, + FBC_MISC_BWRITE1_DISABLE = 2, + FBC_MISC_BWRITE1_ILLEGAL = 3, + + FBC_MISC_BWRITE0_IGNORE = 0, + FBC_MISC_BWRITE0_ENABLE = 1, + FBC_MISC_BWRITE0_DISABLE = 2, + FBC_MISC_BWRITE0_ILLEGAL = 3, + + FBC_MISC_DRAW_IGNORE = 0, + FBC_MISC_DRAW_RENDER = 1, + FBC_MISC_DRAW_PICK = 2, + FBC_MISC_DRAW_ILLEGAL = 3, + + FBC_MISC_DATA_IGNORE = 0, + FBC_MISC_DATA_COLOR8 = 1, + FBC_MISC_DATA_COLOR1 = 2, + FBC_MISC_DATA_HRMONO = 3, + + FBC_MISC_BLIT_IGNORE = 0, + FBC_MISC_BLIT_NOSRC = 1, + FBC_MISC_BLIT_SRC = 2, + FBC_MISC_BLIT_ILLEGAL = 3 + }; + + inline uint32_t fbc_misc_index() { return (m_fbc.m_misc >> FBC_MISC_INDEX_SHIFT) & FBC_MISC_INDEX_MASK; } + inline uint32_t fbc_misc_index_mod() { return (m_fbc.m_misc >> FBC_MISC_INDEX_MOD_SHIFT) & FBC_MISC_INDEX_MOD_MASK; } + inline uint32_t fbc_misc_bdisp() { return (m_fbc.m_misc >> FBC_MISC_BDISP_SHIFT) & FBC_MISC_BDISP_MASK; } + inline uint32_t fbc_misc_bread() { return (m_fbc.m_misc >> FBC_MISC_BREAD_SHIFT) & FBC_MISC_BREAD_MASK; } + inline uint32_t fbc_misc_bwrite1() { return (m_fbc.m_misc >> FBC_MISC_BWRITE1_SHIFT) & FBC_MISC_BWRITE1_MASK; } + inline uint32_t fbc_misc_bwrite0() { return (m_fbc.m_misc >> FBC_MISC_BWRITE0_SHIFT) & FBC_MISC_BWRITE0_MASK; } + inline uint32_t fbc_misc_draw() { return (m_fbc.m_misc >> FBC_MISC_DRAW_SHIFT) & FBC_MISC_DRAW_MASK; } + inline uint32_t fbc_misc_data() { return (m_fbc.m_misc >> FBC_MISC_DATA_SHIFT) & FBC_MISC_DATA_MASK; } + inline uint32_t fbc_misc_blit() { return (m_fbc.m_misc >> FBC_MISC_BLIT_SHIFT) & FBC_MISC_BLIT_MASK; } + + enum + { + FBC_RASTEROP_ROP00_SHIFT = 0, + FBC_RASTEROP_ROP01_SHIFT = 4, + FBC_RASTEROP_ROP10_SHIFT = 8, + FBC_RASTEROP_ROP11_SHIFT = 12, + FBC_RASTEROP_PLOT_SHIFT = 16, + FBC_RASTEROP_RAST_SHIFT = 17, + FBC_RASTEROP_ATTR_SHIFT = 22, + FBC_RASTEROP_POLYG_SHIFT = 24, + FBC_RASTEROP_PATT_SHIFT = 26, + FBC_RASTEROP_PIXEL_SHIFT = 28, + FBC_RASTEROP_PLANE_SHIFT = 30 + }; + + enum + { + FBC_RASTEROP_ROP00_MASK = 0xf, + FBC_RASTEROP_ROP01_MASK = 0xf, + FBC_RASTEROP_ROP10_MASK = 0xf, + FBC_RASTEROP_ROP11_MASK = 0xf, + FBC_RASTEROP_PLOT_MASK = 0x1, + FBC_RASTEROP_RAST_MASK = 0x1, + FBC_RASTEROP_ATTR_MASK = 0x3, + FBC_RASTEROP_POLYG_MASK = 0x3, + FBC_RASTEROP_PATT_MASK = 0x3, + FBC_RASTEROP_PIXEL_MASK = 0x3, + FBC_RASTEROP_PLANE_MASK = 0x3 + }; + + enum + { + FBC_RASTEROP_PLOT_PLOT = 0, + FBC_RASTEROP_PLOT_UNPLOT = 1, + + FBC_RASTEROP_RAST_BOOL = 0, + FBC_RASTEROP_RAST_LINEAR = 1, + + FBC_RASTEROP_ATTR_IGNORE = 0, + FBC_RASTEROP_ATTR_UNSUPP = 1, + FBC_RASTEROP_ATTR_SUPP = 2, + FBC_RASTEROP_ATTR_ILLEGAL = 3, + + FBC_RASTEROP_POLYG_IGNORE = 0, + FBC_RASTEROP_POLYG_OVERLAP = 1, + FBC_RASTEROP_POLYG_NONOVERLAP = 2, + FBC_RASTEROP_POLYG_ILLEGAL = 3, + + FBC_RASTEROP_PATTERN_IGNORE = 0, + FBC_RASTEROP_PATTERN_ZEROES = 1, + FBC_RASTEROP_PATTERN_ONES = 2, + FBC_RASTEROP_PATTERN_MSK = 3, + + FBC_RASTEROP_PIXEL_IGNORE = 0, + FBC_RASTEROP_PIXEL_ZEROES = 1, + FBC_RASTEROP_PIXEL_ONES = 2, + FBC_RASTEROP_PIXEL_MSK = 3, + + FBC_RASTEROP_PLANE_IGNORE = 0, + FBC_RASTEROP_PLANE_ZEROES = 1, + FBC_RASTEROP_PLANE_ONES = 2, + FBC_RASTEROP_PLANE_MSK = 3 + }; + + inline uint32_t fbc_rasterop_rop00() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP00_SHIFT) & FBC_RASTEROP_ROP00_MASK; } + inline uint32_t fbc_rasterop_rop01() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP01_SHIFT) & FBC_RASTEROP_ROP01_MASK; } + inline uint32_t fbc_rasterop_rop10() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP10_SHIFT) & FBC_RASTEROP_ROP10_MASK; } + inline uint32_t fbc_rasterop_rop11() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ROP11_SHIFT) & FBC_RASTEROP_ROP11_MASK; } + inline uint32_t fbc_rasterop_plot() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PLOT_SHIFT) & FBC_RASTEROP_PLOT_MASK; } + inline uint32_t fbc_rasterop_rast() { return (m_fbc.m_rasterop >> FBC_RASTEROP_RAST_SHIFT) & FBC_RASTEROP_RAST_MASK; } + inline uint32_t fbc_rasterop_attr() { return (m_fbc.m_rasterop >> FBC_RASTEROP_ATTR_SHIFT) & FBC_RASTEROP_ATTR_MASK; } + inline uint32_t fbc_rasterop_polyg() { return (m_fbc.m_rasterop >> FBC_RASTEROP_POLYG_SHIFT) & FBC_RASTEROP_POLYG_MASK; } + inline uint32_t fbc_rasterop_pattern() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PATT_SHIFT) & FBC_RASTEROP_PATT_MASK; } + inline uint32_t fbc_rasterop_pixel() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PIXEL_SHIFT) & FBC_RASTEROP_PIXEL_MASK; } + inline uint32_t fbc_rasterop_plane() { return (m_fbc.m_rasterop >> FBC_RASTEROP_PLANE_SHIFT) & FBC_RASTEROP_PLANE_MASK; } + + enum + { + FBC_MISC = 0x004/4, + FBC_CLIP_CHECK = 0x008/4, + + FBC_STATUS = 0x010/4, + FBC_DRAW_STATUS = 0x014/4, + FBC_BLIT_STATUS = 0x018/4, + FBC_FONT = 0x01c/4, + + FBC_X0 = 0x080/4, + FBC_Y0 = 0x084/4, + FBC_Z0 = 0x088/4, + FBC_COLOR0 = 0x08c/4, + FBC_X1 = 0x090/4, + FBC_Y1 = 0x094/4, + FBC_Z1 = 0x098/4, + FBC_COLOR1 = 0x09c/4, + FBC_X2 = 0x0a0/4, + FBC_Y2 = 0x0a4/4, + FBC_Z2 = 0x0a8/4, + FBC_COLOR2 = 0x0ac/4, + FBC_X3 = 0x0b0/4, + FBC_Y3 = 0x0b4/4, + FBC_Z3 = 0x0b8/4, + FBC_COLOR3 = 0x0bc/4, + + FBC_RASTER_OFFX = 0x0c0/4, + FBC_RASTER_OFFY = 0x0c4/4, + FBC_AUTOINCX = 0x0d0/4, + FBC_AUTOINCY = 0x0d4/4, + FBC_CLIP_MINX = 0x0e0/4, + FBC_CLIP_MINY = 0x0e4/4, + FBC_CLIP_MAXX = 0x0f0/4, + FBC_CLIP_MAXY = 0x0f4/4, + + FBC_FCOLOR = 0x100/4, + FBC_BCOLOR = 0x104/4, + FBC_RASTEROP = 0x108/4, + FBC_PLANE_MASK = 0x10c/4, + FBC_PIXEL_MASK = 0x110/4, + + FBC_PATT_ALIGN = 0x11c/4, + FBC_PATTERN0 = 0x120/4, + FBC_PATTERN1 = 0x124/4, + FBC_PATTERN2 = 0x128/4, + FBC_PATTERN3 = 0x12c/4, + FBC_PATTERN4 = 0x130/4, + FBC_PATTERN5 = 0x134/4, + FBC_PATTERN6 = 0x138/4, + FBC_PATTERN7 = 0x13c/4, + + FBC_IPOINT_ABSX = 0x800/4, + FBC_IPOINT_ABSY = 0x804/4, + FBC_IPOINT_ABSZ = 0x808/4, + FBC_IPOINT_RELX = 0x810/4, + FBC_IPOINT_RELY = 0x814/4, + FBC_IPOINT_RELZ = 0x818/4, + FBC_IPOINT_R = 0x830/4, + FBC_IPOINT_G = 0x834/4, + FBC_IPOINT_B = 0x838/4, + FBC_IPOINT_A = 0x83c/4, + + FBC_ILINE_ABSX = 0x840/4, + FBC_ILINE_ABSY = 0x844/4, + FBC_ILINE_ABSZ = 0x848/4, + FBC_ILINE_RELX = 0x850/4, + FBC_ILINE_RELY = 0x854/4, + FBC_ILINE_RELZ = 0x858/4, + FBC_ILINE_R = 0x870/4, + FBC_ILINE_G = 0x874/4, + FBC_ILINE_B = 0x878/4, + FBC_ILINE_A = 0x87c/4, + + FBC_ITRI_ABSX = 0x880/4, + FBC_ITRI_ABSY = 0x884/4, + FBC_ITRI_ABSZ = 0x888/4, + FBC_ITRI_RELX = 0x890/4, + FBC_ITRI_RELY = 0x894/4, + FBC_ITRI_RELZ = 0x898/4, + FBC_ITRI_R = 0x8b0/4, + FBC_ITRI_G = 0x8b4/4, + FBC_ITRI_B = 0x8b8/4, + FBC_ITRI_A = 0x8bc/4, + + FBC_IQUAD_ABSX = 0x8c0/4, + FBC_IQUAD_ABSY = 0x8c4/4, + FBC_IQUAD_ABSZ = 0x8c8/4, + FBC_IQUAD_RELX = 0x8d0/4, + FBC_IQUAD_RELY = 0x8d4/4, + FBC_IQUAD_RELZ = 0x8d8/4, + FBC_IQUAD_R = 0x8f0/4, + FBC_IQUAD_G = 0x8f4/4, + FBC_IQUAD_B = 0x8f8/4, + FBC_IQUAD_A = 0x8fc/4, + + FBC_IRECT_ABSX = 0x900/4, + FBC_IRECT_ABSY = 0x904/4, + FBC_IRECT_ABSZ = 0x908/4, + FBC_IRECT_RELX = 0x910/4, + FBC_IRECT_RELY = 0x914/4, + FBC_IRECT_RELZ = 0x918/4, + FBC_IRECT_R = 0x930/4, + FBC_IRECT_G = 0x934/4, + FBC_IRECT_B = 0x938/4, + FBC_IRECT_A = 0x93c/4, + }; + + struct vertex_t + { + uint32_t m_absx; + uint32_t m_absy; + uint32_t m_absz; + uint32_t m_relx; + uint32_t m_rely; + uint32_t m_relz; + uint32_t m_r; + uint32_t m_g; + uint32_t m_b; + uint32_t m_a; + }; + + enum prim_type : uint32_t + { + PRIM_POINT = 0, + PRIM_LINE, + PRIM_TRI, + PRIM_QUAD, + PRIM_RECT, + + PRIM_COUNT + }; + + struct fbc_t + { + uint32_t m_misc; + uint32_t m_clip_check; + uint32_t m_status; + uint32_t m_draw_status; + uint32_t m_blit_status; + uint32_t m_font; + + uint32_t m_x0; + uint32_t m_y0; + uint32_t m_z0; + uint32_t m_color0; + uint32_t m_x1; + uint32_t m_y1; + uint32_t m_z1; + uint32_t m_color1; + uint32_t m_x2; + uint32_t m_y2; + uint32_t m_z2; + uint32_t m_color2; + uint32_t m_x3; + uint32_t m_y3; + uint32_t m_z3; + uint32_t m_color3; + + uint32_t m_raster_offx; + uint32_t m_raster_offy; + + uint32_t m_autoincx; + uint32_t m_autoincy; + + uint32_t m_clip_minx; + uint32_t m_clip_miny; + + uint32_t m_clip_maxx; + uint32_t m_clip_maxy; + + uint8_t m_fcolor; + uint8_t m_bcolor; + + uint32_t m_rasterop; + + uint32_t m_plane_mask; + uint32_t m_pixel_mask; + + uint32_t m_patt_align; + uint32_t m_pattern[8]; + + uint32_t m_ipoint_absx; + uint32_t m_ipoint_absy; + uint32_t m_ipoint_absz; + uint32_t m_ipoint_relx; + uint32_t m_ipoint_rely; + uint32_t m_ipoint_relz; + uint32_t m_ipoint_r; + uint32_t m_ipoint_g; + uint32_t m_ipoint_b; + uint32_t m_ipoint_a; + + uint32_t m_iline_absx; + uint32_t m_iline_absy; + uint32_t m_iline_absz; + uint32_t m_iline_relx; + uint32_t m_iline_rely; + uint32_t m_iline_relz; + uint32_t m_iline_r; + uint32_t m_iline_g; + uint32_t m_iline_b; + uint32_t m_iline_a; + + uint32_t m_itri_absx; + uint32_t m_itri_absy; + uint32_t m_itri_absz; + uint32_t m_itri_relx; + uint32_t m_itri_rely; + uint32_t m_itri_relz; + uint32_t m_itri_r; + uint32_t m_itri_g; + uint32_t m_itri_b; + uint32_t m_itri_a; + + uint32_t m_iquad_absx; + uint32_t m_iquad_absy; + uint32_t m_iquad_absz; + uint32_t m_iquad_relx; + uint32_t m_iquad_rely; + uint32_t m_iquad_relz; + uint32_t m_iquad_r; + uint32_t m_iquad_g; + uint32_t m_iquad_b; + uint32_t m_iquad_a; + + uint32_t m_irect_absx; + uint32_t m_irect_absy; + uint32_t m_irect_absz; + uint32_t m_irect_relx; + uint32_t m_irect_rely; + uint32_t m_irect_relz; + uint32_t m_irect_r; + uint32_t m_irect_g; + uint32_t m_irect_b; + uint32_t m_irect_a; + + vertex_t m_prim_buf[0x1000]; // unknown size + uint32_t m_vertex_count; + uint32_t m_curr_prim_type; + }; + + required_memory_region m_rom; + std::unique_ptr m_vram; + required_device m_screen; + required_device m_ramdac; + + fbc_t m_fbc; + + uint32_t m_vram_size; +}; + +class sbus_turbogx_device : public sbus_cgsix_device +{ +public: + sbus_turbogx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + // device_t overrides + virtual const tiny_rom_entry *device_rom_region() const override; + void device_add_mconfig(machine_config &config) override; + + // device_sbus_slot_interface overrides + virtual void install_device() override; + + void mem_map(address_map &map) override; +}; + +class sbus_turbogxp_device : public sbus_cgsix_device +{ +public: + sbus_turbogxp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + // device_t overrides + virtual const tiny_rom_entry *device_rom_region() const override; + void device_add_mconfig(machine_config &config) override; + + // device_sbus_slot_interface overrides + virtual void install_device() override; + + void mem_map(address_map &map) override; +}; + +DECLARE_DEVICE_TYPE(SBUS_TURBOGX, sbus_turbogx_device) +DECLARE_DEVICE_TYPE(SBUS_TURBOGXP, sbus_turbogxp_device) + +#endif // MAME_BUS_SBUS_CGSIX_H diff --git a/src/devices/bus/sbus/cgthree.cpp b/src/devices/bus/sbus/cgthree.cpp new file mode 100644 index 00000000000..091efef3b21 --- /dev/null +++ b/src/devices/bus/sbus/cgthree.cpp @@ -0,0 +1,121 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Sun cgthree color video controller + +***************************************************************************/ + +#include "emu.h" +#include "cgthree.h" +#include "screen.h" + +DEFINE_DEVICE_TYPE(SBUS_CGTHREE, sbus_cgthree_device, "cgthree", "Sun cgthree SBus Video") + +void sbus_cgthree_device::mem_map(address_map &map) +{ + map(0x00000000, 0x01ffffff).rw(FUNC(sbus_cgthree_device::unknown_r), FUNC(sbus_cgthree_device::unknown_w)); + map(0x00000000, 0x000007ff).r(FUNC(sbus_cgthree_device::rom_r)); + map(0x00400000, 0x0040000f).m(m_ramdac, FUNC(bt458_device::map)).umask32(0xff000000); + map(0x007ff800, 0x007ff81f).rw(FUNC(sbus_cgthree_device::regs_r), FUNC(sbus_cgthree_device::regs_w)); + map(0x00800000, 0x008fffff).rw(FUNC(sbus_cgthree_device::vram_r), FUNC(sbus_cgthree_device::vram_w)); + map(0x00bff800, 0x00cff7ff).rw(FUNC(sbus_cgthree_device::vram_r), FUNC(sbus_cgthree_device::vram_w)); +} + +ROM_START( sbus_cgthree ) + ROM_REGION32_BE(0x800, "prom", ROMREGION_ERASEFF) + ROM_LOAD( "sunw,501-1415.bin", 0x0000, 0x0800, CRC(d1eb6f4d) SHA1(9bef98b2784b6e70167337bb27cd07952b348b5a)) +ROM_END + +const tiny_rom_entry *sbus_cgthree_device::device_rom_region() const +{ + return ROM_NAME( sbus_cgthree ); +} + +void sbus_cgthree_device::device_add_mconfig(machine_config &config) +{ + SCREEN(config, m_screen, SCREEN_TYPE_RASTER); + m_screen->set_screen_update(FUNC(sbus_cgthree_device::screen_update)); + m_screen->set_raw(92.9405_MHz_XTAL, 1504, 0, 1152, 937, 0, 900); + + BT458(config, m_ramdac, 0); +} + +sbus_cgthree_device::sbus_cgthree_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, SBUS_CGTHREE, tag, owner, clock) + , device_sbus_card_interface(mconfig, *this) + , m_rom(*this, "prom") + , m_screen(*this, "screen") + , m_ramdac(*this, "ramdac") +{ +} + +void sbus_cgthree_device::device_start() +{ + m_vram = std::make_unique(0x100000/4); + save_pointer(NAME(m_vram), 0x100000/4); +} + +void sbus_cgthree_device::device_reset() +{ +} + +void sbus_cgthree_device::install_device() +{ + m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_cgthree_device::mem_map); +} + +uint32_t sbus_cgthree_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) +{ + const pen_t *pens = m_ramdac->pens(); + uint8_t *vram = (uint8_t *)&m_vram[0]; + + for (int y = 0; y < 900; y++) + { + uint32_t *scanline = &bitmap.pix32(y); + for (int x = 0; x < 1152; x++) + { + const uint8_t pixel = vram[y * 1152 + BYTE4_XOR_BE(x)]; + *scanline++ = pens[pixel]; + } + } + + return 0; +} + +READ32_MEMBER(sbus_cgthree_device::unknown_r) +{ + logerror("%s: unknown_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask); + return 0; +} + +WRITE32_MEMBER(sbus_cgthree_device::unknown_w) +{ + logerror("%s: unknown_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask); +} + +READ8_MEMBER(sbus_cgthree_device::regs_r) +{ + logerror("%s: regs_r: Unimplemented: %08x\n", machine().describe_context(), 0x7ff800 + offset); + return 0; +} + +WRITE8_MEMBER(sbus_cgthree_device::regs_w) +{ + logerror("%s: regs_w: Unimplemented: %08x = %02x\n", machine().describe_context(), 0x7ff800 + offset, data); +} + +READ32_MEMBER(sbus_cgthree_device::rom_r) +{ + return ((uint32_t*)m_rom->base())[offset]; +} + +READ32_MEMBER(sbus_cgthree_device::vram_r) +{ + return m_vram[offset]; +} + +WRITE32_MEMBER(sbus_cgthree_device::vram_w) +{ + COMBINE_DATA(&m_vram[offset]); +} diff --git a/src/devices/bus/sbus/cgthree.h b/src/devices/bus/sbus/cgthree.h new file mode 100644 index 00000000000..9b99d4a2fba --- /dev/null +++ b/src/devices/bus/sbus/cgthree.h @@ -0,0 +1,58 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Sun cgthree color video controller + +***************************************************************************/ + +#ifndef MAME_BUS_SBUS_CGTHREE_H +#define MAME_BUS_SBUS_CGTHREE_H + +#pragma once + +#include "sbus.h" +#include "video/bt45x.h" + +class sbus_cgthree_device : public device_t, public device_sbus_card_interface +{ +public: + static constexpr feature_type imperfect_features() { return feature::GRAPHICS; } + + // construction/destruction + sbus_cgthree_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + // device_t overrides + virtual const tiny_rom_entry *device_rom_region() const override; + virtual void device_add_mconfig(machine_config &config) override; + virtual void device_start() override; + virtual void device_reset() override; + + // device_sbus_slot_interface overrides + virtual void install_device() override; + + DECLARE_READ32_MEMBER(unknown_r); + DECLARE_WRITE32_MEMBER(unknown_w); + DECLARE_WRITE32_MEMBER(palette_w); + DECLARE_READ8_MEMBER(regs_r); + DECLARE_WRITE8_MEMBER(regs_w); + DECLARE_READ32_MEMBER(rom_r); + DECLARE_READ32_MEMBER(vram_r); + DECLARE_WRITE32_MEMBER(vram_w); + +private: + uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); + + void mem_map(address_map &map) override; + + required_memory_region m_rom; + std::unique_ptr m_vram; + required_device m_screen; + required_device m_ramdac; +}; + + +DECLARE_DEVICE_TYPE(SBUS_CGTHREE, sbus_cgthree_device) + +#endif // MAME_BUS_SBUS_CGTHREE_H diff --git a/src/devices/bus/sbus/hme.cpp b/src/devices/bus/sbus/hme.cpp new file mode 100644 index 00000000000..eb6d5852138 --- /dev/null +++ b/src/devices/bus/sbus/hme.cpp @@ -0,0 +1,71 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Sun SunSwift 10/100 + Fast Wide SCSI "Colossus" skeleton + + Notable parts on board: + - 1x 32-pin PLCC ROM, label 525 / 1409 / -08 on separate lines + - 1x Sun STP2002QFP, marked 100-4156-05 / 609-0392458 / DP03972 + - 1x National Semiconductor DP83840AVCE-1 Ethernet Physical Layer + - 1x National Semiconductor DP83223V Twisted Pair Transceiver + +***************************************************************************/ + +#include "emu.h" +#include "hme.h" + +DEFINE_DEVICE_TYPE(SBUS_HME, sbus_hme_device, "sbus_hme", "Sun 10/100 + Fast Wide SCSI") + +void sbus_hme_device::mem_map(address_map &map) +{ + map(0x00000000, 0x01ffffff).rw(FUNC(sbus_hme_device::unknown_r), FUNC(sbus_hme_device::unknown_w)); + map(0x00000000, 0x0000ffff).r(FUNC(sbus_hme_device::rom_r)); +} + +ROM_START( sbus_hme ) + ROM_REGION32_BE(0x10000, "prom", ROMREGION_ERASEFF) + ROM_LOAD( "525 1409 -08.bin", 0x00000, 0x10000, CRC(10f0b28f) SHA1(b54bb0f01c45accdbc58c3a86f8de34949374880)) +ROM_END + +const tiny_rom_entry *sbus_hme_device::device_rom_region() const +{ + return ROM_NAME( sbus_hme ); +} + +void sbus_hme_device::device_add_mconfig(machine_config &config) +{ +} + + +sbus_hme_device::sbus_hme_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, SBUS_HME, tag, owner, clock) + , device_sbus_card_interface(mconfig, *this) + , m_rom(*this, "prom") +{ +} + +void sbus_hme_device::device_start() +{ +} + +void sbus_hme_device::install_device() +{ + m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_hme_device::mem_map); +} + +READ32_MEMBER(sbus_hme_device::unknown_r) +{ + logerror("%s: unknown_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask); + return 0; +} + +WRITE32_MEMBER(sbus_hme_device::unknown_w) +{ + logerror("%s: unknown_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask); +} + +READ32_MEMBER(sbus_hme_device::rom_r) +{ + return ((uint32_t*)m_rom->base())[offset]; +} diff --git a/src/devices/bus/sbus/hme.h b/src/devices/bus/sbus/hme.h new file mode 100644 index 00000000000..c3bb4ff2dfd --- /dev/null +++ b/src/devices/bus/sbus/hme.h @@ -0,0 +1,45 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Sun SunSwift 10/100 + Fast Wide SCSI "Colossus" skeleton + +***************************************************************************/ + +#ifndef MAME_BUS_SBUS_HME_H +#define MAME_BUS_SBUS_HME_H + +#pragma once + +#include "sbus.h" + + +class sbus_hme_device : public device_t, public device_sbus_card_interface +{ +public: + // construction/destruction + sbus_hme_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + // device_t overrides + virtual const tiny_rom_entry *device_rom_region() const override; + virtual void device_add_mconfig(machine_config &config) override; + virtual void device_start() override; + + // device_sbus_slot_interface overrides + virtual void install_device() override; + + DECLARE_READ32_MEMBER(unknown_r); + DECLARE_WRITE32_MEMBER(unknown_w); + DECLARE_READ32_MEMBER(rom_r); + +private: + void mem_map(address_map &map) override; + + required_memory_region m_rom; +}; + + +DECLARE_DEVICE_TYPE(SBUS_HME, sbus_hme_device) + +#endif // MAME_BUS_SBUS_HME_H diff --git a/src/devices/bus/sbus/sbus.cpp b/src/devices/bus/sbus/sbus.cpp new file mode 100644 index 00000000000..f8363194c5a --- /dev/null +++ b/src/devices/bus/sbus/sbus.cpp @@ -0,0 +1,220 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + sbus.c - Sun SBus slot bus and card emulation + +***************************************************************************/ + +#include "emu.h" + +// Display boards +#include "bwtwo.h" +#include "cgthree.h" +#include "cgsix.h" + +// Accelerator boards +#include "sunpc.h" + +// Peripheral boards +#include "artecon.h" +#include "hme.h" + +#include "sbus.h" + +void sbus_cards(device_slot_interface &device) +{ + device.option_add("bwtwo", SBUS_BWTWO); /* Sun bwtwo monochrome display board */ + device.option_add("cgthree", SBUS_CGTHREE); /* Sun cgthree color display board */ + device.option_add("turbogx", SBUS_TURBOGX); /* Sun TurboGX 8-bit color display board */ + device.option_add("turbogxp", SBUS_TURBOGXP); /* Sun TurboGX+ 8-bit color display board */ + device.option_add("sunpc", SBUS_SUNPC); /* Sun SunPC 5x86 Accelerator board */ + device.option_add("hme", SBUS_HME); /* Sun SunSwift 10/100 + Fast Wide SCSI "Colossus" board */ + device.option_add("sb300p", SBUS_SB300P); /* Artecon CB300P 3-serial/1-parallel board */ +} + +DEFINE_DEVICE_TYPE(SBUS_SLOT, sbus_slot_device, "sbus_slot", "Sun SBus Slot") + +sbus_slot_device::sbus_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : sbus_slot_device(mconfig, SBUS_SLOT, tag, owner, clock) +{ +} + +sbus_slot_device::sbus_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, type, tag, owner, clock) + , device_slot_interface(mconfig, *this) + , m_sbus(*this, finder_base::DUMMY_TAG) +{ +} + +void sbus_slot_device::device_validity_check(validity_checker &valid) const +{ + device_t *const card(get_card_device()); + if (card && !dynamic_cast(card)) + osd_printf_error("Card device %s (%s) does not implement device_sbus_card_interface\n", card->tag(), card->name()); +} + +void sbus_slot_device::device_resolve_objects() +{ + device_sbus_card_interface *const sbus_card(dynamic_cast(get_card_device())); + if (sbus_card) + sbus_card->set_sbus(m_sbus, tag()); +} + +void sbus_slot_device::device_start() +{ + device_t *const card(get_card_device()); + if (card && !dynamic_cast(card)) + throw emu_fatalerror("sbus_slot_device: card device %s (%s) does not implement device_sbus_card_interface\n", card->tag(), card->name()); +} + + +DEFINE_DEVICE_TYPE(SBUS, sbus_device, "sbus", "Sun SBus") + +device_memory_interface::space_config_vector sbus_device::memory_space_config() const +{ + return space_config_vector { + std::make_pair(0, &m_space_config) + }; +} + +sbus_device::sbus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : sbus_device(mconfig, SBUS, tag, owner, clock) +{ +} + +sbus_device::sbus_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, type, tag, owner, clock) + , device_memory_interface(mconfig, *this) + , m_space_config("SBus Space", ENDIANNESS_BIG, 32, 32, 0, address_map_constructor()) + , m_maincpu(*this, finder_base::DUMMY_TAG) + , m_type1space(*this, finder_base::DUMMY_TAG) + , m_irq_cb{{*this}, {*this}, {*this}, {*this}, {*this}, {*this}, {*this}} + , m_buserr(*this) +{ +} + +void sbus_device::device_resolve_objects() +{ + // resolve callbacks + for (int i = 0; i < 7; i++) + m_irq_cb[i].resolve_safe(); + m_buserr.resolve_safe(); +} + +void sbus_device::device_start() +{ + std::fill(std::begin(m_device_list), std::end(m_device_list), nullptr); + + m_space = &space(0); + m_space->install_readwrite_handler(0x00000000, 0x01ffffff, read32_delegate(FUNC(sbus_device::slot_timeout_r<0>), this), write32_delegate(FUNC(sbus_device::slot_timeout_w<0>), this)); + m_space->install_readwrite_handler(0x02000000, 0x03ffffff, read32_delegate(FUNC(sbus_device::slot_timeout_r<1>), this), write32_delegate(FUNC(sbus_device::slot_timeout_w<1>), this)); + m_space->install_readwrite_handler(0x04000000, 0x05ffffff, read32_delegate(FUNC(sbus_device::slot_timeout_r<2>), this), write32_delegate(FUNC(sbus_device::slot_timeout_w<2>), this)); +} + +template READ32_MEMBER(sbus_device::slot_timeout_r) +{ + m_maincpu->set_mae(); + m_buserr(0, 0x20); + m_buserr(1, 0xffa00000 + (Slot << 21)); + return 0; +} + +template WRITE32_MEMBER(sbus_device::slot_timeout_w) +{ + m_maincpu->set_mae(); + m_buserr(0, 0x8020); + m_buserr(1, 0xffa00000 + (Slot << 21)); +} + +READ32_MEMBER(sbus_device::read) +{ + return m_space->read_dword(offset << 2, mem_mask); +} + +WRITE32_MEMBER(sbus_device::write) +{ + m_space->write_dword(offset << 2, data, mem_mask); +} + +device_sbus_card_interface *sbus_device::get_sbus_card(int slot) +{ + if (slot < 0) + { + return nullptr; + } + + if (m_device_list[slot]) + { + return m_device_list[slot]; + } + + return nullptr; +} + +void sbus_device::add_sbus_card(int slot, device_sbus_card_interface *card) +{ + m_device_list[slot] = card; + card->install_device(); +} + +void sbus_device::set_irq_line(int state, int line) +{ + m_irq_cb[line](state); +} + + + +device_sbus_card_interface::device_sbus_card_interface(const machine_config &mconfig, device_t &device) + : device_slot_card_interface(mconfig, device) + , m_sbus_finder(device, finder_base::DUMMY_TAG) + , m_sbus(nullptr) + , m_sbus_slottag(nullptr) + , m_slot(-1) + , m_base(0) +{ +} + +device_sbus_card_interface::~device_sbus_card_interface() +{ +} + +void device_sbus_card_interface::interface_validity_check(validity_checker &valid) const +{ + if (m_sbus_finder && m_sbus && (m_sbus != m_sbus_finder)) + osd_printf_error("Contradictory buses configured (%s and %s)\n", m_sbus_finder->tag(), m_sbus->tag()); +} + +void device_sbus_card_interface::interface_pre_start() +{ + device_slot_card_interface::interface_pre_start(); + + if (!m_sbus) + { + m_sbus = m_sbus_finder; + if (!m_sbus) + fatalerror("Can't find Sun SBus device %s\n", m_sbus_finder.finder_tag()); + } + + if (0 > m_slot) + { + if (!m_sbus->started()) + throw device_missing_dependencies(); + + // extract the slot number from the last digit of the slot tag + size_t const tlen = strlen(m_sbus_slottag); + + m_slot = (m_sbus_slottag[tlen - 1] - '1'); + if (m_slot < 0 || m_slot > 2) + fatalerror("Slot %x out of range for Sun SBus\n", m_slot); + + m_base = m_slot << 25; + m_sbus->add_sbus_card(m_slot, this); + } +} + +void device_sbus_card_interface::set_sbus(sbus_device *sbus, const char *slottag) +{ + m_sbus = sbus; + m_sbus_slottag = slottag; +} diff --git a/src/devices/bus/sbus/sbus.h b/src/devices/bus/sbus/sbus.h new file mode 100644 index 00000000000..5349c2c8e42 --- /dev/null +++ b/src/devices/bus/sbus/sbus.h @@ -0,0 +1,160 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + sbus.h - Sun SBus slot bus and card emulation + +***************************************************************************/ + +#ifndef MAME_BUS_SBUS_SBUS_H +#define MAME_BUS_SBUS_SBUS_H + +#pragma once + +#include "cpu/sparc/sparc.h" +#include "machine/bankdev.h" + +class sbus_device; + +class sbus_slot_device : public device_t, public device_slot_interface +{ +public: + // construction/destruction + template + sbus_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&sbus_tag, U &&opts, const char *dflt, bool fixed = false) + : sbus_slot_device(mconfig, tag, owner, clock) + { + option_reset(); + opts(*this); + set_default_option(dflt); + set_fixed(fixed); + m_sbus.set_tag(std::forward(sbus_tag)); + } + sbus_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + sbus_slot_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); + + // device-level overrides + virtual void device_validity_check(validity_checker &valid) const override; + virtual void device_resolve_objects() override; + virtual void device_start() override; + + // configuration + required_device m_sbus; + + DECLARE_READ32_MEMBER(timeout_r); + DECLARE_WRITE32_MEMBER(timeout_w); +}; + +DECLARE_DEVICE_TYPE(SBUS_SLOT, sbus_slot_device) + + +class device_sbus_card_interface; + +class sbus_device : public device_t, + public device_memory_interface +{ + friend class device_sbus_card_interface; +public: + // construction/destruction + template + sbus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag, U &&space_tag) + : sbus_device(mconfig, tag, owner, clock) + { + set_cpu_tag(std::forward(cpu_tag)); + set_space_tag(std::forward(space_tag)); + } + + sbus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + // inline configuration + template void set_cpu_tag(T &&tag) { m_maincpu.set_tag(std::forward(tag)); } + template void set_space_tag(T &&tag) { m_type1space.set_tag(std::forward(tag)); } + + // devcb3 + template auto irq() { return m_irq_cb[Line].bind(); } + auto buserr() { return m_buserr.bind(); } + + virtual space_config_vector memory_space_config() const override; + + const address_space_config m_space_config; + + void add_sbus_card(int slot, device_sbus_card_interface *card); + device_sbus_card_interface *get_sbus_card(int slot); + + void set_irq_line(int state, int line); + + template void install_device(offs_t addrstart, offs_t addrend, T &device, void (T::*map)(class address_map &map), uint64_t unitmask = ~u64(0)) + { + m_space->install_device(addrstart, addrend, device, map, unitmask); + } + + DECLARE_READ32_MEMBER(read); + DECLARE_WRITE32_MEMBER(write); + +protected: + sbus_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); + + // device-level overrides + virtual void device_resolve_objects() override; + virtual void device_start() override; + + // internal state + required_device m_maincpu; + required_device m_type1space; + address_space *m_space; + + devcb_write_line m_irq_cb[7]; + devcb_write32 m_buserr; + + device_sbus_card_interface *m_device_list[3]; + +private: + void slot1_timeout_map(address_map &map); + void slot2_timeout_map(address_map &map); + void slot3_timeout_map(address_map &map); + + template DECLARE_READ32_MEMBER(slot_timeout_r); + template DECLARE_WRITE32_MEMBER(slot_timeout_w); +}; + +DECLARE_DEVICE_TYPE(SBUS, sbus_device) + + +// class representing interface-specific live sbus card +class device_sbus_card_interface : public device_slot_card_interface +{ + friend class sbus_device; +public: + // construction/destruction + virtual ~device_sbus_card_interface(); + + // inline configuration + void set_sbus(sbus_device *sbus, const char *slottag); + template void set_onboard(T &&sbus) { m_sbus_finder.set_tag(std::forward(sbus)); m_sbus_slottag = device().tag(); } + + virtual void mem_map(address_map &map) = 0; + +protected: + void raise_irq(int line) { m_sbus->set_irq_line(ASSERT_LINE, line); } + void lower_irq(int line) { m_sbus->set_irq_line(CLEAR_LINE, line); } + + device_sbus_card_interface(const machine_config &mconfig, device_t &device); + + virtual void interface_validity_check(validity_checker &valid) const override; + virtual void interface_pre_start() override; + virtual void install_device() = 0; + + sbus_device &sbus() { assert(m_sbus); return *m_sbus; } + + optional_device m_sbus_finder; + sbus_device *m_sbus; + const char *m_sbus_slottag; + int m_slot; + uint32_t m_base; +}; + +void sbus_cards(device_slot_interface &device); + +#endif // MAME_BUS_SBUS_SBUS_H diff --git a/src/devices/bus/sbus/sunpc.cpp b/src/devices/bus/sbus/sunpc.cpp new file mode 100644 index 00000000000..7036e857393 --- /dev/null +++ b/src/devices/bus/sbus/sunpc.cpp @@ -0,0 +1,71 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Sun SunPC 5x86 Accelerator (501-4230) skeleton + + Notable parts on board: + - 1x AMD AM27C256 PLCC ROM + - 1x Motorola SunPC Accelerator 100-3069-03, mfr/date AANL9732 + - 6x Cypress CY7B185-10VC 64kBit Static RAM + - 1x AMD 5x86 (under heatsink; markings unknown) + +***************************************************************************/ + +#include "emu.h" +#include "sunpc.h" + +DEFINE_DEVICE_TYPE(SBUS_SUNPC, sbus_sunpc_device, "sbus_sunpc", "Sun SunPC accelerator") + +void sbus_sunpc_device::mem_map(address_map &map) +{ + map(0x00000000, 0x01ffffff).rw(FUNC(sbus_sunpc_device::unknown_r), FUNC(sbus_sunpc_device::unknown_w)); + map(0x00000000, 0x00007fff).r(FUNC(sbus_sunpc_device::rom_r)); +} + +ROM_START( sbus_sunpc ) + ROM_REGION32_BE(0x8000, "prom", ROMREGION_ERASEFF) + ROM_LOAD( "sunw,501-1763-01.bin", 0x0000, 0x8000, CRC(171f50f8) SHA1(21c4c02bc5a3a0494301f19c54ba0e207568fb42)) +ROM_END + +const tiny_rom_entry *sbus_sunpc_device::device_rom_region() const +{ + return ROM_NAME( sbus_sunpc ); +} + +void sbus_sunpc_device::device_add_mconfig(machine_config &config) +{ +} + + +sbus_sunpc_device::sbus_sunpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, SBUS_SUNPC, tag, owner, clock) + , device_sbus_card_interface(mconfig, *this) + , m_rom(*this, "prom") +{ +} + +void sbus_sunpc_device::device_start() +{ +} + +void sbus_sunpc_device::install_device() +{ + m_sbus->install_device(m_base, m_base + 0x1ffffff, *this, &sbus_sunpc_device::mem_map); +} + +READ32_MEMBER(sbus_sunpc_device::unknown_r) +{ + logerror("%s: unknown_r: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask); + return 0; +} + +WRITE32_MEMBER(sbus_sunpc_device::unknown_w) +{ + logerror("%s: unknown_w: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask); +} + +READ32_MEMBER(sbus_sunpc_device::rom_r) +{ + return ((uint32_t*)m_rom->base())[offset]; +} diff --git a/src/devices/bus/sbus/sunpc.h b/src/devices/bus/sbus/sunpc.h new file mode 100644 index 00000000000..8c20c1be27e --- /dev/null +++ b/src/devices/bus/sbus/sunpc.h @@ -0,0 +1,45 @@ +// license:BSD-3-Clause +// copyright-holders:Ryan Holtz +/*************************************************************************** + + Sun SunPC 5x86 Accelerator (501-4230) skeleton + +***************************************************************************/ + +#ifndef MAME_BUS_SBUS_SUNPC_H +#define MAME_BUS_SBUS_SUNPC_H + +#pragma once + +#include "sbus.h" + + +class sbus_sunpc_device : public device_t, public device_sbus_card_interface +{ +public: + // construction/destruction + sbus_sunpc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + +protected: + // device_t overrides + virtual const tiny_rom_entry *device_rom_region() const override; + virtual void device_add_mconfig(machine_config &config) override; + virtual void device_start() override; + + // device_sbus_slot_interface overrides + virtual void install_device() override; + + DECLARE_READ32_MEMBER(unknown_r); + DECLARE_WRITE32_MEMBER(unknown_w); + DECLARE_READ32_MEMBER(rom_r); + +private: + void mem_map(address_map &map) override; + + required_memory_region m_rom; +}; + + +DECLARE_DEVICE_TYPE(SBUS_SUNPC, sbus_sunpc_device) + +#endif // MAME_BUS_SBUS_SUNPC_H diff --git a/src/mame/drivers/indy_indigo2.cpp b/src/mame/drivers/indy_indigo2.cpp index dea0bc4bc73..95e96d94298 100644 --- a/src/mame/drivers/indy_indigo2.cpp +++ b/src/mame/drivers/indy_indigo2.cpp @@ -54,6 +54,8 @@ #include "emu.h" +#include "bus/gio64/gio64.h" + #include "cpu/mips/r4000.h" #include "machine/hpc3.h" @@ -79,6 +81,10 @@ public: , m_scsi_ctrl(*this, "scsibus:0:wd33c93") , m_hpc3(*this, "hpc3") , m_vino(*this, "vino") + , m_gio64(*this, "gio64") + , m_gio64_gfx(*this, "gio64_gfx") + , m_gio64_exp0(*this, "gio64_exp0") + , m_gio64_exp1(*this, "gio64_exp1") { } @@ -105,6 +111,10 @@ protected: required_device m_scsi_ctrl; required_device m_hpc3; optional_device m_vino; + optional_device m_gio64; + optional_device m_gio64_gfx; + optional_device m_gio64_exp0; + optional_device m_gio64_exp1; }; class ip24_state : public ip22_state @@ -162,6 +172,7 @@ void ip22_state::ip22_base_map(address_map &map) { map(0x00000000, 0x0007ffff).bankrw("bank1"); /* mirror of first 512k of main RAM */ map(0x08000000, 0x0fffffff).share("mainram").ram().w(FUNC(ip22_state::write_ram)); /* 128 MB of main RAM */ + map(0x1f000000, 0x1f9fffff).rw(m_gio64, FUNC(gio64_device::read), FUNC(gio64_device::write)); map(0x1fa00000, 0x1fa1ffff).rw(m_mem_ctrl, FUNC(sgi_mc_device::read), FUNC(sgi_mc_device::write)); map(0x1fb00000, 0x1fb7ffff).r(FUNC(ip22_state::bus_error)); map(0x1fb80000, 0x1fbfffff).m(m_hpc3, FUNC(hpc3_base_device::map)); @@ -232,6 +243,12 @@ void ip22_state::ip22_base(machine_config &config) NSCSI_CONNECTOR(config, "scsibus:5", scsi_devices, nullptr, false); NSCSI_CONNECTOR(config, "scsibus:6", scsi_devices, "cdrom", false); NSCSI_CONNECTOR(config, "scsibus:7", scsi_devices, nullptr, false); + + // GIO64 + GIO64(config, m_gio64, m_maincpu, m_hpc3); + GIO64_SLOT(config, m_gio64_gfx, m_gio64, gio64_cards, "xl24"); + GIO64_SLOT(config, m_gio64_exp0, m_gio64, gio64_cards, nullptr); + GIO64_SLOT(config, m_gio64_exp1, m_gio64, gio64_cards, nullptr); } void ip22_state::ip225015(machine_config &config) diff --git a/src/mame/drivers/sun4.cpp b/src/mame/drivers/sun4.cpp index 1b605651042..50d7016544c 100644 --- a/src/mame/drivers/sun4.cpp +++ b/src/mame/drivers/sun4.cpp @@ -414,6 +414,8 @@ #include "bus/rs232/rs232.h" #include "bus/sunkbd/sunkbd.h" #include "bus/sunmouse/sunmouse.h" +#include "bus/sbus/sbus.h" +#include "bus/sbus/bwtwo.h" #include "cpu/sparc/sparc.h" #include "imagedev/floppy.h" #include "machine/am79c90.h" @@ -539,6 +541,8 @@ public: , m_lance(*this, LANCE_TAG) , m_scsibus(*this, "scsibus") , m_scsi(*this, "scsibus:7:ncr53c90a") + , m_sbus(*this, "sbus") + , m_sbus_slot(*this, "slot%u", 1U) , m_type0space(*this, "type0") , m_type1space(*this, "type1") , m_ram(*this, RAM_TAG) @@ -654,6 +658,7 @@ private: void type0space_map(address_map &map); void type1space_map(address_map &map); + void type1space_sbus_map(address_map &map); void type1space_s4_map(address_map &map); enum sun4_arch @@ -676,6 +681,8 @@ private: required_device m_scsibus; required_device m_scsi; + optional_device m_sbus; + optional_device_array m_sbus_slot; optional_device m_type0space; optional_device m_type1space; memory_access_cache<2, 0, ENDIANNESS_BIG> *m_type1_cache; @@ -1152,6 +1159,12 @@ void sun4_state::type1space_map(address_map &map) map(0x08c00000, 0x08c00003).rw(m_lance, FUNC(am79c90_device::regs_r), FUNC(am79c90_device::regs_w)); } +void sun4_state::type1space_sbus_map(address_map &map) +{ + type1space_map(map); + map(0x0a000000, 0x0fffffff).rw(m_sbus, FUNC(sbus_device::read), FUNC(sbus_device::write)); +} + void sun4_state::type1space_s4_map(address_map &map) { map(0x00000000, 0x0000000f).rw(m_scc1, FUNC(z80scc_device::ba_cd_inv_r), FUNC(z80scc_device::ba_cd_inv_w)).umask32(0xff00ff00); @@ -1949,7 +1962,7 @@ void sun4_state::sun4c(machine_config &config) ADDRESS_MAP_BANK(config, m_type0space).set_map(&sun4_state::type0space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000); // MMU Type 1 device space - ADDRESS_MAP_BANK(config, m_type1space).set_map(&sun4_state::type1space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000); + ADDRESS_MAP_BANK(config, m_type1space).set_map(&sun4_state::type1space_sbus_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000); // Ethernet AM79C90(config, m_lance); @@ -2001,6 +2014,12 @@ void sun4_state::sun4c(machine_config &config) NSCSI_CONNECTOR(config, "scsibus:5", sun_scsi_devices, nullptr); NSCSI_CONNECTOR(config, "scsibus:6", sun_scsi_devices, nullptr); NSCSI_CONNECTOR(config, "scsibus:7", sun_scsi_devices, "ncr53c90a", true).set_option_machine_config("ncr53c90a", [this] (device_t *device) { ncr53c90a(device); }); + + // SBus + SBUS(config, m_sbus, 20'000'000, "maincpu", "type1"); + SBUS_SLOT(config, m_sbus_slot[0], 20'000'000, m_sbus, sbus_cards, nullptr); + SBUS_SLOT(config, m_sbus_slot[1], 20'000'000, m_sbus, sbus_cards, nullptr); + SBUS_SLOT(config, m_sbus_slot[2], 20'000'000, m_sbus, sbus_cards, nullptr); } void sun4_state::sun4_20(machine_config &config) @@ -2008,6 +2027,11 @@ void sun4_state::sun4_20(machine_config &config) sun4c(config); m_ram->set_extra_options("4M,8M,12M,16M"); + + m_sbus_slot[0]->set_fixed(true); + m_sbus_slot[1]->set_fixed(true); + m_sbus_slot[2]->set_default_option("bwtwo"); + m_sbus_slot[2]->set_fixed(true); } void sun4_state::sun4_40(machine_config &config) @@ -2018,6 +2042,13 @@ void sun4_state::sun4_40(machine_config &config) m_mmu->set_clock(25'000'000); m_maincpu->set_clock(25'000'000); + + m_sbus->set_clock(25'000'000); + m_sbus_slot[0]->set_clock(25'000'000); + m_sbus_slot[1]->set_clock(25'000'000); + m_sbus_slot[2]->set_clock(25'000'000); + m_sbus_slot[2]->set_default_option("bwtwo"); + m_sbus_slot[2]->set_fixed(true); } void sun4_state::sun4_50(machine_config &config) @@ -2029,6 +2060,13 @@ void sun4_state::sun4_50(machine_config &config) m_mmu->set_clock(40'000'000); m_maincpu->set_clock(40'000'000); + + m_sbus->set_clock(20'000'000); + m_sbus_slot[0]->set_clock(20'000'000); + m_sbus_slot[1]->set_clock(20'000'000); + m_sbus_slot[2]->set_clock(20'000'000); + m_sbus_slot[2]->set_default_option("turbogx"); // not accurate, should be gxp, not turbogx + m_sbus_slot[2]->set_fixed(true); } void sun4_state::sun4_60(machine_config &config) @@ -2042,6 +2080,12 @@ void sun4_state::sun4_65(machine_config &config) m_mmu->set_clock(25'000'000); m_maincpu->set_clock(25'000'000); + + m_sbus->set_clock(25'000'000); + m_sbus_slot[0]->set_clock(25'000'000); + m_sbus_slot[1]->set_clock(25'000'000); + m_sbus_slot[2]->set_clock(25'000'000); + m_sbus_slot[2]->set_default_option("bwtwo"); } void sun4_state::sun4_75(machine_config &config)