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https://github.com/holub/mame
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-iris3130: Renamed from sgi_ip2 to iris3130, converted to logmacro, added preliminary MMU support, added ROM board support. [Ryan Holtz]
This commit is contained in:
mooglyguy
MooglyGuy
parent
705cb6f011
commit
855a46c020
@ -2,21 +2,19 @@
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// copyright-holders:Ryan Holtz
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/****************************************************************************
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drivers/sgi_ip2.cpp
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SGI IRIS 3130 skeleton driver with some meat on its bones
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by Ryan Holtz
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SGI IRIS 3130 skeleton driver
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0x00000000 - ? RAM (?)
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0x30000000 - 0x30017fff ROM (3x32k)
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0x30800000 - 0x30800000 Mouse Buttons (1)
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0x31000000 - 0x31000001 Mouse Quadrature (2)
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0x31800000 - 0x31800001 DIP Switches
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0x32000000 - 0x3200000f DUART0 (serial console on channel B at 19200 baud 8N1, channel A set to 600 baud 8N1 (mouse?))
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0x32800000 - 0x3280000f DUART1 (printer/modem?)
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0x33000000 - 0x330007ff SRAM (2k)
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0x34000000 - 0x34000000 Clock Control (1)
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0x35000000 - 0x35000000 Clock Data (1)
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0x36000000 - 0x36000000 OS Base (1)
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0x36000000 - 0x36000000 Kernel Base (1)
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0x38000000 - 0x38000001 Status Register (2)
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0x39000000 - 0x39000000 Parity control (1)
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0x3a000000 - 0x3a000000 Multibus Protection (1)
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@ -27,10 +25,7 @@
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0x3f000000 - 0x3f000001 Stack Limit (2)
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TODO:
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Hook up keyboard
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Hook up mouse
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Hook up graphics
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Hook up mass storage
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Most everything
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Interrupts:
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M68K:
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@ -39,376 +34,563 @@
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****************************************************************************/
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#include "emu.h"
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#include "imagedev/snapquik.h"
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#include "bus/rs232/rs232.h"
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#include "cpu/m68000/m68000.h"
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#include "machine/mc146818.h" /* TOD clock */
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#include "machine/mc68681.h" /* DUART0, DUART1 */
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#include "machine/bankdev.h"
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#include "machine/mc146818.h"
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#include "machine/mc68681.h"
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#include <vector>
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class sgi_ip2_state : public driver_device
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#define LOG_RTC (1 << 0)
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#define LOG_INVALID_SEGMENT (1 << 1)
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#define LOG_OTHER (1 << 2)
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#define VERBOSE (LOG_OTHER)
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#include "logmacro.h"
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class iris3000_state : public driver_device
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{
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public:
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sgi_ip2_state(const machine_config &mconfig, device_type type, const char *tag)
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iris3000_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_mainram(*this, "mainram"),
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m_duarta(*this, "duart68681a"),
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m_duartb(*this, "duart68681b"),
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m_bss(*this, "bss"),
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m_ptmap(*this, "ptmap"),
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m_rtc(*this, "rtc")
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m_text_data_space(*this, "text_data"),
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m_stack_space(*this, "stack"),
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m_kernel_space(*this, "kernel"),
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m_system_space(*this, "system"),
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m_multibus_mem_space(*this, "multibus_mem"),
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m_multibus_io_space(*this, "multibus_io"),
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m_geometry_pipe_space(*this, "geometry_pipe"),
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m_fpa_space(*this, "fpa"),
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m_page_table_map(*this, "ptmap"),
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m_rtc(*this, "rtc"),
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m_dips(*this, "DIPS")
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{
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}
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void sgi_ip2(machine_config &config);
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void iris3130(machine_config &config);
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void init_sgi_ip2();
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DECLARE_QUICKLOAD_LOAD_MEMBER(load_romboard);
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private:
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DECLARE_READ8_MEMBER(sgi_ip2_m_but_r);
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DECLARE_WRITE8_MEMBER(sgi_ip2_m_but_w);
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DECLARE_READ16_MEMBER(sgi_ip2_m_quad_r);
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DECLARE_WRITE16_MEMBER(sgi_ip2_m_quad_w);
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DECLARE_READ16_MEMBER(sgi_ip2_swtch_r);
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DECLARE_READ8_MEMBER(sgi_ip2_clock_ctl_r);
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DECLARE_WRITE8_MEMBER(sgi_ip2_clock_ctl_w);
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DECLARE_READ8_MEMBER(sgi_ip2_clock_data_r);
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DECLARE_WRITE8_MEMBER(sgi_ip2_clock_data_w);
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DECLARE_READ8_MEMBER(sgi_ip2_os_base_r);
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DECLARE_WRITE8_MEMBER(sgi_ip2_os_base_w);
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DECLARE_READ16_MEMBER(sgi_ip2_status_r);
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DECLARE_WRITE16_MEMBER(sgi_ip2_status_w);
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DECLARE_READ8_MEMBER(sgi_ip2_parctl_r);
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DECLARE_WRITE8_MEMBER(sgi_ip2_parctl_w);
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DECLARE_READ8_MEMBER(sgi_ip2_mbp_r);
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DECLARE_WRITE8_MEMBER(sgi_ip2_mbp_w);
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DECLARE_READ32_MEMBER(sgi_ip2_ptmap_r);
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DECLARE_WRITE32_MEMBER(sgi_ip2_ptmap_w);
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DECLARE_READ16_MEMBER(sgi_ip2_tdbase_r);
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DECLARE_WRITE16_MEMBER(sgi_ip2_tdbase_w);
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DECLARE_READ16_MEMBER(sgi_ip2_tdlmt_r);
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DECLARE_WRITE16_MEMBER(sgi_ip2_tdlmt_w);
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DECLARE_READ16_MEMBER(sgi_ip2_stkbase_r);
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DECLARE_WRITE16_MEMBER(sgi_ip2_stkbase_w);
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DECLARE_READ16_MEMBER(sgi_ip2_stklmt_r);
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DECLARE_WRITE16_MEMBER(sgi_ip2_stklmt_w);
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virtual void machine_start() override;
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virtual void machine_reset() override;
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void text_data_map(address_map &map);
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void stack_map(address_map &map);
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void kernel_map(address_map &map);
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void system_map(address_map &map);
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void multibus_mem_map(address_map &map);
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void multibus_io_map(address_map &map);
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void geometry_pipe_map(address_map &map);
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void fpa_map(address_map &map);
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DECLARE_READ32_MEMBER(mmu_r);
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DECLARE_WRITE32_MEMBER(mmu_w);
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DECLARE_READ8_MEMBER(mouse_buttons_r);
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DECLARE_WRITE8_MEMBER(mouse_buttons_w);
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DECLARE_READ16_MEMBER(mouse_quad_r);
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DECLARE_WRITE16_MEMBER(mouse_quad_w);
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DECLARE_READ16_MEMBER(dips_r);
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DECLARE_READ8_MEMBER(clock_ctrl_r);
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DECLARE_WRITE8_MEMBER(clock_ctrl_w);
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DECLARE_READ8_MEMBER(clock_data_r);
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DECLARE_WRITE8_MEMBER(clock_data_w);
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DECLARE_READ8_MEMBER(kernel_base_r);
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DECLARE_WRITE8_MEMBER(kernel_base_w);
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DECLARE_READ16_MEMBER(status_r);
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DECLARE_WRITE16_MEMBER(status_w);
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DECLARE_READ8_MEMBER(parity_ctrl_r);
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DECLARE_WRITE8_MEMBER(parity_ctrl_w);
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DECLARE_READ8_MEMBER(multibus_prot_r);
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DECLARE_WRITE8_MEMBER(multibus_prot_w);
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DECLARE_READ32_MEMBER(page_table_map_r);
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DECLARE_WRITE32_MEMBER(page_table_map_w);
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DECLARE_READ16_MEMBER(text_data_base_r);
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DECLARE_WRITE16_MEMBER(text_data_base_w);
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DECLARE_READ16_MEMBER(text_data_limit_r);
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DECLARE_WRITE16_MEMBER(text_data_limit_w);
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DECLARE_READ16_MEMBER(stack_base_r);
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DECLARE_WRITE16_MEMBER(stack_base_w);
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DECLARE_READ16_MEMBER(stack_limit_r);
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DECLARE_WRITE16_MEMBER(stack_limit_w);
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DECLARE_READ8_MEMBER(romboard_r);
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DECLARE_WRITE8_MEMBER(romboard_w);
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DECLARE_WRITE_LINE_MEMBER(duarta_irq_handler);
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DECLARE_WRITE_LINE_MEMBER(duartb_irq_handler);
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required_device<cpu_device> m_maincpu;
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void sgi_ip2_map(address_map &map);
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void mem_map(address_map &map);
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required_device<m68020_device> m_maincpu;
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required_shared_ptr<uint32_t> m_mainram;
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required_device<mc68681_device> m_duarta;
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required_device<mc68681_device> m_duartb;
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required_shared_ptr<uint32_t> m_bss;
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required_shared_ptr<uint32_t> m_ptmap;
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required_device<mc146818_device> m_rtc;
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uint8_t m_mbut;
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uint16_t m_mquad;
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uint16_t m_tdbase;
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uint16_t m_tdlmt;
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uint16_t m_stkbase;
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uint16_t m_stklmt;
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uint8_t m_parctl;
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uint8_t m_mbp;
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virtual void machine_start() override;
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virtual void machine_reset() override;
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inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ... );
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required_device<address_map_bank_device> m_text_data_space;
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required_device<address_map_bank_device> m_stack_space;
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required_device<address_map_bank_device> m_kernel_space;
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required_device<address_map_bank_device> m_system_space;
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required_device<address_map_bank_device> m_multibus_mem_space;
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required_device<address_map_bank_device> m_multibus_io_space;
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required_device<address_map_bank_device> m_geometry_pipe_space;
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required_device<address_map_bank_device> m_fpa_space;
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required_shared_ptr<uint32_t> m_page_table_map;
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required_device<mc146818_device> m_rtc;
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required_ioport m_dips;
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enum
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{
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MOUSE_BUTTON_RIGHT = 0x01,
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MOUSE_BUTTON_MIDDLE = 0x02,
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MOUSE_BUTTON_LEFT = 0x04,
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BOARD_REV1 = 0x60, /* Board revision - #1 */
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BOARD_REV2 = 0x50, /* Board revision - #2 */
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MOUSE_XFIRE = 0x01, /* X Quadrature Fired, active low */
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MOUSE_XCHANGE = 0x02, /* MOUSE_XCHANGE ? x-- : x++ */
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MOUSE_YFIRE = 0x04, /* Y Quadrature Fired, active low */
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MOUSE_YCHANGE = 0x08, /* MOUSE_YCHANGE ? y-- : y++ */
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PAR_UR = 0x01, /* Check parity on user-mode reads */
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PAR_UW = 0x02, /* Check parity on user-mode writes */
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PAR_KR = 0x04, /* Check parity on kernel-mode reads */
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PAR_KW = 0x08, /* Check parity on kernel-mode writes */
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PAR_DIS0 = 0x10, /* Disable access to DUART0 and LEDs */
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PAR_DIS1 = 0x20, /* Disable access to DUART1 */
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PAR_MBR = 0x40, /* Check parity on multibus reads */
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PAR_MBW = 0x80, /* Check parity on multibus writes */
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MBP_DCACC = 0x01, /* Display controller access (I/O page 4) */
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MBP_UCACC = 0x02, /* Update controller access (I/O page 3) */
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MBP_GFACC = 0x04, /* Allow GF access (I/O page 1) */
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MBP_DMACC = 0x08, /* Allow GL2 DMA access (0x8nnnnn - x0bnnnnn) */
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MBP_LIOACC = 0x10, /* Allow lower I/O access (0x0nnnnn - 0x7nnnnn) */
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MBP_HIOACC = 0x20, /* Allow upper I/O access (0x8nnnnn - 0xfnnnnn) */
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MBP_LMACC = 0x40, /* Allow lower memory access (0x0nnnnn - 0x7nnnnn) */
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MBP_HMACC = 0x80, /* Allow upper memory access (0x8nnnnn - 0xfnnnnn) */
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STATUS_DIAG0 = 0,
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STATUS_DIAG1 = 1,
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STATUS_DIAG2 = 2,
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STATUS_DIAG3 = 3,
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STATUS_ENABEXT = 4,
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STATUS_ENABINT = 5,
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STATUS_BINIT = 6,
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STATUS_NOTBOOT = 7,
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STATUS_USERFPA = 8,
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STATUS_USERGE = 9,
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STATUS_SLAVE = 10,
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STATUS_ENABCBRQ = 11,
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STATUS_NOTGEMASTER = 12,
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STATUS_GENBAD = 13,
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STATUS_ENABWDOG = 14,
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STATUS_QUICK_TOUT = 15
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};
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std::vector<uint8_t> m_file_data;
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uint8_t m_mouse_buttons;
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uint16_t m_mouse_quadrature;
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uint16_t m_text_data_base;
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uint16_t m_text_data_limit;
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uint16_t m_stack_base;
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uint16_t m_stack_limit;
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uint16_t m_status;
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uint8_t m_parity_ctrl;
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uint8_t m_multibus_prot;
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};
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#define VERBOSE_LEVEL ( 0 )
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#define ENABLE_VERBOSE_LOG (0)
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inline void ATTR_PRINTF(3,4) sgi_ip2_state::verboselog( int n_level, const char *s_fmt, ... )
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QUICKLOAD_LOAD_MEMBER(iris3000_state::load_romboard)
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{
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#if ENABLE_VERBOSE_LOG
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if( VERBOSE_LEVEL >= n_level )
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m_file_data.resize(quickload_size);
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if (!quickload_size || image.fread(&m_file_data[0], quickload_size) != quickload_size)
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{
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va_list v;
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char buf[ 32768 ];
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va_start( v, s_fmt );
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vsprintf( buf, s_fmt, v );
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va_end( v );
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logerror("%s: %s", machine().describe_context(), buf);
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m_file_data.clear();
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return image_init_result::FAIL;
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}
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#endif
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return image_init_result::PASS;
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}
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/***************************************************************************
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MACHINE FUNCTIONS
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***************************************************************************/
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#define MBUT_RIGHT 0x01 /* Right button */
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#define MBUT_MIDDLE 0x02 /* Middle button */
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#define MBUT_LEFT 0x04 /* Left button */
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#define BOARD_REV1 0x60 /* Board revision - #1 */
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#define BOARD_REV2 0x50 /* Board revision - #2 */
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READ8_MEMBER(sgi_ip2_state::sgi_ip2_m_but_r)
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READ32_MEMBER(iris3000_state::mmu_r)
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{
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verboselog(0, "sgi_ip2_m_but_r: %02x\n", m_mbut | BOARD_REV1);
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return m_mbut | BOARD_REV1;
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}
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const uint8_t type = (offset >> 26) & 0xf;
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const uint32_t vaddr = offset & 0x03ffffff;
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WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_m_but_w)
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{
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verboselog(0, "sgi_ip2_m_but_w: %02x\n", data);
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m_mbut = data;
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}
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const uint32_t page_offset = vaddr & 0x000003ff;
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const uint32_t page_index = (vaddr >> 10) & 0x3fff;
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const uint32_t phys_page = m_page_table_map[page_index] & 0x1fff;
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const uint32_t paddr = (phys_page << 10) | page_offset;
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#define MOUSE_XFIRE 0x01 /* X Quadrature Fired, active low */
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#define MOUSE_XCHANGE 0x02 /* MOUSE_XCHANGE ? x-- : x++ */
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#define MOUSE_YFIRE 0x04 /* Y Quadrature Fired, active low */
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#define MOUSE_YCHANGE 0x08 /* MOUSE_YCHANGE ? y-- : y++ */
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READ16_MEMBER(sgi_ip2_state::sgi_ip2_m_quad_r)
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{
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verboselog(0, "sgi_ip2_m_quad_r: %04x\n", m_mquad);
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return m_mquad;
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}
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WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_m_quad_w)
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{
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verboselog(0, "sgi_ip2_m_quad_w = %04x & %04x\n", data, mem_mask);
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COMBINE_DATA(&m_mquad);
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}
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READ16_MEMBER(sgi_ip2_state::sgi_ip2_swtch_r)
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{
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verboselog(0, "sgi_ip2_swtch_r: %04x\n", ioport("SWTCH")->read());
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return ioport("SWTCH")->read();
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}
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READ8_MEMBER(sgi_ip2_state::sgi_ip2_clock_ctl_r)
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{
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uint8_t ret = m_rtc->read(1);
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verboselog(1, "sgi_ip2_clock_ctl_r: %02x\n", ret);
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uint32_t ret;
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switch (type)
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{
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case 0: // Text/Data Segment
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ret = m_text_data_space->read32(paddr, mem_mask);
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break;
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case 1: // Stack Segment
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ret = m_stack_space->read32(paddr, mem_mask);
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break;
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case 2: // Kernel Segment
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ret = m_kernel_space->read32(paddr, mem_mask);
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break;
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case 3: // System Segment
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ret = m_system_space->read32(vaddr, mem_mask);
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break;
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case 4: // Multibus Memory Segment
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ret = m_multibus_mem_space->read32(vaddr, mem_mask);
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break;
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case 5: // Multibus I/O Segment
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ret = m_multibus_io_space->read32(vaddr, mem_mask);
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break;
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case 6: // Geometry Pipe Segment
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ret = m_geometry_pipe_space->read32(vaddr, mem_mask);
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break;
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case 15: // Floating-Point Accelerator Segment
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ret = m_fpa_space->read32(vaddr, mem_mask);
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break;
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default: // Unused/Unknown Segment
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LOGMASKED(LOG_INVALID_SEGMENT, "%s: Invalid segment read: %08x & %08x\n", machine().describe_context(), offset << 2, mem_mask);
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ret = 0;
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break;
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}
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return ret;
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}
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WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_clock_ctl_w)
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WRITE32_MEMBER(iris3000_state::mmu_w)
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{
|
||||
verboselog(1, "sgi_ip2_clock_ctl_w: %02x\n", data);
|
||||
const uint8_t type = (offset >> 26) & 0xf;
|
||||
const uint32_t vaddr = offset & 0x03ffffff;
|
||||
|
||||
const uint32_t page_offset = vaddr & 0x000003ff;
|
||||
const uint32_t page_index = (vaddr >> 10) & 0x3fff;
|
||||
const uint32_t phys_page = m_page_table_map[page_index] & 0x1fff;
|
||||
const uint32_t paddr = (phys_page << 10) | page_offset;
|
||||
|
||||
switch (type)
|
||||
{
|
||||
case 0: // Text/Data Segment
|
||||
m_text_data_space->write32(paddr, data, mem_mask);
|
||||
break;
|
||||
case 1: // Stack Segment
|
||||
m_stack_space->write32(paddr, data, mem_mask);
|
||||
break;
|
||||
case 2: // Kernel Segment
|
||||
m_kernel_space->write32(paddr, data, mem_mask);
|
||||
break;
|
||||
case 3: // System Segment
|
||||
m_system_space->write32(vaddr, data, mem_mask);
|
||||
break;
|
||||
case 4: // Multibus Memory Segment
|
||||
m_multibus_mem_space->write32(vaddr, data, mem_mask);
|
||||
break;
|
||||
case 5: // Multibus I/O Segment
|
||||
m_multibus_io_space->write32(vaddr, data, mem_mask);
|
||||
break;
|
||||
case 6: // Geometry Pipe Segment
|
||||
m_geometry_pipe_space->write32(vaddr, data, mem_mask);
|
||||
break;
|
||||
case 15: // Floating-Point Accelerator Segment
|
||||
m_fpa_space->write32(vaddr, data, mem_mask);
|
||||
break;
|
||||
default: // Unused/Unknown Segment
|
||||
LOGMASKED(LOG_INVALID_SEGMENT, "%s: Invalid segment write: %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(iris3000_state::mouse_buttons_r)
|
||||
{
|
||||
LOGMASKED(LOG_OTHER, "%s: mouse_buttons_r: %02x\n", machine().describe_context(), m_mouse_buttons | BOARD_REV1);
|
||||
return m_mouse_buttons | BOARD_REV1;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(iris3000_state::mouse_buttons_w)
|
||||
{
|
||||
LOGMASKED(LOG_OTHER, "%s: mouse_buttons_w (ignored): %02x\n", machine().describe_context(), data);
|
||||
}
|
||||
|
||||
READ16_MEMBER(iris3000_state::mouse_quad_r)
|
||||
{
|
||||
LOGMASKED(LOG_OTHER, "%s: mouse_quad_r: %04x & %04x\n", machine().describe_context(), m_mouse_quadrature, mem_mask);
|
||||
return m_mouse_quadrature;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(iris3000_state::mouse_quad_w)
|
||||
{
|
||||
LOGMASKED(LOG_OTHER, "%s: mouse_quad_w (ignored): %04x & %04x\n", machine().describe_context(), data, mem_mask);
|
||||
}
|
||||
|
||||
READ16_MEMBER(iris3000_state::dips_r)
|
||||
{
|
||||
const uint16_t data = m_dips->read();
|
||||
LOGMASKED(LOG_OTHER, "%s: dips_r: %04x & %04x\n", machine().describe_context(), data, mem_mask);
|
||||
return data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(iris3000_state::clock_ctrl_r)
|
||||
{
|
||||
const uint8_t data = m_rtc->read(1);
|
||||
LOGMASKED(LOG_RTC, "%s: clock_ctrl_r: %02x\n", machine().describe_context(), data);
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(iris3000_state::clock_ctrl_w)
|
||||
{
|
||||
LOGMASKED(LOG_RTC, "%s: clock_ctrl_w: %02x\n", machine().describe_context(), data);
|
||||
m_rtc->write(1, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(sgi_ip2_state::sgi_ip2_clock_data_r)
|
||||
READ8_MEMBER(iris3000_state::clock_data_r)
|
||||
{
|
||||
uint8_t ret = m_rtc->read(0);
|
||||
verboselog(1, "sgi_ip2_clock_data_r: %02x\n", ret);
|
||||
return ret;
|
||||
uint8_t data = m_rtc->read(0);
|
||||
LOGMASKED(LOG_RTC, "%s: clock_data_r: %02x\n", machine().describe_context(), data);
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_clock_data_w)
|
||||
WRITE8_MEMBER(iris3000_state::clock_data_w)
|
||||
{
|
||||
verboselog(1, "sgi_ip2_clock_data_w: %02x\n", data);
|
||||
LOGMASKED(LOG_RTC, "%s: clock_data_w: %02x\n", machine().describe_context(), data);
|
||||
m_rtc->write(0, data);
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER(sgi_ip2_state::sgi_ip2_os_base_r)
|
||||
READ8_MEMBER(iris3000_state::kernel_base_r)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
default:
|
||||
verboselog(0, "sgi_ip2_os_base_r: Unknown Register %08x\n", 0x36000000 + offset);
|
||||
LOGMASKED(LOG_OTHER, "%s: kernel_base_r: Unknown Register %08x\n", machine().describe_context(), 0x36000000 + offset);
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_os_base_w)
|
||||
WRITE8_MEMBER(iris3000_state::kernel_base_w)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
default:
|
||||
verboselog(0, "sgi_ip2_os_base_w: Unknown Register %08x = %02x\n", 0x36000000 + offset, data);
|
||||
LOGMASKED(LOG_OTHER, "%s: kernel_base_w: Unknown Register %08x = %02x\n", machine().describe_context(), 0x36000000 + offset, data);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(sgi_ip2_state::sgi_ip2_status_r)
|
||||
READ16_MEMBER(iris3000_state::status_r)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
default:
|
||||
verboselog(0, "sgi_ip2_status_r: Unknown Register %08x & %04x\n", 0x38000000 + (offset << 1), mem_mask);
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
LOGMASKED(LOG_OTHER, "%s: status_r: %04x & %04x\n", machine().describe_context(), m_status, mem_mask);
|
||||
return m_status;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_status_w)
|
||||
WRITE16_MEMBER(iris3000_state::status_w)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
default:
|
||||
verboselog(0, "sgi_ip2_status_w: Unknown Register %08x = %04x & %04x\n", 0x38000000 + (offset << 1), data, mem_mask);
|
||||
break;
|
||||
}
|
||||
LOGMASKED(LOG_OTHER, "%s: status_w: %04x & %04x (DIAG:%x, ENABEXT:%d, ENABINT:%d, BINIT:%d, NOTBOOT:%d)\n", machine().describe_context(), data, mem_mask,
|
||||
data & 0xf, BIT(data, STATUS_ENABEXT), BIT(data, STATUS_ENABINT), BIT(data, STATUS_BINIT), BIT(data, STATUS_NOTBOOT));
|
||||
LOGMASKED(LOG_OTHER, "%s: (USERFPA:%d, USERGE:%d, SLAVE:%d, ENABCBRQ:%d)\n", machine().describe_context(),
|
||||
BIT(data, STATUS_USERFPA), BIT(data, STATUS_USERGE), BIT(data, STATUS_SLAVE), BIT(data, STATUS_ENABCBRQ));
|
||||
LOGMASKED(LOG_OTHER, "%s: (NOTGEMASTER:%d, GENBAD:%d, ENABWDOG:%d, QUICK_TOUT:%d)\n", machine().describe_context(),
|
||||
BIT(data, STATUS_NOTGEMASTER), BIT(data, STATUS_GENBAD), BIT(data, STATUS_ENABWDOG), BIT(data, STATUS_QUICK_TOUT));
|
||||
COMBINE_DATA(&m_status);
|
||||
}
|
||||
|
||||
#define PAR_UR 0x01 /* Check parity on user-mode reads */
|
||||
#define PAR_UW 0x02 /* Check parity on user-mode writes */
|
||||
#define PAR_KR 0x04 /* Check parity on kernel-mode reads */
|
||||
#define PAR_KW 0x08 /* Check parity on kernel-mode writes */
|
||||
#define PAR_DIS0 0x10 /* Disable access to DUART0 and LEDs */
|
||||
#define PAR_DIS1 0x20 /* Disable access to DUART1 */
|
||||
#define PAR_MBR 0x40 /* Check parity on multibus reads */
|
||||
#define PAR_MBW 0x80 /* Check parity on multibus writes */
|
||||
|
||||
|
||||
READ8_MEMBER(sgi_ip2_state::sgi_ip2_parctl_r)
|
||||
READ8_MEMBER(iris3000_state::parity_ctrl_r)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_parctl_r: %02x\n", m_parctl);
|
||||
return m_parctl;
|
||||
LOGMASKED(LOG_OTHER, "%s: parity_ctrl_r: %02x\n", m_parity_ctrl);
|
||||
return m_parity_ctrl;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_parctl_w)
|
||||
WRITE8_MEMBER(iris3000_state::parity_ctrl_w)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_parctl_w: %02x\n", data);
|
||||
m_parctl = data;
|
||||
LOGMASKED(LOG_OTHER, "%s: parity_ctrl_w: %02x\n", machine().describe_context(), data);
|
||||
m_parity_ctrl = data;
|
||||
}
|
||||
|
||||
#define MBP_DCACC 0x01 /* Display controller access (I/O page 4) */
|
||||
#define MBP_UCACC 0x02 /* Update controller access (I/O page 3) */
|
||||
#define MBP_GFACC 0x04 /* Allow GF access (I/O page 1) */
|
||||
#define MBP_DMACC 0x08 /* Allow GL2 DMA access (0x8nnnnn - x0bnnnnn) */
|
||||
#define MBP_LIOACC 0x10 /* Allow lower I/O access (0x0nnnnn - 0x7nnnnn) */
|
||||
#define MBP_HIOACC 0x20 /* Allow upper I/O access (0x8nnnnn - 0xfnnnnn) */
|
||||
#define MBP_LMACC 0x40 /* Allow lower memory access (0x0nnnnn - 0x7nnnnn) */
|
||||
#define MBP_HMACC 0x80 /* Allow upper memory access (0x8nnnnn - 0xfnnnnn) */
|
||||
|
||||
|
||||
READ8_MEMBER(sgi_ip2_state::sgi_ip2_mbp_r)
|
||||
READ8_MEMBER(iris3000_state::multibus_prot_r)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_mbp_r: %02x\n", m_mbp);
|
||||
return m_mbp;
|
||||
LOGMASKED(LOG_OTHER, "%s: multibus_prot_r: %02x\n", machine().describe_context(), m_multibus_prot);
|
||||
return m_multibus_prot;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(sgi_ip2_state::sgi_ip2_mbp_w)
|
||||
WRITE8_MEMBER(iris3000_state::multibus_prot_w)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_mbp_w: %02x\n", data);
|
||||
m_mbp = data;
|
||||
LOGMASKED(LOG_OTHER, "%s: multibus_prot_w: %02x\n", machine().describe_context(), data);
|
||||
m_multibus_prot = data;
|
||||
}
|
||||
|
||||
READ32_MEMBER(iris3000_state::page_table_map_r)
|
||||
{
|
||||
LOGMASKED(LOG_OTHER, "%s: page_table_map_r: %08x = %08x & %08x\n", machine().describe_context(), 0x3b000000 + (offset << 2), m_page_table_map[offset], mem_mask);
|
||||
return m_page_table_map[offset];
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(iris3000_state::page_table_map_w)
|
||||
{
|
||||
LOGMASKED(LOG_OTHER, "%s: page_table_map_w: %08x = %08x & %08x\n", machine().describe_context(), 0x3b000000 + (offset << 2), data, mem_mask);
|
||||
COMBINE_DATA(&m_page_table_map[offset]);
|
||||
}
|
||||
|
||||
READ16_MEMBER(iris3000_state::text_data_base_r)
|
||||
{
|
||||
LOGMASKED(LOG_OTHER, "%s: text_data_base_r: %04x & %04x\n", machine().describe_context(), m_text_data_base, mem_mask);
|
||||
return m_text_data_base;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(iris3000_state::text_data_base_w)
|
||||
{
|
||||
LOGMASKED(LOG_OTHER, "%s: text_data_base_w: %04x & %04x\n", machine().describe_context(), data, mem_mask);
|
||||
COMBINE_DATA(&m_text_data_base);
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(sgi_ip2_state::sgi_ip2_ptmap_r)
|
||||
READ16_MEMBER(iris3000_state::text_data_limit_r)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_ptmap_r: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), m_ptmap[offset], mem_mask);
|
||||
return m_ptmap[offset];
|
||||
LOGMASKED(LOG_OTHER, "%s: text_data_limit_r: %04x & %04x\n", machine().describe_context(), m_text_data_limit, mem_mask);
|
||||
return m_text_data_limit;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(sgi_ip2_state::sgi_ip2_ptmap_w)
|
||||
WRITE16_MEMBER(iris3000_state::text_data_limit_w)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_ptmap_w: %08x = %08x & %08x\n", 0x3b000000 + (offset << 2), data, mem_mask);
|
||||
COMBINE_DATA(&m_ptmap[offset]);
|
||||
LOGMASKED(LOG_OTHER, "%s: text_data_limit_w: %04x & %04x\n", machine().describe_context(), data, mem_mask);
|
||||
COMBINE_DATA(&m_text_data_limit);
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(sgi_ip2_state::sgi_ip2_tdbase_r)
|
||||
READ16_MEMBER(iris3000_state::stack_base_r)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_tdbase_r: %04x\n", m_tdbase);
|
||||
return m_tdbase;
|
||||
LOGMASKED(LOG_OTHER, "%s: stack_base_r: %04x & %04x\n", machine().describe_context(), m_stack_base, mem_mask);
|
||||
return m_stack_base;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_tdbase_w)
|
||||
WRITE16_MEMBER(iris3000_state::stack_base_w)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_tdbase_w: %04x & %04x\n", data, mem_mask);
|
||||
COMBINE_DATA(&m_tdbase);
|
||||
LOGMASKED(LOG_OTHER, "%s: stack_base_w: %04x & %04x\n", machine().describe_context(), data, mem_mask);
|
||||
COMBINE_DATA(&m_stack_base);
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(sgi_ip2_state::sgi_ip2_tdlmt_r)
|
||||
READ16_MEMBER(iris3000_state::stack_limit_r)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_tdlmt_r: %04x\n", m_tdlmt);
|
||||
return m_tdlmt;
|
||||
LOGMASKED(LOG_OTHER, "%s: stack_limit_r: %04x & %04x\n", machine().describe_context(), m_stack_limit, mem_mask);
|
||||
return m_stack_limit;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_tdlmt_w)
|
||||
WRITE16_MEMBER(iris3000_state::stack_limit_w)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_tdlmt_w: %04x & %04x\n", data, mem_mask);
|
||||
COMBINE_DATA(&m_tdlmt);
|
||||
LOGMASKED(LOG_OTHER, "%s: stack_limit_w: %04x & %04x\n", machine().describe_context(), data, mem_mask);
|
||||
COMBINE_DATA(&m_stack_limit);
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(sgi_ip2_state::sgi_ip2_stkbase_r)
|
||||
READ8_MEMBER(iris3000_state::romboard_r)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_stkbase_r: %04x\n", m_stkbase);
|
||||
return m_stkbase;
|
||||
const uint8_t data = offset < m_file_data.size() ? m_file_data[offset] : 0;
|
||||
LOGMASKED(LOG_OTHER, "%s: romboard_r: %08x = %02x\n", machine().describe_context(), 0x40000000 + offset, data);
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_stkbase_w)
|
||||
WRITE8_MEMBER(iris3000_state::romboard_w)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_stkbase_w: %04x & %04x\n", data, mem_mask);
|
||||
COMBINE_DATA(&m_stkbase);
|
||||
if (offset > m_file_data.size())
|
||||
m_file_data.resize(offset + 1);
|
||||
m_file_data[offset] = data;
|
||||
LOGMASKED(LOG_OTHER, "%s: romboard write: %08x = %02x\n", machine().describe_context(), 0x40000000 + offset, data);
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(sgi_ip2_state::sgi_ip2_stklmt_r)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_stklmt_r: %04x\n", m_stklmt);
|
||||
return m_stklmt;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(sgi_ip2_state::sgi_ip2_stklmt_w)
|
||||
{
|
||||
verboselog(0, "sgi_ip2_stklmt_w: %04x & %04x\n", data, mem_mask);
|
||||
COMBINE_DATA(&m_stklmt);
|
||||
}
|
||||
|
||||
void sgi_ip2_state::machine_start()
|
||||
void iris3000_state::machine_start()
|
||||
{
|
||||
}
|
||||
|
||||
void sgi_ip2_state::machine_reset()
|
||||
void iris3000_state::machine_reset()
|
||||
{
|
||||
uint32_t *src = (uint32_t*)(memregion("maincpu")->base());
|
||||
uint32_t *dst = m_mainram;
|
||||
memcpy(dst, src, 8);
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
ADDRESS MAPS
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
void sgi_ip2_state::sgi_ip2_map(address_map &map)
|
||||
void iris3000_state::text_data_map(address_map &map)
|
||||
{
|
||||
map(0x00000000, 0x00ffffff).ram().share("mainram");
|
||||
map(0x02100000, 0x0210ffff).ram().share("bss"); // ??? I don't understand the need for this...
|
||||
map(0x30000000, 0x30017fff).rom().region("maincpu", 0);
|
||||
map(0x30800000, 0x30800003).rw(FUNC(sgi_ip2_state::sgi_ip2_m_but_r), FUNC(sgi_ip2_state::sgi_ip2_m_but_w));
|
||||
map(0x31000000, 0x31000003).rw(FUNC(sgi_ip2_state::sgi_ip2_m_quad_r), FUNC(sgi_ip2_state::sgi_ip2_m_quad_w));
|
||||
map(0x31800000, 0x31800003).r(FUNC(sgi_ip2_state::sgi_ip2_swtch_r));
|
||||
map(0x32000000, 0x3200000f).rw(m_duarta, FUNC(mc68681_device::read), FUNC(mc68681_device::write));
|
||||
map(0x32800000, 0x3280000f).rw(m_duartb, FUNC(mc68681_device::read), FUNC(mc68681_device::write));
|
||||
map(0x33000000, 0x330007ff).ram();
|
||||
map(0x34000000, 0x34000003).rw(FUNC(sgi_ip2_state::sgi_ip2_clock_ctl_r), FUNC(sgi_ip2_state::sgi_ip2_clock_ctl_w));
|
||||
map(0x35000000, 0x35000003).rw(FUNC(sgi_ip2_state::sgi_ip2_clock_data_r), FUNC(sgi_ip2_state::sgi_ip2_clock_data_w));
|
||||
map(0x36000000, 0x36000003).rw(FUNC(sgi_ip2_state::sgi_ip2_os_base_r), FUNC(sgi_ip2_state::sgi_ip2_os_base_w));
|
||||
map(0x38000000, 0x38000003).rw(FUNC(sgi_ip2_state::sgi_ip2_status_r), FUNC(sgi_ip2_state::sgi_ip2_status_w));
|
||||
map(0x39000000, 0x39000003).rw(FUNC(sgi_ip2_state::sgi_ip2_parctl_r), FUNC(sgi_ip2_state::sgi_ip2_parctl_w));
|
||||
map(0x3a000000, 0x3a000003).rw(FUNC(sgi_ip2_state::sgi_ip2_mbp_r), FUNC(sgi_ip2_state::sgi_ip2_mbp_w));
|
||||
map(0x3b000000, 0x3b003fff).rw(FUNC(sgi_ip2_state::sgi_ip2_ptmap_r), FUNC(sgi_ip2_state::sgi_ip2_ptmap_w)).share("ptmap");
|
||||
map(0x3c000000, 0x3c000003).rw(FUNC(sgi_ip2_state::sgi_ip2_tdbase_r), FUNC(sgi_ip2_state::sgi_ip2_tdbase_w));
|
||||
map(0x3d000000, 0x3d000003).rw(FUNC(sgi_ip2_state::sgi_ip2_tdlmt_r), FUNC(sgi_ip2_state::sgi_ip2_tdlmt_w));
|
||||
map(0x3e000000, 0x3e000003).rw(FUNC(sgi_ip2_state::sgi_ip2_stkbase_r), FUNC(sgi_ip2_state::sgi_ip2_stkbase_w));
|
||||
map(0x3f000000, 0x3f000003).rw(FUNC(sgi_ip2_state::sgi_ip2_stklmt_r), FUNC(sgi_ip2_state::sgi_ip2_stklmt_w));
|
||||
map(0x0000000, 0x03fffff).ram().share("mainram");
|
||||
}
|
||||
|
||||
void iris3000_state::stack_map(address_map &map)
|
||||
{
|
||||
map(0x0000000, 0x03fffff).ram().share("mainram");
|
||||
}
|
||||
|
||||
void iris3000_state::kernel_map(address_map &map)
|
||||
{
|
||||
map(0x0000000, 0x03fffff).ram().share("mainram");
|
||||
}
|
||||
|
||||
void iris3000_state::system_map(address_map &map)
|
||||
{
|
||||
map(0x0000000, 0x0017fff).rom().region("maincpu", 0);
|
||||
map(0x0800000, 0x0800003).rw(FUNC(iris3000_state::mouse_buttons_r), FUNC(iris3000_state::mouse_buttons_w));
|
||||
map(0x1000000, 0x1000003).rw(FUNC(iris3000_state::mouse_quad_r), FUNC(iris3000_state::mouse_quad_w));
|
||||
map(0x1800000, 0x1800003).r(FUNC(iris3000_state::dips_r));
|
||||
map(0x2000000, 0x200000f).rw(m_duarta, FUNC(mc68681_device::read), FUNC(mc68681_device::write));
|
||||
map(0x2800000, 0x280000f).rw(m_duartb, FUNC(mc68681_device::read), FUNC(mc68681_device::write));
|
||||
map(0x3000000, 0x30007ff).ram();
|
||||
map(0x4000000, 0x4000003).rw(FUNC(iris3000_state::clock_ctrl_r), FUNC(iris3000_state::clock_ctrl_w));
|
||||
map(0x5000000, 0x5000003).rw(FUNC(iris3000_state::clock_data_r), FUNC(iris3000_state::clock_data_w));
|
||||
map(0x6000000, 0x6000003).rw(FUNC(iris3000_state::kernel_base_r), FUNC(iris3000_state::kernel_base_w));
|
||||
map(0x8000000, 0x8000003).rw(FUNC(iris3000_state::status_r), FUNC(iris3000_state::status_w));
|
||||
map(0x9000000, 0x9000003).rw(FUNC(iris3000_state::parity_ctrl_r), FUNC(iris3000_state::parity_ctrl_w));
|
||||
map(0xa000000, 0xa000003).rw(FUNC(iris3000_state::multibus_prot_r), FUNC(iris3000_state::multibus_prot_w));
|
||||
map(0xb000000, 0xb00ffff).rw(FUNC(iris3000_state::page_table_map_r), FUNC(iris3000_state::page_table_map_w)).share("ptmap");
|
||||
map(0xc000000, 0xc000003).rw(FUNC(iris3000_state::text_data_base_r), FUNC(iris3000_state::text_data_base_w));
|
||||
map(0xd000000, 0xd000003).rw(FUNC(iris3000_state::text_data_limit_r), FUNC(iris3000_state::text_data_limit_w));
|
||||
map(0xe000000, 0xe000003).rw(FUNC(iris3000_state::stack_base_r), FUNC(iris3000_state::stack_base_w));
|
||||
map(0xf000000, 0xf000003).rw(FUNC(iris3000_state::stack_limit_r), FUNC(iris3000_state::stack_limit_w));
|
||||
}
|
||||
|
||||
void iris3000_state::multibus_mem_map(address_map &map)
|
||||
{
|
||||
map(0x0200000, 0x03fffff).r(FUNC(iris3000_state::romboard_r));
|
||||
}
|
||||
|
||||
void iris3000_state::multibus_io_map(address_map &map)
|
||||
{
|
||||
}
|
||||
|
||||
void iris3000_state::geometry_pipe_map(address_map &map)
|
||||
{
|
||||
}
|
||||
|
||||
void iris3000_state::fpa_map(address_map &map)
|
||||
{
|
||||
}
|
||||
|
||||
void iris3000_state::mem_map(address_map &map)
|
||||
{
|
||||
map(0x00000000, 0xffffffff).rw(FUNC(iris3000_state::mmu_r), FUNC(iris3000_state::mmu_w));
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
MACHINE DRIVERS
|
||||
***************************************************************************/
|
||||
|
||||
WRITE_LINE_MEMBER(sgi_ip2_state::duarta_irq_handler)
|
||||
WRITE_LINE_MEMBER(iris3000_state::duarta_irq_handler)
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_IRQ_6, state);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(sgi_ip2_state::duartb_irq_handler)
|
||||
WRITE_LINE_MEMBER(iris3000_state::duartb_irq_handler)
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_IRQ_6, state);
|
||||
}
|
||||
@ -422,28 +604,40 @@ static DEVICE_INPUT_DEFAULTS_START( ip2_terminal )
|
||||
DEVICE_INPUT_DEFAULTS( "RS232_STOPBITS", 0xff, RS232_STOPBITS_1 )
|
||||
DEVICE_INPUT_DEFAULTS_END
|
||||
|
||||
void sgi_ip2_state::sgi_ip2(machine_config &config)
|
||||
void iris3000_state::iris3130(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
M68020(config, m_maincpu, 16000000);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &sgi_ip2_state::sgi_ip2_map);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &iris3000_state::mem_map);
|
||||
|
||||
ADDRESS_MAP_BANK(config, "text_data").set_map(&iris3000_state::text_data_map).set_options(ENDIANNESS_BIG, 32, 32);
|
||||
ADDRESS_MAP_BANK(config, "stack").set_map(&iris3000_state::stack_map).set_options(ENDIANNESS_BIG, 32, 32);
|
||||
ADDRESS_MAP_BANK(config, "kernel").set_map(&iris3000_state::kernel_map).set_options(ENDIANNESS_BIG, 32, 32);
|
||||
ADDRESS_MAP_BANK(config, "system").set_map(&iris3000_state::system_map).set_options(ENDIANNESS_BIG, 32, 32);
|
||||
ADDRESS_MAP_BANK(config, "multibus_mem").set_map(&iris3000_state::multibus_mem_map).set_options(ENDIANNESS_BIG, 32, 32);
|
||||
ADDRESS_MAP_BANK(config, "multibus_io").set_map(&iris3000_state::multibus_io_map).set_options(ENDIANNESS_BIG, 32, 32);
|
||||
ADDRESS_MAP_BANK(config, "geometry_pipe").set_map(&iris3000_state::geometry_pipe_map).set_options(ENDIANNESS_BIG, 32, 32);
|
||||
ADDRESS_MAP_BANK(config, "fpa").set_map(&iris3000_state::fpa_map).set_options(ENDIANNESS_BIG, 32, 32);
|
||||
|
||||
MC68681(config, m_duarta, 3.6864_MHz_XTAL); /* Y3 3.6864MHz Xtal ??? copy-over from dectalk */
|
||||
m_duarta->irq_cb().set(FUNC(sgi_ip2_state::duarta_irq_handler));
|
||||
m_duarta->irq_cb().set(FUNC(iris3000_state::duarta_irq_handler));
|
||||
m_duarta->b_tx_cb().set("rs232", FUNC(rs232_port_device::write_txd));
|
||||
|
||||
MC68681(config, m_duartb, 3.6864_MHz_XTAL); /* Y3 3.6864MHz Xtal ??? copy-over from dectalk */
|
||||
m_duartb->irq_cb().set(FUNC(sgi_ip2_state::duartb_irq_handler));
|
||||
m_duartb->irq_cb().set(FUNC(iris3000_state::duartb_irq_handler));
|
||||
|
||||
MC146818(config, m_rtc, 4.194304_MHz_XTAL);
|
||||
|
||||
rs232_port_device &rs232(RS232_PORT(config, "rs232", default_rs232_devices, "terminal"));
|
||||
rs232.rxd_handler().set(m_duarta, FUNC(mc68681_device::rx_b_w));
|
||||
rs232.set_option_device_input_defaults("terminal", DEVICE_INPUT_DEFAULTS_NAME(ip2_terminal));
|
||||
|
||||
quickload_image_device &quickload(QUICKLOAD(config, "quickload", ""));
|
||||
quickload.set_load_callback(FUNC(iris3000_state::load_romboard));
|
||||
}
|
||||
|
||||
static INPUT_PORTS_START( sgi_ip2 )
|
||||
PORT_START("SWTCH")
|
||||
static INPUT_PORTS_START( iris3130 )
|
||||
PORT_START("DIPS")
|
||||
PORT_DIPNAME( 0x8000, 0x8000, "Master/Slave" )
|
||||
PORT_DIPSETTING( 0x0000, "Slave" )
|
||||
PORT_DIPSETTING( 0x8000, "Master" )
|
||||
@ -487,28 +681,20 @@ static INPUT_PORTS_START( sgi_ip2 )
|
||||
PORT_DIPSETTING( 0x000d, "DSD Tape Boot (1)" )
|
||||
PORT_DIPSETTING( 0x000e, "DSD Tape Boot (2)" )
|
||||
PORT_DIPSETTING( 0x000f, "DSD Hard Disk Boot" )
|
||||
|
||||
INPUT_PORTS_END
|
||||
|
||||
void sgi_ip2_state::init_sgi_ip2()
|
||||
{
|
||||
uint32_t *src = (uint32_t*)(memregion("maincpu")->base());
|
||||
uint32_t *dst = m_mainram;
|
||||
memcpy(dst, src, 8);
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
|
||||
ROM definition(s)
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
ROM_START( sgi_ip2 )
|
||||
ROM_START( iris3130 )
|
||||
ROM_REGION32_BE(0x18000, "maincpu", 0)
|
||||
ROM_LOAD( "sgi-ip2-u91.nolabel.od", 0x00000, 0x8000, CRC(32e1f6b5) SHA1(2bd928c3fe2e364b9a38189158e9bad0e5271a59) )
|
||||
ROM_LOAD( "sgi-ip2-u92.nolabel.od", 0x08000, 0x8000, CRC(13dbfdb3) SHA1(3361fb62f7a8c429653700bccfc3e937f7508182) )
|
||||
ROM_LOAD( "sgi-ip2-u93.ip2.2-008.od", 0x10000, 0x8000, CRC(bf967590) SHA1(1aac48e4f5531a25c5482f64de5cd3c7a9931f11) )
|
||||
ROM_END
|
||||
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1985, sgi_ip2, 0, 0, sgi_ip2, sgi_ip2, sgi_ip2_state, init_sgi_ip2, "Silicon Graphics Inc", "IRIS 3130 (IP2)", MACHINE_NOT_WORKING )
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1985, iris3130, 0, 0, iris3130, iris3130, iris3000_state, empty_init, "Silicon Graphics Inc", "IRIS 3130 (IP2)", MACHINE_IS_SKELETON )
|
||||
|
||||
@ -16466,7 +16466,7 @@ iqblock // (c) 1993
|
||||
iqunlim // 199? IQ Unlimited (680x0)
|
||||
|
||||
@source:iris3130.cpp
|
||||
sgi_ip2 // IP2: IRIS 3xx0, 68020, 16MHz
|
||||
iris3130 // IP2: IRIS 3xx0, 68020, 16MHz
|
||||
|
||||
@source:irisha.cpp
|
||||
irisha //
|
||||
|
||||
Loading…
Reference in New Issue
Block a user