er1400: Correct clock phase and better handle data reads

Fixes various issues in drivers.

src/devices/machine/er1400.cpp

@@ -323,7 +323,7 @@ WRITE_LINE_MEMBER(er1400_device::clock_w)
 	m_clock_input = bool(state);
 
 	// Commands are clocked by a logical 1 -> 0 transition (i.e. rising edge)
-	if (!state)
+	if (state)
 	{
 		if (machine().time() >= m_write_time)
 			write_data();
@@ -398,5 +398,5 @@ WRITE_LINE_MEMBER(er1400_device::clock_w)
 
 READ_LINE_MEMBER(er1400_device::data_r)
 {
-	return m_data_input | m_data_output;
+	return m_data_input & m_data_output;
 }

src/mame/dec/decwritr.cpp

@@ -180,12 +180,10 @@ void decwriter_state::la120_NVR_w(offs_t offset, uint8_t data)
 	m_nvm->c3_w(BIT(offset, 10));
 	m_nvm->c2_w(BIT(offset, 9));
 	m_nvm->c1_w(BIT(offset, 8));
-
-	// FIXME: clock line shouldn't be inverted relative to C1-C3, but accesses only seems to work this way
-	m_nvm->clock_w(!BIT(offset, 0));
+	m_nvm->clock_w(BIT(offset, 0));
 
 	// C2 is used to disable pullup on data line
-	m_nvm->data_w(!BIT(offset, 9) ? 0 : !BIT(data, 7));
+	m_nvm->data_w(BIT(offset, 9) ? !BIT(data, 7) : 1);
 }
 
 /* todo: fully reverse engineer DC305 ASIC */

src/mame/dec/vt100.cpp

@@ -179,7 +179,7 @@ void vt100_state::nvr_latch_w(u8 data)
 	m_nvr->c1_w(!BIT(data, 1));
 
 	// C2 is used to disable pullup on data line
-	m_nvr->data_w(BIT(data, 2) ? 0 : !BIT(data, 0));
+	m_nvr->data_w(BIT(data, 2) ? 1 : !BIT(data, 0));
 
 	// SPDS present on pins 11, 19 and 23 of EIA connector
 	m_rs232->write_spds(BIT(data, 5));

src/mame/facit/f4431.cpp

@@ -310,20 +310,11 @@ void f4431_state::latch_w(uint8_t data)
 	// ------1-  earom data
 	// -------0  earom c1
 
-	if (0)
-		logerror("latch_w: %02x\n", data);
-
 	m_earom->c1_w(BIT(data, 0));
-	m_earom->data_w(BIT(data, 4) ? 0 : BIT(data, 1));
+	m_earom->data_w(BIT(data, 1));
 	m_earom->c3_w(BIT(data, 2));
 	m_earom->c2_w(BIT(data, 3));
-
-	// don't clock a 'standby' state. the system clocks this and afterwards
-	// the real state; this causes the real state to be ignored, losing the
-	// first bit. to avoid this we don't clock the standby state. maybe it
-	// works in the real system because of timing.
-	if (data & 0x1d)
-		m_earom->clock_w(BIT(data, 4));
+	m_earom->clock_w(BIT(data, 4));
 
 	m_display_enabled = bool(BIT(data, 5));
 	m_nmi_disabled = bool(BIT(data, 6));

src/mame/facit/facit4440.cpp

@@ -100,15 +100,6 @@ private:
 void facit4440_state::earom_latch_w(u8 data)
 {
 	// SN74LS174 latch + SN7406 inverter
-
-	// Prevent outputs from interfering with data reads
-	if (!BIT(data, 2))
-		data &= 0xfc;
-
-	// FIXME: clock must be written first here due to data/control setup time
-	m_earom[0]->clock_w(BIT(data, 5));
-	m_earom[1]->clock_w(BIT(data, 5));
-
 	m_earom[0]->data_w(BIT(data, 0));
 	m_earom[1]->data_w(BIT(data, 1));
 
@@ -117,6 +108,7 @@ void facit4440_state::earom_latch_w(u8 data)
 		earom->c2_w(BIT(data, 2));
 		earom->c1_w(BIT(data, 3));
 		earom->c3_w(BIT(data, 4));
+		earom->clock_w(BIT(data, 5));
 	}
 }
 

src/mame/learsiegler/adm36.cpp

@@ -87,7 +87,7 @@ u8 adm36_state::pio_pb_r()
 
 void adm36_state::pio_pb_w(u8 data)
 {
-	m_earom->clock_w(!BIT(data, 4));
+	m_earom->clock_w(BIT(data, 4));
 	m_earom->c3_w(BIT(data, 3));
 	m_earom->c2_w(BIT(data, 2));
 	m_earom->c1_w(BIT(data, 1));

src/mame/wyse/wy50.cpp

@@ -222,11 +222,11 @@ void wy50_state::earom_w(u8 data)
 	// Bit 3 = EAROM C2
 	// Bit 4 = EAROM C1
 	// Bit 5 = UPCHAR/NORM
+	m_earom->data_w(BIT(data, 3) ? BIT(data, 0) : 1);
 	m_earom->clock_w(BIT(data, 1));
 	m_earom->c3_w(BIT(data, 2));
 	m_earom->c2_w(BIT(data, 3));
 	m_earom->c1_w(BIT(data, 4));
-	m_earom->data_w(BIT(data, 3) ? BIT(data, 0) : 0);
 	m_font2 = BIT(data, 5);
 }
 

src/mame/wyse/wy85.cpp

@@ -99,7 +99,7 @@ void wy85_state::earom_w(u8 data)
 	m_earom->c3_w(BIT(data, 2));
 	m_earom->c2_w(BIT(data, 3));
 	m_earom->c1_w(BIT(data, 4));
-	m_earom->data_w(BIT(data, 3) ? BIT(data, 0) : 0);
+	m_earom->data_w(BIT(data, 3) ? BIT(data, 0) : 1);
 }
 
 u8 wy85_state::misc_r()