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powerpc: Modernised cpu core (nw)

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This commit is contained in:
Wilbert Pol 2014-06-30 20:38:12 +00:00
parent 38d3fa734c
commit 866e9562dd
23 changed files with 2999 additions and 3267 deletions
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304
src/emu/cpu/powerpc/ppc.c
View File

@ -109,34 +109,34 @@ static void ppc403_spu_w(UINT32 a, UINT8 d);
#define AABIT (op & 0x2)
#define LKBIT (op & 0x1)
#define REG(x) (ppc.r[x])
#define LR (ppc.lr)
#define CTR (ppc.ctr)
#define XER (ppc.xer)
#define CR(x) (ppc.cr[x])
#define MSR (ppc.msr)
#define SRR0 (ppc.srr0)
#define SRR1 (ppc.srr1)
#define SRR2 (ppc.srr2)
#define SRR3 (ppc.srr3)
#define EVPR (ppc.evpr)
#define EXIER (ppc.exier)
#define EXISR (ppc.exisr)
#define DEC (ppc.dec)
#define REG(x) (m_r[x])
#define LR (m_lr)
#define CTR (m_ctr)
#define XER (m_xer)
#define CR(x) (m_cr[x])
#define MSR (m_msr)
#define SRR0 (m_srr0)
#define SRR1 (m_srr1)
#define SRR2 (m_srr2)
#define SRR3 (m_srr3)
#define EVPR (m_evpr)
#define EXIER (m_exier)
#define EXISR (m_exisr)
#define DEC (m_dec)
// Stuff added for the 6xx
#define FPR(x) (ppc.fpr[x])
#define FPR(x) (m_fpr[x])
#define FM ((op >> 17) & 0xFF)
#define SPRF (((op >> 6) & 0x3E0) | ((op >> 16) & 0x1F))
#define CHECK_SUPERVISOR() \
if((ppc.msr & 0x4000) != 0){ \
if((m_msr & 0x4000) != 0){ \
}
#define CHECK_FPU_AVAILABLE() \
if((ppc.msr & 0x2000) == 0){ \
if((m_msr & 0x2000) == 0){ \
}
static UINT32 ppc_field_xlat[256];
@ -154,7 +154,7 @@ static UINT32 ppc_field_xlat[256];
#define BITMASK_0(n) (UINT32)(((UINT64)1 << n) - 1)
#define CRBIT(x) ((ppc.cr[x / 4] & (1 << (3 - (x % 4)))) ? 1 : 0)
#define CRBIT(x) ((m_cr[x / 4] & (1 << (3 - (x % 4)))) ? 1 : 0)
#define _BIT(n) (1 << (n))
#define GET_ROTATE_MASK(mb,me) (ppc_rotate_mask[mb][me])
#define ADD_CA(r,a,b) ((UINT32)r < (UINT32)a)
@ -195,163 +195,19 @@ static UINT32 ppc_field_xlat[256];
#define BYTE_REVERSE16(x) ((((x) >> 8) & 0xff) | (((x) << 8) & 0xff00))
#define BYTE_REVERSE32(x) ((((x) >> 24) & 0xff) | (((x) >> 8) & 0xff00) | (((x) << 8) & 0xff0000) | (((x) << 24) & 0xff000000))
struct DMA_REGS {
UINT32 cr;
UINT32 da;
UINT32 sa;
UINT32 ct;
UINT32 cc;
};
struct SPU_REGS {
UINT8 spls;
UINT8 sphs;
UINT16 brd;
UINT8 spctl;
UINT8 sprc;
UINT8 sptc;
UINT8 sprb;
UINT8 sptb;
emu_timer *rx_timer;
emu_timer *tx_timer;
};
union FPR {
UINT64 id;
double fd;
};
union FPR32 {
UINT32 i;
float f;
};
struct BATENT {
UINT32 u;
UINT32 l;
};
struct PPC_REGS {
UINT32 r[32];
UINT32 pc;
UINT32 npc;
UINT32 lr;
UINT32 ctr;
UINT32 xer;
UINT32 msr;
UINT8 cr[8];
UINT32 pvr;
UINT32 srr0;
UINT32 srr1;
UINT32 srr2;
UINT32 srr3;
UINT32 hid0;
UINT32 hid1;
UINT32 hid2;
UINT32 sdr1;
UINT32 sprg[4];
UINT32 dsisr;
UINT32 dar;
UINT32 ear;
UINT32 dmiss;
UINT32 dcmp;
UINT32 hash1;
UINT32 hash2;
UINT32 imiss;
UINT32 icmp;
UINT32 rpa;
BATENT ibat[4];
BATENT dbat[4];
UINT32 evpr;
UINT32 exier;
UINT32 exisr;
UINT32 bear;
UINT32 besr;
UINT32 iocr;
UINT32 br[8];
UINT32 iabr;
UINT32 esr;
UINT32 iccr;
UINT32 dccr;
UINT32 pit;
UINT32 pit_counter;
UINT32 pit_int_enable;
UINT32 tsr;
UINT32 dbsr;
UINT32 sgr;
UINT32 pid;
UINT32 pbl1, pbl2, pbu1, pbu2;
UINT32 fit_bit;
UINT32 fit_int_enable;
UINT32 wdt_bit;
UINT32 wdt_int_enable;
UINT32 dac1, dac2;
UINT32 iac1, iac2;
SPU_REGS spu;
DMA_REGS dma[4];
UINT32 dmasr;
int reserved;
UINT32 reserved_address;
int interrupt_pending;
UINT64 tb; /* 56-bit timebase register */
device_irq_acknowledge_delegate irq_callback;
legacy_cpu_device *device;
address_space *program;
// STUFF added for the 6xx series
UINT32 dec, dec_frac;
UINT32 fpscr;
FPR fpr[32];
UINT32 sr[16];
int is603;
int is602;
/* PowerPC 602 specific registers */
UINT32 lt;
UINT32 sp;
UINT32 tcr;
UINT32 ibr;
UINT32 esasrr;
UINT32 sebr;
UINT32 ser;
/* PowerPC function pointers for memory accesses/exceptions */
jmp_buf exception_jmpbuf;
UINT8 (*read8)(address_space &space, offs_t address);
UINT16 (*read16)(address_space &space, offs_t address);
UINT32 (*read32)(address_space &space, offs_t address);
UINT64 (*read64)(address_space &space, offs_t address);
void (*write8)(address_space &space, offs_t address, UINT8 data);
void (*write16)(address_space &space, offs_t address, UINT16 data);
void (*write32)(address_space &space, offs_t address, UINT32 data);
void (*write64)(address_space &space, offs_t address, UINT64 data);
UINT16 (*read16_unaligned)(address_space &space, offs_t address);
UINT32 (*read32_unaligned)(address_space &space, offs_t address);
UINT64 (*read64_unaligned)(address_space &space, offs_t address);
void (*write16_unaligned)(address_space &space, offs_t address, UINT16 data);
void (*write32_unaligned)(address_space &space, offs_t address, UINT32 data);
void (*write64_unaligned)(address_space &space, offs_t address, UINT64 data);
void (* optable19[1024])(UINT32);
void (* optable31[1024])(UINT32);
void (* optable59[1024])(UINT32);
void (* optable63[1024])(UINT32);
void (* optable[64])(UINT32);
};
const device_type PPC403 = &device_creator<ppc403_device>;
const device_type PPC405 = &device_creator<ppc405_device>;
const device_type PPC601 = &device_creator<ppc601_device>;
const device_type PPC602 = &device_creator<ppc602_device>;
const device_type PPC603 = &device_creator<ppc603_device>;
const device_type PPC603E = &device_creator<ppc603e_device>;
const device_type PPC603R = &device_creator<ppc603r_device>;
const device_type PPC604 = &device_creator<ppc604_device>;
const device_type MPC8240 = &device_creator<mpc8240_device>;
const device_type PPC403GA = &device_creator<ppc403ga_device>;
const device_type PPC403GCX = &device_creator<ppc403gcx_device>;
const device_type PPC405GP = &device_creator<ppc405gp_device>;
struct PPC_OPCODE {
@ -362,30 +218,104 @@ struct PPC_OPCODE {
static int ppc_icount;
static int ppc_tb_base_icount;
static int ppc_dec_base_icount;
static int ppc_dec_trigger_cycle;
static int bus_freq_multiplier = 1;
static PPC_REGS ppc;
static UINT32 ppc_rotate_mask[32][32];
#define ROPCODE(pc) memory_decrypted_read_dword(ppc.program, pc)
#define ROPCODE64(pc) memory_decrypted_read_qword(ppc.program, DWORD_XOR_BE(pc))
#define ROPCODE(pc) memory_decrypted_read_dword(m_program, pc)
#define ROPCODE64(pc) memory_decrypted_read_qword(m_program, DWORD_XOR_BE(pc))
ppc_device::ppc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int address_bits, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor)
: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__)
, m_program_config("program", ENDIANNESS_BIG, address_bits, 32)
, m_core(NULL)
, c_bus_frequency(0)
, m_bus_freq_multiplier(1)
, m_flavor(flavor)
, m_cap(cap)
, m_tb_divisor(tb_divisor)
, m_vtlb(NULL)
, m_cache(CACHE_SIZE + sizeof(internal_ppc_state))
{
}
//ppc403_device::ppc403_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
// : ppc_device(mconfig, PPC403, "PPC403", tag, owner, clock, "ppc403", 32)
//{
//}
//
//ppc405_device::ppc405_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
// : ppc_device(mconfig, PPC405, "PPC405", tag, owner, clock, "ppc405", 32)
//{
//}
ppc603_device::ppc603_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ppc_device(mconfig, PPC603", "PowerPC 603", tag, owner, clock, "ppc603", 64, PPC_MODEL_603, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4)
{
}
ppc603e_device::ppc603e_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ppc_device(mconfig, PPC603E, "PowerPC 603e", tag, owner, clock, "ppc603e", 64, PPC_MODEL_603E, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4)
{
}
ppc603r_device::ppc603r_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ppc_device(mconfig, PPC603R, "PowerPC 603R", tag, owner, clock, "ppc603r", 64, PPC_MODEL_603R, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4)
{
}
ppc602_device::ppc602_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ppc_device(mconfig, PPC602, "PowerPC 602", tag, owner, clock, "ppc602", 64, PPC_MODEL_602, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4)
{
}
mpc8240_device::mpc8240_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ppc_device(mconfig, MPC8240, "PowerPC MPC8240", tag, owner, clock, "mpc8240", 64, PPC_MODEL_MPC8240, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_603_MMU, 4/* unknown */)
{
}
ppc601_device::ppc601_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ppc_device(mconfig, PPC601, "PowerPC 601", tag, owner, clock, "ppc601", 64, PPC_MODEL_601, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_MFIOC | PPCCAP_601BAT, 0/* no TB */)
{
}
ppc604_device::ppc604_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ppc_device(mconfig, PPC604, "PowerPC 604", tag, owner, clock, "ppc604", 64, PPC_MODEL_604, PPCCAP_OEA | PPCCAP_VEA | PPCCAP_FPU | PPCCAP_MISALIGNED | PPCCAP_604_MMU, 4)
{
}
ppc4xx_device::ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor)
: ppc_device(mconfig, type, name, tag, owner, clock, shortname, 64, flavor, cap, tb_divisor) // TODO address bits, ppccom has 31 address bits??
{
}
ppc403ga_device::ppc403ga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ppc4xx_device(mconfig, PPC403GA, "PowerPC 403GA", tag, owner, clock, "ppc403ga", PPC_MODEL_403GA, PPCCAP_4XX, 1)
{
}
ppc403gcx_device::ppc403gcx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ppc4xx_device(mconfig, PPC403GCX, "PowerPC 403GCX", tag, owner, clock, "ppc403gcx", PPC_MODEL_403GCX, PPCCAP_4XX, 1)
{
}
ppc405gp_device::ppc405gp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: ppc4xx_device(mconfig, PPC405GP, "PowerPC 405GP", tag, owner, clock, "ppc405gp", PPC_MODEL_405GP, PPCCAP_4XX | PPCCAP_VEA, 1)
{
}
/*********************************************************************/
INLINE int IS_PPC602(void)
inline int ppc_device::IS_PPC602(void)
{
return ppc.is602;
return m_is602;
}
INLINE int IS_PPC603(void)
inline int ppc_device::IS_PPC603(void)
{
return ppc.is603;
return m_is603;
}
INLINE int IS_PPC403(void)
inline int ppc_device::IS_PPC403(void)
{
return !IS_PPC602() && !IS_PPC603();
}

653
src/emu/cpu/powerpc/ppc.h
View File

@ -14,6 +14,11 @@
#ifndef __PPC_H__
#define __PPC_H__
#include <setjmp.h>
#include "cpu/vtlb.h"
#include "cpu/drcfe.h"
#include "cpu/drcuml.h"
#include "cpu/drcumlsh.h"
/***************************************************************************
@ -162,10 +167,6 @@ enum
typedef void (*ppc4xx_spu_tx_handler)(device_t *device, UINT8 data);
struct powerpc_config
{
UINT32 bus_frequency;
};
typedef void (*ppc_dcstore_handler)(device_t *device, UINT32 address);
typedef UINT32 (*ppc4xx_dma_read_handler)(device_t *device, int width);
@ -176,65 +177,643 @@ typedef void (*ppc4xx_dma_write_handler)(device_t *device, int width, UINT32 dat
PUBLIC FUNCTIONS
***************************************************************************/
void ppcdrc_set_options(device_t *device, UINT32 options);
void ppcdrc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base);
void ppcdrc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles);
#define MCFG_PPC_BUS_FREQUENCY(_frequency) \
ppc_device::set_bus_frequency(*device, _frequency);
void ppc4xx_spu_set_tx_handler(device_t *device, ppc4xx_spu_tx_handler handler);
void ppc4xx_spu_receive_byte(device_t *device, UINT8 byteval);
void ppc_set_dcstore_callback(device_t *device, ppc_dcstore_handler handler);
void ppc4xx_set_dma_read_handler(device_t *device, int channel, ppc4xx_dma_read_handler handler, int rate);
void ppc4xx_set_dma_write_handler(device_t *device, int channel, ppc4xx_dma_write_handler handler, int rate);
void ppc4xx_set_dcr_read_handler(device_t *device, read32_delegate dcr_read_func);
void ppc4xx_set_dcr_write_handler(device_t *device, write32_delegate dcr_write_func);
class ppc_frontend;
class ppc4xx_device : public legacy_cpu_device
class ppc_device : public cpu_device
{
friend class ppc_frontend;
protected:
/* PowerPC flavors */
enum powerpc_flavor
{
PPC_MODEL_403GA = 0x00200000,
PPC_MODEL_403GB = 0x00200100,
PPC_MODEL_403GC = 0x00200200,
PPC_MODEL_403GCX = 0x00201400,
PPC_MODEL_405GP = 0x40110000,
PPC_MODEL_601 = 0x00010000,
PPC_MODEL_603 = 0x00030000, /* "Wart" */
PPC_MODEL_604 = 0x00040000, /* "Zephyr" */
PPC_MODEL_602 = 0x00050200, /* "Galahad" */
PPC_MODEL_603E = 0x00060103, /* "Stretch", version 1.3 */
PPC_MODEL_603EV = 0x00070000, /* "Valiant" */
PPC_MODEL_603R = 0x00071202, /* "Goldeneye", version 2.1 */
PPC_MODEL_740 = 0x00080301, /* "Arthur", version 3.1 */
PPC_MODEL_750 = PPC_MODEL_740,
PPC_MODEL_740P = 0x00080202, /* "Conan Doyle", version 1.2 */
PPC_MODEL_750P = PPC_MODEL_740P,
PPC_MODEL_755 = 0x00083203, /* "Goldfinger", version 2.3 */
PPC_MODEL_7400 = 0x000c0209, /* "Max", version 2.9 */
PPC_MODEL_7410 = 0x800c1104, /* "Nitro", version 3.4 */
PPC_MODEL_7450 = 0x80000201, /* "Vger", version 2.1 */
PPC_MODEL_7451 = 0x80000203, /* "Vger", version 2.3 */
PPC_MODEL_7441 = PPC_MODEL_7451,
PPC_MODEL_7455 = 0x80010303, /* "Apollo 6", version 3.3 */
PPC_MODEL_7445 = PPC_MODEL_7455,
PPC_MODEL_7457 = 0x80020101, /* "Apollo 7", version 1.1 */
PPC_MODEL_MPC8240 = 0x00810101, /* "Kahlua" */
PPC_MODEL_MPC8241 = 0x80811014, /* "Kahlua Lt" */
PPC_MODEL_MPC8245 = 0x80811014, /* "Kahlua II" */
};
public:
ppc4xx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info);
DECLARE_READ8_MEMBER( ppc4xx_spu_r );
DECLARE_WRITE8_MEMBER( ppc4xx_spu_w );
// construction/destruction
ppc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int address_bits, int data_bits, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor, address_map_constructor internal_map);
static void set_bus_frequency(device_t &device, UINT32 bus_frequency) { downcast<ppc_device &>(device).c_bus_frequency = bus_frequency; }
void ppc_set_dcstore_callback(ppc_dcstore_handler handler);
void ppcdrc_set_options(UINT32 options);
void ppcdrc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
void ppcdrc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
TIMER_CALLBACK_MEMBER(decrementer_int_callback);
TIMER_CALLBACK_MEMBER(ppc4xx_buffered_dma_callback);
TIMER_CALLBACK_MEMBER(ppc4xx_fit_callback);
TIMER_CALLBACK_MEMBER(ppc4xx_pit_callback);
TIMER_CALLBACK_MEMBER(ppc4xx_spu_callback);
void ppc_cfunc_printf_exception();
void ppc_cfunc_printf_debug();
void ppc_cfunc_printf_probe();
void ppc_cfunc_unimplemented();
void ppccom_tlb_fill();
void ppccom_update_fprf();
void ppccom_dcstore_callback();
void ppccom_execute_tlbie();
void ppccom_execute_tlbia();
void ppccom_execute_tlbl();
void ppccom_execute_mfspr();
void ppccom_execute_mftb();
void ppccom_execute_mtspr();
void ppccom_tlb_flush();
void ppccom_execute_mfdcr();
void ppccom_execute_mtdcr();
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
virtual void device_stop();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 40; }
virtual UINT32 execute_input_lines() const { return 1; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
virtual bool memory_translate(address_spacenum spacenum, int intention, offs_t &address);
// device_state_interface overrides
virtual void state_export(const device_state_entry &entry);
virtual void state_import(const device_state_entry &entry);
virtual void state_string_export(const device_state_entry &entry, astring &string);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 4; }
virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
/* exception types */
enum
{
EXCEPTION_RESET = 1,
EXCEPTION_MACHCHECK = 2,
EXCEPTION_DSI = 3, /* PPCCAP_OEA */
EXCEPTION_PROTECTION = 3, /* PPCCAP_4XX */
EXCEPTION_ISI = 4,
EXCEPTION_EI = 5,
EXCEPTION_ALIGN = 6,
EXCEPTION_PROGRAM = 7,
EXCEPTION_NOFPU = 8,
EXCEPTION_DECREMENT = 9,
EXCEPTION_SYSCALL = 12,
EXCEPTION_TRACE = 13,
EXCEPTION_FPASSIST = 14,
EXCEPTION_ITLBMISS = 16, /* PPCCAP_603_MMU */
EXCEPTION_DTLBMISSL = 17, /* PPCCAP_603_MMU */
EXCEPTION_DTLBMISSS = 18, /* PPCCAP_603_MMU */
EXCEPTION_COUNT
};
address_space_config m_program_config;
address_space *m_program;
UINT32 c_bus_frequency;
struct internal_ppc_state
{
UINT32 pc;
UINT32 r[32];
double f[32];
UINT32 cr[8];
UINT32 fpscr;
UINT32 msr;
UINT32 xerso;
UINT32 sr[16];
UINT32 spr[1024];
int icount;
UINT32 mode; /* current global mode */
UINT32 irq_pending;
/* parameters for calls */
UINT32 param0;
UINT32 param1;
/* PowerPC 603-specific state */
UINT32 mmu603_cmp;
UINT32 mmu603_hash[2];
UINT32 mmu603_r[4];
/* parameters for subroutines */
UINT32 tempaddr; /* temporary address storage */
drcuml_ireg tempdata; /* temporary data storage */
UINT32 updateaddr; /* update address storage */
UINT32 swcount; /* counter for sw instructions */
const char * format; /* format string for printing */
UINT32 arg0; /* print_debug argument 1 */
double fp0; /* floating point 0 */
};
internal_ppc_state *m_core;
int m_ppc_tb_base_icount;
int m_ppc_dec_base_icount;
int m_ppc_dec_trigger_cycle;
int m_bus_freq_multiplier;
UINT32 m_npc;
UINT32 m_dcr[256];
UINT32 m_lr;
UINT32 m_ctr;
UINT32 m_xer;
UINT32 m_pvr;
UINT32 m_srr0;
UINT32 m_srr1;
UINT32 m_srr2;
UINT32 m_srr3;
UINT32 m_hid0;
UINT32 m_hid1;
UINT32 m_hid2;
UINT32 m_sdr1;
UINT32 m_sprg[4];
UINT32 m_dsisr;
UINT32 m_dar;
UINT32 m_ear;
UINT32 m_dmiss;
UINT32 m_dcmp;
UINT32 m_hash1;
UINT32 m_hash2;
UINT32 m_imiss;
UINT32 m_icmp;
UINT32 m_rpa;
struct BATENT {
UINT32 u;
UINT32 l;
};
BATENT m_ibat[4];
BATENT m_dbat[4];
UINT32 m_evpr;
UINT32 m_exier;
UINT32 m_exisr;
UINT32 m_bear;
UINT32 m_besr;
UINT32 m_iocr;
UINT32 m_br[8];
UINT32 m_iabr;
UINT32 m_esr;
UINT32 m_iccr;
UINT32 m_dccr;
UINT32 m_pit;
UINT32 m_pit_counter;
UINT32 m_pit_int_enable;
UINT32 m_tsr;
UINT32 m_dbsr;
UINT32 m_sgr;
UINT32 m_pid;
UINT32 m_pbl1;
UINT32 m_pbl2;
UINT32 m_pbu1;
UINT32 m_pbu2;
UINT32 m_fit_bit;
UINT32 m_fit_int_enable;
UINT32 m_wdt_bit;
UINT32 m_wdt_int_enable;
UINT32 m_dac1;
UINT32 m_dac2;
UINT32 m_iac1;
UINT32 m_iac2;
struct SPU_REGS {
UINT8 spls;
UINT8 sphs;
UINT16 brd;
UINT8 spctl;
UINT8 sprc;
UINT8 sptc;
UINT8 sprb;
UINT8 sptb;
emu_timer *rx_timer;
emu_timer *tx_timer;
};
SPU_REGS m_spu_old;
struct DMA_REGS {
UINT32 cr;
UINT32 da;
UINT32 sa;
UINT32 ct;
UINT32 cc;
};
DMA_REGS m_dma[4];
UINT32 m_dmasr;
int m_reserved;
UINT32 m_reserved_address;
int m_interrupt_pending;
UINT64 m_tb; /* 56-bit timebase register */
// STUFF added for the 6xx series
UINT32 m_dec, m_dec_frac;
union FPR {
UINT64 id;
double fd;
};
union FPR32 {
UINT32 i;
float f;
};
FPR m_fpr[32];
int m_is603;
int m_is602;
/* PowerPC 602 specific registers */
UINT32 m_lt;
UINT32 m_sp;
UINT32 m_tcr;
UINT32 m_ibr;
UINT32 m_esasrr;
UINT32 m_sebr;
UINT32 m_ser;
/* MMU */
vtlb_state *m_vtlb;
/* architectural distinctions */
powerpc_flavor m_flavor;
UINT32 m_cap;
UINT8 m_cache_line_size;
UINT32 m_tb_divisor;
/* PowerPC 4xx-specific state */
/* PowerPC 4XX-specific serial port state */
struct ppc4xx_spu_state
{
UINT8 regs[9];
UINT8 txbuf;
UINT8 rxbuf;
emu_timer * timer;
UINT8 rxbuffer[256];
UINT32 rxin, rxout;
ppc4xx_spu_tx_handler tx_handler;
};
ppc4xx_spu_state m_spu;
emu_timer * m_fit_timer;
emu_timer * m_pit_timer;
emu_timer * m_wdog_timer;
UINT32 m_pit_reload;
UINT32 m_irqstate;
emu_timer * m_buffered_dma_timer[4];
int m_buffered_dma_rate[4];
/* internal stuff */
direct_read_data *m_direct;
offs_t m_codexor;
UINT32 m_system_clock;
UINT32 m_cpu_clock;
UINT64 m_tb_zero_cycles;
UINT64 m_dec_zero_cycles;
emu_timer * m_decrementer_int_timer;
read32_delegate m_dcr_read_func;
write32_delegate m_dcr_write_func;
ppc_dcstore_handler m_dcstore_handler;
ppc4xx_dma_read_handler m_ext_dma_read_handler[4];
ppc4xx_dma_write_handler m_ext_dma_write_handler[4];
/* PowerPC function pointers for memory accesses/exceptions */
jmp_buf m_exception_jmpbuf;
UINT8 (*m_ppcread8)(address_space &space, offs_t address);
UINT16 (*m_ppcread16)(address_space &space, offs_t address);
UINT32 (*m_ppcread32)(address_space &space, offs_t address);
UINT64 (*m_ppcread64)(address_space &space, offs_t address);
void (*m_ppcwrite8)(address_space &space, offs_t address, UINT8 data);
void (*m_ppcwrite16)(address_space &space, offs_t address, UINT16 data);
void (*m_ppcwrite32)(address_space &space, offs_t address, UINT32 data);
void (*m_ppcwrite64)(address_space &space, offs_t address, UINT64 data);
UINT16 (*m_ppcread16_unaligned)(address_space &space, offs_t address);
UINT32 (*m_ppcread32_unaligned)(address_space &space, offs_t address);
UINT64 (*m_ppcread64_unaligned)(address_space &space, offs_t address);
void (*m_ppcwrite16_unaligned)(address_space &space, offs_t address, UINT16 data);
void (*m_ppcwrite32_unaligned)(address_space &space, offs_t address, UINT32 data);
void (*m_ppcwrite64_unaligned)(address_space &space, offs_t address, UINT64 data);
void (*m_optable19[1024])(UINT32);
void (*m_optable31[1024])(UINT32);
void (*m_optable59[1024])(UINT32);
void (*m_optable63[1024])(UINT32);
void (*m_optable[64])(UINT32);
/* core state */
drc_cache m_cache; /* pointer to the DRC code cache */
drcuml_state * m_drcuml; /* DRC UML generator state */
ppc_frontend * m_drcfe; /* pointer to the DRC front-end state */
UINT32 m_drcoptions; /* configurable DRC options */
/* parameters for subroutines */
UINT32 m_arg1; /* print_debug argument 2 */
/* tables */
UINT8 m_fpmode[4]; /* FPU mode table */
UINT8 m_sz_cr_table[32]; /* SZ CR table */
UINT8 m_cmp_cr_table[32]; /* CMP CR table */
UINT8 m_cmpl_cr_table[32]; /* CMPL CR table */
UINT8 m_fcmp_cr_table[32]; /* FCMP CR table */
/* internal stuff */
UINT8 m_cache_dirty; /* true if we need to flush the cache */
/* register mappings */
uml::parameter m_regmap[32]; /* parameter to register mappings for all 32 integer registers */
uml::parameter m_fdregmap[32]; /* parameter to register mappings for all 32 floating point registers */
/* subroutines */
uml::code_handle * m_entry; /* entry point */
uml::code_handle * m_nocode; /* nocode exception handler */
uml::code_handle * m_out_of_cycles; /* out of cycles exception handler */
uml::code_handle * m_tlb_mismatch; /* tlb mismatch handler */
uml::code_handle * m_swap_tgpr; /* swap TGPR handler */
uml::code_handle * m_lsw[8][32]; /* lsw entries */
uml::code_handle * m_stsw[8][32]; /* stsw entries */
uml::code_handle * m_read8[8]; /* read byte */
uml::code_handle * m_write8[8]; /* write byte */
uml::code_handle * m_read16[8]; /* read half */
uml::code_handle * m_read16mask[8]; /* read half */
uml::code_handle * m_write16[8]; /* write half */
uml::code_handle * m_write16mask[8]; /* write half */
uml::code_handle * m_read32[8]; /* read word */
uml::code_handle * m_read32align[8]; /* read word aligned */
uml::code_handle * m_read32mask[8]; /* read word */
uml::code_handle * m_write32[8]; /* write word */
uml::code_handle * m_write32align[8]; /* write word aligned */
uml::code_handle * m_write32mask[8]; /* write word */
uml::code_handle * m_read64[8]; /* read double */
uml::code_handle * m_read64mask[8]; /* read double */
uml::code_handle * m_write64[8]; /* write double */
uml::code_handle * m_write64mask[8]; /* write double */
uml::code_handle * m_exception[EXCEPTION_COUNT]; /* array of exception handlers */
uml::code_handle * m_exception_norecover[EXCEPTION_COUNT]; /* array of exception handlers */
/* fast RAM */
/* fast RAM info */
struct fast_ram_info
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
UINT8 readonly; /* TRUE if read-only */
void * base; /* base in memory where the RAM lives */
};
UINT32 m_fastram_select;
fast_ram_info m_fastram[PPC_MAX_FASTRAM];
/* hotspots */
/* hotspot info */
struct hotspot_info
{
offs_t pc; /* PC to consider */
UINT32 opcode; /* required opcode at that PC */
UINT32 cycles; /* number of cycles to eat when hit */
};
UINT32 m_hotspot_select;
hotspot_info m_hotspot[PPC_MAX_HOTSPOTS];
UINT64 m_debugger_temp;
/* internal compiler state */
struct compiler_state
{
UINT32 cycles; /* accumulated cycles */
UINT8 checkints; /* need to check interrupts before next instruction */
UINT8 checksoftints; /* need to check software interrupts before next instruction */
uml::code_label labelnum; /* index for local labels */
};
int IS_PPC602(void);
int IS_PPC603(void);
int IS_PPC403(void);
UINT32 get_cr();
void set_cr(UINT32 value);
UINT32 get_xer();
void set_xer(UINT32 value);
UINT64 get_timebase();
void set_timebase(UINT64 newtb);
UINT32 get_decrementer();
void set_decrementer(UINT32 newdec);
UINT32 ppccom_translate_address_internal(int intention, offs_t &address);
void ppc4xx_set_irq_line(UINT32 bitmask, int state);
int ppc4xx_get_irq_line(UINT32 bitmask);
void ppc4xx_dma_update_irq_states();
int ppc4xx_dma_decrement_count(int dmachan);
int ppc4xx_dma_fetch_transmit_byte(int dmachan, UINT8 *byte);
int ppc4xx_dma_handle_receive_byte(int dmachan, UINT8 byte);
void ppc4xx_dma_exec(int dmachan);
void ppc4xx_spu_update_irq_states();
void ppc4xx_spu_rx_data(UINT8 data);
void ppc4xx_spu_timer_reset();
void alloc_handle(drcuml_state *drcuml, uml::code_handle **handleptr, const char *name);
void load_fast_iregs(drcuml_block *block);
void save_fast_iregs(drcuml_block *block);
UINT32 compute_rlw_mask(UINT8 mb, UINT8 me);
UINT32 compute_crf_mask(UINT8 crm);
UINT32 compute_spr(UINT32 spr);
void code_flush_cache();
void code_compile_block(UINT8 mode, offs_t pc);
void static_generate_entry_point();
void static_generate_nocode_handler();
void static_generate_out_of_cycles();
void static_generate_tlb_mismatch();
void static_generate_exception(UINT8 exception, int recover, const char *name);
void static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, uml::code_handle *&handleptr, uml::code_handle *masked);
void static_generate_swap_tgpr();
void static_generate_lsw_entries(int mode);
void static_generate_stsw_entries(int mode);
void generate_update_mode(drcuml_block *block);
void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void generate_compute_flags(drcuml_block *block, const opcode_desc *desc, int updatecr, UINT32 xermask, int invertcarry);
void generate_shift_flags(drcuml_block *block, const opcode_desc *desc, UINT32 op);
void generate_fp_flags(drcuml_block *block, const opcode_desc *desc, int updatefprf);
void generate_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int source, UINT8 link);
void generate_branch_bo(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 bo, UINT32 bi, int source, int link);
int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
int generate_instruction_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
int generate_instruction_1f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
int generate_instruction_3b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
int generate_instruction_3f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op);
const char *log_desc_flags_to_string(UINT32 flags);
void log_register_list(drcuml_state *drcuml, const char *string, const UINT32 *reglist, const UINT32 *regnostarlist);
void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent);
};
//class ppc403_device : public ppc_device
//{
//public:
// ppc403_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
//
//protected:
// virtual UINT32 execute_input_lines() const { return 8; }
//};
//
//
//class ppc405_device : public ppc_device
//{
//public:
// ppc405_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
//
//protected:
// virtual UINT32 execute_input_lines() const { return 8; }
//};
class ppc603_device : public ppc_device
{
public:
ppc603_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class ppc603e_device : public ppc_device
{
public:
ppc603e_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class ppc603r_device : public ppc_device
{
public:
ppc603r_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class ppc602_device : public ppc_device
{
public:
ppc602_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class mpc8240_device : public ppc_device
{
public:
mpc8240_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class ppc601_device : public ppc_device
{
public:
ppc601_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class ppc604_device : public ppc_device
{
public:
ppc604_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class ppc4xx_device : public ppc_device
{
public:
ppc4xx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, powerpc_flavor flavor, UINT32 cap, UINT32 tb_divisor);
void ppc4xx_spu_set_tx_handler(ppc4xx_spu_tx_handler handler);
void ppc4xx_spu_receive_byte(UINT8 byteval);
void ppc4xx_set_dma_read_handler(int channel, ppc4xx_dma_read_handler handler, int rate);
void ppc4xx_set_dma_write_handler(int channel, ppc4xx_dma_write_handler handler, int rate);
void ppc4xx_set_dcr_read_handler(read32_delegate dcr_read_func);
void ppc4xx_set_dcr_write_handler(write32_delegate dcr_write_func);
DECLARE_READ8_MEMBER( ppc4xx_spu_r );
DECLARE_WRITE8_MEMBER( ppc4xx_spu_w );
protected:
virtual UINT32 execute_input_lines() const { return 5; }
virtual void execute_set_input(int inputnum, int state);
};
CPU_GET_INFO( ppc403ga );
class ppc403ga_device : public ppc4xx_device
{
public:
ppc403ga_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
ppc403ga_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
extern const device_type PPC403GA;
CPU_GET_INFO( ppc403gcx );
class ppc403gcx_device : public ppc4xx_device
{
public:
ppc403gcx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
ppc403gcx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
extern const device_type PPC403GCX;
CPU_GET_INFO( ppc405gp );
class ppc405gp_device : public ppc4xx_device
{
public:
ppc405gp_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
ppc405gp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
extern const device_type PPC405GP;
DECLARE_LEGACY_CPU_DEVICE(PPC601, ppc601);
DECLARE_LEGACY_CPU_DEVICE(PPC602, ppc602);
DECLARE_LEGACY_CPU_DEVICE(PPC603, ppc603);
DECLARE_LEGACY_CPU_DEVICE(PPC603E, ppc603e);
DECLARE_LEGACY_CPU_DEVICE(PPC603R, ppc603r);
DECLARE_LEGACY_CPU_DEVICE(PPC604, ppc604);
DECLARE_LEGACY_CPU_DEVICE(MPC8240, mpc8240);
extern const device_type PPC601;
extern const device_type PPC602;
extern const device_type PPC603;
extern const device_type PPC603E;
extern const device_type PPC603R;
extern const device_type PPC604;
extern const device_type MPC8240;
extern const device_type PPC403GA;
extern const device_type PPC403GCX;
extern const device_type PPC405GP;
#endif /* __PPC_H__ */

2218
src/emu/cpu/powerpc/ppccom.c
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187
src/emu/cpu/powerpc/ppccom.h
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@ -12,13 +12,39 @@
#define __PPCCOM_H__
#include "ppc.h"
#include "cpu/vtlb.h"
/***************************************************************************
DEBUGGING
***************************************************************************/
#define LOG_UML (0)
#define LOG_NATIVE (0)
#define DISABLE_FLAG_OPTIMIZATIONS (0)
#define DISABLE_FAST_REGISTERS (0)
#define SINGLE_INSTRUCTION_MODE (0)
#define PRINTF_EXCEPTIONS (0)
#define PRINTF_MMU (0)
#define PROBE_ADDRESS ~0
/***************************************************************************
CONSTANTS
***************************************************************************/
/* size of the execution code cache */
#define CACHE_SIZE (32 * 1024 * 1024)
/* compilation boundaries -- how far back/forward does the analysis extend? */
#define COMPILE_BACKWARDS_BYTES 128
#define COMPILE_FORWARDS_BYTES 512
#define COMPILE_MAX_INSTRUCTIONS ((COMPILE_BACKWARDS_BYTES/4) + (COMPILE_FORWARDS_BYTES/4))
#define COMPILE_MAX_SEQUENCE 64
/* core parameters */
#define POWERPC_MIN_PAGE_SHIFT 12
#define POWERPC_MIN_PAGE_SIZE (1 << POWERPC_MIN_PAGE_SHIFT)
@ -43,39 +69,6 @@
#define PPCCAP_601BAT 0x80 /* TRUE if we're doing 601-style BATs (unified I/D, different bit layout) */
#define PPCCAP_604_MMU 0x100 /* TRUE if we have 604-class MMU features */
/* PowerPC flavors */
enum powerpc_flavor
{
PPC_MODEL_403GA = 0x00200000,
PPC_MODEL_403GB = 0x00200100,
PPC_MODEL_403GC = 0x00200200,
PPC_MODEL_403GCX = 0x00201400,
PPC_MODEL_405GP = 0x40110000,
PPC_MODEL_601 = 0x00010000,
PPC_MODEL_603 = 0x00030000, /* "Wart" */
PPC_MODEL_604 = 0x00040000, /* "Zephyr" */
PPC_MODEL_602 = 0x00050200, /* "Galahad" */
PPC_MODEL_603E = 0x00060103, /* "Stretch", version 1.3 */
PPC_MODEL_603EV = 0x00070000, /* "Valiant" */
PPC_MODEL_603R = 0x00071202, /* "Goldeneye", version 2.1 */
PPC_MODEL_740 = 0x00080301, /* "Arthur", version 3.1 */
PPC_MODEL_750 = PPC_MODEL_740,
PPC_MODEL_740P = 0x00080202, /* "Conan Doyle", version 1.2 */
PPC_MODEL_750P = PPC_MODEL_740P,
PPC_MODEL_755 = 0x00083203, /* "Goldfinger", version 2.3 */
PPC_MODEL_7400 = 0x000c0209, /* "Max", version 2.9 */
PPC_MODEL_7410 = 0x800c1104, /* "Nitro", version 3.4 */
PPC_MODEL_7450 = 0x80000201, /* "Vger", version 2.1 */
PPC_MODEL_7451 = 0x80000203, /* "Vger", version 2.3 */
PPC_MODEL_7441 = PPC_MODEL_7451,
PPC_MODEL_7455 = 0x80010303, /* "Apollo 6", version 3.3 */
PPC_MODEL_7445 = PPC_MODEL_7455,
PPC_MODEL_7457 = 0x80020101, /* "Apollo 7", version 1.1 */
PPC_MODEL_MPC8240 = 0x00810101, /* "Kahlua" */
PPC_MODEL_MPC8241 = 0x80811014, /* "Kahlua Lt" */
PPC_MODEL_MPC8245 = 0x80811014, /* "Kahlua II" */
};
/* exception types */
enum
@ -485,130 +478,4 @@ enum
/***************************************************************************
STRUCTURES & TYPEDEFS
***************************************************************************/
/* PowerPC 4XX-specific serial port state */
struct ppc4xx_spu_state
{
UINT8 regs[9];
UINT8 txbuf;
UINT8 rxbuf;
emu_timer * timer;
UINT8 rxbuffer[256];
UINT32 rxin, rxout;
ppc4xx_spu_tx_handler tx_handler;
};
/* forward declaration of implementation-specific state */
struct ppcimp_state;
/* PowerPC state */
struct powerpc_state
{
/* core registers */
UINT32 pc;
int icount;
UINT32 r[32];
double f[32];
UINT32 cr[8];
UINT32 xerso;
UINT32 fpscr;
UINT32 msr;
UINT32 sr[16];
UINT32 spr[1024];
UINT32 dcr[256];
/* parameters for calls */
UINT32 param0;
UINT32 param1;
/* MMU */
vtlb_state * vtlb;
/* architectural distinctions */
powerpc_flavor flavor;
UINT32 cap;
UINT8 cache_line_size;
UINT32 tb_divisor;
/* PowerPC 4xx-specific state */
ppc4xx_spu_state spu;
emu_timer * fit_timer;
emu_timer * pit_timer;
emu_timer * wdog_timer;
UINT32 pit_reload;
UINT32 irqstate;
emu_timer * buffered_dma_timer[4];
int buffered_dma_rate[4];
/* PowerPC 603-specific state */
UINT32 mmu603_cmp;
UINT32 mmu603_hash[2];
UINT32 mmu603_r[4];
/* internal stuff */
device_irq_acknowledge_delegate irq_callback;
legacy_cpu_device * device;
address_space *program;
direct_read_data *direct;
offs_t codexor;
UINT32 irq_pending;
UINT32 system_clock;
UINT32 cpu_clock;
UINT64 tb_zero_cycles;
UINT64 dec_zero_cycles;
emu_timer * decrementer_int_timer;
/* for use by specific implementations */
ppcimp_state * impstate;
read32_delegate dcr_read_func;
write32_delegate dcr_write_func;
ppc_dcstore_handler dcstore_handler;
ppc4xx_dma_read_handler ext_dma_read_handler[4];
ppc4xx_dma_write_handler ext_dma_write_handler[4];
};
/***************************************************************************
FUNCTION PROTOTYPES
***************************************************************************/
void ppccom_init(powerpc_state *ppc, powerpc_flavor flavor, UINT32 cap, int tb_divisor, legacy_cpu_device *device, device_irq_acknowledge_delegate irqcallback);
void ppccom_exit(powerpc_state *ppc);
void ppccom_reset(powerpc_state *ppc);
offs_t ppccom_dasm(powerpc_state *ppc, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
int ppccom_translate_address(powerpc_state *ppc, address_spacenum space, int intention, offs_t *address);
void ppccom_set_info(powerpc_state *ppc, UINT32 state, cpuinfo *info);
void ppccom_get_info(powerpc_state *ppc, UINT32 state, cpuinfo *info);
void ppccom_tlb_fill(powerpc_state *ppc);
void ppccom_tlb_flush(powerpc_state *ppc);
void ppccom_execute_tlbie(powerpc_state *ppc);
void ppccom_execute_tlbia(powerpc_state *ppc);
void ppccom_execute_tlbl(powerpc_state *ppc);
void ppccom_execute_mftb(powerpc_state *ppc);
void ppccom_execute_mfspr(powerpc_state *ppc);
void ppccom_execute_mtspr(powerpc_state *ppc);
void ppccom_execute_mfdcr(powerpc_state *ppc);
void ppccom_execute_mtdcr(powerpc_state *ppc);
void ppccom_update_fprf(powerpc_state *ppc);
void ppccom_dcstore_callback(powerpc_state *ppc);
void ppc4xx_set_info(powerpc_state *ppc, UINT32 state, cpuinfo *info);
void ppc4xx_get_info(powerpc_state *ppc, UINT32 state, cpuinfo *info);
#endif /* __PPCCOM_H__ */

2613
src/emu/cpu/powerpc/ppcdrc.c
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82
src/emu/cpu/powerpc/ppcfe.c
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@ -56,9 +56,9 @@
// ppc_frontend - constructor
//-------------------------------------------------
ppc_frontend::ppc_frontend(powerpc_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
: drc_frontend(*state.device, window_start, window_end, max_sequence),
m_context(state)
ppc_frontend::ppc_frontend(ppc_device *ppc, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
: drc_frontend(*ppc, window_start, window_end, max_sequence),
m_ppc(ppc)
{
}
@ -74,7 +74,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
int regnum;
// compute the physical PC
if (!ppccom_translate_address(&m_context, AS_PROGRAM, TRANSLATE_FETCH, &desc.physpc))
if (!m_ppc->memory_translate(AS_PROGRAM, TRANSLATE_FETCH, desc.physpc))
{
// uh-oh: a page fault; leave the description empty and just if this is the first instruction, leave it empty and
// mark as needing to validate; otherwise, just end the sequence here
@ -83,7 +83,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
}
// fetch the opcode
op = desc.opptr.l[0] = m_context.direct->read_decrypted_dword(desc.physpc, m_context.codexor);
op = desc.opptr.l[0] = m_ppc->m_direct->read_decrypted_dword(desc.physpc, m_ppc->m_codexor);
// all instructions are 4 bytes and default to a single cycle each
desc.length = 4;
@ -172,7 +172,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return true;
case 0x11: // SC
if (!(m_context.cap & (PPCCAP_OEA | PPCCAP_4XX)))
if (!(m_ppc->m_cap & (PPCCAP_OEA | PPCCAP_4XX)))
return false;
desc.flags |= OPFLAG_WILL_CAUSE_EXCEPTION;
if (is_601_class())
@ -305,7 +305,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
case 0x30: // LFS
case 0x32: // LFD
if (!(m_context.cap & PPCCAP_FPU))
if (!(m_ppc->m_cap & PPCCAP_FPU))
return false;
GPR_USED_OR_ZERO(desc, G_RA(op));
FPR_MODIFIED(desc, G_RD(op));
@ -314,7 +314,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
case 0x31: // LFSU
case 0x33: // LFDU
if (!(m_context.cap & PPCCAP_FPU))
if (!(m_ppc->m_cap & PPCCAP_FPU))
return false;
if (G_RA(op) == 0)
return false;
@ -326,7 +326,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
case 0x34: // STFS
case 0x36: // STFD
if (!(m_context.cap & PPCCAP_FPU))
if (!(m_ppc->m_cap & PPCCAP_FPU))
return false;
GPR_USED_OR_ZERO(desc, G_RA(op));
FPR_USED(desc, G_RS(op));
@ -335,7 +335,7 @@ bool ppc_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
case 0x35: // STFSU
case 0x37: // STFDU
if (!(m_context.cap & PPCCAP_FPU))
if (!(m_ppc->m_cap & PPCCAP_FPU))
return false;
if (G_RA(op) == 0)
return false;
@ -411,7 +411,7 @@ bool ppc_frontend::describe_13(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x032: // RFI
if (!(m_context.cap & (PPCCAP_OEA | PPCCAP_4XX)))
if (!(m_ppc->m_cap & (PPCCAP_OEA | PPCCAP_4XX)))
return false;
desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CHANGE_MODES | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE | OPFLAG_CAN_CAUSE_EXCEPTION;
desc.targetpc = BRANCH_TARGET_DYNAMIC;
@ -424,14 +424,14 @@ bool ppc_frontend::describe_13(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x033: // RFCI
if (!(m_context.cap & PPCCAP_4XX))
if (!(m_ppc->m_cap & PPCCAP_4XX))
return false;
desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CHANGE_MODES | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE | OPFLAG_CAN_CAUSE_EXCEPTION;
desc.targetpc = BRANCH_TARGET_DYNAMIC;
return true;
case 0x096: // ISYNC
if (!(m_context.cap & (PPCCAP_VEA | PPCCAP_4XX)))
if (!(m_ppc->m_cap & (PPCCAP_VEA | PPCCAP_4XX)))
return false;
if (is_601_class())
desc.cycles = 6; // 601
@ -709,7 +709,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x136: // ECIWX
if (!(m_context.cap & PPCCAP_VEA))
if (!(m_ppc->m_cap & PPCCAP_VEA))
return false;
case 0x014: // LWARX
case 0x017: // LWZX
@ -774,14 +774,14 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
case 0x116: // DCBT
case 0x2f6: // DCBA
case 0x3d6: // ICBI
if (!(m_context.cap & (PPCCAP_VEA | PPCCAP_4XX)))
if (!(m_ppc->m_cap & (PPCCAP_VEA | PPCCAP_4XX)))
return false;
GPR_USED_OR_ZERO(desc, G_RA(op));
GPR_USED(desc, G_RB(op));
return true;
case 0x1d6: // DCBI
if (!(m_context.cap & (PPCCAP_OEA | PPCCAP_4XX)))
if (!(m_ppc->m_cap & (PPCCAP_OEA | PPCCAP_4XX)))
return false;
GPR_USED_OR_ZERO(desc, G_RA(op));
GPR_USED(desc, G_RB(op));
@ -817,11 +817,11 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
}
if (spr & 0x010)
desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION;
if ((m_context.cap & PPCCAP_4XX) && spr == SPR4XX_TBLU)
if ((m_ppc->m_cap & PPCCAP_4XX) && spr == SPR4XX_TBLU)
desc.cycles = POWERPC_COUNT_READ_TBL;
else if ((m_context.cap & PPCCAP_VEA) && spr == SPRVEA_TBL_R)
else if ((m_ppc->m_cap & PPCCAP_VEA) && spr == SPRVEA_TBL_R)
desc.cycles = POWERPC_COUNT_READ_TBL;
else if ((m_context.cap & PPCCAP_OEA) && spr == SPROEA_DEC)
else if ((m_ppc->m_cap & PPCCAP_OEA) && spr == SPROEA_DEC)
desc.cycles = POWERPC_COUNT_READ_DEC;
return true;
@ -844,7 +844,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x173: // MFTB
if (!(m_context.cap & PPCCAP_VEA))
if (!(m_ppc->m_cap & PPCCAP_VEA))
return false;
GPR_MODIFIED(desc, G_RD(op));
spr = compute_spr(G_SPR(op));
@ -893,7 +893,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x0d2: // MTSR
if (!(m_context.cap & PPCCAP_OEA))
if (!(m_ppc->m_cap & PPCCAP_OEA))
return false;
GPR_USED(desc, G_RS(op));
desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION;
@ -918,7 +918,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x1b6: // ECOWX
if (!(m_context.cap & PPCCAP_VEA))
if (!(m_ppc->m_cap & PPCCAP_VEA))
return false;
case 0x096: // STWCX.
case 0x097: // STWX
@ -945,7 +945,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x0f2: // MTSRIN
if (!(m_context.cap & PPCCAP_OEA))
if (!(m_ppc->m_cap & PPCCAP_OEA))
return false;
GPR_USED(desc, G_RS(op));
GPR_USED(desc, G_RB(op));
@ -953,21 +953,21 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x132: // TLBIE
if (!(m_context.cap & PPCCAP_OEA))
if (!(m_ppc->m_cap & PPCCAP_OEA))
return false;
GPR_USED(desc, G_RB(op));
desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION;
return true;
case 0x172: // TLBIA
if (!(m_context.cap & PPCCAP_OEA) || (m_context.cap & PPCCAP_603_MMU))
if (!(m_ppc->m_cap & PPCCAP_OEA) || (m_ppc->m_cap & PPCCAP_603_MMU))
return false;
desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION;
return true;
case 0x3d2: // TLBLD
case 0x3f2: // TLBLI
if (!(m_context.cap & PPCCAP_603_MMU) && !is_602_class())
if (!(m_ppc->m_cap & PPCCAP_603_MMU) && !is_602_class())
return false;
desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION;
return true;
@ -993,7 +993,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
case 0x217: // LFSX
case 0x257: // LFDX
if (!(m_context.cap & PPCCAP_FPU))
if (!(m_ppc->m_cap & PPCCAP_FPU))
return false;
GPR_USED_OR_ZERO(desc, G_RA(op));
GPR_USED(desc, G_RB(op));
@ -1002,7 +1002,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x236: // TLBSYNC
if (!(m_context.cap & PPCCAP_OEA))
if (!(m_ppc->m_cap & PPCCAP_OEA))
return false;
desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION;
return true;
@ -1011,13 +1011,13 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x356: // EIEIO
if (!(m_context.cap & (PPCCAP_VEA | PPCCAP_4XX)))
if (!(m_ppc->m_cap & (PPCCAP_VEA | PPCCAP_4XX)))
return false;
return true;
case 0x237: // LFSUX
case 0x277: // LFDUX
if (!(m_context.cap & PPCCAP_FPU))
if (!(m_ppc->m_cap & PPCCAP_FPU))
return false;
if (G_RA(op) == 0)
return false;
@ -1056,7 +1056,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
case 0x297: // STFSX
case 0x2d7: // STFDX
case 0x3d7: // STFIWX
if (!(m_context.cap & PPCCAP_FPU))
if (!(m_ppc->m_cap & PPCCAP_FPU))
return false;
GPR_USED_OR_ZERO(desc, G_RA(op));
GPR_USED(desc, G_RB(op));
@ -1066,7 +1066,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
case 0x2b7: // STFSUX
case 0x2f7: // STFDUX
if (!(m_context.cap & PPCCAP_FPU))
if (!(m_ppc->m_cap & PPCCAP_FPU))
return false;
if (G_RA(op) == 0)
return false;
@ -1089,7 +1089,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x3f6: // DCBZ
if (!(m_context.cap & (PPCCAP_VEA | PPCCAP_4XX)))
if (!(m_ppc->m_cap & (PPCCAP_VEA | PPCCAP_4XX)))
return false;
GPR_USED_OR_ZERO(desc, G_RA(op));
GPR_USED(desc, G_RB(op));
@ -1099,7 +1099,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
case 0x106: // ICBT
case 0x1c6: // DCCCI
case 0x3c6: // ICCCI
if (!(m_context.cap & PPCCAP_4XX))
if (!(m_ppc->m_cap & PPCCAP_4XX))
return false;
GPR_USED_OR_ZERO(desc, G_RA(op));
GPR_USED(desc, G_RB(op));
@ -1108,7 +1108,7 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
case 0x1e6: // DCREAD
case 0x3e6: // ICREAD
if (!(m_context.cap & PPCCAP_4XX))
if (!(m_ppc->m_cap & PPCCAP_4XX))
return false;
GPR_USED_OR_ZERO(desc, G_RA(op));
GPR_USED(desc, G_RB(op));
@ -1117,28 +1117,28 @@ bool ppc_frontend::describe_1f(UINT32 op, opcode_desc &desc, const opcode_desc *
return true;
case 0x143: // MFDCR
if (!(m_context.cap & PPCCAP_4XX))
if (!(m_ppc->m_cap & PPCCAP_4XX))
return false;
GPR_MODIFIED(desc, G_RD(op));
desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION;
return true;
case 0x1c3: // MTDCR
if (!(m_context.cap & PPCCAP_4XX))
if (!(m_ppc->m_cap & PPCCAP_4XX))
return false;
GPR_USED(desc, G_RS(op));
desc.flags |= OPFLAG_PRIVILEGED | OPFLAG_CAN_CAUSE_EXCEPTION | OPFLAG_CAN_EXPOSE_EXTERNAL_INT;
return true;
case 0x083: // WRTEE
if (!(m_context.cap & PPCCAP_4XX))
if (!(m_ppc->m_cap & PPCCAP_4XX))
return false;
GPR_USED(desc, G_RS(op));
desc.flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT;
return true;
case 0x0a3: // WRTEEI
if (!(m_context.cap & PPCCAP_4XX))
if (!(m_ppc->m_cap & PPCCAP_4XX))
return false;
if (op & MSR_EE)
desc.flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT;
@ -1166,7 +1166,7 @@ bool ppc_frontend::describe_3b(UINT32 op, opcode_desc &desc, const opcode_desc *
{
UINT32 opswitch = (op >> 1) & 0x1f;
if (!(m_context.cap & PPCCAP_FPU))
if (!(m_ppc->m_cap & PPCCAP_FPU))
return false;
switch (opswitch)
@ -1242,7 +1242,7 @@ bool ppc_frontend::describe_3f(UINT32 op, opcode_desc &desc, const opcode_desc *
{
UINT32 opswitch = (op >> 1) & 0x3ff;
if (!(m_context.cap & PPCCAP_FPU))
if (!(m_ppc->m_cap & PPCCAP_FPU))
return false;
if (opswitch & 0x10)

14
src/emu/cpu/powerpc/ppcfe.h
View File

@ -11,7 +11,7 @@
#ifndef __PPCFE_H__
#define __PPCFE_H__
#include "ppccom.h"
#include "ppc.h"
#include "cpu/drcfe.h"
@ -49,7 +49,7 @@ class ppc_frontend : public drc_frontend
{
public:
// construction/destruction
ppc_frontend(powerpc_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence);
ppc_frontend(ppc_device *ppc, UINT32 window_start, UINT32 window_end, UINT32 max_sequence);
protected:
// required overrides
@ -58,10 +58,10 @@ protected:
private:
// inlines
UINT32 compute_spr(UINT32 spr) const { return ((spr >> 5) | (spr << 5)) & 0x3ff; }
bool is_403_class() const { return (m_context.flavor == PPC_MODEL_403GA || m_context.flavor == PPC_MODEL_403GB || m_context.flavor == PPC_MODEL_403GC || m_context.flavor == PPC_MODEL_403GCX || m_context.flavor == PPC_MODEL_405GP); }
bool is_601_class() const { return (m_context.flavor == PPC_MODEL_601); }
bool is_602_class() const { return (m_context.flavor == PPC_MODEL_602); }
bool is_603_class() const { return (m_context.flavor == PPC_MODEL_603 || m_context.flavor == PPC_MODEL_603E || m_context.flavor == PPC_MODEL_603EV || m_context.flavor == PPC_MODEL_603R); }
bool is_403_class() const { return (m_ppc->m_flavor == ppc_device::PPC_MODEL_403GA || m_ppc->m_flavor == ppc_device::PPC_MODEL_403GB || m_ppc->m_flavor == ppc_device::PPC_MODEL_403GC || m_ppc->m_flavor == ppc_device::PPC_MODEL_403GCX || m_ppc->m_flavor == ppc_device::PPC_MODEL_405GP); }
bool is_601_class() const { return (m_ppc->m_flavor == ppc_device::PPC_MODEL_601); }
bool is_602_class() const { return (m_ppc->m_flavor == ppc_device::PPC_MODEL_602); }
bool is_603_class() const { return (m_ppc->m_flavor == ppc_device::PPC_MODEL_603 || m_ppc->m_flavor == ppc_device::PPC_MODEL_603E || m_ppc->m_flavor == ppc_device::PPC_MODEL_603EV || m_ppc->m_flavor == ppc_device::PPC_MODEL_603R); }
// internal helpers
bool describe_13(UINT32 op, opcode_desc &desc, const opcode_desc *prev);
@ -70,7 +70,7 @@ private:
bool describe_3f(UINT32 op, opcode_desc &desc, const opcode_desc *prev);
// internal state
powerpc_state &m_context;
ppc_device *m_ppc;
};

10
src/emu/drivers/testcpu.c
View File

@ -97,7 +97,7 @@ public:
m_space = &m_cpu->space(AS_PROGRAM);
// configure DRC in the most compatible mode
ppcdrc_set_options(m_cpu, PPCDRC_COMPATIBLE_OPTIONS);
m_cpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
// set a timer to go off right away
timer_set(attotime::zero);
@ -185,17 +185,11 @@ ADDRESS_MAP_END
// MACHINE DRIVERS
//**************************************************************************
static const powerpc_config ppc_config =
{
// 603e, Stretch, 1.3
66000000 // Multiplier 1, Bus = 66MHz, Core = 66MHz
};
static MACHINE_CONFIG_START( testcpu, testcpu_state )
// CPUs
MCFG_CPU_ADD("maincpu", PPC603E, 66000000)
MCFG_CPU_CONFIG(ppc_config)
MCFG_PPC_BUS_FREQUENCY(66000000) // Multiplier 1, Bus = 66MHz, Core = 66MHz
MCFG_CPU_PROGRAM_MAP(ppc_mem)
MACHINE_CONFIG_END

32
src/mame/drivers/cobra.c
View File

@ -617,9 +617,9 @@ public:
{
}
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_subcpu;
required_device<cpu_device> m_gfxcpu;
required_device<ppc_device> m_maincpu;
required_device<ppc4xx_device> m_subcpu;
required_device<ppc_device> m_gfxcpu;
required_shared_ptr<UINT64> m_gfx_pagetable;
required_device<k001604_device> m_k001604;
required_device<ata_interface_device> m_ata;
@ -1923,6 +1923,7 @@ static void sub_sound_dma_w(device_t *device, int width, UINT32 data)
static void sub_jvs_w(device_t *device, UINT8 data)
{
cobra_state *cobra = device->machine().driver_data<cobra_state>();
cobra_jvs_host *jvs = downcast<cobra_jvs_host *>(device->machine().device("cobra_jvs_host"));
#if LOG_JVS
@ -1947,7 +1948,7 @@ static void sub_jvs_w(device_t *device, UINT8 data)
for (int i=0; i < rec_size; i++)
{
ppc4xx_spu_receive_byte(device, rec_data[i]);
cobra->m_subcpu->ppc4xx_spu_receive_byte(rec_data[i]);
}
}
}
@ -3116,17 +3117,6 @@ INPUT_PORTS_START( cobra )
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_PLAYER(2)
INPUT_PORTS_END
static powerpc_config main_ppc_cfg =
{
XTAL_66_6667MHz /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */
};
static powerpc_config gfx_ppc_cfg =
{
XTAL_66_6667MHz /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */
};
WRITE_LINE_MEMBER(cobra_state::ide_interrupt)
{
if (state == CLEAR_LINE)
@ -3176,7 +3166,7 @@ static MACHINE_CONFIG_START( cobra, cobra_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", PPC603, 100000000) /* 603EV, 100? MHz */
MCFG_CPU_CONFIG(main_ppc_cfg)
MCFG_PPC_BUS_FREQUENCY(XTAL_66_6667MHz) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */
MCFG_CPU_PROGRAM_MAP(cobra_main_map)
MCFG_CPU_VBLANK_INT_DRIVER("screen", cobra_state, cobra_vblank)
@ -3184,7 +3174,7 @@ static MACHINE_CONFIG_START( cobra, cobra_state )
MCFG_CPU_PROGRAM_MAP(cobra_sub_map)
MCFG_CPU_ADD("gfxcpu", PPC604, 100000000) /* 604, 100? MHz */
MCFG_CPU_CONFIG(gfx_ppc_cfg)
MCFG_PPC_BUS_FREQUENCY(XTAL_66_6667MHz) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */
MCFG_CPU_PROGRAM_MAP(cobra_gfx_map)
MCFG_QUANTUM_TIME(attotime::from_hz(15005))
@ -3273,12 +3263,12 @@ DRIVER_INIT_MEMBER(cobra_state, cobra)
cobra_fifo::event_delegate(FUNC(cobra_state::s2mfifo_event_callback), this))
);
ppc_set_dcstore_callback(m_maincpu, main_cpu_dc_store);
m_maincpu->ppc_set_dcstore_callback(main_cpu_dc_store);
ppc_set_dcstore_callback(m_gfxcpu, gfx_cpu_dc_store);
m_gfxcpu->ppc_set_dcstore_callback(gfx_cpu_dc_store);
ppc4xx_set_dma_write_handler(m_subcpu, 0, sub_sound_dma_w, 44100);
ppc4xx_spu_set_tx_handler(m_subcpu, sub_jvs_w);
m_subcpu->ppc4xx_set_dma_write_handler(0, sub_sound_dma_w, 44100);
m_subcpu->ppc4xx_spu_set_tx_handler(sub_jvs_w);
m_comram[0] = auto_alloc_array(machine(), UINT32, 0x40000/4);

10
src/mame/drivers/firebeat.c
View File

@ -181,7 +181,7 @@ public:
m_ata(*this, "ata")
{ }
required_device<cpu_device> m_maincpu;
required_device<ppc4xx_device> m_maincpu;
required_shared_ptr<UINT32> m_work_ram;
required_device<fujitsu_29f016a_device> m_flash_main;
required_device<fujitsu_29f016a_device> m_flash_snd1;
@ -1483,10 +1483,10 @@ READ16_MEMBER(firebeat_state::spu_unk_r)
MACHINE_START_MEMBER(firebeat_state,firebeat)
{
/* set conservative DRC options */
ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS);
m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x01ffffff, FALSE, m_work_ram);
m_maincpu->ppcdrc_add_fastram(0x00000000, 0x01ffffff, FALSE, m_work_ram);
}
static ADDRESS_MAP_START( firebeat_map, AS_PROGRAM, 32, firebeat_state )
@ -1955,7 +1955,7 @@ static void security_w(device_t *device, UINT8 data)
firebeat_state *state = device->machine().driver_data<firebeat_state>();
int r = state->ibutton_w(data);
if (r >= 0)
ppc4xx_spu_receive_byte(state->m_maincpu, r);
state->m_maincpu->ppc4xx_spu_receive_byte(r);
}
/*****************************************************************************/
@ -1983,7 +1983,7 @@ void firebeat_state::init_firebeat()
m_cur_cab_data = cab_data;
ppc4xx_spu_set_tx_handler(m_maincpu, security_w);
m_maincpu->ppc4xx_spu_set_tx_handler(security_w);
set_ibutton(rom);

6
src/mame/drivers/gticlub.c
View File

@ -265,7 +265,7 @@ public:
static const int m_sound_timer_usec = 2400;
required_shared_ptr<UINT32> m_work_ram;
required_device<cpu_device> m_maincpu;
required_device<ppc_device> m_maincpu;
required_device<cpu_device> m_audiocpu;
required_device<adsp21062_device> m_dsp;
optional_device<cpu_device> m_dsp2;
@ -479,10 +479,10 @@ WRITE16_MEMBER(gticlub_state::soundtimer_count_w)
MACHINE_START_MEMBER(gticlub_state,gticlub)
{
/* set conservative DRC options */
ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS);
m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x000fffff, FALSE, m_work_ram);
m_maincpu->ppcdrc_add_fastram(0x00000000, 0x000fffff, FALSE, m_work_ram);
m_sound_irq_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(gticlub_state::sound_irq), this));
}

28
src/mame/drivers/hornet.c
View File

@ -357,7 +357,7 @@ public:
required_shared_ptr<UINT32> m_workram;
required_shared_ptr<UINT32> m_sharc_dataram0;
optional_shared_ptr<UINT32> m_sharc_dataram1;
required_device<cpu_device> m_maincpu;
required_device<ppc4xx_device> m_maincpu;
required_device<cpu_device> m_audiocpu;
required_device<k056800_device> m_k056800;
optional_device<cpu_device> m_gn680;
@ -919,10 +919,10 @@ void hornet_state::machine_start()
m_jvs_sdata = auto_alloc_array_clear(machine(), UINT8, 1024);
/* set conservative DRC options */
ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS);
m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x003fffff, FALSE, m_workram);
m_maincpu->ppcdrc_add_fastram(0x00000000, 0x003fffff, FALSE, m_workram);
save_item(NAME(m_led_reg0));
save_item(NAME(m_led_reg1));
@ -1161,19 +1161,19 @@ int hornet_state::jvs_encode_data(UINT8 *in, int length)
if (b == 0xe0)
{
sum += 0xd0 + 0xdf;
ppc4xx_spu_receive_byte(m_maincpu, 0xd0);
ppc4xx_spu_receive_byte(m_maincpu, 0xdf);
m_maincpu->ppc4xx_spu_receive_byte(0xd0);
m_maincpu->ppc4xx_spu_receive_byte(0xdf);
}
else if (b == 0xd0)
{
sum += 0xd0 + 0xcf;
ppc4xx_spu_receive_byte(m_maincpu, 0xd0);
ppc4xx_spu_receive_byte(m_maincpu, 0xcf);
m_maincpu->ppc4xx_spu_receive_byte(0xd0);
m_maincpu->ppc4xx_spu_receive_byte(0xcf);
}
else
{
sum += b;
ppc4xx_spu_receive_byte(m_maincpu, b);
m_maincpu->ppc4xx_spu_receive_byte(b);
}
}
return sum;
@ -1266,11 +1266,11 @@ void hornet_state::jamma_jvs_cmd_exec()
// write jvs return data
sum = 0x00 + (rdata_ptr+1);
ppc4xx_spu_receive_byte(m_maincpu, 0xe0); // sync
ppc4xx_spu_receive_byte(m_maincpu, 0x00); // node
ppc4xx_spu_receive_byte(m_maincpu, rdata_ptr + 1); // num of bytes
m_maincpu->ppc4xx_spu_receive_byte(0xe0); // sync
m_maincpu->ppc4xx_spu_receive_byte(0x00); // node
m_maincpu->ppc4xx_spu_receive_byte(rdata_ptr + 1); // num of bytes
sum += jvs_encode_data(rdata, rdata_ptr);
ppc4xx_spu_receive_byte(m_maincpu, sum - 1); // checksum
m_maincpu->ppc4xx_spu_receive_byte(sum - 1); // checksum
m_jvs_sdata_ptr = 0;
}
@ -1283,7 +1283,7 @@ DRIVER_INIT_MEMBER(hornet_state,hornet)
m_konppc->set_cgboard_texture_bank(0, "bank5", memregion("user5")->base());
m_led_reg0 = m_led_reg1 = 0x7f;
ppc4xx_spu_set_tx_handler(m_maincpu, jamma_jvs_w);
m_maincpu->ppc4xx_spu_set_tx_handler(jamma_jvs_w);
}
DRIVER_INIT_MEMBER(hornet_state,hornet_2board)
@ -1292,7 +1292,7 @@ DRIVER_INIT_MEMBER(hornet_state,hornet_2board)
m_konppc->set_cgboard_texture_bank(1, "bank6", memregion("user5")->base());
m_led_reg0 = m_led_reg1 = 0x7f;
ppc4xx_spu_set_tx_handler(m_maincpu, jamma_jvs_w);
m_maincpu->ppc4xx_spu_set_tx_handler(jamma_jvs_w);
}
/*****************************************************************************/

9
src/mame/drivers/konamim2.c
View File

@ -1148,11 +1148,6 @@ static INPUT_PORTS_START( m2 )
INPUT_PORTS_END
static const powerpc_config ppc602_config =
{
33000000 /* Multiplier 2, Bus = 33MHz, Core = 66MHz */
};
INTERRUPT_GEN_MEMBER(konamim2_state::m2)
{
if (m_irq_enable & 0x800000)
@ -1172,12 +1167,12 @@ static MACHINE_CONFIG_START( m2, konamim2_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", PPC602, 66000000) /* actually PPC602, 66MHz */
MCFG_CPU_CONFIG(ppc602_config)
MCFG_PPC_BUS_FREQUENCY(33000000) /* Multiplier 2, Bus = 33MHz, Core = 66MHz */
MCFG_CPU_PROGRAM_MAP(m2_main)
MCFG_CPU_VBLANK_INT_DRIVER("screen", konamim2_state, m2)
MCFG_CPU_ADD("sub", PPC602, 66000000) /* actually PPC602, 66MHz */
MCFG_CPU_CONFIG(ppc602_config)
MCFG_PPC_BUS_FREQUENCY(33000000) /* Multiplier 2, Bus = 33MHz, Core = 66MHz */
MCFG_CPU_PROGRAM_MAP(m2_main)
/* video hardware */

30
src/mame/drivers/model3.c
View File

@ -1184,10 +1184,10 @@ static void configure_fast_ram(running_machine &machine)
{
model3_state *state = machine.driver_data<model3_state>();
/* set conservative DRC options */
ppcdrc_set_options(machine.device("maincpu"), PPCDRC_COMPATIBLE_OPTIONS - PPCDRC_ACCURATE_SINGLES);
machine.device<ppc_device>("maincpu")->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS - PPCDRC_ACCURATE_SINGLES);
/* configure fast RAM regions for DRC */
ppcdrc_add_fastram(machine.device("maincpu"), 0x00000000, 0x007fffff, FALSE, state->m_work_ram);
machine.device<ppc_device>("maincpu")->ppcdrc_add_fastram(0x00000000, 0x007fffff, FALSE, state->m_work_ram);
}
TIMER_CALLBACK_MEMBER(model3_state::model3_sound_timer_tick)
@ -5380,27 +5380,9 @@ TIMER_DEVICE_CALLBACK_MEMBER(model3_state::model3_interrupt)
set_irq_line(0x0d, ASSERT_LINE);
}
static const powerpc_config model3_10 =
{
/* 603e, Stretch, 1.3 */
66000000 /* Multiplier 1, Bus = 66MHz, Core = 66MHz */
};
static const powerpc_config model3_15 =
{
/* 603e, Stretch, 1.3 */
66000000 /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */
};
static const powerpc_config model3_2x =
{
/* 603e-PID7t, Goldeneye, 2.1 */
66000000 /* Multiplier 2.5, Bus = 66MHz, Core = 166MHz */
};
static MACHINE_CONFIG_START( model3_10, model3_state )
MCFG_CPU_ADD("maincpu", PPC603E, 66000000)
MCFG_CPU_CONFIG(model3_10)
MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 1, Bus = 66MHz, Core = 66MHz */
MCFG_CPU_PROGRAM_MAP(model3_mem)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", model3_state, model3_interrupt, "screen", 0, 1)
@ -5447,7 +5429,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_START( model3_15, model3_state )
MCFG_CPU_ADD("maincpu", PPC603E, 100000000)
MCFG_CPU_CONFIG(model3_15)
MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */
MCFG_CPU_PROGRAM_MAP(model3_mem)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", model3_state, model3_interrupt, "screen", 0, 1)
@ -5498,7 +5480,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_START( model3_20, model3_state )
MCFG_CPU_ADD("maincpu", PPC603R, 166000000)
MCFG_CPU_CONFIG(model3_2x)
MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 2.5, Bus = 66MHz, Core = 166MHz */
MCFG_CPU_PROGRAM_MAP(model3_mem)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", model3_state, model3_interrupt, "screen", 0, 1)
@ -5535,7 +5517,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_START( model3_21, model3_state )
MCFG_CPU_ADD("maincpu", PPC603R, 166000000)
MCFG_CPU_CONFIG(model3_2x)
MCFG_PPC_BUS_FREQUENCY(66000000) /* Multiplier 2.5, Bus = 66MHz, Core = 166MHz */
MCFG_CPU_PROGRAM_MAP(model3_mem)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", model3_state, model3_interrupt, "screen", 0, 1)

6
src/mame/drivers/nwk-tr.c
View File

@ -256,7 +256,7 @@ public:
UINT8 m_led_reg0;
UINT8 m_led_reg1;
required_shared_ptr<UINT32> m_work_ram;
required_device<cpu_device> m_maincpu;
required_device<ppc_device> m_maincpu;
required_device<cpu_device> m_audiocpu;
required_device<cpu_device> m_dsp;
required_device<k056800_device> m_k056800;
@ -573,10 +573,10 @@ WRITE16_MEMBER(nwktr_state::soundtimer_count_w)
void nwktr_state::machine_start()
{
/* set conservative DRC options */
ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS);
m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x003fffff, FALSE, m_work_ram);
m_maincpu->ppcdrc_add_fastram(0x00000000, 0x003fffff, FALSE, m_work_ram);
m_sound_irq_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(nwktr_state::sound_irq), this));
}

8
src/mame/drivers/taitopjc.c
View File

@ -504,15 +504,9 @@ INTERRUPT_GEN_MEMBER(taitopjc_state::taitopjc_vbi)
}
static const powerpc_config ppc603e_config =
{
XTAL_66_6667MHz /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */
};
static MACHINE_CONFIG_START( taitopjc, taitopjc_state )
MCFG_CPU_ADD("maincpu", PPC603E, 100000000)
MCFG_CPU_CONFIG(ppc603e_config)
MCFG_PPC_BUS_FREQUENCY(XTAL_66_6667MHz) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */
MCFG_CPU_PROGRAM_MAP(ppc603e_mem)
/* TMP95C063F I/O CPU */

14
src/mame/drivers/taitotz.c
View File

@ -547,7 +547,7 @@ public:
{
}
required_device<cpu_device> m_maincpu;
required_device<ppc_device> m_maincpu;
required_device<cpu_device> m_iocpu;
required_shared_ptr<UINT64> m_work_ram;
required_shared_ptr<UINT16> m_mbox_ram;
@ -2641,10 +2641,10 @@ void taitotz_state::machine_reset()
void taitotz_state::machine_start()
{
/* set conservative DRC options */
ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS);
m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
ppcdrc_add_fastram(m_maincpu, 0x40000000, 0x40ffffff, FALSE, m_work_ram);
m_maincpu->ppcdrc_add_fastram(0x40000000, 0x40ffffff, FALSE, m_work_ram);
}
@ -2658,16 +2658,10 @@ WRITE_LINE_MEMBER(taitotz_state::ide_interrupt)
m_iocpu->set_input_line(TLCS900_INT2, state);
}
static const powerpc_config ppc603e_config =
{
XTAL_66_6667MHz /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */
};
static MACHINE_CONFIG_START( taitotz, taitotz_state )
/* IBM EMPPC603eBG-100 */
MCFG_CPU_ADD("maincpu", PPC603E, 100000000)
MCFG_CPU_CONFIG(ppc603e_config)
MCFG_PPC_BUS_FREQUENCY(XTAL_66_6667MHz) /* Multiplier 1.5, Bus = 66MHz, Core = 100MHz */
MCFG_CPU_PROGRAM_MAP(ppc603e_mem)
/* TMP95C063F I/O CPU */

4
src/mame/drivers/triforce.c
View File

@ -439,7 +439,7 @@ public:
virtual void machine_start();
virtual void video_start();
UINT32 screen_update_triforce(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
required_device<cpu_device> m_maincpu;
required_device<ppc_device> m_maincpu;
};
READ64_MEMBER(triforce_state::gc_pi_r)
@ -537,7 +537,7 @@ static void descrambler(UINT8* data, UINT32 size)
void triforce_state::machine_start()
{
/* set conservative DRC options */
ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS);
m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
UINT8 *rom = (UINT8*)memregion("maincpu")->base();
descrambler(&rom[0x100], 0x1afe00);

6
src/mame/drivers/ultrsprt.c
View File

@ -25,7 +25,7 @@ public:
static const UINT32 VRAM_PAGES = 2;
static const UINT32 VRAM_PAGE_BYTES = 512 * 1024;
required_device<cpu_device> m_maincpu;
required_device<ppc_device> m_maincpu;
required_device<cpu_device> m_audiocpu;
required_device<k056800_device> m_k056800;
required_shared_ptr<UINT32> m_workram;
@ -184,10 +184,10 @@ INPUT_PORTS_END
void ultrsprt_state::machine_start()
{
/* set conservative DRC options */
ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS);
m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
ppcdrc_add_fastram(m_maincpu, 0xff000000, 0xff01ffff, FALSE, m_workram);
m_maincpu->ppcdrc_add_fastram(0xff000000, 0xff01ffff, FALSE, m_workram);
m_vram = auto_alloc_array(machine(), UINT8, VRAM_PAGE_BYTES * VRAM_PAGES);

13
src/mame/drivers/viper.c
View File

@ -363,7 +363,7 @@ public:
void mpc8240_epic_reset(void);
int ds2430_insert_cmd_bit(int bit);
void DS2430_w(int bit);
required_device<cpu_device> m_maincpu;
required_device<ppc_device> m_maincpu;
required_device<ata_interface_device> m_ata;
};
@ -1986,11 +1986,6 @@ INPUT_PORTS_END
/*****************************************************************************/
static const powerpc_config viper_ppc_cfg =
{
100000000
};
INTERRUPT_GEN_MEMBER(viper_state::viper_vblank)
{
mpc8240_interrupt(MPC8240_IRQ0);
@ -2009,10 +2004,10 @@ void viper_state::machine_start()
mpc8240_epic_init();
/* set conservative DRC options */
ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS);
m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x00ffffff, FALSE, workram);
m_maincpu->ppcdrc_add_fastram(0x00000000, 0x00ffffff, FALSE, workram);
ds2430_rom = (UINT8*)memregion("ds2430")->base();
}
@ -2033,7 +2028,7 @@ static MACHINE_CONFIG_START( viper, viper_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", MPC8240, 200000000)
MCFG_CPU_CONFIG(viper_ppc_cfg)
MCFG_PPC_BUS_FREQUENCY(100000000)
MCFG_CPU_PROGRAM_MAP(viper_map)
MCFG_CPU_VBLANK_INT_DRIVER("screen", viper_state, viper_vblank)

6
src/mame/drivers/zr107.c
View File

@ -210,7 +210,7 @@ public:
m_konppc(*this, "konppc") { }
required_device<cpu_device> m_maincpu;
required_device<ppc_device> m_maincpu;
required_device<cpu_device> m_audiocpu;
required_device<cpu_device> m_dsp;
optional_device<k001604_device> m_k001604;
@ -457,10 +457,10 @@ WRITE32_MEMBER(zr107_state::ccu_w)
void zr107_state::machine_start()
{
/* set conservative DRC options */
ppcdrc_set_options(m_maincpu, PPCDRC_COMPATIBLE_OPTIONS);
m_maincpu->ppcdrc_set_options(PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
ppcdrc_add_fastram(m_maincpu, 0x00000000, 0x000fffff, FALSE, m_workram);
m_maincpu->ppcdrc_add_fastram(0x00000000, 0x000fffff, FALSE, m_workram);
}
static ADDRESS_MAP_START( zr107_map, AS_PROGRAM, 32, zr107_state )

11
src/mess/drivers/dm7000.c
View File

@ -257,8 +257,8 @@ void dm7000_state::machine_reset()
dcr[DCRSTB045_FRAME_BUFR_BASE] = 0x0f000000;
m_scc0_lsr = UART_LSR_THRE | UART_LSR_TEMT;
ppc4xx_set_dcr_read_handler(m_maincpu, read32_delegate(FUNC(dm7000_state::dcr_r),this));
ppc4xx_set_dcr_write_handler(m_maincpu, write32_delegate(FUNC(dm7000_state::dcr_w),this));
m_maincpu->ppc4xx_set_dcr_read_handler(read32_delegate(FUNC(dm7000_state::dcr_r),this));
m_maincpu->ppc4xx_set_dcr_write_handler(write32_delegate(FUNC(dm7000_state::dcr_w),this));
}
void dm7000_state::video_start()
@ -297,16 +297,11 @@ WRITE8_MEMBER( dm7000_state::kbd_put )
m_scc0_lsr = 1;
}
static const powerpc_config ppc405_config =
{
252000000
};
static MACHINE_CONFIG_START( dm7000, dm7000_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu",PPC405GP, 252000000 / 10) // Should be PPC405D4?
// Slowed down 10 times in order to get normal response for now
MCFG_CPU_CONFIG(ppc405_config)
MCFG_PPC_BUS_FREQUENCY(252000000)
MCFG_CPU_PROGRAM_MAP(dm7000_mem)

2
src/mess/includes/dm7000.h
View File

@ -17,7 +17,7 @@ public:
{
}
required_device<cpu_device> m_maincpu;
required_device<ppc4xx_device> m_maincpu;
required_device<generic_terminal_device> m_terminal;
DECLARE_WRITE8_MEMBER ( dm7000_iic0_w );