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https://github.com/holub/mame
synced 2025-06-30 07:58:56 +03:00
refactor funkball.c flash access to use intelfsh.c via bankdev, doesn't improve anything tho (nw)
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mamehaze
parent
500801d2bc
commit
86b12e10d8
@ -102,6 +102,8 @@ const device_type INTEL_E28F008SA = &device_creator<intel_e28f008sa_device>;
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const device_type INTEL_TE28F160 = &device_creator<intel_te28f160_device>;
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const device_type SHARP_UNK128MBIT = &device_creator<sharp_unk128mbit_device>;
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const device_type INTEL_28F320J3D = &device_creator<intel_28f320j3d_device>;
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const device_type INTEL_28F320J5 = &device_creator<intel_28f320j5_device>;
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const device_type SST_39VF400A = &device_creator<sst_39vf400a_device>;
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static ADDRESS_MAP_START( memory_map8_512Kb, AS_PROGRAM, 8, intelfsh_device )
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@ -246,6 +248,14 @@ intelfsh_device::intelfsh_device(const machine_config &mconfig, device_type type
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m_sector_is_4k = true;
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map = ADDRESS_MAP_NAME( memory_map16_32Mb );
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break;
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case FLASH_INTEL_28F320J5: // funkball
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m_bits = 16;
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m_size = 0x400000;
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m_maker_id = MFG_INTEL;
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m_device_id = 0x14;
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// m_sector_is_4k = true; 128kb?
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map = ADDRESS_MAP_NAME( memory_map16_32Mb );
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break;
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case FLASH_SST_39VF020:
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m_bits = 8;
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m_size = 0x40000;
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@ -446,6 +456,10 @@ sharp_unk128mbit_device::sharp_unk128mbit_device(const machine_config &mconfig,
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intel_28f320j3d_device::intel_28f320j3d_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: intelfsh16_device(mconfig, INTEL_28F320J3D, "Intel 28F320J3D Flash", tag, owner, clock, FLASH_INTEL_28F320J3D, "intel_28f320j3d", __FILE__) { }
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intel_28f320j5_device::intel_28f320j5_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: intelfsh16_device(mconfig, INTEL_28F320J5, "Intel 28F320J3D_a Flash", tag, owner, clock, FLASH_INTEL_28F320J5, "intel_28f320j5", __FILE__) { }
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sst_39vf400a_device::sst_39vf400a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: intelfsh16_device(mconfig, SST_39VF400A, "SST 39VF400A Flash", tag, owner, clock, FLASH_SST_39VF400A, "sst_39vf400a", __FILE__) { }
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@ -82,6 +82,9 @@
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#define MCFG_INTEL_28F320J3D_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, INTEL_28F320J3D, 0)
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#define MCFG_INTEL_28F320J5_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, INTEL_28F320J5, 0)
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#define MCFG_SST_39VF400A_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, SST_39VF400A, 0)
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@ -128,6 +131,7 @@ public:
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FLASH_INTEL_TE28F160,
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FLASH_SHARP_UNK128MBIT,
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FLASH_INTEL_28F320J3D,
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FLASH_INTEL_28F320J5,
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FLASH_SST_39VF400A
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};
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@ -363,6 +367,12 @@ public:
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intel_28f320j3d_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class intel_28f320j5_device : public intelfsh16_device
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{
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public:
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intel_28f320j5_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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};
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class sst_39vf400a_device : public intelfsh16_device
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{
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public:
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@ -397,6 +407,7 @@ extern const device_type INTEL_E28F008SA;
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extern const device_type INTEL_TE28F160;
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extern const device_type SHARP_UNK128MBIT;
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extern const device_type INTEL_28F320J3D;
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extern const device_type INTEL_28F320J5;
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extern const device_type SST_39VF400A;
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#endif
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@ -76,6 +76,8 @@ Notes:
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#include "machine/idectrl.h"
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#include "video/voodoo.h"
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#include "machine/pcshare.h"
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#include "machine/bankdev.h"
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#include "machine/intelfsh.h"
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class funkball_state : public pcat_base_state
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@ -84,27 +86,27 @@ public:
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funkball_state(const machine_config &mconfig, device_type type, const char *tag)
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: pcat_base_state(mconfig, type, tag),
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m_voodoo(*this, "voodoo_0"),
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m_unk_ram(*this, "unk_ram"){ }
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m_unk_ram(*this, "unk_ram"),
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m_flashbank(*this, "flashbank")
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{ }
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UINT8 m_funkball_config_reg_sel;
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UINT8 m_funkball_config_regs[256];
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UINT32 m_cx5510_regs[256/4];
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UINT16 m_flash_addr;
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UINT8 *m_bios_ram;
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UINT8 m_flash_cmd;
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UINT8 m_flash_data_cmd;
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UINT32 m_biu_ctrl_reg[256/4];
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UINT32 flashbank_addr;
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// devices
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required_device<voodoo_1_device> m_voodoo;
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required_shared_ptr<UINT32> m_unk_ram;
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required_device<address_map_bank_device> m_flashbank;
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DECLARE_READ8_MEMBER( get_slave_ack );
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DECLARE_WRITE8_MEMBER( flash_w );
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DECLARE_READ8_MEMBER( flash_data_r );
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DECLARE_WRITE8_MEMBER( flash_data_w );
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DECLARE_WRITE32_MEMBER( flash_w );
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// DECLARE_WRITE8_MEMBER( bios_ram_w );
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DECLARE_READ8_MEMBER( test_r );
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DECLARE_READ8_MEMBER( serial_r );
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@ -272,63 +274,16 @@ WRITE8_MEMBER(funkball_state::io20_w)
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}
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}
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WRITE8_MEMBER( funkball_state::flash_w )
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WRITE32_MEMBER(funkball_state::flash_w)
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{
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if(!(offset & 0x2))
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{
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m_flash_addr = (offset & 1) ? ((m_flash_addr & 0xff) | (data << 8)) : ((m_flash_addr & 0xff00) | (data));
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//printf("%08x ADDR\n",m_flash_addr << 16);
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}
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else if(offset == 2)
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{
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/* 0x83: read from u29/u30
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0x03: read from u3
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0x81: init device
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*/
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m_flash_cmd = data;
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printf("%02x CMD\n",data);
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}
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else
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printf("%02x %02x\n",offset,data);
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COMBINE_DATA(&flashbank_addr);
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int tempbank = (flashbank_addr & 0x7fff) | ((flashbank_addr & 0x00800000) >> 8);
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m_flashbank->set_bank(tempbank);
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// note, other bits get used, but ignoring to keep the virtual bank space size sane.
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}
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READ8_MEMBER( funkball_state::flash_data_r )
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{
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if(m_flash_data_cmd == 0x90)
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{
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if(offset == 0 && (m_flash_addr == 0))
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return 0x89; // manufacturer code
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if(offset == 2 && (m_flash_addr == 0))
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return (m_flash_cmd & 0x80) ? 0x15 : 0x14; // device code, 32 MBit in both cases
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if(offset > 3)
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printf("%02x FLASH DATA 0x90\n",offset);
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return 0;
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}
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if(m_flash_data_cmd == 0xff)
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{
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UINT8 *ROM = memregion(m_flash_cmd & 0x80 ? "data_flash" : "prg_flash")->base();
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return ROM[offset + (m_flash_addr << 16)];
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}
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printf("%02x %08x %02x %02x\n",offset,m_flash_addr << 16,m_flash_cmd,m_flash_data_cmd);
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return 0;
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}
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WRITE8_MEMBER( funkball_state::flash_data_w )
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{
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if(offset == 0)
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{
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m_flash_data_cmd = data;
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}
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else
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printf("%08x %02x FLASH DATA W %08x\n",offset,data,m_flash_addr << 16);
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}
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READ32_MEMBER(funkball_state::biu_ctrl_r)
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{
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@ -378,7 +333,7 @@ READ8_MEMBER( funkball_state::test_r )
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static ADDRESS_MAP_START(funkball_map, AS_PROGRAM, 32, funkball_state)
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AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
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AM_RANGE(0x000a0000, 0x000affff) AM_RAM
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AM_RANGE(0x000b0000, 0x000bffff) AM_READWRITE8(flash_data_r,flash_data_w,0xffffffff)
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AM_RANGE(0x000b0000, 0x000bffff) AM_DEVICE("flashbank", address_map_bank_device, amap32)
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AM_RANGE(0x000c0000, 0x000cffff) AM_RAM
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AM_RANGE(0x000d0000, 0x000dffff) AM_RAM
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AM_RANGE(0x000e0000, 0x000e3fff) AM_ROMBANK("bios_ext1")
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@ -398,6 +353,13 @@ static ADDRESS_MAP_START(funkball_map, AS_PROGRAM, 32, funkball_state)
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AM_RANGE(0xfffe0000, 0xffffffff) AM_ROM AM_REGION("bios", 0) /* System BIOS */
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( flashbank_map, AS_PROGRAM, 32, funkball_state )
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AM_RANGE(0x00000000, 0x003fffff) AM_DEVREADWRITE16("u29", intel_28f320j5_device, read, write, 0xffffffff )
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AM_RANGE(0x00400000, 0x007fffff) AM_DEVREADWRITE16("u30", intel_28f320j5_device, read, write, 0xffffffff )
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AM_RANGE(0x00800000, 0x00bfffff) AM_DEVREADWRITE16("u3", intel_28f320j5_device, read, write, 0xffffffff )
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/* it checks for 64MBit chips at 0x80000000 the way things are set up, they must return an intel Flash ID of 0x15 */
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(funkball_io, AS_IO, 32, funkball_state)
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AM_RANGE(0x0020, 0x0023) AM_READWRITE8(io20_r, io20_w, 0xffff0000)
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AM_IMPORT_FROM(pcat32_io_common)
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@ -409,7 +371,7 @@ static ADDRESS_MAP_START(funkball_io, AS_IO, 32, funkball_state)
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AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
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AM_RANGE(0x0360, 0x0363) AM_WRITE8(flash_w,0xffffffff)
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AM_RANGE(0x0360, 0x0363) AM_WRITE(flash_w)
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// AM_RANGE(0x0320, 0x0323) AM_READ(test_r)
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AM_RANGE(0x0360, 0x036f) AM_READ8(test_r,0xffffffff) // inputs
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@ -862,6 +824,13 @@ static MACHINE_CONFIG_START( funkball, funkball_state )
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MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
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MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
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MCFG_DEVICE_ADD("flashbank", ADDRESS_MAP_BANK, 0)
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MCFG_DEVICE_PROGRAM_MAP(flashbank_map)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
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MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
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MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(64)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x10000)
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/* video hardware */
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MCFG_DEVICE_ADD("voodoo_0", VOODOO_1, STD_VOODOO_1_CLOCK)
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MCFG_VOODOO_FBMEM(2)
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@ -875,18 +844,24 @@ static MACHINE_CONFIG_START( funkball, funkball_state )
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MCFG_SCREEN_UPDATE_DRIVER(funkball_state, screen_update)
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MCFG_SCREEN_SIZE(1024, 1024)
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MCFG_SCREEN_VISIBLE_AREA(0, 511, 16, 447)
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MCFG_INTEL_28F320J5_ADD("u29")
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MCFG_INTEL_28F320J5_ADD("u30")
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MCFG_INTEL_28F320J5_ADD("u3")
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MACHINE_CONFIG_END
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ROM_START( funkball )
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ROM_REGION32_LE(0x20000, "bios", ROMREGION_ERASEFF)
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ROM_LOAD( "512k-epr.u62", 0x010000, 0x010000, CRC(cced894a) SHA1(298c81716e375da4b7215f3e588a45ca3ea7e35c) )
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ROM_REGION(0x8000000, "prg_flash", ROMREGION_ERASE00)
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ROM_REGION(0x4000000, "u3", ROMREGION_ERASE00)
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ROM_LOAD16_WORD_SWAP( "flash.u3", 0x0000000, 0x400000, CRC(fb376abc) SHA1(ea4c48bb6cd2055431a33f5c426e52c7af6997eb) )
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ROM_REGION(0x8000000, "data_flash", ROMREGION_ERASE00)
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ROM_LOAD( "flash.u29",0x0000000, 0x400000, CRC(7cf6ff4b) SHA1(4ccdd4864ad92cc218998f3923997119a1a9dd1d) )
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ROM_LOAD( "flash.u30",0x0400000, 0x400000, CRC(1d46717a) SHA1(acfbd0a2ccf4d717779733c4a9c639296c3bbe0e) )
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ROM_REGION(0x8000000, "u29", ROMREGION_ERASE00)
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ROM_LOAD16_WORD_SWAP( "flash.u29",0x0000000, 0x400000, CRC(7cf6ff4b) SHA1(4ccdd4864ad92cc218998f3923997119a1a9dd1d) )
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ROM_REGION(0x4000000, "u30", ROMREGION_ERASE00)
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ROM_LOAD16_WORD_SWAP( "flash.u30",0x0400000, 0x400000, CRC(1d46717a) SHA1(acfbd0a2ccf4d717779733c4a9c639296c3bbe0e) )
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ROM_END
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