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https://github.com/holub/mame
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WIP: Intergraph driver support: Enabled more Rx interrupts and fixed error fifo
This commit is contained in:
Joakim Larsson Edstrom
parent
7d401c1ad9
commit
86ca7dcf60
@ -81,14 +81,15 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC
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#define VERBOSE 0
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#define LOGPRINT(x) do { if (VERBOSE) logerror x; } while (0)
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#define LOG(x) {} LOGPRINT(x)
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#define LOGR(x) {} LOGPRINT(x)
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#define LOGR(x) {}
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#define LOGSETUP(x) {} LOGPRINT(x)
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#define LOGINT(x) {} LOGPRINT(x)
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#define LOGTX(x) {} LOGPRINT(x)
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#define LOGRCV(x) {} LOGPRINT(x)
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#define LOGCTS(x) {} LOGPRINT(x)
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#define LOGDCD(x) {} LOGPRINT(x)
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#define LOGSYNC(x) {} LOGPRINT(x)
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#define LOGINT(x) {}
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#define LOGCMD(x) {}
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#define LOGTX(x) {}
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#define LOGRCV(x) {}
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#define LOGCTS(x) {}
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#define LOGDCD(x) {}
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#define LOGSYNC(x) {}
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#if VERBOSE == 2
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#define logerror printf
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#endif
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@ -1321,7 +1322,7 @@ uint8_t z80scc_channel::do_sccreg_rr0()
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{
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uint8_t rr0 = m_rr0;
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LOGINT(("%s %c %s <- %02x\n",tag(), 'A' + m_index, FUNCNAME, m_rr0));
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LOG(("%s %c %s <- %02x\n",tag(), 'A' + m_index, FUNCNAME, m_rr0));
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if (m_extint_latch == 1)
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{
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rr0 &= ((~m_wr15) | WR15_WR7PRIME | WR15_STATUS_FIFO); // clear enabled bits, saving 2 unrelated bits
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@ -1330,7 +1331,7 @@ uint8_t z80scc_channel::do_sccreg_rr0()
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}
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else
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{
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LOGINT(("- %c returning unlatched value: %02x\n", 'A' + m_index, rr0));
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LOG(("- %c returning unlatched value: %02x\n", 'A' + m_index, rr0));
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}
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return rr0;
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@ -1626,30 +1627,6 @@ uint8_t z80scc_channel::control_read()
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return data;
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}
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/* CRC Initialization Code handling - candidate for breaking out in a z80sio_base class
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Handle the WR0 CRC Reset/Init bits separatelly, needed by derived devices separatelly from the commands */
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void z80scc_channel::do_sccreg_wr0_resets(uint8_t data)
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{
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LOG(("%s(%02x) %s",FUNCNAME, data, tag()));
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switch (data & WR0_CRC_RESET_CODE_MASK)
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{
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case WR0_CRC_RESET_NULL:
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LOG((" CRC_RESET_NULL\n"));
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break;
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case WR0_CRC_RESET_RX: /* In Synchronous mode: all Os (zeros) (CCITT-O CRC-16) */
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LOGSYNC((" CRC_RESET_RX - not implemented\n"));
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break;
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case WR0_CRC_RESET_TX: /* In HDLC mode: all 1s (ones) (CCITT-1) */
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LOGSYNC((" CRC_RESET_TX - not implemented\n"));
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break;
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case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the RRO register) */
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LOGSYNC((" CRC_RESET_TX_UNDERRUN - not implemented\n"));
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break;
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default: /* Will not happen unless someone messes with the mask */
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logerror(" Wrong CRC reset/init command:%02x\n", data & WR0_CRC_RESET_CODE_MASK);
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}
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}
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/**/
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void z80scc_channel::do_sccreg_wr0(uint8_t data)
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{
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@ -1688,7 +1665,7 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
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(there are two transitions), another interrupt is not generated. Exceptions to this
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rule are detailed in the RR0 description.*/
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LOGINT(("%s %s %c - Reset External/Status Interrupt, latch %s\n", m_owner->tag(), FUNCNAME, 'A' + m_index,
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LOGCMD(("%s %c - Reset External/Status Interrupt, latch %s\n", m_owner->tag(), 'A' + m_index,
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m_extint_latch == 1? "is released" : "was already released"));
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// Release latch if no other external or status sources are active
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if ((m_extint_latch = m_uart->update_extint(m_index)) == 0)
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@ -1702,18 +1679,18 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
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if (m_uart->m_variant & (SET_NMOS))
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{
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logerror("WR0 SWI ack command not supported on NMOS\n");
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LOGINT(("\"%s\" %s: %c : Reset Highest IUS command not available on NMOS!\n", m_owner->tag(), FUNCNAME, 'A' + m_index));
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LOGCMD(("%s: %c : WR0_RESET_HIGHEST_IUS command not available on NMOS!\n", m_owner->tag(), 'A' + m_index));
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}
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else
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{
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LOGINT(("\"%s\" %s: %c : Reset Highest IUS\n", m_owner->tag(), FUNCNAME, 'A' + m_index));
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LOGCMD(("%s: %c : Reset Highest IUS\n", m_owner->tag(), 'A' + m_index));
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// loop over all interrupt sources
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for (auto & elem : m_uart->m_int_state)
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{
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// find the first channel with an interrupt requested
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if (elem & Z80_DAISY_INT)
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{
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LOGINT(("- %c found IUS bit to clear\n", 'A' + m_index));
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LOGCMD(("- %c found IUS bit to clear\n", 'A' + m_index));
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elem = 0; // Clear IUS bit (called IEO in z80 daisy lingo)
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m_uart->check_interrupts();
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break;
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@ -1727,30 +1704,44 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
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data with the special condition is held in the Receive FIFO until this command is issued. If either
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of these modes is selected and this command is issued before the data has been read from the
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Receive FIFO, the data is lost */
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LOG(("\"%s\" %s: %c : WR0_ERROR_RESET\n", m_owner->tag(), FUNCNAME, 'A' + m_index));
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//do_sccreg_wr0(data); // reset status registers
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LOGCMD(("%s: %c : WR0_ERROR_RESET - not implemented\n", m_owner->tag(), 'A' + m_index));
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m_rx_fifo_rp_step(); // Reset error state in fifo and unlock it. unlock == step to next slot in fifo.
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break;
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case WR0_SEND_ABORT:
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data &= 0xef; // convert SCC SEND_ABORT command to a SIO SEND_ABORT command and fall through
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/* The following commands relies on the SIO default behviour */
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case WR0_NULL:
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LOG(("\"%s\" Channel %c : Null\n", m_owner->tag(), 'A' + m_index));
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case WR0_SEND_ABORT: // Flush transmitter and Send 8-13 bits of '1's, used with SDLC
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LOGCMD(("%s: %c : WR0_SEND_ABORT - not implemented\n", m_owner->tag(), 'A' + m_index));
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break;
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case WR0_ENABLE_INT_NEXT_RX:
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// enable interrupt on next receive character
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LOG(("\"%s\" Channel %c : Enable Interrupt on Next Received Character\n", m_owner->tag(), 'A' + m_index));
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case WR0_NULL: // Do nothing
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LOGCMD(("%s: %c : WR0_NULL\n", m_owner->tag(), 'A' + m_index));
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break;
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case WR0_ENABLE_INT_NEXT_RX: // enable interrupt on next receive character
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LOGCMD(("%s: %c : WR0_ENABLE_INT_NEXT\n", m_owner->tag(), 'A' + m_index));
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m_rx_first = 1;
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break;
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case WR0_RESET_TX_INT:
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// reset transmitter interrupt pending
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LOG(("\"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index));
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logerror("\"%s\" Channel %c : unsupported command: Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index);
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case WR0_RESET_TX_INT: // reset transmitter interrupt pending
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LOGCMD(("%s: %c : WR0_RESET_TX_INT - not implemented\n", m_owner->tag(), 'A' + m_index));
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break;
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default:
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break;
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}
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do_sccreg_wr0_resets(data);
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/* CRC Initialization Code handling */
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switch (data & WR0_CRC_RESET_CODE_MASK)
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{
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case WR0_CRC_RESET_NULL:
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LOGCMD((" CRC_RESET_NULL\n"));
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break;
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case WR0_CRC_RESET_RX: /* In Synchronous mode: all Os (zeros) (CCITT-O CRC-16) */
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LOGCMD((" CRC_RESET_RX - not implemented\n"));
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break;
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case WR0_CRC_RESET_TX: /* In HDLC mode: all 1s (ones) (CCITT-1) */
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LOGCMD((" CRC_RESET_TX - not implemented\n"));
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break;
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case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the RRO register) */
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LOGCMD((" CRC_RESET_TX_UNDERRUN - not implemented\n"));
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break;
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default: /* Will not happen unless someone messes with the mask */
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logerror(" Wrong CRC reset/init command:%02x\n", data & WR0_CRC_RESET_CODE_MASK);
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}
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if ( m_uart->m_variant & SET_Z85X3X)
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{
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@ -2278,27 +2269,14 @@ uint8_t z80scc_channel::data_read()
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data = m_rx_fifo_rp_data();
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// load error status from the FIFO
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m_rr1 = (m_rr1 & ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) | m_rx_error_fifo[m_rx_fifo_rp]; // TODO: Status FIFO needs to be fixed
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m_rr1 = (m_rr1 & ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR)) | m_rx_error_fifo[m_rx_fifo_rp];
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// trigger interrup and lock the fifo if an error is present
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// trigger interrupt and lock the fifo if an error is present
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if (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR))
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{
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logerror("Rx Error %02x\n", m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR));
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switch (m_wr1 & WR1_RX_INT_MODE_MASK)
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{
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case WR1_RX_INT_FIRST:
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if (!m_rx_first)
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{
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m_uart->trigger_interrupt(m_index, INT_SPECIAL);
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}
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break;
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case WR1_RX_INT_ALL_PARITY:
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case WR1_RX_INT_ALL:
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m_uart->trigger_interrupt(m_index, INT_SPECIAL);
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break;
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}
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}
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else
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{
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// decrease FIFO pointer
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@ -2446,22 +2424,30 @@ void z80scc_channel::data_write(uint8_t data)
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//-------------------------------------------------
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// receive_data - receive data word into fifo
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// receive_data - put received data word into fifo
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//-------------------------------------------------
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void z80scc_channel::receive_data(uint8_t data)
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{
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LOG(("\"%s\": %c : Receive Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, data));
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LOG(("\"%s\": %c : Received Data Byte '%c'/%02x put into FIFO\n", m_owner->tag(), 'A' + m_index, isprint(data) ? data : ' ', data));
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if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) ))
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{
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// receive overrun error detected
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m_rx_error_fifo[m_rx_fifo_wp] |= RR1_RX_OVERRUN_ERROR; // = m_rx_error; TODO: Status FIFO needs to be fixed
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m_rx_error_fifo[m_rx_fifo_wp] |= RR1_RX_OVERRUN_ERROR;
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// store received character but do not step the fifo
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m_rx_data_fifo[m_rx_fifo_wp] = data;
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logerror("Receive_data() Error %02x\n", m_rx_error_fifo[m_rx_fifo_wp] & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR));
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}
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else
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{
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m_rx_error_fifo[m_rx_fifo_wp] &= ~RR1_RX_OVERRUN_ERROR; // = m_rx_error; TODO: Status FIFO needs to be fixed
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m_rx_error_fifo[m_rx_fifo_wp] &= ~RR1_RX_OVERRUN_ERROR;
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// store received character
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m_rx_data_fifo[m_rx_fifo_wp] = data;
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m_rx_fifo_wp++;
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if (m_rx_fifo_wp >= m_rx_fifo_sz)
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{
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@ -2469,13 +2455,9 @@ void z80scc_channel::receive_data(uint8_t data)
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}
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}
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// store received character
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m_rx_data_fifo[m_rx_fifo_wp] = data;
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m_rr0 |= RR0_RX_CHAR_AVAILABLE;
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#if 0 // interrupt on exit from fifo
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// receive interrupt
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// receive interrupt on FIRST and ALL character
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switch (m_wr1 & WR1_RX_INT_MODE_MASK)
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{
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case WR1_RX_INT_FIRST:
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@ -2487,12 +2469,10 @@ void z80scc_channel::receive_data(uint8_t data)
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}
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break;
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case WR1_RX_INT_ALL_PARITY:
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case WR1_RX_INT_ALL:
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m_uart->trigger_interrupt(m_index, INT_RECEIVE);
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break;
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}
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#endif
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}
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