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Converted 7420 to macro modul

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This commit is contained in:
couriersud 2016-05-05 14:00:21 +02:00
parent cbe5b6abaa
commit 87541ec5ca
7 changed files with 73 additions and 130 deletions
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2
scripts/src/netlist.lua
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@ -86,8 +86,6 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_4020.h",
MAME_DIR .. "src/lib/netlist/devices/nld_4066.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4066.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7420.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7420.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7425.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7425.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7430.cpp",

2
src/lib/netlist/devices/net_lib.cpp
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@ -98,7 +98,6 @@ void initialize_factory(factory_list_t &factory)
ENTRY(switch2, SWITCH2, "-")
ENTRY(nicRSFF, NETDEV_RSFF, "+S,R")
ENTRY(nicDelay, NETDEV_DELAY, "-")
ENTRY(7420, TTL_7420_NAND, "+A,B,C,D")
ENTRY(7425, TTL_7425_NOR, "+A,B,C,D")
ENTRY(7430, TTL_7430_NAND, "+A,B,C,D,E,F,G,H")
ENTRY(7450, TTL_7450_ANDORINVERT, "+A,B,C,D")
@ -129,7 +128,6 @@ void initialize_factory(factory_list_t &factory)
ENTRY(NE555, NE555, "-")
ENTRY(r2r_dac, R2R_DAC, "+VIN,R,N")
ENTRY(4538_dip, CD4538_DIP, "-")
ENTRY(7420_dip, TTL_7420_DIP, "-")
ENTRY(7425_dip, TTL_7425_DIP, "-")
ENTRY(7430_dip, TTL_7430_DIP, "-")
ENTRY(7448_dip, TTL_7448_DIP, "-")

1
src/lib/netlist/devices/net_lib.h
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@ -16,7 +16,6 @@
#include "nld_4020.h"
#include "nld_4066.h"
#include "nld_7420.h"
#include "nld_7425.h"
#include "nld_7430.h"
#include "nld_7448.h"

59
src/lib/netlist/devices/nld_7420.cpp
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@ -1,59 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_7420.c
*
*/
#include "nld_7420.h"
NETLIB_NAMESPACE_DEVICES_START()
#if (USE_TRUTHTABLE)
nld_7420::truthtable_t nld_7420::m_ttbl;
const char *nld_7420::m_desc[] = {
"A,B,C,D|Q",
"0,X,X,X|1|22",
"X,0,X,X|1|22",
"X,X,0,X|1|22",
"X,X,X,0|1|22",
"1,1,1,1|0|15",
""
};
#endif
NETLIB_START(7420_dip)
{
register_sub("1", m_1);
register_sub("2", m_2);
register_subalias("1", m_1->m_I[0]);
register_subalias("2", m_1->m_I[1]);
register_subalias("4", m_1->m_I[2]);
register_subalias("5", m_1->m_I[3]);
register_subalias("6", m_1->m_Q[0]);
register_subalias("8", m_2->m_Q[0]);
register_subalias("9", m_2->m_I[0]);
register_subalias("10", m_2->m_I[1]);
register_subalias("12", m_2->m_I[2]);
register_subalias("13", m_2->m_I[3]);
}
NETLIB_UPDATE(7420_dip)
{
/* only called during startup */
m_1->update_dev();
m_2->update_dev();
}
NETLIB_RESET(7420_dip)
{
m_1->do_reset();
m_2->do_reset();
}
NETLIB_NAMESPACE_DEVICES_END()

66
src/lib/netlist/devices/nld_7420.h
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@ -1,66 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_7420.h
*
* DM7420: Dual 4-Input NAND Gates
*
* +--------------+
* A1 |1 ++ 14| VCC
* B1 |2 13| D2
* NC |3 12| C2
* C1 |4 7420 11| NC
* D1 |5 10| B2
* Y1 |6 9| A2
* GND |7 8| Y2
* +--------------+
* ____
* Y = ABCD
* +---+---+---+---++---+
* | A | B | C | D || Y |
* +===+===+===+===++===+
* | X | X | X | 0 || 1 |
* | X | X | 0 | X || 1 |
* | X | 0 | X | X || 1 |
* | 0 | X | X | X || 1 |
* | 1 | 1 | 1 | 1 || 0 |
* +---+---+---+---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
#ifndef NLD_7420_H_
#define NLD_7420_H_
#include "nld_signal.h"
#include "nld_truthtable.h"
#define TTL_7420_NAND(_name, _I1, _I2, _I3, _I4) \
NET_REGISTER_DEV(TTL_7420_NAND, _name) \
NET_CONNECT(_name, A, _I1) \
NET_CONNECT(_name, B, _I2) \
NET_CONNECT(_name, C, _I3) \
NET_CONNECT(_name, D, _I4)
#define TTL_7420_DIP(_name) \
NET_REGISTER_DEV(TTL_7420_DIP, _name)
NETLIB_NAMESPACE_DEVICES_START()
#if (USE_TRUTHTABLE)
NETLIB_TRUTHTABLE(7420, 4, 1, 0);
#else
NETLIB_SIGNAL(7420, 4, 0, 0);
#endif
NETLIB_DEVICE(7420_dip,
NETLIB_SUB(7420) m_1;
NETLIB_SUB(7420) m_2;
);
NETLIB_NAMESPACE_DEVICES_END()
#endif /* NLD_7420_H_ */

59
src/lib/netlist/macro/nlm_ttl74xx.cpp
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@ -263,6 +263,44 @@ NETLIST_START(TTL_7416_DIP)
)
NETLIST_END()
/*
* DM7420: Dual 4-Input NAND Gates
*
* ____
* Y = ABCD
* +---+---+---+---++---+
* | A | B | C | D || Y |
* +===+===+===+===++===+
* | X | X | X | 0 || 1 |
* | X | X | 0 | X || 1 |
* | X | 0 | X | X || 1 |
* | 0 | X | X | X || 1 |
* | 1 | 1 | 1 | 1 || 0 |
* +---+---+---+---++---+
*
* Naming conventions follow National Semiconductor datasheet *
*/
NETLIST_START(TTL_7420_DIP)
TTL_7420_GATE(s1)
TTL_7420_GATE(s2)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
DUMMY_INPUT(NC)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VCC.I,
s1.B, /* B1 |2 13| D2 */ s2.D,
NC.I, /* NC |3 12| C2 */ s2.C,
s1.C, /* C1 |4 7420 11| NC */ NC.I,
s1.D, /* D1 |5 10| B2 */ s2.B,
s1.Q, /* Y1 |6 9| A2 */ s2.A,
GND.I, /* GND |7 8| Y2 */ s2.Q
/* +--------------+ */
)
NETLIST_END()
/*
* DM7427: Triple 3-Input NOR Gates
*
@ -491,6 +529,26 @@ NETLIST_START(TTL74XX_lib)
TT_FAMILY("74XXOC")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7420_GATE, 4, 1, 0, "")
TT_HEAD("A,B,C,D|Q ")
TT_LINE("0,X,X,X|1|22")
TT_LINE("X,0,X,X|1|22")
TT_LINE("X,X,0,X|1|22")
TT_LINE("X,X,X,0|1|22")
TT_LINE("1,1,1,1|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7420_NAND, 4, 1, 0, "A,B,C,D")
TT_HEAD("A,B,C,D|Q ")
TT_LINE("0,X,X,X|1|22")
TT_LINE("X,0,X,X|1|22")
TT_LINE("X,X,0,X|1|22")
TT_LINE("X,X,X,0|1|22")
TT_LINE("1,1,1,1|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7427_GATE, 3, 1, 0, "")
TT_HEAD("A,B,C|Q ")
TT_LINE("1,X,X|0|15")
@ -552,6 +610,7 @@ NETLIST_START(TTL74XX_lib)
LOCAL_LIB_ENTRY(TTL_7410_DIP)
LOCAL_LIB_ENTRY(TTL_7411_DIP)
LOCAL_LIB_ENTRY(TTL_7416_DIP)
LOCAL_LIB_ENTRY(TTL_7420_DIP)
LOCAL_LIB_ENTRY(TTL_7427_DIP)
LOCAL_LIB_ENTRY(TTL_7432_DIP)
LOCAL_LIB_ENTRY(TTL_7437_DIP)

14
src/lib/netlist/macro/nlm_ttl74xx.h
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@ -91,6 +91,20 @@
NET_REGISTER_DEV(TTL7416_DIP, _name)
#define TTL_7420_GATE(_name) \
NET_REGISTER_DEV(TTL_7420_GATE, _name)
#define TTL_7420_NAND(_name, _I1, _I2, _I3, _I4) \
NET_REGISTER_DEV(TTL_7420_NAND, _name) \
NET_CONNECT(_name, A, _I1) \
NET_CONNECT(_name, B, _I2) \
NET_CONNECT(_name, C, _I3) \
NET_CONNECT(_name, D, _I4)
#define TTL_7420_DIP(_name) \
NET_REGISTER_DEV(TTL_7420_DIP, _name)
#define TTL_7427_GATE(_name) \
NET_REGISTER_DEV(TTL_7427_GATE, _name)