Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-10-07 09:25:34 +03:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

Cleanups and version bump (nw)

Browse Source
This commit is contained in:
Miodrag Milanovic 2012-11-19 08:40:08 +00:00
parent d60236970a
commit 8813fb6bcd
62 changed files with 1134 additions and 1134 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
hash/cd32.xml
View File

@ -4,8 +4,8 @@
<!--- Preliminary List -->
<!-- playable but there's a scrolling glitch every few frames -->
<!-- playable but there's a scrolling glitch every few frames -->
<software name="morph" supported="partial">
<description>Morph</description>
<year>1993</year>
@ -137,7 +137,7 @@
</diskarea>
</part>
</software>
</softwarelist>

2
hash/neocd.xml
View File

@ -1161,5 +1161,5 @@
</software>
-->
</softwarelist>

42
src/emu/cpu/avr8/avr8.c
View File

@ -9,25 +9,25 @@
the existing opcodes has been shown to wildly corrupt the video output in Craft, so one can assume that the
existing timing is 100% correct.
Unimplemented opcodes: CPSR, LD Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, EICALL,
JMP, CALL
Unimplemented opcodes: CPSR, LD Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, EICALL,
JMP, CALL
- Changelist -
30 Oct. 2012
- Added FMUL, FMULS, FMULSU opcodes [MooglyGuy]
- Fixed incorrect flag calculation in ROR opcode [MooglyGuy]
- Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy]
- Changelist -
30 Oct. 2012
- Added FMUL, FMULS, FMULSU opcodes [MooglyGuy]
- Fixed incorrect flag calculation in ROR opcode [MooglyGuy]
- Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy]
25 Oct. 2012
- Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy]
- Corrected cycle counts for LD and ST opcodes [MooglyGuy]
- Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing
all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy]
- Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy]
25 Oct. 2012
- Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy]
- Corrected cycle counts for LD and ST opcodes [MooglyGuy]
- Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing
all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy]
- Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy]
18 Oct. 2012
- Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy]
- Fixed COM, NEG, LSR opcodes [MooglyGuy]
18 Oct. 2012
- Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy]
- Fixed COM, NEG, LSR opcodes [MooglyGuy]
*/
@ -783,7 +783,7 @@ void avr8_device::timer0_tick()
//UINT8 compare_mode[2] = { (m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0A_MASK) >> AVR8_TCCR0A_COM0A_SHIFT,
//(m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0B_MASK) >> AVR8_TCCR0A_COM0B_SHIFT };
UINT8 ocr0[2] = { m_r[AVR8_REGIDX_OCR0A], m_r[AVR8_REGIDX_OCR0B] };
UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR0_OCF0B_SHIFT) };
UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR0_OCF0B_SHIFT) };
INT32 increment = m_timer0_increment;
for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
@ -854,9 +854,9 @@ void avr8_device::timer0_tick()
m_r[AVR8_REGIDX_TCNT0] = count + increment;
update_interrupt(AVR8_INTIDX_OCF0A);
update_interrupt(AVR8_INTIDX_OCF0B);
update_interrupt(AVR8_INTIDX_TOV0);
update_interrupt(AVR8_INTIDX_OCF0A);
update_interrupt(AVR8_INTIDX_OCF0B);
update_interrupt(AVR8_INTIDX_TOV0);
*/
}
@ -1054,7 +1054,7 @@ void avr8_device::timer1_tick()
break;
default:
verboselog(m_pc, 0, "update_timer1_compare_mode: Unknown waveform generation mode: %02x\n", wgm1);
verboselog(m_pc, 0, "update_timer1_compare_mode: Unknown waveform generation mode: %02x\n", wgm1);
break;
}
/*

32
src/emu/cpu/avr8/avr8.h
View File

@ -9,25 +9,25 @@
the existing opcodes has been shown to wildly corrupt the video output in Craft, so one can assume that the
existing timing is 100% correct.
Unimplemented opcodes: CPSR, LD Z+, ST Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL,
EICALL, JMP, CALL, SBIW
Unimplemented opcodes: CPSR, LD Z+, ST Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL,
EICALL, JMP, CALL, SBIW
- Changelist -
30 Oct. 2012
- Added FMUL, FMULS, FMULSU opcodes [MooglyGuy]
- Fixed incorrect flag calculation in ROR opcode [MooglyGuy]
- Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy]
- Changelist -
30 Oct. 2012
- Added FMUL, FMULS, FMULSU opcodes [MooglyGuy]
- Fixed incorrect flag calculation in ROR opcode [MooglyGuy]
- Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy]
25 Oct. 2012
- Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy]
- Corrected cycle counts for LD and ST opcodes [MooglyGuy]
- Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing
all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy]
- Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy]
25 Oct. 2012
- Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy]
- Corrected cycle counts for LD and ST opcodes [MooglyGuy]
- Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing
all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy]
- Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy]
18 Oct. 2012
- Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy]
- Fixed COM, NEG, LSR opcodes [MooglyGuy]
18 Oct. 2012
- Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy]
- Fixed COM, NEG, LSR opcodes [MooglyGuy]
*/

4
src/emu/cpu/i386/i386.c
View File

@ -2831,7 +2831,7 @@ static UINT32 i386_get_debug_desc(i386_state *cpustate, I386_SREG *seg)
entry = seg->selector & ~0x7;
if (limit == 0 || entry + 7 > limit)
return 0;
address = entry + base;
// todo: bigendian
@ -2910,7 +2910,7 @@ static UINT64 i386_debug_segofftovirt(symbol_table &table, void *ref, int params
if(param[0] > 65535)
return 0;
if (PROTECTED_MODE && !V8086_MODE)
{
memset(&seg, 0, sizeof(seg));

2
src/emu/cpu/m6502/m4510.c
View File

@ -57,7 +57,7 @@ offs_t m4510_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *op
void m4510_device::device_start()
{
if(direct_disabled)
if(direct_disabled)
mintf = new mi_4510_nd(this);
else
mintf = new mi_4510_normal(this);

2
src/emu/cpu/m6502/m6502make.c
View File

@ -211,7 +211,7 @@ static void save_tables(FILE *f)
opc = string(opcode.begin(), k);
fullopc = string(opcode.begin(), ke-1);
mode = string(ke, opcode.end());
bool step_over = opc == "jsr" || opc == "bsr";
bool step_out = opc == "rts" || opc == "rti" || opc == "rtn";
fprintf(f, "\t{ \"%s\", DASM_%s, %s },\n",

2
src/emu/cpu/m6502/m6510.c
View File

@ -76,7 +76,7 @@ void m6510_device::device_start()
read_port.resolve_safe(0);
write_port.resolve_safe();
if(direct_disabled)
if(direct_disabled)
mintf = new mi_6510_nd(this);
else
mintf = new mi_6510_normal(this);

2
src/emu/cpu/m6502/om6502.lst
View File

@ -1962,4 +1962,4 @@ kil_non
read(0xfffe);
for(;;) {
read(0xffff);
}
}

8
src/emu/cpu/m6502/om65c02.lst
View File

@ -533,7 +533,7 @@ trb_aba
if(A & TMP2)
P &= ~F_Z;
else
P |= F_Z;
P |= F_Z;
TMP2 &= ~A;
write(TMP, TMP2);
prefetch();
@ -545,7 +545,7 @@ trb_zpg
if(A & TMP2)
P &= ~F_Z;
else
P |= F_Z;
P |= F_Z;
TMP2 &= ~A;
write(TMP, TMP2);
prefetch();
@ -558,7 +558,7 @@ tsb_aba
if(A & TMP2)
P &= ~F_Z;
else
P |= F_Z;
P |= F_Z;
TMP2 |= A;
write(TMP, TMP2);
prefetch();
@ -570,7 +570,7 @@ tsb_zpg
if(A & TMP2)
P &= ~F_Z;
else
P |= F_Z;
P |= F_Z;
TMP2 |= A;
write(TMP, TMP2);
prefetch();

8
src/emu/cpu/m6502/om65ce02.lst
View File

@ -1459,7 +1459,7 @@ trb_ce_aba
if(A & TMP2)
P &= ~F_Z;
else
P |= F_Z;
P |= F_Z;
TMP2 &= ~A;
write(TMP, TMP2);
prefetch();
@ -1470,7 +1470,7 @@ trb_ce_zpg
if(A & TMP2)
P &= ~F_Z;
else
P |= F_Z;
P |= F_Z;
TMP2 &= ~A;
write(TMP, TMP2);
prefetch();
@ -1482,7 +1482,7 @@ tsb_ce_aba
if(A & TMP2)
P &= ~F_Z;
else
P |= F_Z;
P |= F_Z;
TMP2 |= A;
write(TMP, TMP2);
prefetch();
@ -1493,7 +1493,7 @@ tsb_ce_zpg
if(A & TMP2)
P &= ~F_Z;
else
P |= F_Z;
P |= F_Z;
TMP2 |= A;
write(TMP, TMP2);
prefetch();

32
src/emu/cpu/z8000/z8000ops.c
View File

@ -5829,8 +5829,8 @@ static void ZB7_ssss_dddd(z8000_state *cpustate)
}
/******************************************
trtib @rd,@rs,rr
flags: -ZSV--
trtib @rd,@rs,rr
flags: -ZSV--
******************************************/
static void ZB8_ddN0_0010_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{
@ -5845,8 +5845,8 @@ static void ZB8_ddN0_0010_0000_rrrr_ssN0_0000(z8000_state *cpustate)
}
/******************************************
trtirb @rd,@rs,rbr
flags: -ZSV--
trtirb @rd,@rs,rbr
flags: -ZSV--
******************************************/
static void ZB8_ddN0_0110_0000_rrrr_ssN0_1110(z8000_state *cpustate)
{
@ -5866,8 +5866,8 @@ static void ZB8_ddN0_0110_0000_rrrr_ssN0_1110(z8000_state *cpustate)
}
/******************************************
trtdb @rd,@rs,rbr
flags: -ZSV--
trtdb @rd,@rs,rbr
flags: -ZSV--
******************************************/
static void ZB8_ddN0_1010_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{
@ -5882,8 +5882,8 @@ static void ZB8_ddN0_1010_0000_rrrr_ssN0_0000(z8000_state *cpustate)
}
/******************************************
trtdrb @rd,@rs,rbr
flags: -ZSV--
trtdrb @rd,@rs,rbr
flags: -ZSV--
******************************************/
static void ZB8_ddN0_1110_0000_rrrr_ssN0_1110(z8000_state *cpustate)
{
@ -5903,8 +5903,8 @@ static void ZB8_ddN0_1110_0000_rrrr_ssN0_1110(z8000_state *cpustate)
}
/******************************************
trib @rd,@rs,rbr
flags: -ZSV--
trib @rd,@rs,rbr
flags: -ZSV--
******************************************/
static void ZB8_ddN0_0000_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{
@ -5919,8 +5919,8 @@ static void ZB8_ddN0_0000_0000_rrrr_ssN0_0000(z8000_state *cpustate)
}
/******************************************
trirb @rd,@rs,rbr
flags: -ZSV--
trirb @rd,@rs,rbr
flags: -ZSV--
******************************************/
static void ZB8_ddN0_0100_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{
@ -5935,8 +5935,8 @@ static void ZB8_ddN0_0100_0000_rrrr_ssN0_0000(z8000_state *cpustate)
}
/******************************************
trdb @rd,@rs,rbr
flags: -ZSV--
trdb @rd,@rs,rbr
flags: -ZSV--
******************************************/
static void ZB8_ddN0_1000_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{
@ -5951,8 +5951,8 @@ static void ZB8_ddN0_1000_0000_rrrr_ssN0_0000(z8000_state *cpustate)
}
/******************************************
trdrb @rd,@rs,rbr
flags: -ZSV--
trdrb @rd,@rs,rbr
flags: -ZSV--
******************************************/
static void ZB8_ddN0_1100_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{

4
src/emu/machine/scsicd.c
View File

@ -272,8 +272,8 @@ void scsicd_device::ExecCommand( int *transferLength )
SetPhase( SCSI_PHASE_STATUS );
*transferLength = 0;
break;
case 0x4e: // STOP
case 0x4e: // STOP
if (cdrom)
{
cdda = cdda_from_cdrom(machine(), cdrom);

42
src/emu/sound/tms5110r.c
View File

@ -383,13 +383,13 @@ static const struct tms5100_coeffs tms5200_coeff =
},
/* Chirp table */
/*
{ 0, 42, -44, 50, -78, 18, 37, 20,
2, -31, -59, 2, 95, 90, 5, 15,
38, -4, -91,-91, -42,-35,-36, -4,
37, 43, 34, 33, 15, -1, -8,-18,
-19,-17, -9,-10, -6, 0, 3, 2,
1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },*/
{ 0, 42, -44, 50, -78, 18, 37, 20,
2, -31, -59, 2, 95, 90, 5, 15,
38, -4, -91,-91, -42,-35,-36, -4,
37, 43, 34, 33, 15, -1, -8,-18,
-19,-17, -9,-10, -6, 0, 3, 2,
1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },*/
{ 0,127,127, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -460,13 +460,13 @@ static const struct tms5100_coeffs tms5220_coeff =
},
/* Chirp table */
/*
{ 0, 42, -44, 50, -78, 18, 37, 20,
2, -31, -59, 2, 95, 90, 5, 15,
38, -4, -91,-91, -42,-35,-36, -4,
37, 43, 34, 33, 15, -1, -8,-18,
-19,-17, -9,-10, -6, 0, 3, 2,
1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },*/
{ 0, 42, -44, 50, -78, 18, 37, 20,
2, -31, -59, 2, 95, 90, 5, 15,
38, -4, -91,-91, -42,-35,-36, -4,
37, 43, 34, 33, 15, -1, -8,-18,
-19,-17, -9,-10, -6, 0, 3, 2,
1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },*/
{ 0,127,127, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -541,13 +541,13 @@ static const struct tms5100_coeffs tms5220c_coeff =
},
/* Chirp table */
/*
{ 0, 42, -44, 50, -78, 18, 37, 20,
2, -31, -59, 2, 95, 90, 5, 15,
38, -4, -91,-91, -42,-35,-36, -4,
37, 43, 34, 33, 15, -1, -8,-18,
-19,-17, -9,-10, -6, 0, 3, 2,
1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },*/
{ 0, 42, -44, 50, -78, 18, 37, 20,
2, -31, -59, 2, 95, 90, 5, 15,
38, -4, -91,-91, -42,-35,-36, -4,
37, 43, 34, 33, 15, -1, -8,-18,
-19,-17, -9,-10, -6, 0, 3, 2,
1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },*/
{ 0,127,127, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,

306
src/emu/sound/tms5220.c
View File

@ -418,8 +418,8 @@ struct tms5220_state
UINT8 RDB_flag; /* whether we should read data register or status register */
/* io_ready: page 3 of the datasheet specifies that READY will be asserted until
* data is available or processed by the system.
*/
* data is available or processed by the system.
*/
UINT8 io_ready;
/* flag for "true" timing involving rs/ws */
@ -431,12 +431,12 @@ struct tms5220_state
UINT8 write_latch;
/* The TMS52xx has two different ways of providing output data: the
analog speaker pin (which was usually used) and the Digital I/O pin.
The internal DAC used to feed the analog pin is only 8 bits, and has the
funny clipping/clamping logic, while the digital pin gives full 12? bit
resolution of the output data.
TODO: add a way to set/reset this other than the FORCE_DIGITAL define
*/
analog speaker pin (which was usually used) and the Digital I/O pin.
The internal DAC used to feed the analog pin is only 8 bits, and has the
funny clipping/clamping logic, while the digital pin gives full 12? bit
resolution of the output data.
TODO: add a way to set/reset this other than the FORCE_DIGITAL define
*/
UINT8 digital_select;
device_t *device;
@ -554,7 +554,7 @@ static void register_for_save_states(tms5220_state *tms)
/**********************************************************************************************
printbits helper function: takes a long int input and prints the resulting bits to stderr
printbits helper function: takes a long int input and prints the resulting bits to stderr
***********************************************************************************************/
@ -592,7 +592,7 @@ static void printbits(long data, int num)
/**********************************************************************************************
tms5220_data_write -- handle a write to the TMS5220
tms5220_data_write -- handle a write to the TMS5220
***********************************************************************************************/
@ -652,24 +652,24 @@ static void tms5220_data_write(tms5220_state *tms, int data)
/**********************************************************************************************
update_status_and_ints -- check to see if the various flags should be on or off
Description of flags, and their position in the status register:
From the data sheet:
bit D0(bit 7) = TS - Talk Status is active (high) when the VSP is processing speech data.
Talk Status goes active at the initiation of a Speak command or after nine
bytes of data are loaded into the FIFO following a Speak External command. It
goes inactive (low) when the stop code (Energy=1111) is processed, or
immediately by a buffer empty condition or a reset command.
bit D1(bit 6) = BL - Buffer Low is active (high) when the FIFO buffer is more than half empty.
Buffer Low is set when the "Last-In" byte is shifted down past the half-full
boundary of the stack. Buffer Low is cleared when data is loaded to the stack
so that the "Last-In" byte lies above the half-full boundary and becomes the
eighth data byte of the stack.
bit D2(bit 5) = BE - Buffer Empty is active (high) when the FIFO buffer has run out of data
while executing a Speak External command. Buffer Empty is set when the last bit
of the "Last-In" byte is shifted out to the Synthesis Section. This causes
Talk Status to be cleared. Speech is terminated at some abnormal point and the
Speak External command execution is terminated.
update_status_and_ints -- check to see if the various flags should be on or off
Description of flags, and their position in the status register:
From the data sheet:
bit D0(bit 7) = TS - Talk Status is active (high) when the VSP is processing speech data.
Talk Status goes active at the initiation of a Speak command or after nine
bytes of data are loaded into the FIFO following a Speak External command. It
goes inactive (low) when the stop code (Energy=1111) is processed, or
immediately by a buffer empty condition or a reset command.
bit D1(bit 6) = BL - Buffer Low is active (high) when the FIFO buffer is more than half empty.
Buffer Low is set when the "Last-In" byte is shifted down past the half-full
boundary of the stack. Buffer Low is cleared when data is loaded to the stack
so that the "Last-In" byte lies above the half-full boundary and becomes the
eighth data byte of the stack.
bit D2(bit 5) = BE - Buffer Empty is active (high) when the FIFO buffer has run out of data
while executing a Speak External command. Buffer Empty is set when the last bit
of the "Last-In" byte is shifted out to the Synthesis Section. This causes
Talk Status to be cleared. Speech is terminated at some abnormal point and the
Speak External command execution is terminated.
***********************************************************************************************/
@ -680,8 +680,8 @@ static void update_status_and_ints(tms5220_state *tms)
update_ready_state(tms);
/* BL is set if neither byte 9 nor 8 of the fifo are in use; this
translates to having fifo_count (which ranges from 0 bytes in use to 16
bytes used) being less than or equal to 8. Victory/Victorba depends on this. */
translates to having fifo_count (which ranges from 0 bytes in use to 16
bytes used) being less than or equal to 8. Victory/Victorba depends on this. */
if (tms->fifo_count <= 8)
{
// generate an interrupt if necessary; if /BL was inactive and is now active, set int.
@ -693,7 +693,7 @@ static void update_status_and_ints(tms5220_state *tms)
tms->buffer_low = 0;
/* BE is set if neither byte 15 nor 14 of the fifo are in use; this
translates to having fifo_count equal to exactly 0 */
translates to having fifo_count equal to exactly 0 */
if (tms->fifo_count == 0)
{
// generate an interrupt if necessary; if /BE was inactive and is now active, set int.
@ -705,8 +705,8 @@ static void update_status_and_ints(tms5220_state *tms)
tms->buffer_empty = 0;
/* TS is talk status and is set elsewhere in the fifo parser and in
the SPEAK command handler; however, if /BE is true during speak external
mode, it is immediately unset here. */
the SPEAK command handler; however, if /BE is true during speak external
mode, it is immediately unset here. */
if ((tms->speak_external == 1) && (tms->buffer_empty == 1))
{
// generate an interrupt: /TS was active, and is now inactive.
@ -717,12 +717,12 @@ static void update_status_and_ints(tms5220_state *tms)
}
}
/* Note that TS being unset will also generate an interrupt when a STOP
frame is encountered; this is handled in the sample generator code and not here */
frame is encountered; this is handled in the sample generator code and not here */
}
/**********************************************************************************************
extract_bits -- extract a specific number of bits from the current input stream (FIFO or VSM)
extract_bits -- extract a specific number of bits from the current input stream (FIFO or VSM)
***********************************************************************************************/
@ -759,7 +759,7 @@ static int extract_bits(tms5220_state *tms, int count)
/**********************************************************************************************
tms5220_status_read -- read status or data from the TMS5220
tms5220_status_read -- read status or data from the TMS5220
***********************************************************************************************/
@ -801,9 +801,9 @@ static int tms5220_ready_read(tms5220_state *tms)
/**********************************************************************************************
tms5220_cycles_to_ready -- returns the number of cycles until ready is asserted
NOTE: this function is deprecated and is known to be VERY inaccurate.
Use at your own peril!
tms5220_cycles_to_ready -- returns the number of cycles until ready is asserted
NOTE: this function is deprecated and is known to be VERY inaccurate.
Use at your own peril!
***********************************************************************************************/
@ -829,12 +829,12 @@ static int tms5220_cycles_to_ready(tms5220_state *tms)
val = (tms->fifo[tms->fifo_head] >> tms->fifo_bits_taken) & 0xf;
if (val == 0)
/* 0 -> silence frame: we will only read 4 bits, and we will
* therefore need to read another frame before the FIFO is not
* full any more */
* therefore need to read another frame before the FIFO is not
* full any more */
answer += tms->subc_reload?200:304;
/* 15 -> stop frame, we will only read 4 bits, but the FIFO will
* we cleared; otherwise, we need to parse the repeat flag (1 bit)
* and the pitch (6 bits), so everything will be OK. */
* we cleared; otherwise, we need to parse the repeat flag (1 bit)
* and the pitch (6 bits), so everything will be OK. */
}
}
@ -844,7 +844,7 @@ static int tms5220_cycles_to_ready(tms5220_state *tms)
/**********************************************************************************************
tms5220_int_read -- returns the interrupt state of the TMS5220
tms5220_int_read -- returns the interrupt state of the TMS5220
***********************************************************************************************/
@ -859,7 +859,7 @@ static int tms5220_int_read(tms5220_state *tms)
/**********************************************************************************************
tms5220_process -- fill the buffer with a specific number of samples
tms5220_process -- fill the buffer with a specific number of samples
***********************************************************************************************/
@ -875,7 +875,7 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
goto empty;
/* if speak external is set, but talk status is not (yet) set,
wait for buffer low to clear */
wait for buffer low to clear */
if (!tms->talk_status && tms->speak_external && tms->buffer_low)
goto empty;
@ -883,9 +883,9 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
while ((size > 0) && tms->speaking_now)
{
/* if it is the appropriate time to update the old energy/pitch idxes,
* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
* which happens 4 T-cycles later), we change on the latter.*/
* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
* which happens 4 T-cycles later), we change on the latter.*/
if ((tms->interp_period == 0) && (tms->PC == 0) && (tms->subcycle < 2))
{
tms->OLDE = (tms->new_frame_energy_idx == 0);
@ -893,9 +893,9 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
}
/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
* (In reality, the frame was really loaded incrementally during the entire IP=0
* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
*/
* (In reality, the frame was really loaded incrementally during the entire IP=0
* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
*/
if ((tms->interp_period == 0) && (tms->PC == 12) && (tms->subcycle == 1))
{
// HACK for regression testing, be sure to comment out before release!
@ -939,11 +939,11 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
}
/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
Interpolation inhibit cases:
* Old frame was voiced, new is unvoiced
* Old frame was silence/zero energy, new has nonzero energy
* Old frame was unvoiced, new is voiced
*/
Interpolation inhibit cases:
* Old frame was voiced, new is unvoiced
* Old frame was silence/zero energy, new has nonzero energy
* Old frame was unvoiced, new is voiced
*/
if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
|| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0))
|| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0)) )
@ -1056,12 +1056,12 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
{
// generate voiced samples here
/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
* function has a chirp/peak and then a long chain of zeroes.
* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
* and if the address reaches that point the ADDRESS incrementer is
* disabled, forcing all samples beyond 51d to be == 51d
* (address 51d holds zeroes, which may or may not be inverted to -1)
*/
* function has a chirp/peak and then a long chain of zeroes.
* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
* and if the address reaches that point the ADDRESS incrementer is
* disabled, forcing all samples beyond 51d to be == 51d
* (address 51d holds zeroes, which may or may not be inverted to -1)
*/
if (tms->pitch_count >= 51)
tms->excitation_data = tms->coeff->chirptable[51];
else /*tms->pitch_count < 51*/
@ -1124,14 +1124,14 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
tms->PC++;
}
/* Circuit 412 in the patent ensures that when INHIBIT is true,
* during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch
* count is forced to 0; since the initial stop happens right before
* the switch to IP=0 PC=0 and this code is located after the switch would
* happen, we check for ip=0 inhibit=1, which covers that whole range.
* The purpose of Circuit 412 is to prevent a spurious click caused by
* the voiced source being fed to the filter before all the values have
* been updated during ip=0 when interpolation was inhibited.
*/
* during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch
* count is forced to 0; since the initial stop happens right before
* the switch to IP=0 PC=0 and this code is located after the switch would
* happen, we check for ip=0 inhibit=1, which covers that whole range.
* The purpose of Circuit 412 is to prevent a spurious click caused by
* the voiced source being fed to the filter before all the values have
* been updated during ip=0 when interpolation was inhibited.
*/
tms->pitch_count++;
if (tms->pitch_count >= tms->current_pitch) tms->pitch_count = 0;
if ((tms->interp_period == 0)&&(tms->inhibit==1)) tms->pitch_count = 0;
@ -1165,20 +1165,20 @@ empty:
/**********************************************************************************************
clip_analog -- clips the 14 bit return value from the lattice filter to its final 10 bit value (-512 to 511), and upshifts/range extends this to 16 bits
clip_analog -- clips the 14 bit return value from the lattice filter to its final 10 bit value (-512 to 511), and upshifts/range extends this to 16 bits
***********************************************************************************************/
static INT16 clip_analog(INT16 cliptemp)
{
/* clipping, just like the patent shows:
* the top 10 bits of this result are visible on the digital output IO pin.
* next, if the top 3 bits of the 14 bit result are all the same, the lowest of those 3 bits plus the next 7 bits are the signed analog output, otherwise the low bits are all forced to match the inverse of the topmost bit, i.e.:
* 1x xxxx xxxx xxxx -> 0b10000000
* 11 1bcd efgh xxxx -> 0b1bcdefgh
* 00 0bcd efgh xxxx -> 0b0bcdefgh
* 0x xxxx xxxx xxxx -> 0b01111111
*/
* the top 10 bits of this result are visible on the digital output IO pin.
* next, if the top 3 bits of the 14 bit result are all the same, the lowest of those 3 bits plus the next 7 bits are the signed analog output, otherwise the low bits are all forced to match the inverse of the topmost bit, i.e.:
* 1x xxxx xxxx xxxx -> 0b10000000
* 11 1bcd efgh xxxx -> 0b1bcdefgh
* 00 0bcd efgh xxxx -> 0b0bcdefgh
* 0x xxxx xxxx xxxx -> 0b01111111
*/
#ifdef DEBUG_CLIP
if ((cliptemp > 2047) || (cliptemp < -2048)) fprintf(stderr,"clipping cliptemp to range; was %d\n", cliptemp);
#endif
@ -1203,12 +1203,12 @@ static INT16 clip_analog(INT16 cliptemp)
/**********************************************************************************************
matrix_multiply -- does the proper multiply and shift
a is the k coefficient and is clamped to 10 bits (9 bits plus a sign)
b is the running result and is clamped to 14 bits.
output is 14 bits, but note the result LSB bit is always 1.
Because the low 4 bits of the result are trimmed off before
output, this makes almost no difference in the computation.
matrix_multiply -- does the proper multiply and shift
a is the k coefficient and is clamped to 10 bits (9 bits plus a sign)
b is the running result and is clamped to 14 bits.
output is 14 bits, but note the result LSB bit is always 1.
Because the low 4 bits of the result are trimmed off before
output, this makes almost no difference in the computation.
**********************************************************************************************/
static INT32 matrix_multiply(INT32 a, INT32 b)
@ -1228,9 +1228,9 @@ static INT32 matrix_multiply(INT32 a, INT32 b)
/**********************************************************************************************
lattice_filter -- executes one 'full run' of the lattice filter on a specific byte of
excitation data, and specific values of all the current k constants, and returns the
resulting sample.
lattice_filter -- executes one 'full run' of the lattice filter on a specific byte of
excitation data, and specific values of all the current k constants, and returns the
resulting sample.
***********************************************************************************************/
@ -1239,11 +1239,11 @@ static INT32 lattice_filter(tms5220_state *tms)
// Lattice filter here
// Aug/05/07: redone as unrolled loop, for clarity - LN
/* Originally Copied verbatim from table I in US patent 4,209,804, now updated to be in same order as the actual chip does it, not that it matters.
notation equivalencies from table:
Yn(i) == tms->u[n-1]
Kn = tms->current_k[n-1]
bn = tms->x[n-1]
*/
notation equivalencies from table:
Yn(i) == tms->u[n-1]
Kn = tms->current_k[n-1]
bn = tms->x[n-1]
*/
tms->u[10] = matrix_multiply(tms->previous_energy, (tms->excitation_data<<6)); //Y(11)
tms->u[9] = tms->u[10] - matrix_multiply(tms->current_k[9], tms->x[9]);
tms->u[8] = tms->u[9] - matrix_multiply(tms->current_k[8], tms->x[8]);
@ -1282,7 +1282,7 @@ static INT32 lattice_filter(tms5220_state *tms)
/**********************************************************************************************
process_command -- extract a byte from the FIFO and interpret it as a command
process_command -- extract a byte from the FIFO and interpret it as a command
***********************************************************************************************/
@ -1332,7 +1332,7 @@ static void process_command(tms5220_state *tms, unsigned char cmd)
if (tms->talk_status == 0) /* TALKST must be clear for LA */
{
/* tms5220 data sheet says that if we load only one 4-bit nibble, it won't work.
This code does not care about this. */
This code does not care about this. */
if (tms->intf->load_address)
(*tms->intf->load_address)(tms->device, cmd & 0x0f);
tms->schedule_dummy_read = TRUE;
@ -1403,7 +1403,7 @@ static void parse_frame(tms5220_state *tms)
// We actually don't care how many bits are left in the fifo here; the frame subpart will be processed normally, and any bits extracted 'past the end' of the fifo will be read as zeroes; the fifo being emptied will set the /BE latch which will halt speech exactly as if a stop frame had been encountered (instead of whatever partial frame was read); the same exact circuitry is used for both on the real chip, see us patent 4335277 sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS (decode disable) which is active during speak external).
/* if the chip is a tms5220C, and the rate mode is set to that each frame (0x04 bit set)
has a 2 bit rate preceding it, grab two bits here and store them as the rate; */
has a 2 bit rate preceding it, grab two bits here and store them as the rate; */
if ((tms->variant == SUBTYPE_TMS5220C) && (tms->tms5220c_rate & 0x04))
{
indx = extract_bits(tms, 2);
@ -2177,7 +2177,7 @@ void tms52xx_device::device_reset()
// initialize the chip state
/* Note that we do not actually clear IRQ on start-up: IRQ is even raised
* if m_buffer_empty or m_buffer_low are 0 */
* if m_buffer_empty or m_buffer_low are 0 */
m_speaking_now = false;
m_speak_external = false;
m_talk_status = false;
@ -2314,10 +2314,10 @@ void tms52xx_device::process(INT16 *buffer, unsigned int size)
while ((size > 0) && m_speaking_now)
{
/* if it is the appropriate time to update the old energy/pitch idxes,
* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
* which happens 4 T-cycles later), we change on the latter.
*/
* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
* which happens 4 T-cycles later), we change on the latter.
*/
if ((m_interp_period == 0) && (m_PC == 0) && (m_subcycle < 2))
{
m_OLDE = (m_new_frame_energy_idx == 0);
@ -2325,9 +2325,9 @@ void tms52xx_device::process(INT16 *buffer, unsigned int size)
}
/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
* (In reality, the frame was really loaded incrementally during the
* entire IP=0 PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
*/
* (In reality, the frame was really loaded incrementally during the
* entire IP=0 PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
*/
if ((m_interp_period == 0) && (m_PC == 12) && (m_subcycle == 1))
{
// HACK for regression testing, be sure to comment out before release!
@ -2573,14 +2573,14 @@ void tms52xx_device::process(INT16 *buffer, unsigned int size)
m_PC++;
}
/* Circuit 412 in the patent ensures that when INHIBIT is true,
* during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch
* count is forced to 0; since the initial stop happens right before
* the switch to IP=0 PC=0 and this code is located after the switch would
* happen, we check for ip=0 inhibit=1, which covers that whole range.
* The purpose of Circuit 412 is to prevent a spurious click caused by
* the voiced source being fed to the filter before all the values have
* been updated during ip=0 when interpolation was inhibited.
*/
* during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch
* count is forced to 0; since the initial stop happens right before
* the switch to IP=0 PC=0 and this code is located after the switch would
* happen, we check for ip=0 inhibit=1, which covers that whole range.
* The purpose of Circuit 412 is to prevent a spurious click caused by
* the voiced source being fed to the filter before all the values have
* been updated during ip=0 when interpolation was inhibited.
*/
m_pitch_count++;
if (m_pitch_count >= m_current_pitch) m_pitch_count = 0;
if ((m_interp_period == 0) && m_inhibit) m_pitch_count = 0;
@ -2622,13 +2622,13 @@ INT32 tms52xx_device::lattice_filter()
{
/* Lattice filter here */
/* Aug/05/07: redone as unrolled loop, for clarity - LN
* Originally Copied verbatim from table I in US patent 4,209,804, now updated
* to be in same order as the actual chip does it, not that it matters.
* notation equivalencies from table:
* Yn(i) == m_u[n-1]
* Kn = m_current_k[n-1]
* bn = m_x[n-1]
*/
* Originally Copied verbatim from table I in US patent 4,209,804, now updated
* to be in same order as the actual chip does it, not that it matters.
* notation equivalencies from table:
* Yn(i) == m_u[n-1]
* Kn = m_current_k[n-1]
* bn = m_x[n-1]
*/
m_u[10] = matrix_multiply(m_previous_energy, (m_excitation_data<<6)); //Y(11)
m_u[9] = m_u[10] - matrix_multiply(m_current_k[9], m_x[9]);
@ -2694,9 +2694,9 @@ void tms52xx_device::data_write(int data)
logerror("tms52xx: data_write triggered talk status to go active!\n");
#endif
/* ...then we now have enough bytes to start talking; clear out
* the new frame parameters (it will become old frame just before the first call to parse_frame())
* TODO: the 3 lines below (and others) are needed for victory
* to not fail its selftest due to a sample ending too late, may require additional investigation */
* the new frame parameters (it will become old frame just before the first call to parse_frame())
* TODO: the 3 lines below (and others) are needed for victory
* to not fail its selftest due to a sample ending too late, may require additional investigation */
m_subcycle = m_subc_reload;
m_PC = 0;
m_interp_period = reload_table[m_tms5220c_rate & 0x3]; // is this correct? should this be always 7 instead, so that the new frame is loaded quickly?
@ -2842,16 +2842,16 @@ void tms52xx_device::parse_frame()
int indx, i, rep_flag;
/* We actually don't care how many bits are left in the fifo here; the
* frame subpart will be processed normally, and any bits extracted 'past
* the end' of the fifo will be read as zeroes; the fifo being emptied will
* set the /BE latch which will halt speech exactly as if a stop frame had
* been encountered (instead of whatever partial frame was read); the same
* exact circuitry is used for both on the real chip, see us patent 4335277
* sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS
* (decode disable) which is active during speak external). */
* frame subpart will be processed normally, and any bits extracted 'past
* the end' of the fifo will be read as zeroes; the fifo being emptied will
* set the /BE latch which will halt speech exactly as if a stop frame had
* been encountered (instead of whatever partial frame was read); the same
* exact circuitry is used for both on the real chip, see us patent 4335277
* sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS
* (decode disable) which is active during speak external). */
/* if the chip is a tms5220C, and the rate mode is set to that each frame (0x04 bit set)
* has a 2 bit rate preceding it, grab two bits here and store them as the rate; */
* has a 2 bit rate preceding it, grab two bits here and store them as the rate; */
if ((m_variant == SUBTYPE_TMS5220C) && (m_tms5220c_rate & 0x04))
{
indx = extract_bits(2);
@ -2895,7 +2895,7 @@ void tms52xx_device::parse_frame()
update_status_and_ints();
if (!m_talk_status) goto ranout;
/* if this is a repeat frame, just do nothing, it will reuse the
* old coefficients */
* old coefficients */
if (rep_flag) return;
// extract first 4 K coefficients
@ -2972,8 +2972,8 @@ void tms52xx_device::update_status_and_ints()
update_ready_state();
/* BL is set if neither byte 9 nor 8 of the fifo are in use; this
* translates to having fifo_count (which ranges from 0 bytes in use to 16
* bytes used) being less than or equal to 8. Victory/Victorba depends on this. */
* translates to having fifo_count (which ranges from 0 bytes in use to 16
* bytes used) being less than or equal to 8. Victory/Victorba depends on this. */
if (m_fifo_count <= 8)
{
// generate an interrupt if necessary; if /BL was inactive and is now active, set int.
@ -2984,7 +2984,7 @@ void tms52xx_device::update_status_and_ints()
m_buffer_low = false;
/* BE is set if neither byte 15 nor 14 of the fifo are in use; this
* translates to having fifo_count equal to exactly 0 */
* translates to having fifo_count equal to exactly 0 */
if (m_fifo_count == 0)
{
// generate an interrupt if necessary; if /BE was inactive and is now active, set int.
@ -2995,8 +2995,8 @@ void tms52xx_device::update_status_and_ints()
m_buffer_empty = false;
/* TS is talk status and is set elsewhere in the fifo parser and in
* the SPEAK command handler; however, if /BE is true during speak external
* mode, it is immediately unset here. */
* the SPEAK command handler; however, if /BE is true during speak external
* mode, it is immediately unset here. */
if (m_speak_external && m_buffer_empty)
{
// generate an interrupt: /TS was active, and is now inactive.
@ -3007,7 +3007,7 @@ void tms52xx_device::update_status_and_ints()
}
}
/* Note that TS being unset will also generate an interrupt when a STOP
* frame is encountered; this is handled in the sample generator code and not here */
* frame is encountered; this is handled in the sample generator code and not here */
}
/******************************************************************************
@ -3214,12 +3214,12 @@ WRITE_LINE_MEMBER( tms52xx_device::rsq_w )
logerror("tms52xx: Scheduling ready cycle for /RS...\n");
#endif
/* upon /RS being activated, /READY goes inactive after 100 nsec from
* data sheet, through 3 asynchronous gates on patent. This is effectively
* within one clock, so we immediately set io_ready to 0 and activate the callback. */
* data sheet, through 3 asynchronous gates on patent. This is effectively
* within one clock, so we immediately set io_ready to 0 and activate the callback. */
m_io_ready = 0;
update_ready_state();
/* How long does /READY stay inactive, when /RS is pulled low?
* I believe its almost always ~16 clocks (25 usec at 800khz as shown on the datasheet) */
* I believe its almost always ~16 clocks (25 usec at 800khz as shown on the datasheet) */
m_ready_timer->adjust(attotime::from_hz(clock()/16));
}
}
@ -3270,22 +3270,22 @@ WRITE_LINE_MEMBER( tms52xx_device::wsq_w )
logerror("tms52xx: Scheduling ready cycle for /WS...\n");
#endif
/* upon /WS being activated, /READY goes inactive after 100 nsec
* from data sheet, through 3 asynchronous gates on patent.
* This is effectively within one clock, so we immediately set
* io_ready to 0 and activate the callback. */
* from data sheet, through 3 asynchronous gates on patent.
* This is effectively within one clock, so we immediately set
* io_ready to 0 and activate the callback. */
m_io_ready = 0;
update_ready_state();
/* Now comes the complicated part: long does /READY stay inactive
* when /WS is pulled low? This depends ENTIRELY on the command written,
* or whether the chip is in speak external mode or not...
* Speak external mode: ~16 cycles
* Command Mode:
* SPK: ? cycles
* SPKEXT: ? cycles
* RDBY: between 60 and 140 cycles
* RB: ? cycles (80?)
* RST: between 60 and 140 cycles
* SET RATE (5220C only): ? cycles (probably ~16) */
* when /WS is pulled low? This depends ENTIRELY on the command written,
* or whether the chip is in speak external mode or not...
* Speak external mode: ~16 cycles
* Command Mode:
* SPK: ? cycles
* SPKEXT: ? cycles
* RDBY: between 60 and 140 cycles
* RB: ? cycles (80?)
* RST: between 60 and 140 cycles
* SET RATE (5220C only): ? cycles (probably ~16) */
// TODO: actually HANDLE the timing differences! currently just assuming always 16 cycles
m_ready_timer->adjust(attotime::from_hz(clock()/16));

26
src/emu/video/pc_vga.c
View File

@ -2994,19 +2994,19 @@ bit 0 Horizontal Total bit 8. Bit 8 of the Horizontal Total register (3d4h
/*
3d4h index 5Eh (R/W): Extended Vertical Overflow Register (80x +)
bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h
index 6). Bits 8 and 9 are in 3d4h index 7 bit 0 and 5.
1 Vertical Display End bit 10. Bit 10 of the Vertical Display End
register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bit 1
and 6
2 Start Vertical Blank bit 10. Bit 10 of the Vertical Start Blanking
register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9
in 3d4h index 9 bit 5
4 Vertical Retrace Start bit 10. Bit 10 of the Vertical Start Retrace
register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bit 2
and 7.
6 Line Compare Position bit 10. Bit 10 of the Line Compare register
(3d4h index 18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h
index 9 bit 6.
index 6). Bits 8 and 9 are in 3d4h index 7 bit 0 and 5.
1 Vertical Display End bit 10. Bit 10 of the Vertical Display End
register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bit 1
and 6
2 Start Vertical Blank bit 10. Bit 10 of the Vertical Start Blanking
register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9
in 3d4h index 9 bit 5
4 Vertical Retrace Start bit 10. Bit 10 of the Vertical Start Retrace
register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bit 2
and 7.
6 Line Compare Position bit 10. Bit 10 of the Line Compare register
(3d4h index 18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h
index 9 bit 6.
*/
case 0x5e:
vga.crtc.vert_total = (vga.crtc.vert_total & 0xfbff) | ((data & 0x01) << 10);

6
src/mame/audio/8080bw.c
View File

@ -1107,9 +1107,9 @@ WRITE8_MEMBER(_8080bw_state::lupin3_sh_port_2_w)
UINT8 rising_bits = data & ~m_port_2_last_extra;
if (rising_bits & 0x01) m_samples->start(0, 6); /* Lands on top of building, wife kicks man */
//if (rising_bits & 0x02) m_samples->start(3, 7); /* deposit money, start intermission, end game */
//if (rising_bits & 0x04) m_samples->start(4, 7); /* deposit money, start intermission, Slides down rope */
//if (rising_bits & 0x08) m_samples->start(5, 7); /* start intermission, end game */
//if (rising_bits & 0x02) m_samples->start(3, 7); /* deposit money, start intermission, end game */
//if (rising_bits & 0x04) m_samples->start(4, 7); /* deposit money, start intermission, Slides down rope */
//if (rising_bits & 0x08) m_samples->start(5, 7); /* start intermission, end game */
if (rising_bits & 0x10) m_samples->start(3, 1); /* Dog barking */
m_color_map = data & 0x40;

2
src/mame/drivers/aerofgt.c
View File

@ -1634,7 +1634,7 @@ static MACHINE_CONFIG_START( aerofgtb, aerofgt_state )
MCFG_DEVICE_ADD("vsystem_spr_ol2", VSYSTEM_SPR2, 0)
MCFG_VSYSTEM_SPR2_SET_TILE_INDIRECT( aerofgt_state, aerofgt_ol2_tile_callback )
MCFG_VSYSTEM_SPR2_SET_GFXREGION(3)
MCFG_VIDEO_START_OVERRIDE(aerofgt_state,turbofrc)
/* sound hardware */

8
src/mame/drivers/btime.c
View File

@ -208,7 +208,7 @@ UINT8 deco_cpu7_device::mi_decrypt::read_decrypted(UINT16 adr)
void deco_cpu7_device::mi_decrypt::write(UINT16 adr, UINT8 val)
{
program->write_byte(adr, val);
had_written = true;
had_written = true;
}
@ -2008,9 +2008,9 @@ DRIVER_INIT_MEMBER(btime_state,tisland)
UINT8 *rom = memregion("maincpu")->base();
/* At location 0xa2b6 there's a strange RLA followed by a BPL that reads from an
unmapped area that causes the game to fail in several circumstances.On the Cassette
version the RLA (33) is in reality a BIT (24),so I'm guessing that there's something
wrong going on in the encryption scheme.*/
unmapped area that causes the game to fail in several circumstances.On the Cassette
version the RLA (33) is in reality a BIT (24),so I'm guessing that there's something
wrong going on in the encryption scheme.*/
memset(&rom[0xa2b6],0x24,1);
m_audio_nmi_enable_type = AUDIO_ENABLE_DIRECT;

2
src/mame/drivers/cntsteer.c
View File

@ -887,7 +887,7 @@ static MACHINE_CONFIG_START( cntsteer, cntsteer_state )
MCFG_CPU_ADD("subcpu", M6809, 2000000) /* ? */
MCFG_CPU_PROGRAM_MAP(cntsteer_cpu2_map)
// MCFG_DEVICE_DISABLE()
// MCFG_DEVICE_DISABLE()
MCFG_CPU_VBLANK_INT_DRIVER("screen", cntsteer_state, nmi_line_pulse) /* ? */
MCFG_CPU_ADD("audiocpu", M6502, 1500000) /* ? */

56
src/mame/drivers/cps1.c
View File

@ -1813,18 +1813,18 @@ INPUT_PORTS_END
/* To-Do sf2amf dipswitch SW(B):4 + SW(B):5 + SW(B):6
static INPUT_PORTS_START( sf2amf )
PORT_INCLUDE( )
PORT_INCLUDE( )
PORT_MODIFY("DSWB")
PORT_DIPNAME( 0x08, 0x00, "Turbo Switch 1 of 3" ) PORT_DIPLOCATION("SW(B):4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x00, "Turbo Switch 2 of 3" ) PORT_DIPLOCATION("SW(B):5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x00, "Turbo Switch 3 of 3" ) PORT_DIPLOCATION("SW(B):6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_MODIFY("DSWB")
PORT_DIPNAME( 0x08, 0x00, "Turbo Switch 1 of 3" ) PORT_DIPLOCATION("SW(B):4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x00, "Turbo Switch 2 of 3" ) PORT_DIPLOCATION("SW(B):5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x00, "Turbo Switch 3 of 3" ) PORT_DIPLOCATION("SW(B):6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
*/
@ -6576,13 +6576,13 @@ ROM_END
ROM_START( sf2stt )
ROM_REGION( CODE_SIZE, "maincpu", 0 ) /* 68000 code */
/* do not comment this out, this is only for testing purpose
ROM_LOAD16_BYTE( "12.bin", 0x00000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) )
ROM_LOAD16_BYTE( "09.bin", 0x00001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) )
*/
ROM_LOAD16_BYTE( "12.bin", 0x00000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) )
ROM_LOAD16_BYTE( "09.bin", 0x00001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) )
*/
ROM_LOAD16_BYTE( "prg part 1.stt", 0x00000, 0x40000, NO_DUMP )
ROM_LOAD16_BYTE( "prg part 2.stt", 0x00001, 0x40000, NO_DUMP )
/* there are two empty sockets next to the two following program roms,
these roms may be missing and this PCB is not working on real hardware */
these roms may be missing and this PCB is not working on real hardware */
ROM_LOAD16_BYTE( "ce91e-b", 0x80000, 0x40000, CRC(0862386e) SHA1(9fcfbcbbc17529de75d5419018e7b1dd90b397c0) )
ROM_LOAD16_BYTE( "ce91e-a", 0x80001, 0x40000, CRC(0c83844d) SHA1(4c25ba4a50d62c62789d026e3d304ed1dfb3c248) )
@ -6625,15 +6625,15 @@ ROM_END
ROM_START( sf2unkb )
ROM_REGION( CODE_SIZE, "maincpu", 0 ) /* 68000 code */
/* do not comment this out, this is only for testing purpose
ROM_LOAD16_BYTE( "12.bin", 0x000000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) )
ROM_LOAD16_BYTE( "09.bin", 0x000001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) )
ROM_LOAD16_BYTE( "11.bin", 0x080000, 0x40000, CRC(82097d63) SHA1(881e7ffb78197f6794b5d41f5c2c87da35e8cb15) )
ROM_LOAD16_BYTE( "10.bin", 0x080001, 0x40000, CRC(0c83844d) SHA1(4c25ba4a50d62c62789d026e3d304ed1dfb3c248) )
*/
ROM_LOAD16_BYTE( "12.bin", 0x000000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) )
ROM_LOAD16_BYTE( "09.bin", 0x000001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) )
ROM_LOAD16_BYTE( "11.bin", 0x080000, 0x40000, CRC(82097d63) SHA1(881e7ffb78197f6794b5d41f5c2c87da35e8cb15) )
ROM_LOAD16_BYTE( "10.bin", 0x080001, 0x40000, CRC(0c83844d) SHA1(4c25ba4a50d62c62789d026e3d304ed1dfb3c248) )
*/
ROM_LOAD16_BYTE( "prg part 1.sf2unkb", 0x00000, 0x80000, NO_DUMP )
ROM_LOAD16_BYTE( "prg part 2.sf2unkb", 0x00001, 0x80000, NO_DUMP )
/* there are two empty sockets next to the two following program roms,
these roms may be missing and this PCB is not working on real hardware */
these roms may be missing and this PCB is not working on real hardware */
ROM_LOAD16_BYTE( "w-6", 0x100000, 0x20000, CRC(bb4af315) SHA1(75f0827f4f7e9f292add46467f8d4fe19b2514c9) )
ROM_LOAD16_BYTE( "w-5", 0x100001, 0x20000, CRC(c02a13eb) SHA1(b807cc495bff3f95d03b061fc629c95f965cb6d8) )
@ -6671,8 +6671,8 @@ ROM_START( sf2unkb )
ROM_REGION( 0x40000, "oki", 0 ) /* Samples */
ROM_LOAD( "sample part 1.unkb", 0x20000, 0x20000, NO_DUMP )
/* do not comment this out, this is only for testing purpose
ROM_LOAD( "sf2_18.11c", 0x00000, 0x20000, CRC(7f162009) SHA1(346bf42992b4c36c593e21901e22c87ae4a7d86d) )
*/
ROM_LOAD( "sf2_18.11c", 0x00000, 0x20000, CRC(7f162009) SHA1(346bf42992b4c36c593e21901e22c87ae4a7d86d) )
*/
ROM_LOAD( "w-7", 0x20000, 0x20000, CRC(beade53f) SHA1(277c397dc12752719ec6b47d2224750bd1c07f79) )
ROM_END
@ -8323,14 +8323,14 @@ ROM_START( sf2amf )
ROM_LOAD16_BYTE( "5.amf", 0x000000, 0x80000, CRC(03991fba) SHA1(6c42bf15248640fdb3e98fb01b0a870649deb410) )
ROM_LOAD16_BYTE( "4.amf", 0x000001, 0x80000, CRC(39f15a1e) SHA1(901c4fea76bf5bff7330ed07ffde54cdccdaa680) )
/* there are two empty sockets next to the two former program roms,
these roms may be missing and this PCB is not working on real hardware */
these roms may be missing and this PCB is not working on real hardware */
ROM_LOAD16_BYTE( "prg part 3.amf", 0x100000, 0x40000, NO_DUMP )
ROM_LOAD16_BYTE( "prg part 4.amf", 0x100001, 0x40000, NO_DUMP )
/* do not comment this out, this is only for testing purpose
ROM_LOAD16_BYTE( "u221.rom", 0x100000, 0x20000, CRC(64e6e091) SHA1(32ec05db955e538d4ada26d19ee50926f74b684f) )
ROM_LOAD16_BYTE( "u195.rom", 0x100001, 0x20000, CRC(c95e4443) SHA1(28417dee9ccdfa65b0f4a92aa29b90279fe8cd85) )
*/
ROM_LOAD16_BYTE( "u221.rom", 0x100000, 0x20000, CRC(64e6e091) SHA1(32ec05db955e538d4ada26d19ee50926f74b684f) )
ROM_LOAD16_BYTE( "u195.rom", 0x100001, 0x20000, CRC(c95e4443) SHA1(28417dee9ccdfa65b0f4a92aa29b90279fe8cd85) )
*/
ROM_REGION( 0x600000, "gfx", 0 )
ROMX_LOAD( "y.c.e.c m.k.r-001", 0x000000, 0x80000, CRC(a258de13) SHA1(2e477948c4c8a2fb7cfdc4a739766bc4a4e01c49), ROM_GROUPWORD | ROM_SKIP(6) )
ROM_CONTINUE( 0x000002, 0x80000)

24
src/mame/drivers/ddenlovr.c
View File

@ -445,8 +445,8 @@ static int blit_draw( running_machine &machine, int src, int sx )
arg_size = fetch_word(src_data, src_len, &bit_addr, 4) + 1;
#ifdef MAME_DEBUG
// if (pen_size > 4 || arg_size > 8)
// popmessage("warning: pen_size %d arg_size %d", pen_size, arg_size);
// if (pen_size > 4 || arg_size > 8)
// popmessage("warning: pen_size %d arg_size %d", pen_size, arg_size);
#endif
// sryudens game bug
@ -2513,14 +2513,14 @@ static ADDRESS_MAP_START( kotbinyo_portmap, AS_IO, 8, dynax_state )
AM_RANGE(0x83, 0x84) AM_READ(hanakanz_gfxrom_r)
AM_RANGE(0xa0, 0xa1) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w)
AM_RANGE(0xb0, 0xb0) AM_READ_PORT("SYSTEM")
// AM_RANGE(0xb1, 0xb2) AM_READ(hanakanz_keyb_r)
// AM_RANGE(0xb1, 0xb2) AM_READ(hanakanz_keyb_r)
AM_RANGE(0xb1, 0xb1) AM_READ_PORT("KEYB0")
AM_RANGE(0xb2, 0xb2) AM_READ_PORT("KEYB1")
AM_RANGE(0xb3, 0xb3) AM_WRITE(hanakanz_coincounter_w)
// AM_RANGE(0xb4, 0xb4) AM_WRITE(hanakanz_keyb_w)
// AM_RANGE(0xb4, 0xb4) AM_WRITE(hanakanz_keyb_w)
AM_RANGE(0xb6, 0xb6) AM_READ(hanakanz_rand_r)
AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("oki", okim6295_device, read, write)
// AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
// AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
ADDRESS_MAP_END
@ -2537,14 +2537,14 @@ static ADDRESS_MAP_START( kotbinsp_portmap, AS_IO, 8, dynax_state )
AM_RANGE(0x83, 0x84) AM_READ(hanakanz_gfxrom_r)
AM_RANGE(0xa0, 0xa1) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w)
AM_RANGE(0x90, 0x90) AM_READ_PORT("SYSTEM")
// AM_RANGE(0x91, 0x91) AM_READ(hanakanz_keyb_r)
// AM_RANGE(0x91, 0x91) AM_READ(hanakanz_keyb_r)
AM_RANGE(0x91, 0x91) AM_READ_PORT("KEYB0")
AM_RANGE(0x92, 0x92) AM_READ_PORT("KEYB1")
AM_RANGE(0x93, 0x93) AM_WRITE(hanakanz_coincounter_w)
// AM_RANGE(0x94, 0x94) AM_WRITE(hanakanz_keyb_w)
// AM_RANGE(0x94, 0x94) AM_WRITE(hanakanz_keyb_w)
AM_RANGE(0x96, 0x96) AM_READ(hanakanz_rand_r)
AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("oki", okim6295_device, read, write)
// AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
// AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
ADDRESS_MAP_END
@ -5178,7 +5178,7 @@ static INPUT_PORTS_START( kotbinsp )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("KEYB0")
// Forced Joystick mode wrt kotbinyo:
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 ) // * press at boot for service mode
@ -9133,7 +9133,7 @@ static MACHINE_CONFIG_START( kotbinyo, dynax_state )
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80)
/* devices */
// MCFG_MSM6242_ADD("rtc", hanakanz_rtc_intf)
// MCFG_MSM6242_ADD("rtc", hanakanz_rtc_intf)
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( kotbinsp, kotbinyo )
@ -10531,7 +10531,7 @@ Other - ACTEL A1010B
DIPs - 10-Position (x2)
HSync - 15.1015kHz
VSync - 60.1656Hz
no RTC nor battery (unpopulated)
***************************************************************************/
@ -10579,7 +10579,7 @@ ROM_START( kotbinsp )
ROM_LOAD16_BYTE( "909035.8c", 0x000001, 0x100000, CRC(cea4dbfa) SHA1(581bbcfcb0c900667002b7b744197d039d586833) )
ROM_LOAD16_BYTE( "909034.6b", 0x200000, 0x080000, CRC(9f366a2a) SHA1(2199cf640b665bd1ba3eac081bde288dec521383) )
ROM_LOAD16_BYTE( "909033.6c", 0x200001, 0x080000, CRC(9388b85d) SHA1(a35fe0b585cba256bb5575f7b539b33dd0ca3aa0) )
ROM_FILL( 0x300000, 0x100000, 0xff )
ROM_FILL( 0x300000, 0x100000, 0xff )
// mirror the whole address space (25 bits)
ROM_COPY( "blitter", 0, 0x0400000, 0x400000 )
ROM_COPY( "blitter", 0, 0x0800000, 0x400000 )

74
src/mame/drivers/dec8.c
View File

@ -2079,10 +2079,10 @@ static MACHINE_CONFIG_START( lastmisn, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_lastmisn)
@ -2118,7 +2118,7 @@ static MACHINE_CONFIG_START( shackled, dec8_state )
MCFG_CPU_PROGRAM_MAP(ym3526_s_map)
/* NMIs are caused by the main CPU */
// MCFG_QUANTUM_TIME(attotime::from_hz(100000))
// MCFG_QUANTUM_TIME(attotime::from_hz(100000))
MCFG_QUANTUM_PERFECT_CPU("maincpu") // needs heavy sync, otherwise one of the two CPUs will miss an irq and makes the game to hang
/* video hardware */
@ -2128,10 +2128,10 @@ static MACHINE_CONFIG_START( shackled, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_shackled)
@ -2176,10 +2176,10 @@ static MACHINE_CONFIG_START( gondo, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_gondo)
MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8)
@ -2225,10 +2225,10 @@ static MACHINE_CONFIG_START( garyoret, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_garyoret)
MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8)
@ -2277,10 +2277,10 @@ static MACHINE_CONFIG_START( ghostb, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_ghostb)
MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8)
@ -2328,10 +2328,10 @@ static MACHINE_CONFIG_START( csilver, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_lastmisn)
@ -2384,10 +2384,10 @@ static MACHINE_CONFIG_START( oscar, dec8_state )
deco_mxc06_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_oscar)
@ -2426,10 +2426,10 @@ static MACHINE_CONFIG_START( srdarwin, dec8_state )
MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_srdarwin)
@ -2477,10 +2477,10 @@ static MACHINE_CONFIG_START( cobracom, dec8_state )
MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
// MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_cobracom)

50
src/mame/drivers/firebeat.c
View File

@ -106,26 +106,26 @@
The display list objects seem to be there, but the address is wrong (0x14c400, instead of the correct address)
- The external Yamaha MIDI sound board is not emulated (no keyboard sounds).
- Notes on how the video is supposed to work from Ville / Ian Patterson:
There are four "display contexts" that are set up via registers 20-4E. They are
basically just raw framebuffers. 40-4E sets the base framebuffer pointer, 30-3E
sets the size, 20-2E may set the minimum x and y coordinates but I haven't seen
them set to something other than 0 yet. One context is set as the one the RAMDAC
outputs to the monitor (not sure how this is selected yet, probably the lower
bits of register 12). Thestartup test in the popn BIOS checks all of VRAM, so
it moves the currentdisplay address around so you don't see crazy colors, which
is very helpful in figuring out how this part works.
The other new part is that there are two VRAM write ports, managed by registers
60+68+70 and 64+6A+74, with status read from the lower bits of reg 7A. Each context
can either write to VRAM as currently emulated, or the port can be switched in to
"immediate mode" via registers 68/6A. Immedate mode can be used to run GCU commands
at any point during the frame. It's mainly used to call display lists, which is where
the display list addresses come from. Some games use it to send other commands, so
it appears to be a 4-dword FIFO or something along those lines.
- Notes on how the video is supposed to work from Ville / Ian Patterson:
There are four "display contexts" that are set up via registers 20-4E. They are
basically just raw framebuffers. 40-4E sets the base framebuffer pointer, 30-3E
sets the size, 20-2E may set the minimum x and y coordinates but I haven't seen
them set to something other than 0 yet. One context is set as the one the RAMDAC
outputs to the monitor (not sure how this is selected yet, probably the lower
bits of register 12). Thestartup test in the popn BIOS checks all of VRAM, so
it moves the currentdisplay address around so you don't see crazy colors, which
is very helpful in figuring out how this part works.
The other new part is that there are two VRAM write ports, managed by registers
60+68+70 and 64+6A+74, with status read from the lower bits of reg 7A. Each context
can either write to VRAM as currently emulated, or the port can be switched in to
"immediate mode" via registers 68/6A. Immedate mode can be used to run GCU commands
at any point during the frame. It's mainly used to call display lists, which is where
the display list addresses come from. Some games use it to send other commands, so
it appears to be a 4-dword FIFO or something along those lines.
*/
#include "emu.h"
@ -730,7 +730,7 @@ static void GCU_w(running_machine &machine, int chip, UINT32 offset, UINT32 data
}
case 0x40: /* framebuffer config */
// HACK: switch display lists at the right times for the ParaParaParadise games until we
// HACK: switch display lists at the right times for the ParaParaParadise games until we
// do the video emulation properly
if (mame_strnicmp(machine.system().name, "pp", 2) == 0)
{
@ -1190,14 +1190,14 @@ static void atapi_command_reg_w(running_machine &machine, int reg, UINT16 data)
//if (state->m_atapi_drivesel==1) logerror("!!!ATAPI COMMAND %x\n", state->m_atapi_data[0]&0xff);
switch (state->m_atapi_data[0]&0xff)
{
case 0x55: // MODE SELECT
state->m_atapi_cdata_wait = state->m_atapi_data[4]/2;
state->m_atapi_data_ptr = 0;
logerror("ATAPI: Waiting for %x bytes of MODE SELECT data\n", state->m_atapi_cdata_wait);
break;
case 0xa8: // READ (12)
// indicate data ready: set DRQ and DMA ready, and IO in INTREASON
state->m_atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ | ATAPI_STAT_SERVDSC;
@ -1209,8 +1209,8 @@ static void atapi_command_reg_w(running_machine &machine, int reg, UINT16 data)
case 0x00: // BUS RESET / TEST UNIT READY
case 0xbb: // SET CD SPEED
case 0xa5: // PLAY AUDIO
case 0x1b: // START_STOP_UNIT
case 0x4e: // STOPPLAY_SCAN
case 0x1b: // START_STOP_UNIT
case 0x4e: // STOPPLAY_SCAN
state->m_atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
break;
}
@ -2394,7 +2394,7 @@ ROM_START( ppp1mp )
ROM_REGION(0x400000, "ymz", ROMREGION_ERASE00)
ROM_REGION(0xc0, "user2", 0) // Security dongle
ROM_LOAD( "gqa11-ja", 0x000000, 0x0000c0, CRC(2ed8e2ae) SHA1(b8c3410dab643111b2d2027068175ba018a0a67e) )
ROM_LOAD( "gqa11-ja", 0x000000, 0x0000c0, CRC(2ed8e2ae) SHA1(b8c3410dab643111b2d2027068175ba018a0a67e) )
DISK_REGION( "scsi0" )
DISK_IMAGE_READONLY( "a11jaa01", 0, SHA1(539ec6f1c1d198b0d6ce5543eadcbb4d9917fa42) )

2
src/mame/drivers/funworld.c
View File

@ -5165,7 +5165,7 @@ DRIVER_INIT_MEMBER(funworld_state, ctunk)
CTUNK: Rare board with blue TAB board encryption scheme
plus a daughterboard for program encryption.
*********************************************************/
{
UINT8 *rom = machine().root_device().memregion("maincpu")->base();

24
src/mame/drivers/goldstar.c
View File

@ -634,8 +634,8 @@ static ADDRESS_MAP_START( megaline_portmap, AS_IO, 8, goldstar_state )
AM_RANGE(0xe0, 0xe0) AM_DEVWRITE("sn3", sn76489_device, write) /* SN76489 #3 */
AM_RANGE(0x60, 0x60) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w) /* AY8910 control? */
AM_RANGE(0x80, 0x80) AM_DEVREADWRITE_LEGACY("aysnd", ay8910_r, ay8910_data_w) /* AY8910 Input? */
// AM_RANGE(0x01, 0x01) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
// AM_RANGE(0x02, 0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
// AM_RANGE(0x01, 0x01) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
// AM_RANGE(0x02, 0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
ADDRESS_MAP_END
@ -7012,9 +7012,9 @@ static MACHINE_CONFIG_START( megaline, goldstar_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", goldstar_state, nmi_line_pulse)
/* 3x 8255 */
// MCFG_I8255A_ADD( "ppi8255_0", lucky8_ppi8255_0_intf )
// MCFG_I8255A_ADD( "ppi8255_1", lucky8_ppi8255_1_intf )
// MCFG_I8255A_ADD( "ppi8255_2", lucky8_ppi8255_2_intf )
// MCFG_I8255A_ADD( "ppi8255_0", lucky8_ppi8255_0_intf )
// MCFG_I8255A_ADD( "ppi8255_1", lucky8_ppi8255_1_intf )
// MCFG_I8255A_ADD( "ppi8255_2", lucky8_ppi8255_2_intf )
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@ -7027,7 +7027,7 @@ static MACHINE_CONFIG_START( megaline, goldstar_state )
MCFG_GFXDECODE(megaline)
MCFG_PALETTE_LENGTH(256)
// MCFG_NVRAM_ADD_1FILL("nvram")
// MCFG_NVRAM_ADD_1FILL("nvram")
MCFG_VIDEO_START_OVERRIDE(goldstar_state,goldstar)
@ -10499,7 +10499,7 @@ ROM_END
==========================
Custom 06B53P 9G1 - DIP 28
Custom 06B53P 9G1 - DIP 28
==========================
Pinout
======
@ -10555,7 +10555,7 @@ ROM_END
08 -> M2(16)
09 -> M2(15)
10 -> M2(12)
11 -> N2(19) -> 10k -> +5V
11 -> N2(19) -> 10k -> +5V
12 -> GND
13 -> GND
14 -> M2(06)
@ -10632,7 +10632,7 @@ ROM_END
========
BPROMS:
========
GND-------------+ +----------N3(10)
GND-----------+ | | +--------N3(06)
K5(06)------+ | | | | +------(N/C)
@ -10643,7 +10643,7 @@ ROM_END
|>## 24S10 @M3 ###|
|#################|
+-+-+-+-+-+-+-+-+-+
| | | | | | | |
| | | | | | | |
K5(15)----+ | | | | | | +----GND
K3(12)------+ | | | | +------D3(03)
K3(14)--------+ | | +--------D3(11)
@ -10654,7 +10654,7 @@ ROM_END
J3(10)---+ +----J3(11)
K5(05)---+ | | +----J3(12)
H3(05)----+ | | | | +-----J3(13)
+5V-------+ | | | | | |
+5V-------+ | | | | | |
| | | | | | | +-------------------+
| | | | | | | | |
+-----------------+ |
@ -10778,7 +10778,7 @@ ROM_END
| | | | | | +--------------|-|-+
| | | | | | | +------------|-+
| | | | | | | | +----------+
| | | | | | | | |
| | | | | | | | |
| +---+-+-+-+-+-+-+-+---+
| | 1+---------------+8 |
| | | | | | | | | | | |

6
src/mame/drivers/naomi.c
View File

@ -5617,9 +5617,9 @@ ROM_START( ninjaslt4 )
NAOMI_DEFAULT_EEPROM
ROM_REGION( 0xb000000, "rom_board", ROMREGION_ERASEFF)
ROM_LOAD( "nja1_fl1.2d", 0x0800000, 0x0800000, CRC(a57c0576) SHA1(0c99a3e648798bf6a100512d682c08a3d4f05958) )
ROM_LOAD( "nja1_fl2.2c", 0x1000000, 0x0800000, CRC(1f81f46b) SHA1(7677f881b84233f3f95a792f9be6f618cba6d586) )
ROM_LOAD( "nja1_fl3.2b", 0x1800000, 0x0800000, CRC(24974c3d) SHA1(cd64dec682688e26fca91873e5e7b6e0d931d1ce) )
ROM_LOAD( "nja1_fl1.2d", 0x0800000, 0x0800000, CRC(a57c0576) SHA1(0c99a3e648798bf6a100512d682c08a3d4f05958) )
ROM_LOAD( "nja1_fl2.2c", 0x1000000, 0x0800000, CRC(1f81f46b) SHA1(7677f881b84233f3f95a792f9be6f618cba6d586) )
ROM_LOAD( "nja1_fl3.2b", 0x1800000, 0x0800000, CRC(24974c3d) SHA1(cd64dec682688e26fca91873e5e7b6e0d931d1ce) )
ROM_LOAD( "nja1ma2.4l", 0x2000000, 0x1000000, CRC(5af34ea0) SHA1(b49a50e995cb6682782b0643d40001b9bffe0118) )
ROM_LOAD( "nja1ma3.4k", 0x3000000, 0x1000000, CRC(504a89b3) SHA1(e0b90542f80527e998db7ee3bb75e36c375cacba) )
ROM_LOAD( "nja1ma4.4j", 0x4000000, 0x1000000, CRC(d5c2799a) SHA1(ce46c1aa38479d9e5e350573bc6b214979b88dbc) )

8
src/mame/drivers/s6a.c
View File

@ -261,8 +261,8 @@ INPUT_CHANGED_MEMBER( s6a_state::audio_nmi )
WRITE8_MEMBER( s6a_state::sol0_w )
{
// if (BIT(data, 4))
// m_samples->start(2, 5); // outhole
// if (BIT(data, 4))
// m_samples->start(2, 5); // outhole
}
WRITE8_MEMBER( s6a_state::sol1_w )
@ -287,8 +287,8 @@ WRITE8_MEMBER( s6a_state::sol1_w )
m_pias->cb1_w(m_cb1);
// if (BIT(data, 5))
// m_samples->start(0, 6); // knocker
// if (BIT(data, 5))
// m_samples->start(0, 6); // knocker
}
static const pia6821_interface pia22_intf =

16
src/mame/drivers/scramble.c
View File

@ -1789,18 +1789,18 @@ ROM_END
Triple Punch
(C)1982 KKI
board silkscreend PCO-008-01
board silkscreend PCO-008-01
Empty 24 pin socket at 2E
Empty 40 pin socket at 0A
.2h 2732 stickered TD4
.2k 2732 stickered TC3
.2l 2732 stickered TE2
.2m 2732 stickered TD1
.5h 2716 stickered TA7
.5f 2716 stickered TA6
.6e 82s123 stickered TA
.2h 2732 stickered TD4
.2k 2732 stickered TC3
.2l 2732 stickered TE2
.2m 2732 stickered TD1
.5h 2716 stickered TA7
.5f 2716 stickered TA6
.6e 82s123 stickered TA
***************************************************************************/
ROM_START( triplepa )

74
src/mame/drivers/supercrd.c
View File

@ -34,7 +34,7 @@
ROMs: PRG: 2x 27C512 (IC37, IC51)
GFX: 2x 27C512 (IC10, IC11)
BP: 1x N82S147N
BP: 1x N82S147N
1x Xtal 16 MHz.
1x 8 DIP switches bank.
@ -276,9 +276,9 @@ static ADDRESS_MAP_START( supercrd_map, AS_PROGRAM, 8, supercrd_state )
AM_RANGE(0x0000, 0xbfff) AM_ROM
AM_RANGE(0xc000, 0xcfff) AM_RAM_WRITE(supercrd_videoram_w) AM_SHARE("videoram") // wrong
AM_RANGE(0xd000, 0xdfff) AM_RAM_WRITE(supercrd_colorram_w) AM_SHARE("colorram") // wrong
// AM_RANGE(0x0000, 0x0000) AM_RAM AM_SHARE("nvram")
// AM_RANGE(0xe000, 0xe000) AM_DEVWRITE("crtc", mc6845_device, address_w)
// AM_RANGE(0xe001, 0xe001) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
// AM_RANGE(0x0000, 0x0000) AM_RAM AM_SHARE("nvram")
// AM_RANGE(0xe000, 0xe000) AM_DEVWRITE("crtc", mc6845_device, address_w)
// AM_RANGE(0xe001, 0xe001) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
ADDRESS_MAP_END
@ -401,16 +401,16 @@ GFXDECODE_END
//static const mc6845_interface mc6845_intf =
//{
// "screen", /* screen we are acting on */
// 4, /* number of pixels per video memory address */
// NULL, /* before pixel update callback */
// NULL, /* row update callback */
// NULL, /* after pixel update callback */
// DEVCB_NULL, /* callback for display state changes */
// DEVCB_NULL, /* callback for cursor state changes */
// DEVCB_NULL, /* HSYNC callback */
// DEVCB_NULL, /* VSYNC callback */
// NULL /* update address callback */
// "screen", /* screen we are acting on */
// 4, /* number of pixels per video memory address */
// NULL, /* before pixel update callback */
// NULL, /* row update callback */
// NULL, /* after pixel update callback */
// DEVCB_NULL, /* callback for display state changes */
// DEVCB_NULL, /* callback for cursor state changes */
// DEVCB_NULL, /* HSYNC callback */
// DEVCB_NULL, /* VSYNC callback */
// NULL /* update address callback */
//};
@ -420,24 +420,24 @@ GFXDECODE_END
//static I8255_INTERFACE (ppi8255_intf_0)
//{
// /* (port) Mode X - description */
// DEVCB_UNMAPPED, /* Port A read */
// DEVCB_UNMAPPED, /* Port A write */
// DEVCB_UNMAPPED, /* Port B read */
// DEVCB_UNMAPPED, /* Port B write */
// DEVCB_UNMAPPED, /* Port C read */
// DEVCB_UNMAPPED /* Port C write */
// /* (port) Mode X - description */
// DEVCB_UNMAPPED, /* Port A read */
// DEVCB_UNMAPPED, /* Port A write */
// DEVCB_UNMAPPED, /* Port B read */
// DEVCB_UNMAPPED, /* Port B write */
// DEVCB_UNMAPPED, /* Port C read */
// DEVCB_UNMAPPED /* Port C write */
//};
//static I8255_INTERFACE (ppi8255_intf_1)
//{
// /* (port) Mode X - description */
// DEVCB_UNMAPPED, /* Port A read */
// DEVCB_UNMAPPED, /* Port A write */
// DEVCB_UNMAPPED, /* Port B read */
// DEVCB_UNMAPPED, /* Port B write */
// DEVCB_UNMAPPED, /* Port C read */
// DEVCB_UNMAPPED /* Port C write */
// /* (port) Mode X - description */
// DEVCB_UNMAPPED, /* Port A read */
// DEVCB_UNMAPPED, /* Port A write */
// DEVCB_UNMAPPED, /* Port B read */
// DEVCB_UNMAPPED, /* Port B write */
// DEVCB_UNMAPPED, /* Port C read */
// DEVCB_UNMAPPED /* Port C write */
//};
/**************************
@ -449,10 +449,10 @@ static MACHINE_CONFIG_START( supercrd, supercrd_state )
MCFG_CPU_ADD("maincpu", Z80, MASTER_CLOCK/8) /* 2MHz, guess */
MCFG_CPU_PROGRAM_MAP(supercrd_map)
// MCFG_NVRAM_ADD_0FILL("nvram")
// MCFG_NVRAM_ADD_0FILL("nvram")
// MCFG_I8255_ADD( "ppi8255_0", ppi8255_intf_0 )
// MCFG_I8255_ADD( "ppi8255_1", ppi8255_intf_1 )
// MCFG_I8255_ADD( "ppi8255_0", ppi8255_intf_0 )
// MCFG_I8255_ADD( "ppi8255_1", ppi8255_intf_1 )
/* video hardware */
@ -469,12 +469,12 @@ static MACHINE_CONFIG_START( supercrd, supercrd_state )
MCFG_PALETTE_INIT_OVERRIDE(supercrd_state, supercrd)
MCFG_VIDEO_START_OVERRIDE(supercrd_state, supercrd)
// MCFG_MC6845_ADD("crtc", MC6845, MASTER_CLOCK/8, mc6845_intf)
// MCFG_MC6845_ADD("crtc", MC6845, MASTER_CLOCK/8, mc6845_intf)
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
MACHINE_CONFIG_END
@ -488,10 +488,10 @@ ROM_START( supercrd )
ROM_LOAD( "supca_417_ce2.ic51", 0x10000, 0x08000, CRC(36415f73) SHA1(9881b88991f034d79260502289432a7318aa1647) ) // wrong
ROM_IGNORE( 0x8000)
// ROM_LOAD( "supca_417_ce1.ic37", 0x0000, 0x8000, CRC(b67f7d38) SHA1(eaf8f24d476185d4744858afcbf0005362f49cab) )
// ROM_CONTINUE( 0x0000, 0x8000)
// ROM_LOAD( "supca_417_ce2.ic51", 0x8000, 0x8000, CRC(36415f73) SHA1(9881b88991f034d79260502289432a7318aa1647) )
// ROM_IGNORE( 0x8000)
// ROM_LOAD( "supca_417_ce1.ic37", 0x0000, 0x8000, CRC(b67f7d38) SHA1(eaf8f24d476185d4744858afcbf0005362f49cab) )
// ROM_CONTINUE( 0x0000, 0x8000)
// ROM_LOAD( "supca_417_ce2.ic51", 0x8000, 0x8000, CRC(36415f73) SHA1(9881b88991f034d79260502289432a7318aa1647) )
// ROM_IGNORE( 0x8000)
ROM_REGION( 0x20000, "gfxtemp", 0 )
ROM_LOAD( "supca_410_zg2.ic11", 0x00000, 0x10000, CRC(a4646dc6) SHA1(638ad334bb4f1430381474ddfaa1029cb4d13916) )

4
src/mame/drivers/vastar.c
View File

@ -199,12 +199,12 @@ static INPUT_PORTS_START( vastar )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNKNOWN )
PORT_START("DSW1")
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) ) PORT_DIPLOCATION("DSW1:1,2")
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) ) PORT_DIPLOCATION("DSW1:1,2")
PORT_DIPSETTING( 0x03, "3" )
PORT_DIPSETTING( 0x02, "4" )
PORT_DIPSETTING( 0x01, "5" )
PORT_DIPSETTING( 0x00, "6" )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:3")
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:3")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x04, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, "Show Author Credits" ) PORT_DIPLOCATION("DSW1:4")

2
src/mame/drivers/zn.c
View File

@ -422,7 +422,7 @@ static void zn_driver_init( running_machine &machine )
{
state->m_znsec0->init( zn_config_table[ n_game ].p_n_mainsec );
state->m_znsec1->init( zn_config_table[ n_game ].p_n_gamesec );
// psx_sio_install_handler( machine, 0, sio_pad_handler );
// psx_sio_install_handler( machine, 0, sio_pad_handler );
break;
}
n_game++;

256
src/mame/machine/pgmcrypt.c
View File

@ -161,14 +161,14 @@ void pgm_kovsh_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1_ALT
IGS27_CRYPT1_ALT
IGS27_CRYPT2_ALT2
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
x ^= kovsh_tab[i & 0xff] << 8;
@ -209,12 +209,12 @@ void pgm_photoy2k_decrypt(running_machine &machine)
IGS27_CRYPT1_ALT
IGS27_CRYPT2_ALT3
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5_ALT
IGS27_CRYPT6
IGS27_CRYPT6
IGS27_CRYPT7_ALT
IGS27_CRYPT8
IGS27_CRYPT8
x ^= photoy2k_tab[i & 0xff] << 8;
@ -252,13 +252,13 @@ void pgm_pstar_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8
IGS27_CRYPT1
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8
x = x ^ pstar[(i & 255)] << 8;
src[i] = x ;
@ -294,14 +294,14 @@ void pgm_dfront_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1_ALT
IGS27_CRYPT2
IGS27_CRYPT3
IGS27_CRYPT1_ALT
IGS27_CRYPT2
IGS27_CRYPT3
IGS27_CRYPT4_ALT
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8
x ^= dfront_tab[(i>> 1) & 0xff] << 8;
@ -343,10 +343,10 @@ void pgm_ddp2_decrypt(running_machine &machine)
// NO CRYPT2
// NO CRYPT3
IGS27_CRYPT4_ALT
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7_ALT
IGS27_CRYPT8_ALT
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7_ALT
IGS27_CRYPT8_ALT
x ^= ddp2_tab[(i>> 1) & 0xff] << 8;
@ -384,14 +384,14 @@ void pgm_mm_decrypt(running_machine &machine) // and dw2001
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1
IGS27_CRYPT2_ALT
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT1
IGS27_CRYPT2_ALT
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8_ALT
x ^= mm_tab[(i>> 1) & 0xff] << 8;
@ -428,13 +428,13 @@ void pgm_kov2_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1_ALT
IGS27_CRYPT1_ALT
// NO CRYPT2
IGS27_CRYPT3
IGS27_CRYPT3
IGS27_CRYPT4_ALT
IGS27_CRYPT5_ALT
IGS27_CRYPT6_ALT
IGS27_CRYPT7_ALT
IGS27_CRYPT7_ALT
IGS27_CRYPT8_ALT
x ^= kov2_tab[(i >> 1) & 0xff] << 8;
@ -472,14 +472,14 @@ void pgm_kov2p_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1_ALT
IGS27_CRYPT2_ALT
IGS27_CRYPT3
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT1_ALT
IGS27_CRYPT2_ALT
IGS27_CRYPT3
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
x ^= kov2p_tab[(i >> 1) & 0xff] << 8;
@ -516,14 +516,14 @@ void pgm_puzzli2_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1_ALT
IGS27_CRYPT2_ALT
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8
IGS27_CRYPT1_ALT
IGS27_CRYPT2_ALT
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8
x ^= puzzli2_tab[i & 0xff] << 8;
src[i] = x;
@ -560,14 +560,14 @@ void pgm_theglad_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1_ALT
IGS27_CRYPT2
IGS27_CRYPT3
IGS27_CRYPT4_ALT
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT1_ALT
IGS27_CRYPT2
IGS27_CRYPT3
IGS27_CRYPT4_ALT
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8_ALT
x ^= theglad_tab[(i >> 1) & 0xff] << 8;
@ -605,14 +605,14 @@ void pgm_oldsplus_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
unsigned short x = src[i];
IGS27_CRYPT1
IGS27_CRYPT2_ALT
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5_ALT
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT1
IGS27_CRYPT2_ALT
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5_ALT
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
x ^= oldsplus_tab[i & 0xff] << 8;
@ -650,14 +650,14 @@ void pgm_kovshp_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
unsigned short x = src[i];
IGS27_CRYPT1_ALT
IGS27_CRYPT2_ALT2
IGS27_CRYPT3_ALT2
IGS27_CRYPT4_ALT
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT1_ALT
IGS27_CRYPT2_ALT2
IGS27_CRYPT3_ALT2
IGS27_CRYPT4_ALT
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8_ALT
x ^= kovshp_tab[i & 0xff] << 8;
@ -695,14 +695,14 @@ void pgm_killbldp_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1
IGS27_CRYPT2
IGS27_CRYPT3
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT1
IGS27_CRYPT2
IGS27_CRYPT3
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
x ^= killbldp_tab[(i >> 1) & 0xff] << 8;
@ -721,14 +721,14 @@ void pgm_svg_decrypt(running_machine &machine)
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1_ALT
IGS27_CRYPT2_ALT
IGS27_CRYPT3
IGS27_CRYPT4_ALT
IGS27_CRYPT5_ALT
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT1_ALT
IGS27_CRYPT2_ALT
IGS27_CRYPT3
IGS27_CRYPT4_ALT
IGS27_CRYPT5_ALT
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
src[i] = x;
}
@ -765,13 +765,13 @@ void pgm_svgpcb_decrypt(running_machine &machine)
// preliminary!
IGS27_CRYPT1_ALT; // ok?
IGS27_CRYPT2_ALT3
IGS27_CRYPT2_ALT3
IGS27_CRYPT3
IGS27_CRYPT4 // ok?
IGS27_CRYPT5_ALT //
IGS27_CRYPT6_ALT // ok?
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT8_ALT
x ^= svgpcb_tab[(i >> 1) & 0xff] << 8;
@ -811,9 +811,9 @@ void pgm_py2k2_decrypt(running_machine &machine) // and ddpdoj/ddpdojbl
UINT16 x = src[i];
IGS27_CRYPT1
IGS27_CRYPT2_ALT3
IGS27_CRYPT3_ALT
IGS27_CRYPT4_ALT
IGS27_CRYPT2_ALT3
IGS27_CRYPT3_ALT
IGS27_CRYPT4_ALT
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
@ -859,11 +859,11 @@ void pgm_ket_decrypt(running_machine &machine)
IGS27_CRYPT1
IGS27_CRYPT2_ALT
IGS27_CRYPT3_ALT3
IGS27_CRYPT4_ALT
IGS27_CRYPT4_ALT
IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT8_ALT
x ^= ket_tab[i & 0xff] << 8;
@ -903,13 +903,13 @@ void pgm_espgal_decrypt(running_machine &machine)
UINT16 x = src[i];
IGS27_CRYPT1
IGS27_CRYPT2_ALT3
IGS27_CRYPT3_ALT2
IGS27_CRYPT4_ALT
IGS27_CRYPT5_ALT
IGS27_CRYPT2_ALT3
IGS27_CRYPT3_ALT2
IGS27_CRYPT4_ALT
IGS27_CRYPT5_ALT
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT8_ALT
x ^= espgal_tab[i & 0xff] << 8;
@ -953,10 +953,10 @@ void pgm_happy6_decrypt(running_machine &machine)
IGS27_CRYPT2
IGS27_CRYPT3
IGS27_CRYPT4
IGS27_CRYPT5_ALT
IGS27_CRYPT5_ALT
IGS27_CRYPT6
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT8_ALT
x ^= happy6in1_tab[(i >> 1) & 0xff] << 8;
@ -997,14 +997,14 @@ void sdwx_decrypt(running_machine &machine)
{
UINT16 x = src[i];
IGS27_CRYPT1_ALT2
IGS27_CRYPT2_ALT
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8
IGS27_CRYPT1_ALT2
IGS27_CRYPT2_ALT
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8
x ^= sdwx_tab[(i >> 1) & 0xff] << 8;
@ -1045,10 +1045,10 @@ void hauntedh_decrypt(running_machine &machine)
IGS27_CRYPT1
// IGS27_CRYPT2
// IGS27_CRYPT3
IGS27_CRYPT4_ALT
IGS27_CRYPT4_ALT
// IGS27_CRYPT5
IGS27_CRYPT6
IGS27_CRYPT7_ALT
IGS27_CRYPT7_ALT
IGS27_CRYPT8
x ^= hauntedh_tab[(i>> 1) & 0xff] << 8;
@ -1399,11 +1399,11 @@ void lhzb4_decrypt(running_machine &machine)
IGS27_CRYPT1
// IGS27_CRYPT2
// IGS27_CRYPT3
IGS27_CRYPT4_ALT
IGS27_CRYPT4_ALT
// IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8_ALT
IGS27_CRYPT8_ALT
x ^= lhzb4_tab[(i>> 1) & 0xff] << 8;
@ -1443,14 +1443,14 @@ void fearless_decrypt(running_machine &machine)
UINT16 x = src[i];
// might not be 100% correct...
IGS27_CRYPT1
IGS27_CRYPT1
// IGS27_CRYPT2
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
IGS27_CRYPT3_ALT2
IGS27_CRYPT4
// IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8
x ^= fearless_tab[(i>> 1) & 0xff] << 8;

8
src/mame/machine/scramble.c
View File

@ -637,7 +637,7 @@ WRITE8_MEMBER(scramble_state::harem_decrypt_clk_w)
m_harem_decrypt_mode = ((m_harem_decrypt_mode >> 1) | ((m_harem_decrypt_bit & 1) << 3)) & 0x0f;
m_harem_decrypt_count++;
// logerror("%s: decrypt mode = %02x, count = %x\n", machine().describe_context(), m_harem_decrypt_mode, m_harem_decrypt_count);
// logerror("%s: decrypt mode = %02x, count = %x\n", machine().describe_context(), m_harem_decrypt_mode, m_harem_decrypt_count);
}
m_harem_decrypt_clk = data;
@ -654,11 +654,11 @@ WRITE8_MEMBER(scramble_state::harem_decrypt_clk_w)
logerror("%s: warning, unknown decrypt mode = %02x\n", machine().describe_context(), m_harem_decrypt_mode);
bank = 0;
}
membank("rombank")->set_base (m_harem_decrypted_data + 0x2000 * bank);
membank("rombank")->set_base_decrypted (m_harem_decrypted_opcodes + 0x2000 * bank);
// logerror("%s: decrypt mode = %02x (bank %x) active\n", machine().describe_context(), m_harem_decrypt_mode, bank);
// logerror("%s: decrypt mode = %02x (bank %x) active\n", machine().describe_context(), m_harem_decrypt_mode, bank);
m_harem_decrypt_mode = 0;
m_harem_decrypt_count = 0;
@ -670,7 +670,7 @@ WRITE8_MEMBER(scramble_state::harem_decrypt_rst_w)
m_harem_decrypt_mode = 0;
m_harem_decrypt_count = 0;
// logerror("%s: decrypt mode reset\n", machine().describe_context());
// logerror("%s: decrypt mode reset\n", machine().describe_context());
}
DRIVER_INIT_MEMBER(scramble_state,harem)

4
src/mame/machine/zndip.c
View File

@ -30,7 +30,7 @@ void zndip_device::select(int select)
{
data_out(0, PSX_SIO_IN_DATA | PSX_SIO_IN_DSR);
}
m_select = select;
}
}
@ -41,7 +41,7 @@ void zndip_device::data_in( int data, int mask )
{
int dip = m_data_handler();
int bit = ( ( dip >> m_bit ) & 1 );
// verboselog( machine, 2, "read dip %02x -> %02x\n", n_data, bit * PSX_SIO_IN_DATA );
// verboselog( machine, 2, "read dip %02x -> %02x\n", n_data, bit * PSX_SIO_IN_DATA );
data_out( bit * PSX_SIO_IN_DATA, PSX_SIO_IN_DATA );
m_bit++;
m_bit &= 7;

2
src/mame/machine/znsec.c
View File

@ -172,7 +172,7 @@ void znsec_device::select(int select)
{
data_out(0, PSX_SIO_IN_DATA);
}
m_select = select;
}
}

2
src/mame/mame.lst
View File

@ -5042,7 +5042,7 @@ meltybld // 2005.08 Melty Blood Act Cadenza (Rev C)
ggxxsla // 2005.09 Guilty Gear XX Slash (Rev A)
radirgy // 2005.10 Radirgy
undefeat // 2005.10 Under Defeat
radirgya // 2005.12 Radirgy (Rev A)
radirgya // 2005.12 Radirgy (Rev A)
// 2005.?? Dragon Treasure 3 (Rev A)
// 2005.?? ExZeus
// 2005.?? Mushiking The King Of Beetles II ENG

2
src/mame/video/f1gp.c
View File

@ -82,7 +82,7 @@ UINT32 f1gp_state::f1gp2_tile_callback( UINT32 code )
UINT32 f1gp_state::f1gp_old_tile_callback( UINT32 code )
{
return m_spr1cgram[code % (m_spr1cgram.bytes()/2)];
}
}
UINT32 f1gp_state::f1gp_ol2_tile_callback( UINT32 code )
{

2
src/mame/video/galaxold.c
View File

@ -790,7 +790,7 @@ VIDEO_START_MEMBER(galaxold_state,harem)
{
video_start_common(machine());
m_bg_tilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(galaxold_state::harem_get_tile_info),this),TILEMAP_SCAN_ROWS,8,8,32,32);
// m_bg_tilemap->set_transparent_pen(0); // opaque tilemap to get sky and sand colors
// m_bg_tilemap->set_transparent_pen(0); // opaque tilemap to get sky and sand colors
m_bg_tilemap->set_scroll_cols(32);

4
src/mame/video/konicdev.c
View File

@ -10321,10 +10321,10 @@ void k001604_draw_back_layer( device_t *device, bitmap_rgb32 &bitmap, const rect
x = (x + 320) * 256;
y = (y + 208) * 256;
// xx = (xx);
// xx = (xx);
xy = (-xy);
yx = (-yx);
// yy = (yy);
// yy = (yy);
if ((k001604->reg[0x6c / 4] & (0x08 >> layer)) != 0)
{

2
src/mame/video/vastar.c
View File

@ -130,7 +130,7 @@ static void draw_sprites(running_machine &machine, bitmap_ind16 &bitmap,const re
UINT8 *spriteram_3 = state->m_spriteram3;
int offs;
// for (offs = 0; offs < 0x40; offs += 2)
// for (offs = 0; offs < 0x40; offs += 2)
for (offs = 0x40-2; offs >=0; offs -= 2)
{
int code, sx, sy, color, flipx, flipy;

4
src/mame/video/vsystem_spr2.c
View File

@ -16,7 +16,7 @@
// Pipe Dream
// there were lots of comments saying drivers using the
// static const UINT8 zoomtable[16] = { 0,7,14,20,25,30,34,38,42,46,49,52,54,57,59,61 };
// static const UINT8 zoomtable[16] = { 0,7,14,20,25,30,34,38,42,46,49,52,54,57,59,61 };
// table for zooming needed upgrading, are we sure this isn't one of the
// differences between this sprite chip and the one in vsystem_spr.c, pspikes zooming is very rough
@ -159,7 +159,7 @@ void vsystem_spr2_device::turbofrc_draw_sprites_common( UINT16* spriteram3, int
continue;
}
if (m_pritype == 0) // turbo force etc.
{
usepri = curr_sprite.pri ? 0 : 2;

12
src/mess/drivers/a7800.c
View File

@ -9,14 +9,14 @@
2002/05/13 kubecj added more banks for bankswitching
added PAL machine description
changed clock to be precise
2012/10/25 Robert Tuccitto NTSC Color Generator utilized for
color palette with hue shift/start
based on observation of several
systems across multiple displays
2012/10/25 Robert Tuccitto NTSC Color Generator utilized for
color palette with hue shift/start
based on observation of several
systems across multiple displays
2012/11/09 Robert Tuccitto Fixed 3 degree hue begin point
miscalculation of color palette
miscalculation of color palette
***************************************************************************/

150
src/mess/drivers/adam.c
View File

@ -626,18 +626,18 @@ WRITE8_MEMBER( adam_state::mioc_w )
{
/*
bit description
bit description
0 Lower memory option 0
1 Lower memory option 1
2 Upper memory option 0
3 Upper memory option 1
4
5
6
7
0 Lower memory option 0
1 Lower memory option 1
2 Upper memory option 0
3 Upper memory option 1
4
5
6
7
*/
*/
m_mioc = data;
}
@ -666,18 +666,18 @@ WRITE8_MEMBER( adam_state::adamnet_w )
{
/*
bit description
bit description
0 Network reset
1 EOS enable
2
3
4
5
6
7
0 Network reset
1 EOS enable
2
3
4
5
6
7
*/
*/
if (BIT(m_an, 0) && !BIT(data, 0))
{
@ -698,18 +698,18 @@ WRITE8_MEMBER( adam_state::m6801_p1_w )
{
/*
bit description
bit description
0 BA8
1 BA9
2 BA10
3 BA11
4 BA12
5 BA13
6 BA14
7 BA15
0 BA8
1 BA9
2 BA10
3 BA11
4 BA12
5 BA13
6 BA14
7 BA15
*/
*/
m_ba = (data << 8) | (m_ba & 0xff);
}
@ -723,15 +723,15 @@ READ8_MEMBER( adam_state::m6801_p2_r )
{
/*
bit description
bit description
0 M6801 mode bit 0
1 M6801 mode bit 1
2 M6801 mode bit 2
3 NET RXD
4
0 M6801 mode bit 0
1 M6801 mode bit 1
2 M6801 mode bit 2
3 NET RXD
4
*/
*/
UINT8 data = M6801_MODE_7;
@ -750,15 +750,15 @@ WRITE8_MEMBER( adam_state::m6801_p2_w )
{
/*
bit description
bit description
0 _DMA
1
2 _BWR
3
4 NET TXD
0 _DMA
1
2 _BWR
3
4 NET TXD
*/
*/
// DMA
m_dma = BIT(data, 0);
@ -779,18 +779,18 @@ READ8_MEMBER( adam_state::m6801_p3_r )
{
/*
bit description
bit description
0 BD0
1 BD1
2 BD2
3 BD3
4 BD4
5 BD5
6 BD6
7 BD7
0 BD0
1 BD1
2 BD2
3 BD3
4 BD4
5 BD5
6 BD6
7 BD7
*/
*/
return m_data_out;
}
@ -804,18 +804,18 @@ WRITE8_MEMBER( adam_state::m6801_p3_w )
{
/*
bit description
bit description
0 BD0
1 BD1
2 BD2
3 BD3
4 BD4
5 BD5
6 BD6
7 BD7
0 BD0
1 BD1
2 BD2
3 BD3
4 BD4
5 BD5
6 BD6
7 BD7
*/
*/
m_data_in = data;
}
@ -829,18 +829,18 @@ WRITE8_MEMBER( adam_state::m6801_p4_w )
{
/*
bit description
bit description
0 BA0
1 BA1
2 BA2
3 BA3
4 BA4
5 BA5
6 BA6
7 BA7
0 BA0
1 BA1
2 BA2
3 BA3
4 BA4
5 BA5
6 BA6
7 BA7
*/
*/
m_ba = (m_ba & 0xff00) | data;
}
@ -1168,7 +1168,7 @@ static MACHINE_CONFIG_START( adam, adam_state )
MCFG_ADAM_EXPANSION_SLOT_ADD(ADAM_LEFT_EXPANSION_SLOT_TAG, XTAL_7_15909MHz/2, slot1_intf, adam_slot1_devices, "adamlink", NULL)
MCFG_ADAM_EXPANSION_SLOT_ADD(ADAM_CENTER_EXPANSION_SLOT_TAG, XTAL_7_15909MHz/2, slot2_intf, adam_slot2_devices, NULL, NULL)
MCFG_ADAM_EXPANSION_SLOT_ADD(ADAM_RIGHT_EXPANSION_SLOT_TAG, XTAL_7_15909MHz/2, slot3_intf, adam_slot3_devices, "ram", NULL)
// internal ram
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("64K")

16
src/mess/drivers/alphasma.c
View File

@ -4,10 +4,10 @@
08/28/2012 Skeleton driver
TODO:
- define video HW capabilities
- "Addr. Bus RAM error" string read, presumably memory mapped RAM at 0x8000
is actually a r/w bank register.
TODO:
- define video HW capabilities
- "Addr. Bus RAM error" string read, presumably memory mapped RAM at 0x8000
is actually a r/w bank register.
****************************************************************************/
@ -30,7 +30,7 @@ public:
virtual void machine_start();
virtual void palette_init();
// virtual UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
// virtual UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
};
@ -41,8 +41,8 @@ static ADDRESS_MAP_START(alphasmart_mem, AS_PROGRAM, 8, alphasmart_state)
ADDRESS_MAP_END
static ADDRESS_MAP_START(alphasmart_io, AS_IO, 8, alphasmart_state)
// AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_DEVREADWRITE("hd44780", hd44780_device, control_read, control_write)
// AM_RANGE(MC68HC11_IO_PORTD, MC68HC11_IO_PORTD) AM_DEVREADWRITE("hd44780", hd44780_device, data_read, data_write)
// AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_DEVREADWRITE("hd44780", hd44780_device, control_read, control_write)
// AM_RANGE(MC68HC11_IO_PORTD, MC68HC11_IO_PORTD) AM_DEVREADWRITE("hd44780", hd44780_device, data_read, data_write)
ADDRESS_MAP_END
/* Input ports */
@ -79,7 +79,7 @@ static MACHINE_CONFIG_START( alphasmart, alphasmart_state )
MCFG_CPU_PROGRAM_MAP(alphasmart_mem)
MCFG_CPU_IO_MAP(alphasmart_io)
MCFG_CPU_CONFIG(alphasmart_hc11_config)
// MCFG_CPU_PERIODIC_INT_DRIVER(alphasmart_state, irq0_line_hold, 50)
// MCFG_CPU_PERIODIC_INT_DRIVER(alphasmart_state, irq0_line_hold, 50)
MCFG_HD44780_ADD("hd44780", alphasmart_4line_display)

10
src/mess/drivers/altos5.c
View File

@ -1,6 +1,6 @@
/***************************************************************************
Altos 5-15
Altos 5-15
****************************************************************************/
@ -19,7 +19,7 @@ public:
DECLARE_READ8_MEMBER(altos_2f_r);
DECLARE_WRITE8_MEMBER( kbd_put );
UINT8 m_term_data;
UINT8 m_term_data;
required_device<cpu_device> m_maincpu;
virtual void machine_reset();
};
@ -48,7 +48,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START(altos5_io, AS_IO, 8, altos5_state)
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x2e, 0x2e) AM_DEVWRITE(TERMINAL_TAG, generic_terminal_device, write)
AM_RANGE(0x2f, 0x2f) AM_READ(altos_2f_r)
AM_RANGE(0x2f, 0x2f) AM_READ(altos_2f_r)
ADDRESS_MAP_END
/* Input ports */
@ -67,9 +67,9 @@ static MACHINE_CONFIG_START( altos5, altos5_state )
MCFG_CPU_ADD("maincpu", Z80, XTAL_16MHz / 4)
MCFG_CPU_PROGRAM_MAP(altos5_mem)
MCFG_CPU_IO_MAP(altos5_io)
/* video hardware */
MCFG_GENERIC_TERMINAL_ADD(TERMINAL_TAG, terminal_intf)
MCFG_GENERIC_TERMINAL_ADD(TERMINAL_TAG, terminal_intf)
MACHINE_CONFIG_END

150
src/mess/drivers/apc.c
View File

@ -1,50 +1,50 @@
/***************************************************************************
Advanced Personal Computer (c) 1982 NEC
Advanced Personal Computer (c) 1982 NEC
preliminary driver by Angelo Salese
preliminary driver by Angelo Salese
TODO:
- video emulation
- Floppy device
- keyboard
- Understand interrupt sources
- NMI seems valid, dumps a x86 stack to vram?
- Unknown RTC device type;
- What are exactly APU and MPU devices? They sounds scary ...
- DMA hook-ups
- serial ports
- parallel ports
- Extract info regarding Hard Disk functionality
- Various unknown ports
- What kind of external ROM actually maps at 0xa****?
TODO:
- video emulation
- Floppy device
- keyboard
- Understand interrupt sources
- NMI seems valid, dumps a x86 stack to vram?
- Unknown RTC device type;
- What are exactly APU and MPU devices? They sounds scary ...
- DMA hook-ups
- serial ports
- parallel ports
- Extract info regarding Hard Disk functionality
- Various unknown ports
- What kind of external ROM actually maps at 0xa****?
============================================================================
front ^
|
card
----
69PFCU 7220 PFCU1R 2764
69PTS 7220
-
69PFB2 8086/8087 DFBU2J PFBU2L 2732
69SNB RAM
front ^
|
card
----
69PFCU 7220 PFCU1R 2764
69PTS 7220
-
69PFB2 8086/8087 DFBU2J PFBU2L 2732
69SNB RAM
----------------------------------------------------------------------------
i/o memory map (preliminary):
0x00 - 0x1f DMA
0x20 - 0x23 i8259 master
0x28 - 0x2f i8259 slave (even), pit8253 (odd)
0x30 - 0x37 serial i8251, even #1 / odd #2
0x38 - 0x3f DMA segments
0x40 - 0x43 upd7220, even chr / odd bitmap
0x48 - 0x4f keyboard
0x50 - 0x53 upd765
0x58 rtc
0x5a - 0x5e APU
0x60 MPU (melody)
0x61 - 0x67 (Mirror of pit8253?)
0x68 - 0x6f parallel port
i/o memory map (preliminary):
0x00 - 0x1f DMA
0x20 - 0x23 i8259 master
0x28 - 0x2f i8259 slave (even), pit8253 (odd)
0x30 - 0x37 serial i8251, even #1 / odd #2
0x38 - 0x3f DMA segments
0x40 - 0x43 upd7220, even chr / odd bitmap
0x48 - 0x4f keyboard
0x50 - 0x53 upd765
0x58 rtc
0x5a - 0x5e APU
0x60 MPU (melody)
0x61 - 0x67 (Mirror of pit8253?)
0x68 - 0x6f parallel port
----------------------------------------------------------------------------
0xfe3c2: checks if the floppy has a valid string for booting (either "CP/M-86"
@ -172,33 +172,33 @@ static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
int xi,yi;
int x;
UINT8 char_size;
// UINT8 interlace_on;
// UINT8 interlace_on;
// if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off
// return;
// if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off
// return;
// interlace_on = state->m_video_reg[2] == 0x10; /* TODO: correct? */
// interlace_on = state->m_video_reg[2] == 0x10; /* TODO: correct? */
char_size = 16;
for(x=0;x<pitch;x++)
{
UINT8 tile_data;
// UINT8 secret,reverse,u_line,v_line;
// UINT8 secret,reverse,u_line,v_line;
UINT8 color;
UINT8 tile,attr,pen;
UINT32 tile_addr;
// tile_addr = addr+(x*(state->m_video_ff[WIDTH40_REG]+1));
// tile_addr = addr+(x*(state->m_video_ff[WIDTH40_REG]+1));
tile_addr = addr+(x*(1));
tile = state->m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0x007f;
attr = (state->m_video_ram_1[(tile_addr*2 & 0x1fff) | 0x2000] & 0x00ff);
// secret = (attr & 1) ^ 1;
// secret = (attr & 1) ^ 1;
//blink = attr & 2;
// reverse = attr & 4;
// u_line = attr & 8;
// v_line = attr & 0x10;
// reverse = attr & 4;
// u_line = attr & 8;
// v_line = attr & 0x10;
color = (attr & 0xe0) >> 5;
for(yi=0;yi<lr;yi++)
@ -207,19 +207,19 @@ static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
{
int res_x,res_y;
// res_x = (x*8+xi) * (state->m_video_ff[WIDTH40_REG]+1);
// res_x = (x*8+xi) * (state->m_video_ff[WIDTH40_REG]+1);
res_x = (x*8+xi) * (1);
res_y = y*lr+yi;
if(res_x > 640 || res_y > char_size*25) //TODO
continue;
// tile_data = secret ? 0 : (state->m_char_rom[tile*char_size+interlace_on*0x800+yi]);
// tile_data = secret ? 0 : (state->m_char_rom[tile*char_size+interlace_on*0x800+yi]);
tile_data = (state->m_char_rom[tile+yi*0x80]);
// if(reverse) { tile_data^=0xff; }
// if(u_line && yi == 7) { tile_data = 0xff; }
// if(v_line) { tile_data|=8; }
// if(reverse) { tile_data^=0xff; }
// if(u_line && yi == 7) { tile_data = 0xff; }
// if(v_line) { tile_data|=8; }
if(cursor_on && cursor_addr == tile_addr)
tile_data^=0xff;
@ -232,13 +232,13 @@ static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
if(pen)
bitmap.pix16(res_y, res_x) = pen;
// if(state->m_video_ff[WIDTH40_REG])
// {
// if(res_x+1 > 640 || res_y > char_size*25) //TODO
// continue;
// if(state->m_video_ff[WIDTH40_REG])
// {
// if(res_x+1 > 640 || res_y > char_size*25) //TODO
// continue;
// bitmap.pix16(res_y, res_x+1) = pen;
// }
// bitmap.pix16(res_y, res_x+1) = pen;
// }
}
}
}
@ -387,7 +387,7 @@ WRITE8_MEMBER(apc_state::apc_dma_w)
static ADDRESS_MAP_START( apc_map, AS_PROGRAM, 16, apc_state )
AM_RANGE(0x00000, 0x9ffff) AM_RAM
// AM_RANGE(0xa0000, 0xaffff) space for an external ROM
// AM_RANGE(0xa0000, 0xaffff) space for an external ROM
AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("ipl", 0)
ADDRESS_MAP_END
@ -396,18 +396,18 @@ static ADDRESS_MAP_START( apc_io, AS_IO, 16, apc_state )
AM_RANGE(0x00, 0x1f) AM_READWRITE8(apc_dma_r, apc_dma_w,0xff00)
AM_RANGE(0x20, 0x23) AM_DEVREADWRITE8_LEGACY("pic8259_master", pic8259_r, pic8259_w, 0x00ff) // i8259
AM_RANGE(0x28, 0x2f) AM_READWRITE8(apc_port_28_r, apc_port_28_w, 0xffff)
// 0x30, 0x37 serial port 0/1 (i8251) (even/odd)
// 0x30, 0x37 serial port 0/1 (i8251) (even/odd)
AM_RANGE(0x38, 0x3f) AM_WRITE8(apc_dma_segments_w,0x00ff)
AM_RANGE(0x40, 0x43) AM_READWRITE8(apc_gdc_r, apc_gdc_w, 0xffff)
// 0x46 UPD7220 reset interrupt
AM_RANGE(0x48, 0x4f) AM_READWRITE8(apc_kbd_r, apc_kbd_w, 0x00ff)
AM_RANGE(0x50, 0x53) AM_DEVICE8("upd765", upd765a_device, map, 0x00ff ) // upd765
// 0x5a APU data (Arithmetic Processing Unit!)
// 0x5e APU status/command
// 0x5a APU data (Arithmetic Processing Unit!)
// 0x5e APU status/command
AM_RANGE(0x60, 0x67) AM_READWRITE8(apc_port_60_r, apc_port_60_w, 0xffff)
// 0x60 Melody Processing Unit
// AM_RANGE(0x68, 0x6f) i8255 , printer port (A: status (R) B: data (W) C: command (W))
// AM_DEVREADWRITE8("upd7220_btm", upd7220_device, read, write, 0x00ff)
// 0x60 Melody Processing Unit
// AM_RANGE(0x68, 0x6f) i8255 , printer port (A: status (R) B: data (W) C: command (W))
// AM_DEVREADWRITE8("upd7220_btm", upd7220_device, read, write, 0x00ff)
ADDRESS_MAP_END
static INPUT_PORTS_START( apc )
@ -468,15 +468,15 @@ INPUT_PORTS_END
void apc_state::fdc_drq(bool state)
{
// printf("%02x DRQ\n",state);
// i8237_dreq0_w(m_dma, state);
// printf("%02x DRQ\n",state);
// i8237_dreq0_w(m_dma, state);
m_dmac->dreq1_w(state);
}
void apc_state::fdc_irq(bool state)
{
// printf("IRQ %d\n",state);
// printf("IRQ %d\n",state);
pic8259_ir3_w(machine().device("pic8259_slave"), state);
}
@ -628,7 +628,7 @@ WRITE_LINE_MEMBER(apc_state::apc_dma_hrq_changed)
m_dmac->hack_w(state);
// printf("%02x HLDA\n",state);
// printf("%02x HLDA\n",state);
}
WRITE_LINE_MEMBER( apc_state::apc_tc_w )
@ -655,7 +655,7 @@ WRITE8_MEMBER(apc_state::apc_dma_write_byte)
address_space &program = m_maincpu->space(AS_PROGRAM);
offs_t addr = (m_dma_offset[m_dack] << 16) | offset;
// printf("%08x %02x\n",addr,data);
// printf("%08x %02x\n",addr,data);
program.write_byte(addr, data);
}
@ -673,7 +673,7 @@ WRITE_LINE_MEMBER(apc_state::apc_dack3_w){ /*printf("%02x 3\n",state);*/ set_dma
READ8_MEMBER(apc_state::test_r)
{
// printf("2dd DACK R\n");
// printf("2dd DACK R\n");
return m_fdc->dma_r();
}
@ -767,8 +767,8 @@ ROM_START( apc )
ROM_LOAD16_BYTE( "pfbu2j.bin", 0x00000, 0x001000, CRC(86970df5) SHA1(be59c5dad3bd8afc21e9f2f1404553d4371978be) )
ROM_LOAD16_BYTE( "pfbu2l.bin", 0x00001, 0x001000, CRC(38df2e70) SHA1(a37ccaea00c2b290610d354de08b489fa897ec48) )
// ROM_REGION( 0x10000, "file", ROMREGION_ERASE00 )
// ROM_LOAD( "sioapc.o", 0, 0x10000, CRC(1) SHA1(1) )
// ROM_REGION( 0x10000, "file", ROMREGION_ERASE00 )
// ROM_LOAD( "sioapc.o", 0, 0x10000, CRC(1) SHA1(1) )
ROM_REGION( 0x2000, "gfx", ROMREGION_ERASE00 )
ROM_LOAD("pfcu1r.bin", 0x000000, 0x002000, CRC(683efa94) SHA1(43157984a1746b2e448f3236f571011af9a3aa73) )

2
src/mess/drivers/apple3.c
View File

@ -72,7 +72,7 @@ static MACHINE_CONFIG_START( apple3, apple3_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M6502, 2000000) /* 2 MHz */
MCFG_CPU_PROGRAM_MAP(apple3_map)
// MCFG_CPU_CONFIG( apple3_m6502_interface )
// MCFG_CPU_CONFIG( apple3_m6502_interface )
MCFG_CPU_PERIODIC_INT_DRIVER(apple3_state, apple3_interrupt, 192)
MCFG_QUANTUM_TIME(attotime::from_hz(60))

56
src/mess/drivers/bw2.c
View File

@ -367,16 +367,16 @@ WRITE8_MEMBER( bw2_state::ppi_pa_w )
{
/*
PA0 KB0 Keyboard line select 0
PA1 KB1 Keyboard line select 1
PA2 KB2 Keyboard line select 2
PA3 KB3 Keyboard line select 3
PA4 /DS0 Drive select 0
PA5 /DS1 Drive select 1
PA6 Select RS232 connector
PA7 /STROBE to centronics printer
PA0 KB0 Keyboard line select 0
PA1 KB1 Keyboard line select 1
PA2 KB2 Keyboard line select 2
PA3 KB3 Keyboard line select 3
PA4 /DS0 Drive select 0
PA5 /DS1 Drive select 1
PA6 Select RS232 connector
PA7 /STROBE to centronics printer
*/
*/
// keyboard
m_kb = data & 0x0f;
@ -398,16 +398,16 @@ READ8_MEMBER( bw2_state::ppi_pb_r )
{
/*
PB0 Keyboard column status of selected line
PB1 Keyboard column status of selected line
PB2 Keyboard column status of selected line
PB3 Keyboard column status of selected line
PB4 Keyboard column status of selected line
PB5 Keyboard column status of selected line
PB6 Keyboard column status of selected line
PB7 Keyboard column status of selected line
PB0 Keyboard column status of selected line
PB1 Keyboard column status of selected line
PB2 Keyboard column status of selected line
PB3 Keyboard column status of selected line
PB4 Keyboard column status of selected line
PB5 Keyboard column status of selected line
PB6 Keyboard column status of selected line
PB7 Keyboard column status of selected line
*/
*/
static const char *const rownames[] = { "Y0", "Y1", "Y2", "Y3", "Y4", "Y5", "Y6", "Y7", "Y8", "Y9" };
@ -425,12 +425,12 @@ WRITE8_MEMBER( bw2_state::ppi_pc_w )
{
/*
PC0 Memory bank select
PC1 Memory bank select
PC2 Memory bank select
PC3 Not connected
PC0 Memory bank select
PC1 Memory bank select
PC2 Memory bank select
PC3 Not connected
*/
*/
m_bank = data & 0x07;
}
@ -439,12 +439,12 @@ READ8_MEMBER( bw2_state::ppi_pc_r )
{
/*
PC4 BUSY from centronics printer
PC5 M/FDBK motor feedback
PC6 RLSD Carrier detect from RS232
PC7 /PROT Write protected disk
PC4 BUSY from centronics printer
PC5 M/FDBK motor feedback
PC6 RLSD Carrier detect from RS232
PC7 /PROT Write protected disk
*/
*/
UINT8 data = 0;

240
src/mess/drivers/ng_aes.c
View File

@ -92,22 +92,22 @@ static UINT8* CDEmuReadQChannel(int NeoCDSectorLBA)
if(neocd.cd == NULL) // no cd is there, bail out
return QChannelData;
// NeoCDSectorLBA
// NeoCDSectorLBA
switch (CDEmuStatus) {
case reading:
case playing: {
UINT32 msf;
msf = lba_to_msf_alt(NeoCDSectorLBA+150);
QChannelData[0] = cdrom_get_track(neocd.cd, NeoCDSectorLBA);
QChannelData[1] = (msf >> 16)&0xff;
QChannelData[2] = (msf >> 8)&0xff;
QChannelData[3] = (msf >> 0)&0xff;
int elapsedlba;
elapsedlba = NeoCDSectorLBA - neocd.toc->tracks[ cdrom_get_track(neocd.cd, NeoCDSectorLBA) ].physframeofs;
msf = lba_to_msf_alt (elapsedlba);
@ -115,7 +115,7 @@ static UINT8* CDEmuReadQChannel(int NeoCDSectorLBA)
QChannelData[4] = (msf >> 16)&0xff;
QChannelData[5] = (msf >> 8)&0xff;
QChannelData[6] = (msf >> 0)&0xff;
if (QChannelData[0]==1)
QChannelData[7] = 0x4;
else
@ -140,7 +140,7 @@ static UINT8* CDEmuReadTOC(INT32 track)
static unsigned char TOCEntry[4];
if(neocd.cd == NULL)
if(neocd.cd == NULL)
return TOCEntry;
@ -252,12 +252,12 @@ static void NeoSetTextSlot(INT32 nSlot)
static void MapVectorTable(bool bMapBoardROM)
{
/*
if (!bMapBoardROM && Neo68KROMActive) {
SekMapMemory(Neo68KFix[nNeoActiveSlot], 0x000000, 0x0003FF, SM_ROM);
} else {
SekMapMemory(NeoVectorActive, 0x000000, 0x0003FF, SM_ROM);
}
*/
if (!bMapBoardROM && Neo68KROMActive) {
SekMapMemory(Neo68KFix[nNeoActiveSlot], 0x000000, 0x0003FF, SM_ROM);
} else {
SekMapMemory(NeoVectorActive, 0x000000, 0x0003FF, SM_ROM);
}
*/
}
@ -404,26 +404,26 @@ public:
void ng_aes_state::SekWriteWord(UINT32 a, UINT16 d)
{
// printf("write word %08x %04x\n", a, d);
// printf("write word %08x %04x\n", a, d);
curr_space->write_word(a,d);
}
void ng_aes_state::SekWriteByte(UINT32 a, UINT8 d)
{
// printf("write byte %08x %02x\n", a, d);
// printf("write byte %08x %02x\n", a, d);
curr_space->write_byte(a,d);
}
UINT32 ng_aes_state::SekReadByte(UINT32 a)
{
// printf("read byte %08x\n", a);
// printf("read byte %08x\n", a);
return curr_space->read_byte(a);
}
UINT32 ng_aes_state::SekReadWord(UINT32 a)
{
// printf("read WORD %08x\n", a);
// printf("read WORD %08x\n", a);
return curr_space->read_word(a);
}
@ -947,44 +947,44 @@ void ng_aes_state::NeoCDReadSector()
if ((nff0002 & 0x0500)) {
if (NeoCDAssyStatus == 1 && bNeoCDLoadSector) {
// if (LC8951RegistersW[10] & 0x80) {
// if (LC8951RegistersW[10] & 0x80) {
NeoCDSectorLBA++;
NeoCDSectorLBA = CDEmuLoadSector(NeoCDSectorLBA, NeoCDSectorData + 4) -1;
// }
// }
if (LC8951RegistersW[10] & 0x80) {
LC8951UpdateHeader();
LC8951RegistersR[12] = 0x80; // STAT0
LC8951RegistersR[13] = 0; // STAT1
LC8951RegistersR[14] = 0x10; // STAT2
LC8951RegistersR[15] = 0; // STAT3
// bprintf(PRINT_IMPORTANT, _T(" Sector %08i (%02i:%02i:%02i) read\n"), NeoCDSectorLBA, NeoCDSectorMin, NeoCDSectorSec, NeoCDSectorFrm);
// bprintf(PRINT_IMPORTANT, _T(" Sector %08i (%02i:%02i:%02i) read\n"), NeoCDSectorLBA, NeoCDSectorMin, NeoCDSectorSec, NeoCDSectorFrm);
// CDZ protection hack? (error correction on the CDC should correct this?)
#if 1
if (NeoCDSectorData[4 + 64] == 'g' && !strncmp(NeoCDSectorData + 4, "Copyright by SNK", 16)) {
// printf(PRINT_ERROR, _T(" simulated CDZ protection error\n"));
// bprintf(PRINT_ERROR, _T(" %.70hs\n"), NeoCDSectorData + 4);
// printf(PRINT_ERROR, _T(" simulated CDZ protection error\n"));
// bprintf(PRINT_ERROR, _T(" %.70hs\n"), NeoCDSectorData + 4);
NeoCDSectorData[4 + 64] = 'f';
// LC8951RegistersR[12] = 0x00; // STAT0
// LC8951RegistersR[12] = 0x00; // STAT0
}
#endif
nIRQAcknowledge &= ~0x20;
NeoCDIRQUpdate(0);
LC8951RegistersR[1] &= ~0x20;
// bprintf(PRINT_IMPORTANT, _T(" DECI interrupt triggered\n"));
// bprintf(PRINT_IMPORTANT, _T(" DECI interrupt triggered\n"));
}
}
bNeoCDLoadSector = true;
// bNeoCDLoadSector = false;
// bNeoCDLoadSector = false;
}
}
@ -992,9 +992,9 @@ void ng_aes_state::NeoCDReadSector()
UINT8 ng_aes_state::neogeoReadTransfer(UINT32 sekAddress, int is_byte_transfer)
{
// if ((sekAddress & 0x0FFFFF) < 16)
// printf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (byte, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
// if ((sekAddress & 0x0FFFFF) < 16)
// printf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (byte, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
sekAddress ^= 1;
switch (nActiveTransferArea) {
@ -1012,18 +1012,18 @@ UINT8 ng_aes_state::neogeoReadTransfer(UINT32 sekAddress, int is_byte_transfer)
return NeoTextRAM[(sekAddress & 0x3FFFF) >> 1];
break;
}
return ~0;
}
void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int is_byte_transfer)
{
// if ((sekAddress & 0x0FFFFF) < 16)
// bprintf(PRINT_NORMAL, _T(" - Transfer: 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
// if ((sekAddress & 0x0FFFFF) < 16)
// bprintf(PRINT_NORMAL, _T(" - Transfer: 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
if (!nTransferWriteEnable) {
// return;
// return;
}
int address;
@ -1033,14 +1033,14 @@ void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int i
switch (nActiveTransferArea) {
case 0: // Sprites
address = (nSpriteTransferBank + (sekAddress & 0x0FFFFF));
// wtf? is this just due to how we decode the sprite gfx or is something bad happening?
if ((address&3)==0) NeoSpriteRAM[address] = byteValue;
if ((address&3)==1) NeoSpriteRAM[address^3] = byteValue;
if ((address&3)==2) NeoSpriteRAM[address^3] = byteValue;
if ((address&3)==3) NeoSpriteRAM[address] = byteValue;
// NeoCDOBJBankUpdate[nSpriteTransferBank >> 20] = true;
// NeoCDOBJBankUpdate[nSpriteTransferBank >> 20] = true;
break;
case 1: // ADPCM
YM2610ADPCMAROM[nNeoActiveSlot][nADPCMTransferBank + ((sekAddress & 0x0FFFFF) >> 1)] = byteValue;
@ -1058,7 +1058,7 @@ void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int i
break;
case 5: // Text
NeoTextRAM[(sekAddress & 0x3FFFF) >> 1] = byteValue;
// NeoUpdateTextOne((sekAddress & 0x3FFFF) >> 1, byteValue);
// NeoUpdateTextOne((sekAddress & 0x3FFFF) >> 1, byteValue);
break;
}
}
@ -1067,7 +1067,7 @@ void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int i
UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
{
// bprintf(PRINT_NORMAL, _T(" - CDROM: 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - CDROM: 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
switch (sekAddress & 0xFFFF) {
@ -1077,10 +1077,10 @@ UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
// LC8951 registers
case 0x0100:
// bprintf(PRINT_NORMAL, _T(" - LC8951 register read (PC: 0x%06X)\n"), SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - LC8951 register read (PC: 0x%06X)\n"), SekGetPC(-1));
return nLC8951Register;
case 0x0102: {
// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X read (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X read (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
INT32 reg = LC8951RegistersR[nLC8951Register];
@ -1101,14 +1101,14 @@ UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
// CD mechanism communication
case 0x0160:
return NeoCDCommsread();
return NeoCDCommsread();
case 0x011C: // region
return ~((0x10 | (NeoSystem & 3)) << 8);
}
// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
return ~0;
}
@ -1116,20 +1116,20 @@ UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
{
// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
int byteValue = wordValue & 0xff;
switch (sekAddress & 0xFFFE) {
case 0x0002:
// bprintf(PRINT_IMPORTANT, _T(" - NGCD Interrupt mask -> 0x%04X (PC: 0x%06X)\n"), wordValue, SekGetPC(-1));
nff0002 = wordValue;
// bprintf(PRINT_IMPORTANT, _T(" - NGCD Interrupt mask -> 0x%04X (PC: 0x%06X)\n"), wordValue, SekGetPC(-1));
nff0002 = wordValue;
// LC8951RegistersR[1] |= 0x20;
//if (nff0002 & 0x0500)
// nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
// nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
//else
// nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
// nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
break;
@ -1182,7 +1182,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
case 0x007E:
NeoCDDMAMode = wordValue;
// bprintf(PRINT_NORMAL, _T(" - DMA controller 0x%2X -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0xFF, wordValue, SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - DMA controller 0x%2X -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0xFF, wordValue, SekGetPC(-1));
break;
// upload DMA controller program
@ -1195,16 +1195,16 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
case 0x008A:
case 0x008C:
case 0x008E:
// bprintf(PRINT_NORMAL, _T(" - DMA controller program[%02i] -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0x0F, wordValue, SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - DMA controller program[%02i] -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0x0F, wordValue, SekGetPC(-1));
break;
// LC8951 registers
case 0x0100:
nLC8951Register = byteValue & 0x0F;
// bprintf(PRINT_NORMAL, _T(" - LC8951 register -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - LC8951 register -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
break;
case 0x0102:
// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, byteValue, SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, byteValue, SekGetPC(-1));
switch (nLC8951Register) {
case 3: // DBCH
LC8951RegistersW[ 3] = byteValue & 0x0F;
@ -1217,10 +1217,10 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
LC8951RegistersW[ 7] = ~0x00;
LC8951RegistersR[ 1] &= ~0x40;
break;
// case 10:
// LC8951RegistersW[nLC8951Register] = byteValue;
// bprintf(PRINT_NORMAL, _T(" - CTRL0 -> %02X (PC: 0x%06X)\n"), LC8951RegistersW[nLC8951Register], byteValue, SekGetPC(-1));
// break;
// case 10:
// LC8951RegistersW[nLC8951Register] = byteValue;
// bprintf(PRINT_NORMAL, _T(" - CTRL0 -> %02X (PC: 0x%06X)\n"), LC8951RegistersW[nLC8951Register], byteValue, SekGetPC(-1));
// break;
case 11:
LC8951RegistersW[11] = byteValue; // CTRL1
LC8951UpdateHeader();
@ -1235,43 +1235,43 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
break;
case 0x0104:
// bprintf(PRINT_NORMAL, _T(" - NGCD 0xE00000 area -> 0x%02X (PC: 0x%06X)\n"), byteValue, SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD 0xE00000 area -> 0x%02X (PC: 0x%06X)\n"), byteValue, SekGetPC(-1));
nActiveTransferArea = byteValue;
break;
case 0x0120:
// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
NeoSetSpriteSlot(1);
memset(NeoCDOBJBankUpdate, 0, sizeof(NeoCDOBJBankUpdate));
break;
case 0x0122:
// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 1 (PC: 0x%06X) %x\n"), SekGetPC(-1), byteValue);
// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 1 (PC: 0x%06X) %x\n"), SekGetPC(-1), byteValue);
break;
case 0x0126:
// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
curr_space->machine().scheduler().synchronize();
curr_space->machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
break;
case 0x0128:
// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
NeoSetTextSlot(1);
break;
case 0x0140:
// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
video_reset();
break;
case 0x0142:
// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
break;
case 0x0146:
// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
curr_space->machine().scheduler().synchronize();
curr_space->machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
break;
case 0x0148:
// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
video_reset();
break;
@ -1284,7 +1284,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
break;
case 0x016c:
// bprintf(PRINT_ERROR, _T(" - NGCD port 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
// bprintf(PRINT_ERROR, _T(" - NGCD port 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
MapVectorTable(!(byteValue == 0xFF));
@ -1293,7 +1293,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
break;
case 0x016e:
// bprintf(PRINT_IMPORTANT, _T(" - NGCD 0xE00000 area write access %s (0x%02X, PC: 0x%06X)\n"), byteValue ? _T("enabled") : _T("disabled"), byteValue, SekGetPC(-1));
// bprintf(PRINT_IMPORTANT, _T(" - NGCD 0xE00000 area write access %s (0x%02X, PC: 0x%06X)\n"), byteValue ? _T("enabled") : _T("disabled"), byteValue, SekGetPC(-1));
nTransferWriteEnable = byteValue;
break;
@ -1301,19 +1301,19 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
case 0x0180: {
static UINT8 clara = 0;
if (!byteValue && clara) {
// bprintf(PRINT_IMPORTANT, _T(" - NGCD CD communication reset (PC: 0x%06X)\n"), SekGetPC(-1));
// NeoCDCommsReset();
// bprintf(PRINT_IMPORTANT, _T(" - NGCD CD communication reset (PC: 0x%06X)\n"), SekGetPC(-1));
// NeoCDCommsReset();
}
clara = byteValue;
clara = byteValue;
break;
}
case 0x0182: {
static UINT8 clara = 0;
if (!byteValue && clara) {
// bprintf(PRINT_IMPORTANT, _T(" - NGCD Z80 reset (PC: 0x%06X)\n"), SekGetPC(-1));
// bprintf(PRINT_IMPORTANT, _T(" - NGCD Z80 reset (PC: 0x%06X)\n"), SekGetPC(-1));
//ZetReset();
}
clara = byteValue;
clara = byteValue;
break;
}
case 0x01A0:
@ -1325,10 +1325,10 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
default: {
// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
}
}
}
@ -1394,12 +1394,12 @@ void ng_aes_state::NeoCDDoDMA()
// Here, only bus access is used to get a rough approximation --
// each read/write takes a single cycle, setup and everything else is ignored.
// bprintf(PRINT_IMPORTANT, _T(" - DMA controller transfer started (PC: 0x%06X)\n"), SekGetPC(-1));
// bprintf(PRINT_IMPORTANT, _T(" - DMA controller transfer started (PC: 0x%06X)\n"), SekGetPC(-1));
switch (NeoCDDMAMode) {
case 0xCFFD: {
// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 8);
// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 8);
// - DMA controller 0x7E -> 0xCFFD (PC: 0xC07CE2)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
@ -1425,7 +1425,7 @@ void ng_aes_state::NeoCDDoDMA()
}
case 0xE2DD: {
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X, skip odd bytes\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X, skip odd bytes\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// - DMA controller 0x7E -> 0xE2DD (PC: 0xC0A190)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
@ -1450,7 +1450,7 @@ void ng_aes_state::NeoCDDoDMA()
}
case 0xFC2D: {
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// - DMA controller 0x7E -> 0xFC2D (PC: 0xC0A190)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
@ -1494,7 +1494,7 @@ void ng_aes_state::NeoCDDoDMA()
// - DMA controller program[14] -> 0xFCF5 (PC: 0xC0A1A0)
case 0xFE6D: {
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
// - DMA controller 0x7E -> 0xFE6D (PC: 0xC0FD7A)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0FD7C)
@ -1516,15 +1516,15 @@ void ng_aes_state::NeoCDDoDMA()
if (NeoCDDMAAddress2 == 0x0800) {
// MapVectorTable(false);
// bprintf(PRINT_ERROR, _T(" RAM vectors mapped (PC = 0x%08X\n"), SekGetPC(0));
// extern INT32 bRunPause;
// bRunPause = 1;
// bprintf(PRINT_ERROR, _T(" RAM vectors mapped (PC = 0x%08X\n"), SekGetPC(0));
// extern INT32 bRunPause;
// bRunPause = 1;
}
break;
}
case 0xFEF5: {
// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// - DMA controller 0x7E -> 0xFEF5 (PC: 0xC07CE2)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
@ -1548,7 +1548,7 @@ if (NeoCDDMAAddress2 == 0x0800) {
}
case 0xFFC5: {
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
// - DMA controller 0x7E -> 0xFFC5 (PC: 0xC0A190)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
@ -1592,7 +1592,7 @@ if (NeoCDDMAAddress2 == 0x0800) {
// - DMA controller program[14] -> 0x13FC (PC: 0xC0A1A0)
case 0xFFDD: {
// bprintf(PRINT_NORMAL, _T(" Fill: 0x%08X - 0x%08X <- 0x%04X\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2, NeoCDDMAValue1);
// bprintf(PRINT_NORMAL, _T(" Fill: 0x%08X - 0x%08X <- 0x%04X\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2, NeoCDDMAValue1);
// - DMA controller 0x7E -> 0xFFDD (PC: 0xC07CE2)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
@ -1637,14 +1637,14 @@ void ng_aes_state::NeoCDProcessCommand()
case 0:
break;
case 1:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
CDEmuStop();
NeoCDAssyStatus = 0x0E;
bNeoCDLoadSector = false;
break;
case 2:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDCommsStatusFIFO[1] = NeoCDCommsCommandFIFO[3];
switch (NeoCDCommsCommandFIFO[3]) {
@ -1659,7 +1659,7 @@ void ng_aes_state::NeoCDProcessCommand()
NeoCDCommsStatusFIFO[6] = ChannelData[3] / 10;
NeoCDCommsStatusFIFO[7] = ChannelData[3] % 10;
NeoCDCommsStatusFIFO[8] = ChannelData[7];
// //bprintf(PRINT_ERROR, _T(" %02i %02i:%02i:%02i %02i:%02i:%02i %02i\n"), ChannelData[0], ChannelData[1], ChannelData[2], ChannelData[3], ChannelData[4], ChannelData[5], ChannelData[6], ChannelData[7]);
@ -1786,7 +1786,7 @@ void ng_aes_state::NeoCDProcessCommand()
NeoCDSectorLBA -= CD_FRAMES_PREGAP;
CDEmuStartRead();
// LC8951RegistersR[1] |= 0x20;
// LC8951RegistersR[1] |= 0x20;
} else {
if (CDEmuGetStatus() == reading) {
@ -1802,22 +1802,22 @@ void ng_aes_state::NeoCDProcessCommand()
break;
}
case 4:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
CDEmuPause();
break;
case 5:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
// NeoCDAssyStatus = 9;
// bNeoCDLoadSector = false;
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
// NeoCDAssyStatus = 9;
// bNeoCDLoadSector = false;
break;
case 6:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDAssyStatus = 4;
bNeoCDLoadSector = false;
break;
case 7:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDAssyStatus = 1;
bNeoCDLoadSector = true;
break;
@ -1830,7 +1830,7 @@ void ng_aes_state::NeoCDProcessCommand()
case 13:
case 14:
case 15:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDAssyStatus = 9;
bNeoCDLoadSector = false;
break;
@ -1853,13 +1853,13 @@ void ng_aes_state::NeoCDCommsControl(UINT8 clock, UINT8 send)
printf("has command %02x\n", NeoCDCommsCommandFIFO[0]);
// bprintf(PRINT_NORMAL, _T(" - CD mechanism command receive completed : 0x"));
// bprintf(PRINT_NORMAL, _T(" - CD mechanism command receive completed : 0x"));
for (INT32 i = 0; i < 9; i++) {
// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsCommandFIFO[i]);
// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsCommandFIFO[i]);
sum += NeoCDCommsCommandFIFO[i];
}
sum = ~(sum + 5) & 0x0F;
// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsCommandFIFO[9], (sum == NeoCDCommsCommandFIFO[9]) ? _T("OK") : _T("NG"));
// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsCommandFIFO[9], (sum == NeoCDCommsCommandFIFO[9]) ? _T("OK") : _T("NG"));
if (sum == NeoCDCommsCommandFIFO[9]) {
printf("request to process command %02x\n", NeoCDCommsCommandFIFO[0]);
@ -1892,21 +1892,21 @@ void ng_aes_state::NeoCDCommsControl(UINT8 clock, UINT8 send)
// status send complete
// if (NeoCDCommsStatusFIFO[0] || NeoCDCommsStatusFIFO[1]) {
// INT32 sum = 0;
// if (NeoCDCommsStatusFIFO[0] || NeoCDCommsStatusFIFO[1]) {
// INT32 sum = 0;
//
// bprintf(PRINT_NORMAL, _T(" - CD mechanism status send completed : 0x"));
// for (INT32 i = 0; i < 9; i++) {
// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsStatusFIFO[i]);
// sum += NeoCDCommsStatusFIFO[i];
// }
// sum = ~(sum + 5) & 0x0F;
// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsStatusFIFO[9], (sum == NeoCDCommsStatusFIFO[9]) ? _T("OK") : _T("NG"));
// }
// bprintf(PRINT_NORMAL, _T(" - CD mechanism status send completed : 0x"));
// for (INT32 i = 0; i < 9; i++) {
// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsStatusFIFO[i]);
// sum += NeoCDCommsStatusFIFO[i];
// }
// sum = ~(sum + 5) & 0x0F;
// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsStatusFIFO[9], (sum == NeoCDCommsStatusFIFO[9]) ? _T("OK") : _T("NG"));
// }
// if (NeoCDAssyStatus == 0xE) {
// NeoCDAssyStatus = 9;
// }
// if (NeoCDAssyStatus == 0xE) {
// NeoCDAssyStatus = 9;
// }
}
}
@ -1956,7 +1956,7 @@ char* ng_aes_state::LC8915InitTransfer()
}
return NeoCDSectorData + ((LC8951RegistersW[5] << 8) | LC8951RegistersW[4]);
}
}
void ng_aes_state::LC8915EndTransfer()
{
@ -2014,7 +2014,7 @@ READ16_MEMBER(ng_aes_state::neocd_transfer_r)
UINT16 ret = 0x0000;
if (mem_mask & 0x00ff)
{
ret |= neogeoReadTransfer(0xe00000+ (offset*2)+1, is_byte_transfer) & 0xff;
@ -2038,7 +2038,7 @@ WRITE16_MEMBER(ng_aes_state::neocd_transfer_w)
{
neogeoWriteTransfer(0xe00000+ (offset*2), data>>8, is_byte_transfer);
}
if (mem_mask & 0x00ff)
{
neogeoWriteTransfer(0xe00000+ (offset*2)+1, data&0xff, is_byte_transfer);
@ -2426,10 +2426,10 @@ static ADDRESS_MAP_START( neocd_audio_io_map, AS_IO, 8, ng_aes_state )
AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READ(audio_command_r)
AM_RANGE(0x04, 0x07) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY("ymsnd", ym2610_r, ym2610_w)
AM_RANGE(0x08, 0x08) AM_MIRROR(0xff00) /* write - NMI enable / acknowledge? (the data written doesn't matter) */
// AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_f000_f7ff_r)
// AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_e000_efff_r)
// AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_c000_dfff_r)
// AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_8000_bfff_r)
// AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_f000_f7ff_r)
// AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_e000_efff_r)
// AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_c000_dfff_r)
// AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_8000_bfff_r)
AM_RANGE(0x0c, 0x0c) AM_MIRROR(0xff00) AM_WRITE(audio_result_w)
AM_RANGE(0x18, 0x18) AM_MIRROR(0xff00) /* write - NMI disable? (the data written doesn't matter) */
ADDRESS_MAP_END

64
src/mess/drivers/pc100.c
View File

@ -2,8 +2,8 @@
NEC PC-100
preliminary driver by Angelo Salese
Thanks to Carl for the i8259 tip;
preliminary driver by Angelo Salese
Thanks to Carl for the i8259 tip;
TODO:
- floppy support (no images available right now);
@ -20,33 +20,33 @@
F8216: FA cli
F8217: 0A E9 or ch,cl
F8219: 74 15 je 0F8230h
- Second one is for the vblank irq timing:
F8238: 8B D3 mov dx,bx
F823A: 8B D9 mov bx,cx
F823C: CF iret
F824D: E4 02 in al,2h
F824F: 8A E0 mov ah,al
F8251: B0 EF mov al,0EFh
F8253: E6 02 out 2h,al
F8255: BB 00 00 mov bx,0h
F8258: BA 00 00 mov dx,0h
F825B: B9 20 4E mov cx,4E20h
F825E: FB sti
F825F: E2 FE loop 0F825Fh ;calculates the vblank here
F8261: FA cli
F8262: 8A C4 mov al,ah
F8264: E6 02 out 2h,al
F8266: 2B D3 sub dx,bx
F8268: 81 FA 58 1B cmp dx,1B58h
F826C: 78 06 js 0F8274h ;error if DX is smaller than 0x1b58
F826E: 81 FA 40 1F cmp dx,1F40h
F8272: 78 0A js 0F827Eh ;error if DX is greater than 0x1f40
F8274: B1 05 mov cl,5h
F8276: E8 CB 03 call 0F8644h
F8279: E8 79 FF call 0F81F5h
F827C: EB FE jmp 0F827Ch
F827E: B0 FF mov al,0FFh
fwiw with current timings, we get DX=0x1f09, enough for passing the test;
- Second one is for the vblank irq timing:
F8238: 8B D3 mov dx,bx
F823A: 8B D9 mov bx,cx
F823C: CF iret
F824D: E4 02 in al,2h
F824F: 8A E0 mov ah,al
F8251: B0 EF mov al,0EFh
F8253: E6 02 out 2h,al
F8255: BB 00 00 mov bx,0h
F8258: BA 00 00 mov dx,0h
F825B: B9 20 4E mov cx,4E20h
F825E: FB sti
F825F: E2 FE loop 0F825Fh ;calculates the vblank here
F8261: FA cli
F8262: 8A C4 mov al,ah
F8264: E6 02 out 2h,al
F8266: 2B D3 sub dx,bx
F8268: 81 FA 58 1B cmp dx,1B58h
F826C: 78 06 js 0F8274h ;error if DX is smaller than 0x1b58
F826E: 81 FA 40 1F cmp dx,1F40h
F8272: 78 0A js 0F827Eh ;error if DX is greater than 0x1f40
F8274: B1 05 mov cl,5h
F8276: E8 CB 03 call 0F8644h
F8279: E8 79 FF call 0F81F5h
F827C: EB FE jmp 0F827Ch
F827E: B0 FF mov al,0FFh
fwiw with current timings, we get DX=0x1f09, enough for passing the test;
****************************************************************************/
@ -352,9 +352,9 @@ GFXDECODE_END
WRITE8_MEMBER( pc100_state::rtc_porta_w )
{
/*
---- -x-- chip select
---- --x- read
---- ---x write
---- -x-- chip select
---- --x- read
---- ---x write
*/
m_rtc->write_w(data & 1);

2
src/mess/drivers/pc9801.c
View File

@ -9,7 +9,7 @@
- proper 8251 uart hook-up on keyboard
- boot is too slow right now, might be due of the floppy / HDD devices
- investigate on POR bit
- Write a PC80S31K device (also used on PC-8801 and PC-88VA, it's the FDC + Z80 sub-system);
- Write a PC80S31K device (also used on PC-8801 and PC-88VA, it's the FDC + Z80 sub-system);
TODO (PC-9801RS):
- floppy disk hook-up;

68
src/mess/machine/adam_ddp.c
View File

@ -166,18 +166,18 @@ WRITE8_MEMBER( adam_digital_data_pack_device::p1_w )
{
/*
bit description
bit description
0 SPD SEL (0=20 ips, 1=80ips)
1 STOP0
2 STOP1
3 _GO FWD
4 _GO REV
5 BRAKE
6 _WR0
7 _WR1
0 SPD SEL (0=20 ips, 1=80ips)
1 STOP0
2 STOP1
3 _GO FWD
4 _GO REV
5 BRAKE
6 _WR0
7 _WR1
*/
*/
if (m_ddp0->exists())
{
@ -211,15 +211,15 @@ READ8_MEMBER( adam_digital_data_pack_device::p2_r )
{
/*
bit description
bit description
0 mode bit 0
1 mode bit 1 / CIP1
2 mode bit 2
3 NET RXD
4
0 mode bit 0
1 mode bit 1 / CIP1
2 mode bit 2
3 NET RXD
4
*/
*/
UINT8 data = 0;
@ -243,15 +243,15 @@ WRITE8_MEMBER( adam_digital_data_pack_device::p2_w )
{
/*
bit description
bit description
0 WRT DATA
1
2 TRACK A/B (0=B, 1=A)
3
4 NET TXD
0 WRT DATA
1
2 TRACK A/B (0=B, 1=A)
3
4 NET TXD
*/
*/
if (m_ddp0->exists())
{
@ -278,18 +278,18 @@ READ8_MEMBER( adam_digital_data_pack_device::p4_r )
{
/*
bit description
bit description
0 A8
1 A9
2 A10 (2114 _S)
3 MSENSE 0
4 MSENSE 1
5 CIP0
6 RD DATA 0 (always 1)
7 RD DATA 1 (data from drives ORed together)
0 A8
1 A9
2 A10 (2114 _S)
3 MSENSE 0
4 MSENSE 1
5 CIP0
6 RD DATA 0 (always 1)
7 RD DATA 1 (data from drives ORed together)
*/
*/
UINT8 data = 0;

68
src/mess/machine/adam_fdc.c
View File

@ -215,18 +215,18 @@ READ8_MEMBER( adam_fdc_device::p1_r )
{
/*
bit description
bit description
0 disk in place
1
2 FDC DRQ
3
4
5
6
7 SW3 (0=DS1, 1=DS2)
0 disk in place
1
2 FDC DRQ
3
4
5
6
7 SW3 (0=DS1, 1=DS2)
*/
*/
UINT8 data = 0;
@ -251,18 +251,18 @@ WRITE8_MEMBER( adam_fdc_device::p1_w )
{
/*
bit description
bit description
0
1 FDC ENP
2
3 FDC _DDEN
4
5 DRIVE SELECT
6 MOTOR ON
7
0
1 FDC ENP
2
3 FDC _DDEN
4
5 DRIVE SELECT
6 MOTOR ON
7
*/
*/
// write precompensation
//m_fdc->enp_w(BIT(data, 1));
@ -293,15 +293,15 @@ READ8_MEMBER( adam_fdc_device::p2_r )
{
/*
bit description
bit description
0 mode bit 0
1 mode bit 1
2 mode bit 2
3 NET RXD
4
0 mode bit 0
1 mode bit 1
2 mode bit 2
3 NET RXD
4
*/
*/
UINT8 data = M6801_MODE_2;
@ -320,15 +320,15 @@ WRITE8_MEMBER( adam_fdc_device::p2_w )
{
/*
bit description
bit description
0
1
2
3
4 NET TXD
0
1
2
3
4 NET TXD
*/
*/
m_bus->txd_w(this, BIT(data, 4));
}

48
src/mess/machine/adam_ide.c
View File

@ -9,11 +9,11 @@
/*
TODO:
TODO:
- parallel status port
- memory bank switching port
- boot ROM
- parallel status port
- memory bank switching port
- boot ROM
*/
@ -126,35 +126,35 @@ UINT8 powermate_ide_device::adam_bd_r(address_space &space, offs_t offset, UINT8
case 0x40: // Printer status
/*
bit description
0
1
2
3
4
5
6
7
*/
bit description
0
1
2
3
4
5
6
7
*/
break;
case 0x58:
m_ide_data = ide_bus_r(m_ide, 0, 0);
data = m_ide_data & 0xff;
break;
case 0x59:
data = m_ide_data >> 8;
break;
case 0x5a:
data = ide_bus_r(m_ide, 1, 6) & 0xff;
break;
case 0x5b: // Digital Input Register
data = 0xff;
break;
@ -190,16 +190,16 @@ void powermate_ide_device::adam_bd_w(address_space &space, offs_t offset, UINT8
case 0x42: // Bank Number
break;
case 0x58:
m_ide_data |= data;
ide_bus_w(m_ide, 0, 0, m_ide_data);
break;
case 0x59:
m_ide_data = data << 8;
break;
case 0x5a: // Fixed Disk Control Register
break;
}

88
src/mess/machine/adam_kb.c
View File

@ -261,18 +261,18 @@ READ8_MEMBER( adam_keyboard_device::p1_r )
{
/*
bit description
bit description
0 X0
1 X1
2 X2
3 X3
4 X4
5 X5
6 X6
7 X7
0 X0
1 X1
2 X2
3 X3
4 X4
5 X5
6 X6
7 X7
*/
*/
UINT8 data = 0xff;
@ -302,15 +302,15 @@ READ8_MEMBER( adam_keyboard_device::p2_r )
{
/*
bit description
bit description
0 mode bit 0
1 mode bit 1
2 mode bit 2
3 NET RXD
4
0 mode bit 0
1 mode bit 1
2 mode bit 2
3 NET RXD
4
*/
*/
UINT8 data = M6801_MODE_7;
@ -329,15 +329,15 @@ WRITE8_MEMBER( adam_keyboard_device::p2_w )
{
/*
bit description
bit description
0
1
2
3
4 NET TXD
0
1
2
3
4 NET TXD
*/
*/
m_bus->txd_w(this, BIT(data, 4));
}
@ -361,18 +361,18 @@ WRITE8_MEMBER( adam_keyboard_device::p3_w )
{
/*
bit description
bit description
0 Y0
1 Y1
2 Y2
3 Y3
4 Y4
5 Y5
6 Y6
7 Y7
0 Y0
1 Y1
2 Y2
3 Y3
4 Y4
5 Y5
6 Y6
7 Y7
*/
*/
m_key_y = (m_key_y & 0x1f00) | data;
}
@ -396,18 +396,18 @@ WRITE8_MEMBER( adam_keyboard_device::p4_w )
{
/*
bit description
bit description
0 Y8
1 Y9
2 Y10
3 Y11
4 Y12
5
6
7
0 Y8
1 Y9
2 Y10
3 Y11
4 Y12
5
6
7
*/
*/
m_key_y = ((data & 0x1f) << 8) | (m_key_y & 0xff);
}

88
src/mess/machine/adam_prn.c
View File

@ -136,18 +136,18 @@ WRITE8_MEMBER( adam_printer_device::p1_w )
{
/*
bit description
bit description
0 M2 phase D
1 M2 phase B
2 M2 phase C
3 M2 phase A
4 M3 phase B
5 M3 phase D
6 M3 phase A
7 M3 phase C
0 M2 phase D
1 M2 phase B
2 M2 phase C
3 M2 phase A
4 M3 phase B
5 M3 phase D
6 M3 phase A
7 M3 phase C
*/
*/
}
@ -159,15 +159,15 @@ READ8_MEMBER( adam_printer_device::p2_r )
{
/*
bit description
bit description
0 mode bit 0
1 mode bit 1
2 mode bit 2
3 NET RXD
4 NET TXD
0 mode bit 0
1 mode bit 1
2 mode bit 2
3 NET RXD
4 NET TXD
*/
*/
UINT8 data = M6801_MODE_7;
@ -186,15 +186,15 @@ WRITE8_MEMBER( adam_printer_device::p2_w )
{
/*
bit description
bit description
0 mode bit 0
1 mode bit 1
2 mode bit 2
3 NET RXD
4 NET TXD
0 mode bit 0
1 mode bit 1
2 mode bit 2
3 NET RXD
4 NET TXD
*/
*/
m_bus->txd_w(this, BIT(data, 4));
}
@ -218,18 +218,18 @@ READ8_MEMBER( adam_printer_device::p4_r )
{
/*
bit description
bit description
0
1
2
3
4 left margin
5 platen detent
6 wheel home
7 self-test
0
1
2
3
4 left margin
5 platen detent
6 wheel home
7 self-test
*/
*/
return 0x80;
}
@ -243,16 +243,16 @@ WRITE8_MEMBER( adam_printer_device::p4_w )
{
/*
bit description
bit description
0 print hammer solenoid
1 ribbon advance solenoid
2 platen motor advance
3 platen motor break
4
5
6
7
0 print hammer solenoid
1 ribbon advance solenoid
2 platen motor advance
3 platen motor break
4
5
6
7
*/
*/
}

28
src/mess/machine/adam_spi.c
View File

@ -134,15 +134,15 @@ READ8_MEMBER( adam_spi_device::p2_r )
{
/*
bit description
bit description
0 mode bit 0
1 mode bit 1
2 mode bit 2
3 NET RXD
4
0 mode bit 0
1 mode bit 1
2 mode bit 2
3 NET RXD
4
*/
*/
UINT8 data = M6801_MODE_7;
@ -161,15 +161,15 @@ WRITE8_MEMBER( adam_spi_device::p2_w )
{
/*
bit description
bit description
0
1
2
3
4 NET TXD
0
1
2
3
4 NET TXD
*/
*/
m_bus->txd_w(this, BIT(data, 4));
}

2
src/mess/machine/adamlink.c
View File

@ -77,7 +77,7 @@ void adamlink_device::adam_bd_w(address_space &space, offs_t offset, UINT8 data,
{
case 0x5e:
break;
case 0x5f:
break;
}

6
src/mess/video/isa_cga.c
View File

@ -2044,14 +2044,14 @@ void isa8_wyse700_device::change_resolution(UINT8 mode)
machine().root_device().membank("bank_wy1")->set_base(m_vram);
}
if ((m_control & 0xf0) == (mode & 0xf0)) return;
switch(mode & 0xf0) {
case 0xc0: width = 1280; height = 800; break;
case 0xa0: width = 1280; height = 400; break;
case 0x80: width = 640; height = 400; break;
case 0x00: width = 640; height = 400; break; // unhandled
}
rectangle visarea(0, width-1, 0, height-1);
rectangle visarea(0, width-1, 0, height-1);
subdevice<screen_device>(CGA_SCREEN_NAME)->configure(width, height, visarea, HZ_TO_ATTOSECONDS(60));
}
@ -2115,7 +2115,7 @@ isa8_wyse700_device::isa8_wyse700_device(const machine_config &mconfig, const ch
isa8_cga_device( mconfig, ISA8_WYSE700, "Wyse 700", tag, owner, clock )
{
m_vram_size = 0x20000;
m_start_offset = 0x18000;
m_start_offset = 0x18000;
}

2
src/mess/video/isa_cga.h
View File

@ -205,7 +205,7 @@ public:
virtual DECLARE_WRITE8_MEMBER( io_write );
virtual UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
void change_resolution(UINT8 mode);
UINT8 m_bank_offset;
UINT8 m_bank_base;
UINT8 m_control;

2
src/version.c
View File

@ -38,4 +38,4 @@
***************************************************************************/
extern const char build_version[];
const char build_version[] = "0.147u2 ("__DATE__")";
const char build_version[] = "0.147u3 ("__DATE__")";