Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-10-07 17:27:06 +03:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

Cleanups and version bump (nw)

Browse Source
This commit is contained in:
Miodrag Milanovic 2012-11-19 08:40:08 +00:00
parent d60236970a
commit 8813fb6bcd
62 changed files with 1134 additions and 1134 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hash/cd32.xml
View File

@ -5,7 +5,7 @@
<!--- Preliminary List --> <!--- Preliminary List -->
<!-- playable but there's a scrolling glitch every few frames --> <!-- playable but there's a scrolling glitch every few frames -->
<software name="morph" supported="partial"> <software name="morph" supported="partial">
<description>Morph</description> <description>Morph</description>
<year>1993</year> <year>1993</year>

42
src/emu/cpu/avr8/avr8.c
View File

@ -9,25 +9,25 @@
the existing opcodes has been shown to wildly corrupt the video output in Craft, so one can assume that the the existing opcodes has been shown to wildly corrupt the video output in Craft, so one can assume that the
existing timing is 100% correct. existing timing is 100% correct.
Unimplemented opcodes: CPSR, LD Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, EICALL, Unimplemented opcodes: CPSR, LD Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, EICALL,
JMP, CALL JMP, CALL
- Changelist - - Changelist -
30 Oct. 2012 30 Oct. 2012
- Added FMUL, FMULS, FMULSU opcodes [MooglyGuy] - Added FMUL, FMULS, FMULSU opcodes [MooglyGuy]
- Fixed incorrect flag calculation in ROR opcode [MooglyGuy] - Fixed incorrect flag calculation in ROR opcode [MooglyGuy]
- Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy] - Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy]
25 Oct. 2012 25 Oct. 2012
- Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy] - Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy]
- Corrected cycle counts for LD and ST opcodes [MooglyGuy] - Corrected cycle counts for LD and ST opcodes [MooglyGuy]
- Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing - Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing
all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy] all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy]
- Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy] - Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy]
18 Oct. 2012 18 Oct. 2012
- Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy] - Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy]
- Fixed COM, NEG, LSR opcodes [MooglyGuy] - Fixed COM, NEG, LSR opcodes [MooglyGuy]
*/ */
@ -783,7 +783,7 @@ void avr8_device::timer0_tick()
//UINT8 compare_mode[2] = { (m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0A_MASK) >> AVR8_TCCR0A_COM0A_SHIFT, //UINT8 compare_mode[2] = { (m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0A_MASK) >> AVR8_TCCR0A_COM0A_SHIFT,
//(m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0B_MASK) >> AVR8_TCCR0A_COM0B_SHIFT }; //(m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0B_MASK) >> AVR8_TCCR0A_COM0B_SHIFT };
UINT8 ocr0[2] = { m_r[AVR8_REGIDX_OCR0A], m_r[AVR8_REGIDX_OCR0B] }; UINT8 ocr0[2] = { m_r[AVR8_REGIDX_OCR0A], m_r[AVR8_REGIDX_OCR0B] };
UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR0_OCF0B_SHIFT) }; UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR0_OCF0B_SHIFT) };
INT32 increment = m_timer0_increment; INT32 increment = m_timer0_increment;
for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++) for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
@ -854,9 +854,9 @@ void avr8_device::timer0_tick()
m_r[AVR8_REGIDX_TCNT0] = count + increment; m_r[AVR8_REGIDX_TCNT0] = count + increment;
update_interrupt(AVR8_INTIDX_OCF0A); update_interrupt(AVR8_INTIDX_OCF0A);
update_interrupt(AVR8_INTIDX_OCF0B); update_interrupt(AVR8_INTIDX_OCF0B);
update_interrupt(AVR8_INTIDX_TOV0); update_interrupt(AVR8_INTIDX_TOV0);
*/ */
} }
@ -1054,7 +1054,7 @@ void avr8_device::timer1_tick()
break; break;
default: default:
verboselog(m_pc, 0, "update_timer1_compare_mode: Unknown waveform generation mode: %02x\n", wgm1); verboselog(m_pc, 0, "update_timer1_compare_mode: Unknown waveform generation mode: %02x\n", wgm1);
break; break;
} }
/* /*

32
src/emu/cpu/avr8/avr8.h
View File

@ -9,25 +9,25 @@
the existing opcodes has been shown to wildly corrupt the video output in Craft, so one can assume that the the existing opcodes has been shown to wildly corrupt the video output in Craft, so one can assume that the
existing timing is 100% correct. existing timing is 100% correct.
Unimplemented opcodes: CPSR, LD Z+, ST Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, Unimplemented opcodes: CPSR, LD Z+, ST Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL,
EICALL, JMP, CALL, SBIW EICALL, JMP, CALL, SBIW
- Changelist - - Changelist -
30 Oct. 2012 30 Oct. 2012
- Added FMUL, FMULS, FMULSU opcodes [MooglyGuy] - Added FMUL, FMULS, FMULSU opcodes [MooglyGuy]
- Fixed incorrect flag calculation in ROR opcode [MooglyGuy] - Fixed incorrect flag calculation in ROR opcode [MooglyGuy]
- Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy] - Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy]
25 Oct. 2012 25 Oct. 2012
- Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy] - Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy]
- Corrected cycle counts for LD and ST opcodes [MooglyGuy] - Corrected cycle counts for LD and ST opcodes [MooglyGuy]
- Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing - Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing
all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy] all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy]
- Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy] - Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy]
18 Oct. 2012 18 Oct. 2012
- Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy] - Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy]
- Fixed COM, NEG, LSR opcodes [MooglyGuy] - Fixed COM, NEG, LSR opcodes [MooglyGuy]
*/ */

2
src/emu/cpu/m6502/m4510.c
View File

@ -57,7 +57,7 @@ offs_t m4510_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *op
void m4510_device::device_start() void m4510_device::device_start()
{ {
if(direct_disabled) if(direct_disabled)
mintf = new mi_4510_nd(this); mintf = new mi_4510_nd(this);
else else
mintf = new mi_4510_normal(this); mintf = new mi_4510_normal(this);

2
src/emu/cpu/m6502/m6510.c
View File

@ -76,7 +76,7 @@ void m6510_device::device_start()
read_port.resolve_safe(0); read_port.resolve_safe(0);
write_port.resolve_safe(); write_port.resolve_safe();
if(direct_disabled) if(direct_disabled)
mintf = new mi_6510_nd(this); mintf = new mi_6510_nd(this);
else else
mintf = new mi_6510_normal(this); mintf = new mi_6510_normal(this);

32
src/emu/cpu/z8000/z8000ops.c
View File

@ -5829,8 +5829,8 @@ static void ZB7_ssss_dddd(z8000_state *cpustate)
} }
/****************************************** /******************************************
trtib @rd,@rs,rr trtib @rd,@rs,rr
flags: -ZSV-- flags: -ZSV--
******************************************/ ******************************************/
static void ZB8_ddN0_0010_0000_rrrr_ssN0_0000(z8000_state *cpustate) static void ZB8_ddN0_0010_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{ {
@ -5845,8 +5845,8 @@ static void ZB8_ddN0_0010_0000_rrrr_ssN0_0000(z8000_state *cpustate)
} }
/****************************************** /******************************************
trtirb @rd,@rs,rbr trtirb @rd,@rs,rbr
flags: -ZSV-- flags: -ZSV--
******************************************/ ******************************************/
static void ZB8_ddN0_0110_0000_rrrr_ssN0_1110(z8000_state *cpustate) static void ZB8_ddN0_0110_0000_rrrr_ssN0_1110(z8000_state *cpustate)
{ {
@ -5866,8 +5866,8 @@ static void ZB8_ddN0_0110_0000_rrrr_ssN0_1110(z8000_state *cpustate)
} }
/****************************************** /******************************************
trtdb @rd,@rs,rbr trtdb @rd,@rs,rbr
flags: -ZSV-- flags: -ZSV--
******************************************/ ******************************************/
static void ZB8_ddN0_1010_0000_rrrr_ssN0_0000(z8000_state *cpustate) static void ZB8_ddN0_1010_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{ {
@ -5882,8 +5882,8 @@ static void ZB8_ddN0_1010_0000_rrrr_ssN0_0000(z8000_state *cpustate)
} }
/****************************************** /******************************************
trtdrb @rd,@rs,rbr trtdrb @rd,@rs,rbr
flags: -ZSV-- flags: -ZSV--
******************************************/ ******************************************/
static void ZB8_ddN0_1110_0000_rrrr_ssN0_1110(z8000_state *cpustate) static void ZB8_ddN0_1110_0000_rrrr_ssN0_1110(z8000_state *cpustate)
{ {
@ -5903,8 +5903,8 @@ static void ZB8_ddN0_1110_0000_rrrr_ssN0_1110(z8000_state *cpustate)
} }
/****************************************** /******************************************
trib @rd,@rs,rbr trib @rd,@rs,rbr
flags: -ZSV-- flags: -ZSV--
******************************************/ ******************************************/
static void ZB8_ddN0_0000_0000_rrrr_ssN0_0000(z8000_state *cpustate) static void ZB8_ddN0_0000_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{ {
@ -5919,8 +5919,8 @@ static void ZB8_ddN0_0000_0000_rrrr_ssN0_0000(z8000_state *cpustate)
} }
/****************************************** /******************************************
trirb @rd,@rs,rbr trirb @rd,@rs,rbr
flags: -ZSV-- flags: -ZSV--
******************************************/ ******************************************/
static void ZB8_ddN0_0100_0000_rrrr_ssN0_0000(z8000_state *cpustate) static void ZB8_ddN0_0100_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{ {
@ -5935,8 +5935,8 @@ static void ZB8_ddN0_0100_0000_rrrr_ssN0_0000(z8000_state *cpustate)
} }
/****************************************** /******************************************
trdb @rd,@rs,rbr trdb @rd,@rs,rbr
flags: -ZSV-- flags: -ZSV--
******************************************/ ******************************************/
static void ZB8_ddN0_1000_0000_rrrr_ssN0_0000(z8000_state *cpustate) static void ZB8_ddN0_1000_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{ {
@ -5951,8 +5951,8 @@ static void ZB8_ddN0_1000_0000_rrrr_ssN0_0000(z8000_state *cpustate)
} }
/****************************************** /******************************************
trdrb @rd,@rs,rbr trdrb @rd,@rs,rbr
flags: -ZSV-- flags: -ZSV--
******************************************/ ******************************************/
static void ZB8_ddN0_1100_0000_rrrr_ssN0_0000(z8000_state *cpustate) static void ZB8_ddN0_1100_0000_rrrr_ssN0_0000(z8000_state *cpustate)
{ {

2
src/emu/machine/scsicd.c
View File

@ -273,7 +273,7 @@ void scsicd_device::ExecCommand( int *transferLength )
*transferLength = 0; *transferLength = 0;
break; break;
case 0x4e: // STOP case 0x4e: // STOP
if (cdrom) if (cdrom)
{ {
cdda = cdda_from_cdrom(machine(), cdrom); cdda = cdda_from_cdrom(machine(), cdrom);

42
src/emu/sound/tms5110r.c
View File

@ -383,13 +383,13 @@ static const struct tms5100_coeffs tms5200_coeff =
}, },
/* Chirp table */ /* Chirp table */
/* /*
{ 0, 42, -44, 50, -78, 18, 37, 20, { 0, 42, -44, 50, -78, 18, 37, 20,
2, -31, -59, 2, 95, 90, 5, 15, 2, -31, -59, 2, 95, 90, 5, 15,
38, -4, -91,-91, -42,-35,-36, -4, 38, -4, -91,-91, -42,-35,-36, -4,
37, 43, 34, 33, 15, -1, -8,-18, 37, 43, 34, 33, 15, -1, -8,-18,
-19,-17, -9,-10, -6, 0, 3, 2, -19,-17, -9,-10, -6, 0, 3, 2,
1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },*/ 0, 0, 0, 0 },*/
{ 0,127,127, 0, 0, 0, 0, 0, { 0,127,127, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -460,13 +460,13 @@ static const struct tms5100_coeffs tms5220_coeff =
}, },
/* Chirp table */ /* Chirp table */
/* /*
{ 0, 42, -44, 50, -78, 18, 37, 20, { 0, 42, -44, 50, -78, 18, 37, 20,
2, -31, -59, 2, 95, 90, 5, 15, 2, -31, -59, 2, 95, 90, 5, 15,
38, -4, -91,-91, -42,-35,-36, -4, 38, -4, -91,-91, -42,-35,-36, -4,
37, 43, 34, 33, 15, -1, -8,-18, 37, 43, 34, 33, 15, -1, -8,-18,
-19,-17, -9,-10, -6, 0, 3, 2, -19,-17, -9,-10, -6, 0, 3, 2,
1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },*/ 0, 0, 0, 0 },*/
{ 0,127,127, 0, 0, 0, 0, 0, { 0,127,127, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -541,13 +541,13 @@ static const struct tms5100_coeffs tms5220c_coeff =
}, },
/* Chirp table */ /* Chirp table */
/* /*
{ 0, 42, -44, 50, -78, 18, 37, 20, { 0, 42, -44, 50, -78, 18, 37, 20,
2, -31, -59, 2, 95, 90, 5, 15, 2, -31, -59, 2, 95, 90, 5, 15,
38, -4, -91,-91, -42,-35,-36, -4, 38, -4, -91,-91, -42,-35,-36, -4,
37, 43, 34, 33, 15, -1, -8,-18, 37, 43, 34, 33, 15, -1, -8,-18,
-19,-17, -9,-10, -6, 0, 3, 2, -19,-17, -9,-10, -6, 0, 3, 2,
1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },*/ 0, 0, 0, 0 },*/
{ 0,127,127, 0, 0, 0, 0, 0, { 0,127,127, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

306
src/emu/sound/tms5220.c
View File

@ -418,8 +418,8 @@ struct tms5220_state
UINT8 RDB_flag; /* whether we should read data register or status register */ UINT8 RDB_flag; /* whether we should read data register or status register */
/* io_ready: page 3 of the datasheet specifies that READY will be asserted until /* io_ready: page 3 of the datasheet specifies that READY will be asserted until
* data is available or processed by the system. * data is available or processed by the system.
*/ */
UINT8 io_ready; UINT8 io_ready;
/* flag for "true" timing involving rs/ws */ /* flag for "true" timing involving rs/ws */
@ -431,12 +431,12 @@ struct tms5220_state
UINT8 write_latch; UINT8 write_latch;
/* The TMS52xx has two different ways of providing output data: the /* The TMS52xx has two different ways of providing output data: the
analog speaker pin (which was usually used) and the Digital I/O pin. analog speaker pin (which was usually used) and the Digital I/O pin.
The internal DAC used to feed the analog pin is only 8 bits, and has the The internal DAC used to feed the analog pin is only 8 bits, and has the
funny clipping/clamping logic, while the digital pin gives full 12? bit funny clipping/clamping logic, while the digital pin gives full 12? bit
resolution of the output data. resolution of the output data.
TODO: add a way to set/reset this other than the FORCE_DIGITAL define TODO: add a way to set/reset this other than the FORCE_DIGITAL define
*/ */
UINT8 digital_select; UINT8 digital_select;
device_t *device; device_t *device;
@ -554,7 +554,7 @@ static void register_for_save_states(tms5220_state *tms)
/********************************************************************************************** /**********************************************************************************************
printbits helper function: takes a long int input and prints the resulting bits to stderr printbits helper function: takes a long int input and prints the resulting bits to stderr
***********************************************************************************************/ ***********************************************************************************************/
@ -592,7 +592,7 @@ static void printbits(long data, int num)
/********************************************************************************************** /**********************************************************************************************
tms5220_data_write -- handle a write to the TMS5220 tms5220_data_write -- handle a write to the TMS5220
***********************************************************************************************/ ***********************************************************************************************/
@ -652,24 +652,24 @@ static void tms5220_data_write(tms5220_state *tms, int data)
/********************************************************************************************** /**********************************************************************************************
update_status_and_ints -- check to see if the various flags should be on or off update_status_and_ints -- check to see if the various flags should be on or off
Description of flags, and their position in the status register: Description of flags, and their position in the status register:
From the data sheet: From the data sheet:
bit D0(bit 7) = TS - Talk Status is active (high) when the VSP is processing speech data. bit D0(bit 7) = TS - Talk Status is active (high) when the VSP is processing speech data.
Talk Status goes active at the initiation of a Speak command or after nine Talk Status goes active at the initiation of a Speak command or after nine
bytes of data are loaded into the FIFO following a Speak External command. It bytes of data are loaded into the FIFO following a Speak External command. It
goes inactive (low) when the stop code (Energy=1111) is processed, or goes inactive (low) when the stop code (Energy=1111) is processed, or
immediately by a buffer empty condition or a reset command. immediately by a buffer empty condition or a reset command.
bit D1(bit 6) = BL - Buffer Low is active (high) when the FIFO buffer is more than half empty. bit D1(bit 6) = BL - Buffer Low is active (high) when the FIFO buffer is more than half empty.
Buffer Low is set when the "Last-In" byte is shifted down past the half-full Buffer Low is set when the "Last-In" byte is shifted down past the half-full
boundary of the stack. Buffer Low is cleared when data is loaded to the stack boundary of the stack. Buffer Low is cleared when data is loaded to the stack
so that the "Last-In" byte lies above the half-full boundary and becomes the so that the "Last-In" byte lies above the half-full boundary and becomes the
eighth data byte of the stack. eighth data byte of the stack.
bit D2(bit 5) = BE - Buffer Empty is active (high) when the FIFO buffer has run out of data bit D2(bit 5) = BE - Buffer Empty is active (high) when the FIFO buffer has run out of data
while executing a Speak External command. Buffer Empty is set when the last bit while executing a Speak External command. Buffer Empty is set when the last bit
of the "Last-In" byte is shifted out to the Synthesis Section. This causes of the "Last-In" byte is shifted out to the Synthesis Section. This causes
Talk Status to be cleared. Speech is terminated at some abnormal point and the Talk Status to be cleared. Speech is terminated at some abnormal point and the
Speak External command execution is terminated. Speak External command execution is terminated.
***********************************************************************************************/ ***********************************************************************************************/
@ -680,8 +680,8 @@ static void update_status_and_ints(tms5220_state *tms)
update_ready_state(tms); update_ready_state(tms);
/* BL is set if neither byte 9 nor 8 of the fifo are in use; this /* BL is set if neither byte 9 nor 8 of the fifo are in use; this
translates to having fifo_count (which ranges from 0 bytes in use to 16 translates to having fifo_count (which ranges from 0 bytes in use to 16
bytes used) being less than or equal to 8. Victory/Victorba depends on this. */ bytes used) being less than or equal to 8. Victory/Victorba depends on this. */
if (tms->fifo_count <= 8) if (tms->fifo_count <= 8)
{ {
// generate an interrupt if necessary; if /BL was inactive and is now active, set int. // generate an interrupt if necessary; if /BL was inactive and is now active, set int.
@ -693,7 +693,7 @@ static void update_status_and_ints(tms5220_state *tms)
tms->buffer_low = 0; tms->buffer_low = 0;
/* BE is set if neither byte 15 nor 14 of the fifo are in use; this /* BE is set if neither byte 15 nor 14 of the fifo are in use; this
translates to having fifo_count equal to exactly 0 */ translates to having fifo_count equal to exactly 0 */
if (tms->fifo_count == 0) if (tms->fifo_count == 0)
{ {
// generate an interrupt if necessary; if /BE was inactive and is now active, set int. // generate an interrupt if necessary; if /BE was inactive and is now active, set int.
@ -705,8 +705,8 @@ static void update_status_and_ints(tms5220_state *tms)
tms->buffer_empty = 0; tms->buffer_empty = 0;
/* TS is talk status and is set elsewhere in the fifo parser and in /* TS is talk status and is set elsewhere in the fifo parser and in
the SPEAK command handler; however, if /BE is true during speak external the SPEAK command handler; however, if /BE is true during speak external
mode, it is immediately unset here. */ mode, it is immediately unset here. */
if ((tms->speak_external == 1) && (tms->buffer_empty == 1)) if ((tms->speak_external == 1) && (tms->buffer_empty == 1))
{ {
// generate an interrupt: /TS was active, and is now inactive. // generate an interrupt: /TS was active, and is now inactive.
@ -717,12 +717,12 @@ static void update_status_and_ints(tms5220_state *tms)
} }
} }
/* Note that TS being unset will also generate an interrupt when a STOP /* Note that TS being unset will also generate an interrupt when a STOP
frame is encountered; this is handled in the sample generator code and not here */ frame is encountered; this is handled in the sample generator code and not here */
} }
/********************************************************************************************** /**********************************************************************************************
extract_bits -- extract a specific number of bits from the current input stream (FIFO or VSM) extract_bits -- extract a specific number of bits from the current input stream (FIFO or VSM)
***********************************************************************************************/ ***********************************************************************************************/
@ -759,7 +759,7 @@ static int extract_bits(tms5220_state *tms, int count)
/********************************************************************************************** /**********************************************************************************************
tms5220_status_read -- read status or data from the TMS5220 tms5220_status_read -- read status or data from the TMS5220
***********************************************************************************************/ ***********************************************************************************************/
@ -801,9 +801,9 @@ static int tms5220_ready_read(tms5220_state *tms)
/********************************************************************************************** /**********************************************************************************************
tms5220_cycles_to_ready -- returns the number of cycles until ready is asserted tms5220_cycles_to_ready -- returns the number of cycles until ready is asserted
NOTE: this function is deprecated and is known to be VERY inaccurate. NOTE: this function is deprecated and is known to be VERY inaccurate.
Use at your own peril! Use at your own peril!
***********************************************************************************************/ ***********************************************************************************************/
@ -829,12 +829,12 @@ static int tms5220_cycles_to_ready(tms5220_state *tms)
val = (tms->fifo[tms->fifo_head] >> tms->fifo_bits_taken) & 0xf; val = (tms->fifo[tms->fifo_head] >> tms->fifo_bits_taken) & 0xf;
if (val == 0) if (val == 0)
/* 0 -> silence frame: we will only read 4 bits, and we will /* 0 -> silence frame: we will only read 4 bits, and we will
* therefore need to read another frame before the FIFO is not * therefore need to read another frame before the FIFO is not
* full any more */ * full any more */
answer += tms->subc_reload?200:304; answer += tms->subc_reload?200:304;
/* 15 -> stop frame, we will only read 4 bits, but the FIFO will /* 15 -> stop frame, we will only read 4 bits, but the FIFO will
* we cleared; otherwise, we need to parse the repeat flag (1 bit) * we cleared; otherwise, we need to parse the repeat flag (1 bit)
* and the pitch (6 bits), so everything will be OK. */ * and the pitch (6 bits), so everything will be OK. */
} }
} }
@ -844,7 +844,7 @@ static int tms5220_cycles_to_ready(tms5220_state *tms)
/********************************************************************************************** /**********************************************************************************************
tms5220_int_read -- returns the interrupt state of the TMS5220 tms5220_int_read -- returns the interrupt state of the TMS5220
***********************************************************************************************/ ***********************************************************************************************/
@ -859,7 +859,7 @@ static int tms5220_int_read(tms5220_state *tms)
/********************************************************************************************** /**********************************************************************************************
tms5220_process -- fill the buffer with a specific number of samples tms5220_process -- fill the buffer with a specific number of samples
***********************************************************************************************/ ***********************************************************************************************/
@ -875,7 +875,7 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
goto empty; goto empty;
/* if speak external is set, but talk status is not (yet) set, /* if speak external is set, but talk status is not (yet) set,
wait for buffer low to clear */ wait for buffer low to clear */
if (!tms->talk_status && tms->speak_external && tms->buffer_low) if (!tms->talk_status && tms->speak_external && tms->buffer_low)
goto empty; goto empty;
@ -883,9 +883,9 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
while ((size > 0) && tms->speaking_now) while ((size > 0) && tms->speaking_now)
{ {
/* if it is the appropriate time to update the old energy/pitch idxes, /* if it is the appropriate time to update the old energy/pitch idxes,
* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17 * i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1), * is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
* which happens 4 T-cycles later), we change on the latter.*/ * which happens 4 T-cycles later), we change on the latter.*/
if ((tms->interp_period == 0) && (tms->PC == 0) && (tms->subcycle < 2)) if ((tms->interp_period == 0) && (tms->PC == 0) && (tms->subcycle < 2))
{ {
tms->OLDE = (tms->new_frame_energy_idx == 0); tms->OLDE = (tms->new_frame_energy_idx == 0);
@ -893,9 +893,9 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
} }
/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1 /* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
* (In reality, the frame was really loaded incrementally during the entire IP=0 * (In reality, the frame was really loaded incrementally during the entire IP=0
* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens) * PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
*/ */
if ((tms->interp_period == 0) && (tms->PC == 12) && (tms->subcycle == 1)) if ((tms->interp_period == 0) && (tms->PC == 12) && (tms->subcycle == 1))
{ {
// HACK for regression testing, be sure to comment out before release! // HACK for regression testing, be sure to comment out before release!
@ -939,11 +939,11 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
} }
/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it. /* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
Interpolation inhibit cases: Interpolation inhibit cases:
* Old frame was voiced, new is unvoiced * Old frame was voiced, new is unvoiced
* Old frame was silence/zero energy, new has nonzero energy * Old frame was silence/zero energy, new has nonzero energy
* Old frame was unvoiced, new is voiced * Old frame was unvoiced, new is voiced
*/ */
if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1)) if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
|| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0)) || ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0))
|| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0)) ) || ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0)) )
@ -1056,12 +1056,12 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
{ {
// generate voiced samples here // generate voiced samples here
/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp /* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
* function has a chirp/peak and then a long chain of zeroes. * function has a chirp/peak and then a long chain of zeroes.
* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample, * The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
* and if the address reaches that point the ADDRESS incrementer is * and if the address reaches that point the ADDRESS incrementer is
* disabled, forcing all samples beyond 51d to be == 51d * disabled, forcing all samples beyond 51d to be == 51d
* (address 51d holds zeroes, which may or may not be inverted to -1) * (address 51d holds zeroes, which may or may not be inverted to -1)
*/ */
if (tms->pitch_count >= 51) if (tms->pitch_count >= 51)
tms->excitation_data = tms->coeff->chirptable[51]; tms->excitation_data = tms->coeff->chirptable[51];
else /*tms->pitch_count < 51*/ else /*tms->pitch_count < 51*/
@ -1124,14 +1124,14 @@ static void tms5220_process(tms5220_state *tms, INT16 *buffer, unsigned int size
tms->PC++; tms->PC++;
} }
/* Circuit 412 in the patent ensures that when INHIBIT is true, /* Circuit 412 in the patent ensures that when INHIBIT is true,
* during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch * during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch
* count is forced to 0; since the initial stop happens right before * count is forced to 0; since the initial stop happens right before
* the switch to IP=0 PC=0 and this code is located after the switch would * the switch to IP=0 PC=0 and this code is located after the switch would
* happen, we check for ip=0 inhibit=1, which covers that whole range. * happen, we check for ip=0 inhibit=1, which covers that whole range.
* The purpose of Circuit 412 is to prevent a spurious click caused by * The purpose of Circuit 412 is to prevent a spurious click caused by
* the voiced source being fed to the filter before all the values have * the voiced source being fed to the filter before all the values have
* been updated during ip=0 when interpolation was inhibited. * been updated during ip=0 when interpolation was inhibited.
*/ */
tms->pitch_count++; tms->pitch_count++;
if (tms->pitch_count >= tms->current_pitch) tms->pitch_count = 0; if (tms->pitch_count >= tms->current_pitch) tms->pitch_count = 0;
if ((tms->interp_period == 0)&&(tms->inhibit==1)) tms->pitch_count = 0; if ((tms->interp_period == 0)&&(tms->inhibit==1)) tms->pitch_count = 0;
@ -1165,20 +1165,20 @@ empty:
/********************************************************************************************** /**********************************************************************************************
clip_analog -- clips the 14 bit return value from the lattice filter to its final 10 bit value (-512 to 511), and upshifts/range extends this to 16 bits clip_analog -- clips the 14 bit return value from the lattice filter to its final 10 bit value (-512 to 511), and upshifts/range extends this to 16 bits
***********************************************************************************************/ ***********************************************************************************************/
static INT16 clip_analog(INT16 cliptemp) static INT16 clip_analog(INT16 cliptemp)
{ {
/* clipping, just like the patent shows: /* clipping, just like the patent shows:
* the top 10 bits of this result are visible on the digital output IO pin. * the top 10 bits of this result are visible on the digital output IO pin.
* next, if the top 3 bits of the 14 bit result are all the same, the lowest of those 3 bits plus the next 7 bits are the signed analog output, otherwise the low bits are all forced to match the inverse of the topmost bit, i.e.: * next, if the top 3 bits of the 14 bit result are all the same, the lowest of those 3 bits plus the next 7 bits are the signed analog output, otherwise the low bits are all forced to match the inverse of the topmost bit, i.e.:
* 1x xxxx xxxx xxxx -> 0b10000000 * 1x xxxx xxxx xxxx -> 0b10000000
* 11 1bcd efgh xxxx -> 0b1bcdefgh * 11 1bcd efgh xxxx -> 0b1bcdefgh
* 00 0bcd efgh xxxx -> 0b0bcdefgh * 00 0bcd efgh xxxx -> 0b0bcdefgh
* 0x xxxx xxxx xxxx -> 0b01111111 * 0x xxxx xxxx xxxx -> 0b01111111
*/ */
#ifdef DEBUG_CLIP #ifdef DEBUG_CLIP
if ((cliptemp > 2047) || (cliptemp < -2048)) fprintf(stderr,"clipping cliptemp to range; was %d\n", cliptemp); if ((cliptemp > 2047) || (cliptemp < -2048)) fprintf(stderr,"clipping cliptemp to range; was %d\n", cliptemp);
#endif #endif
@ -1203,12 +1203,12 @@ static INT16 clip_analog(INT16 cliptemp)
/********************************************************************************************** /**********************************************************************************************
matrix_multiply -- does the proper multiply and shift matrix_multiply -- does the proper multiply and shift
a is the k coefficient and is clamped to 10 bits (9 bits plus a sign) a is the k coefficient and is clamped to 10 bits (9 bits plus a sign)
b is the running result and is clamped to 14 bits. b is the running result and is clamped to 14 bits.
output is 14 bits, but note the result LSB bit is always 1. output is 14 bits, but note the result LSB bit is always 1.
Because the low 4 bits of the result are trimmed off before Because the low 4 bits of the result are trimmed off before
output, this makes almost no difference in the computation. output, this makes almost no difference in the computation.
**********************************************************************************************/ **********************************************************************************************/
static INT32 matrix_multiply(INT32 a, INT32 b) static INT32 matrix_multiply(INT32 a, INT32 b)
@ -1228,9 +1228,9 @@ static INT32 matrix_multiply(INT32 a, INT32 b)
/********************************************************************************************** /**********************************************************************************************
lattice_filter -- executes one 'full run' of the lattice filter on a specific byte of lattice_filter -- executes one 'full run' of the lattice filter on a specific byte of
excitation data, and specific values of all the current k constants, and returns the excitation data, and specific values of all the current k constants, and returns the
resulting sample. resulting sample.
***********************************************************************************************/ ***********************************************************************************************/
@ -1239,11 +1239,11 @@ static INT32 lattice_filter(tms5220_state *tms)
// Lattice filter here // Lattice filter here
// Aug/05/07: redone as unrolled loop, for clarity - LN // Aug/05/07: redone as unrolled loop, for clarity - LN
/* Originally Copied verbatim from table I in US patent 4,209,804, now updated to be in same order as the actual chip does it, not that it matters. /* Originally Copied verbatim from table I in US patent 4,209,804, now updated to be in same order as the actual chip does it, not that it matters.
notation equivalencies from table: notation equivalencies from table:
Yn(i) == tms->u[n-1] Yn(i) == tms->u[n-1]
Kn = tms->current_k[n-1] Kn = tms->current_k[n-1]
bn = tms->x[n-1] bn = tms->x[n-1]
*/ */
tms->u[10] = matrix_multiply(tms->previous_energy, (tms->excitation_data<<6)); //Y(11) tms->u[10] = matrix_multiply(tms->previous_energy, (tms->excitation_data<<6)); //Y(11)
tms->u[9] = tms->u[10] - matrix_multiply(tms->current_k[9], tms->x[9]); tms->u[9] = tms->u[10] - matrix_multiply(tms->current_k[9], tms->x[9]);
tms->u[8] = tms->u[9] - matrix_multiply(tms->current_k[8], tms->x[8]); tms->u[8] = tms->u[9] - matrix_multiply(tms->current_k[8], tms->x[8]);
@ -1282,7 +1282,7 @@ static INT32 lattice_filter(tms5220_state *tms)
/********************************************************************************************** /**********************************************************************************************
process_command -- extract a byte from the FIFO and interpret it as a command process_command -- extract a byte from the FIFO and interpret it as a command
***********************************************************************************************/ ***********************************************************************************************/
@ -1332,7 +1332,7 @@ static void process_command(tms5220_state *tms, unsigned char cmd)
if (tms->talk_status == 0) /* TALKST must be clear for LA */ if (tms->talk_status == 0) /* TALKST must be clear for LA */
{ {
/* tms5220 data sheet says that if we load only one 4-bit nibble, it won't work. /* tms5220 data sheet says that if we load only one 4-bit nibble, it won't work.
This code does not care about this. */ This code does not care about this. */
if (tms->intf->load_address) if (tms->intf->load_address)
(*tms->intf->load_address)(tms->device, cmd & 0x0f); (*tms->intf->load_address)(tms->device, cmd & 0x0f);
tms->schedule_dummy_read = TRUE; tms->schedule_dummy_read = TRUE;
@ -1403,7 +1403,7 @@ static void parse_frame(tms5220_state *tms)
// We actually don't care how many bits are left in the fifo here; the frame subpart will be processed normally, and any bits extracted 'past the end' of the fifo will be read as zeroes; the fifo being emptied will set the /BE latch which will halt speech exactly as if a stop frame had been encountered (instead of whatever partial frame was read); the same exact circuitry is used for both on the real chip, see us patent 4335277 sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS (decode disable) which is active during speak external). // We actually don't care how many bits are left in the fifo here; the frame subpart will be processed normally, and any bits extracted 'past the end' of the fifo will be read as zeroes; the fifo being emptied will set the /BE latch which will halt speech exactly as if a stop frame had been encountered (instead of whatever partial frame was read); the same exact circuitry is used for both on the real chip, see us patent 4335277 sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS (decode disable) which is active during speak external).
/* if the chip is a tms5220C, and the rate mode is set to that each frame (0x04 bit set) /* if the chip is a tms5220C, and the rate mode is set to that each frame (0x04 bit set)
has a 2 bit rate preceding it, grab two bits here and store them as the rate; */ has a 2 bit rate preceding it, grab two bits here and store them as the rate; */
if ((tms->variant == SUBTYPE_TMS5220C) && (tms->tms5220c_rate & 0x04)) if ((tms->variant == SUBTYPE_TMS5220C) && (tms->tms5220c_rate & 0x04))
{ {
indx = extract_bits(tms, 2); indx = extract_bits(tms, 2);
@ -2177,7 +2177,7 @@ void tms52xx_device::device_reset()
// initialize the chip state // initialize the chip state
/* Note that we do not actually clear IRQ on start-up: IRQ is even raised /* Note that we do not actually clear IRQ on start-up: IRQ is even raised
* if m_buffer_empty or m_buffer_low are 0 */ * if m_buffer_empty or m_buffer_low are 0 */
m_speaking_now = false; m_speaking_now = false;
m_speak_external = false; m_speak_external = false;
m_talk_status = false; m_talk_status = false;
@ -2314,10 +2314,10 @@ void tms52xx_device::process(INT16 *buffer, unsigned int size)
while ((size > 0) && m_speaking_now) while ((size > 0) && m_speaking_now)
{ {
/* if it is the appropriate time to update the old energy/pitch idxes, /* if it is the appropriate time to update the old energy/pitch idxes,
* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17 * i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1), * is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
* which happens 4 T-cycles later), we change on the latter. * which happens 4 T-cycles later), we change on the latter.
*/ */
if ((m_interp_period == 0) && (m_PC == 0) && (m_subcycle < 2)) if ((m_interp_period == 0) && (m_PC == 0) && (m_subcycle < 2))
{ {
m_OLDE = (m_new_frame_energy_idx == 0); m_OLDE = (m_new_frame_energy_idx == 0);
@ -2325,9 +2325,9 @@ void tms52xx_device::process(INT16 *buffer, unsigned int size)
} }
/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1 /* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
* (In reality, the frame was really loaded incrementally during the * (In reality, the frame was really loaded incrementally during the
* entire IP=0 PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens) * entire IP=0 PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
*/ */
if ((m_interp_period == 0) && (m_PC == 12) && (m_subcycle == 1)) if ((m_interp_period == 0) && (m_PC == 12) && (m_subcycle == 1))
{ {
// HACK for regression testing, be sure to comment out before release! // HACK for regression testing, be sure to comment out before release!
@ -2573,14 +2573,14 @@ void tms52xx_device::process(INT16 *buffer, unsigned int size)
m_PC++; m_PC++;
} }
/* Circuit 412 in the patent ensures that when INHIBIT is true, /* Circuit 412 in the patent ensures that when INHIBIT is true,
* during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch * during the period from IP=7 PC=12 T12, to IP=0 PC=12 T12, the pitch
* count is forced to 0; since the initial stop happens right before * count is forced to 0; since the initial stop happens right before
* the switch to IP=0 PC=0 and this code is located after the switch would * the switch to IP=0 PC=0 and this code is located after the switch would
* happen, we check for ip=0 inhibit=1, which covers that whole range. * happen, we check for ip=0 inhibit=1, which covers that whole range.
* The purpose of Circuit 412 is to prevent a spurious click caused by * The purpose of Circuit 412 is to prevent a spurious click caused by
* the voiced source being fed to the filter before all the values have * the voiced source being fed to the filter before all the values have
* been updated during ip=0 when interpolation was inhibited. * been updated during ip=0 when interpolation was inhibited.
*/ */
m_pitch_count++; m_pitch_count++;
if (m_pitch_count >= m_current_pitch) m_pitch_count = 0; if (m_pitch_count >= m_current_pitch) m_pitch_count = 0;
if ((m_interp_period == 0) && m_inhibit) m_pitch_count = 0; if ((m_interp_period == 0) && m_inhibit) m_pitch_count = 0;
@ -2622,13 +2622,13 @@ INT32 tms52xx_device::lattice_filter()
{ {
/* Lattice filter here */ /* Lattice filter here */
/* Aug/05/07: redone as unrolled loop, for clarity - LN /* Aug/05/07: redone as unrolled loop, for clarity - LN
* Originally Copied verbatim from table I in US patent 4,209,804, now updated * Originally Copied verbatim from table I in US patent 4,209,804, now updated
* to be in same order as the actual chip does it, not that it matters. * to be in same order as the actual chip does it, not that it matters.
* notation equivalencies from table: * notation equivalencies from table:
* Yn(i) == m_u[n-1] * Yn(i) == m_u[n-1]
* Kn = m_current_k[n-1] * Kn = m_current_k[n-1]
* bn = m_x[n-1] * bn = m_x[n-1]
*/ */
m_u[10] = matrix_multiply(m_previous_energy, (m_excitation_data<<6)); //Y(11) m_u[10] = matrix_multiply(m_previous_energy, (m_excitation_data<<6)); //Y(11)
m_u[9] = m_u[10] - matrix_multiply(m_current_k[9], m_x[9]); m_u[9] = m_u[10] - matrix_multiply(m_current_k[9], m_x[9]);
@ -2694,9 +2694,9 @@ void tms52xx_device::data_write(int data)
logerror("tms52xx: data_write triggered talk status to go active!\n"); logerror("tms52xx: data_write triggered talk status to go active!\n");
#endif #endif
/* ...then we now have enough bytes to start talking; clear out /* ...then we now have enough bytes to start talking; clear out
* the new frame parameters (it will become old frame just before the first call to parse_frame()) * the new frame parameters (it will become old frame just before the first call to parse_frame())
* TODO: the 3 lines below (and others) are needed for victory * TODO: the 3 lines below (and others) are needed for victory
* to not fail its selftest due to a sample ending too late, may require additional investigation */ * to not fail its selftest due to a sample ending too late, may require additional investigation */
m_subcycle = m_subc_reload; m_subcycle = m_subc_reload;
m_PC = 0; m_PC = 0;
m_interp_period = reload_table[m_tms5220c_rate & 0x3]; // is this correct? should this be always 7 instead, so that the new frame is loaded quickly? m_interp_period = reload_table[m_tms5220c_rate & 0x3]; // is this correct? should this be always 7 instead, so that the new frame is loaded quickly?
@ -2842,16 +2842,16 @@ void tms52xx_device::parse_frame()
int indx, i, rep_flag; int indx, i, rep_flag;
/* We actually don't care how many bits are left in the fifo here; the /* We actually don't care how many bits are left in the fifo here; the
* frame subpart will be processed normally, and any bits extracted 'past * frame subpart will be processed normally, and any bits extracted 'past
* the end' of the fifo will be read as zeroes; the fifo being emptied will * the end' of the fifo will be read as zeroes; the fifo being emptied will
* set the /BE latch which will halt speech exactly as if a stop frame had * set the /BE latch which will halt speech exactly as if a stop frame had
* been encountered (instead of whatever partial frame was read); the same * been encountered (instead of whatever partial frame was read); the same
* exact circuitry is used for both on the real chip, see us patent 4335277 * exact circuitry is used for both on the real chip, see us patent 4335277
* sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS * sheet 16, gates 232a (decode stop frame) and 232b (decode /BE plus DDIS
* (decode disable) which is active during speak external). */ * (decode disable) which is active during speak external). */
/* if the chip is a tms5220C, and the rate mode is set to that each frame (0x04 bit set) /* if the chip is a tms5220C, and the rate mode is set to that each frame (0x04 bit set)
* has a 2 bit rate preceding it, grab two bits here and store them as the rate; */ * has a 2 bit rate preceding it, grab two bits here and store them as the rate; */
if ((m_variant == SUBTYPE_TMS5220C) && (m_tms5220c_rate & 0x04)) if ((m_variant == SUBTYPE_TMS5220C) && (m_tms5220c_rate & 0x04))
{ {
indx = extract_bits(2); indx = extract_bits(2);
@ -2895,7 +2895,7 @@ void tms52xx_device::parse_frame()
update_status_and_ints(); update_status_and_ints();
if (!m_talk_status) goto ranout; if (!m_talk_status) goto ranout;
/* if this is a repeat frame, just do nothing, it will reuse the /* if this is a repeat frame, just do nothing, it will reuse the
* old coefficients */ * old coefficients */
if (rep_flag) return; if (rep_flag) return;
// extract first 4 K coefficients // extract first 4 K coefficients
@ -2972,8 +2972,8 @@ void tms52xx_device::update_status_and_ints()
update_ready_state(); update_ready_state();
/* BL is set if neither byte 9 nor 8 of the fifo are in use; this /* BL is set if neither byte 9 nor 8 of the fifo are in use; this
* translates to having fifo_count (which ranges from 0 bytes in use to 16 * translates to having fifo_count (which ranges from 0 bytes in use to 16
* bytes used) being less than or equal to 8. Victory/Victorba depends on this. */ * bytes used) being less than or equal to 8. Victory/Victorba depends on this. */
if (m_fifo_count <= 8) if (m_fifo_count <= 8)
{ {
// generate an interrupt if necessary; if /BL was inactive and is now active, set int. // generate an interrupt if necessary; if /BL was inactive and is now active, set int.
@ -2984,7 +2984,7 @@ void tms52xx_device::update_status_and_ints()
m_buffer_low = false; m_buffer_low = false;
/* BE is set if neither byte 15 nor 14 of the fifo are in use; this /* BE is set if neither byte 15 nor 14 of the fifo are in use; this
* translates to having fifo_count equal to exactly 0 */ * translates to having fifo_count equal to exactly 0 */
if (m_fifo_count == 0) if (m_fifo_count == 0)
{ {
// generate an interrupt if necessary; if /BE was inactive and is now active, set int. // generate an interrupt if necessary; if /BE was inactive and is now active, set int.
@ -2995,8 +2995,8 @@ void tms52xx_device::update_status_and_ints()
m_buffer_empty = false; m_buffer_empty = false;
/* TS is talk status and is set elsewhere in the fifo parser and in /* TS is talk status and is set elsewhere in the fifo parser and in
* the SPEAK command handler; however, if /BE is true during speak external * the SPEAK command handler; however, if /BE is true during speak external
* mode, it is immediately unset here. */ * mode, it is immediately unset here. */
if (m_speak_external && m_buffer_empty) if (m_speak_external && m_buffer_empty)
{ {
// generate an interrupt: /TS was active, and is now inactive. // generate an interrupt: /TS was active, and is now inactive.
@ -3007,7 +3007,7 @@ void tms52xx_device::update_status_and_ints()
} }
} }
/* Note that TS being unset will also generate an interrupt when a STOP /* Note that TS being unset will also generate an interrupt when a STOP
* frame is encountered; this is handled in the sample generator code and not here */ * frame is encountered; this is handled in the sample generator code and not here */
} }
/****************************************************************************** /******************************************************************************
@ -3214,12 +3214,12 @@ WRITE_LINE_MEMBER( tms52xx_device::rsq_w )
logerror("tms52xx: Scheduling ready cycle for /RS...\n"); logerror("tms52xx: Scheduling ready cycle for /RS...\n");
#endif #endif
/* upon /RS being activated, /READY goes inactive after 100 nsec from /* upon /RS being activated, /READY goes inactive after 100 nsec from
* data sheet, through 3 asynchronous gates on patent. This is effectively * data sheet, through 3 asynchronous gates on patent. This is effectively
* within one clock, so we immediately set io_ready to 0 and activate the callback. */ * within one clock, so we immediately set io_ready to 0 and activate the callback. */
m_io_ready = 0; m_io_ready = 0;
update_ready_state(); update_ready_state();
/* How long does /READY stay inactive, when /RS is pulled low? /* How long does /READY stay inactive, when /RS is pulled low?
* I believe its almost always ~16 clocks (25 usec at 800khz as shown on the datasheet) */ * I believe its almost always ~16 clocks (25 usec at 800khz as shown on the datasheet) */
m_ready_timer->adjust(attotime::from_hz(clock()/16)); m_ready_timer->adjust(attotime::from_hz(clock()/16));
} }
} }
@ -3270,22 +3270,22 @@ WRITE_LINE_MEMBER( tms52xx_device::wsq_w )
logerror("tms52xx: Scheduling ready cycle for /WS...\n"); logerror("tms52xx: Scheduling ready cycle for /WS...\n");
#endif #endif
/* upon /WS being activated, /READY goes inactive after 100 nsec /* upon /WS being activated, /READY goes inactive after 100 nsec
* from data sheet, through 3 asynchronous gates on patent. * from data sheet, through 3 asynchronous gates on patent.
* This is effectively within one clock, so we immediately set * This is effectively within one clock, so we immediately set
* io_ready to 0 and activate the callback. */ * io_ready to 0 and activate the callback. */
m_io_ready = 0; m_io_ready = 0;
update_ready_state(); update_ready_state();
/* Now comes the complicated part: long does /READY stay inactive /* Now comes the complicated part: long does /READY stay inactive
* when /WS is pulled low? This depends ENTIRELY on the command written, * when /WS is pulled low? This depends ENTIRELY on the command written,
* or whether the chip is in speak external mode or not... * or whether the chip is in speak external mode or not...
* Speak external mode: ~16 cycles * Speak external mode: ~16 cycles
* Command Mode: * Command Mode:
* SPK: ? cycles * SPK: ? cycles
* SPKEXT: ? cycles * SPKEXT: ? cycles
* RDBY: between 60 and 140 cycles * RDBY: between 60 and 140 cycles
* RB: ? cycles (80?) * RB: ? cycles (80?)
* RST: between 60 and 140 cycles * RST: between 60 and 140 cycles
* SET RATE (5220C only): ? cycles (probably ~16) */ * SET RATE (5220C only): ? cycles (probably ~16) */
// TODO: actually HANDLE the timing differences! currently just assuming always 16 cycles // TODO: actually HANDLE the timing differences! currently just assuming always 16 cycles
m_ready_timer->adjust(attotime::from_hz(clock()/16)); m_ready_timer->adjust(attotime::from_hz(clock()/16));

26
src/emu/video/pc_vga.c
View File

@ -2994,19 +2994,19 @@ bit 0 Horizontal Total bit 8. Bit 8 of the Horizontal Total register (3d4h
/* /*
3d4h index 5Eh (R/W): Extended Vertical Overflow Register (80x +) 3d4h index 5Eh (R/W): Extended Vertical Overflow Register (80x +)
bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h
index 6). Bits 8 and 9 are in 3d4h index 7 bit 0 and 5. index 6). Bits 8 and 9 are in 3d4h index 7 bit 0 and 5.
1 Vertical Display End bit 10. Bit 10 of the Vertical Display End 1 Vertical Display End bit 10. Bit 10 of the Vertical Display End
register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bit 1 register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bit 1
and 6 and 6
2 Start Vertical Blank bit 10. Bit 10 of the Vertical Start Blanking 2 Start Vertical Blank bit 10. Bit 10 of the Vertical Start Blanking
register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9 register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9
in 3d4h index 9 bit 5 in 3d4h index 9 bit 5
4 Vertical Retrace Start bit 10. Bit 10 of the Vertical Start Retrace 4 Vertical Retrace Start bit 10. Bit 10 of the Vertical Start Retrace
register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bit 2 register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bit 2
and 7. and 7.
6 Line Compare Position bit 10. Bit 10 of the Line Compare register 6 Line Compare Position bit 10. Bit 10 of the Line Compare register
(3d4h index 18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h (3d4h index 18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h
index 9 bit 6. index 9 bit 6.
*/ */
case 0x5e: case 0x5e:
vga.crtc.vert_total = (vga.crtc.vert_total & 0xfbff) | ((data & 0x01) << 10); vga.crtc.vert_total = (vga.crtc.vert_total & 0xfbff) | ((data & 0x01) << 10);

6
src/mame/audio/8080bw.c
View File

@ -1107,9 +1107,9 @@ WRITE8_MEMBER(_8080bw_state::lupin3_sh_port_2_w)
UINT8 rising_bits = data & ~m_port_2_last_extra; UINT8 rising_bits = data & ~m_port_2_last_extra;
if (rising_bits & 0x01) m_samples->start(0, 6); /* Lands on top of building, wife kicks man */ if (rising_bits & 0x01) m_samples->start(0, 6); /* Lands on top of building, wife kicks man */
//if (rising_bits & 0x02) m_samples->start(3, 7); /* deposit money, start intermission, end game */ //if (rising_bits & 0x02) m_samples->start(3, 7); /* deposit money, start intermission, end game */
//if (rising_bits & 0x04) m_samples->start(4, 7); /* deposit money, start intermission, Slides down rope */ //if (rising_bits & 0x04) m_samples->start(4, 7); /* deposit money, start intermission, Slides down rope */
//if (rising_bits & 0x08) m_samples->start(5, 7); /* start intermission, end game */ //if (rising_bits & 0x08) m_samples->start(5, 7); /* start intermission, end game */
if (rising_bits & 0x10) m_samples->start(3, 1); /* Dog barking */ if (rising_bits & 0x10) m_samples->start(3, 1); /* Dog barking */
m_color_map = data & 0x40; m_color_map = data & 0x40;

6
src/mame/drivers/btime.c
View File

@ -2008,9 +2008,9 @@ DRIVER_INIT_MEMBER(btime_state,tisland)
UINT8 *rom = memregion("maincpu")->base(); UINT8 *rom = memregion("maincpu")->base();
/* At location 0xa2b6 there's a strange RLA followed by a BPL that reads from an /* At location 0xa2b6 there's a strange RLA followed by a BPL that reads from an
unmapped area that causes the game to fail in several circumstances.On the Cassette unmapped area that causes the game to fail in several circumstances.On the Cassette
version the RLA (33) is in reality a BIT (24),so I'm guessing that there's something version the RLA (33) is in reality a BIT (24),so I'm guessing that there's something
wrong going on in the encryption scheme.*/ wrong going on in the encryption scheme.*/
memset(&rom[0xa2b6],0x24,1); memset(&rom[0xa2b6],0x24,1);
m_audio_nmi_enable_type = AUDIO_ENABLE_DIRECT; m_audio_nmi_enable_type = AUDIO_ENABLE_DIRECT;

2
src/mame/drivers/cntsteer.c
View File

@ -887,7 +887,7 @@ static MACHINE_CONFIG_START( cntsteer, cntsteer_state )
MCFG_CPU_ADD("subcpu", M6809, 2000000) /* ? */ MCFG_CPU_ADD("subcpu", M6809, 2000000) /* ? */
MCFG_CPU_PROGRAM_MAP(cntsteer_cpu2_map) MCFG_CPU_PROGRAM_MAP(cntsteer_cpu2_map)
// MCFG_DEVICE_DISABLE() // MCFG_DEVICE_DISABLE()
MCFG_CPU_VBLANK_INT_DRIVER("screen", cntsteer_state, nmi_line_pulse) /* ? */ MCFG_CPU_VBLANK_INT_DRIVER("screen", cntsteer_state, nmi_line_pulse) /* ? */
MCFG_CPU_ADD("audiocpu", M6502, 1500000) /* ? */ MCFG_CPU_ADD("audiocpu", M6502, 1500000) /* ? */

54
src/mame/drivers/cps1.c
View File

@ -1813,18 +1813,18 @@ INPUT_PORTS_END
/* To-Do sf2amf dipswitch SW(B):4 + SW(B):5 + SW(B):6 /* To-Do sf2amf dipswitch SW(B):4 + SW(B):5 + SW(B):6
static INPUT_PORTS_START( sf2amf ) static INPUT_PORTS_START( sf2amf )
PORT_INCLUDE( ) PORT_INCLUDE( )
PORT_MODIFY("DSWB") PORT_MODIFY("DSWB")
PORT_DIPNAME( 0x08, 0x00, "Turbo Switch 1 of 3" ) PORT_DIPLOCATION("SW(B):4") PORT_DIPNAME( 0x08, 0x00, "Turbo Switch 1 of 3" ) PORT_DIPLOCATION("SW(B):4")
PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x00, "Turbo Switch 2 of 3" ) PORT_DIPLOCATION("SW(B):5") PORT_DIPNAME( 0x10, 0x00, "Turbo Switch 2 of 3" ) PORT_DIPLOCATION("SW(B):5")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x00, "Turbo Switch 3 of 3" ) PORT_DIPLOCATION("SW(B):6") PORT_DIPNAME( 0x20, 0x00, "Turbo Switch 3 of 3" ) PORT_DIPLOCATION("SW(B):6")
PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END INPUT_PORTS_END
*/ */
@ -6576,13 +6576,13 @@ ROM_END
ROM_START( sf2stt ) ROM_START( sf2stt )
ROM_REGION( CODE_SIZE, "maincpu", 0 ) /* 68000 code */ ROM_REGION( CODE_SIZE, "maincpu", 0 ) /* 68000 code */
/* do not comment this out, this is only for testing purpose /* do not comment this out, this is only for testing purpose
ROM_LOAD16_BYTE( "12.bin", 0x00000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) ) ROM_LOAD16_BYTE( "12.bin", 0x00000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) )
ROM_LOAD16_BYTE( "09.bin", 0x00001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) ) ROM_LOAD16_BYTE( "09.bin", 0x00001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) )
*/ */
ROM_LOAD16_BYTE( "prg part 1.stt", 0x00000, 0x40000, NO_DUMP ) ROM_LOAD16_BYTE( "prg part 1.stt", 0x00000, 0x40000, NO_DUMP )
ROM_LOAD16_BYTE( "prg part 2.stt", 0x00001, 0x40000, NO_DUMP ) ROM_LOAD16_BYTE( "prg part 2.stt", 0x00001, 0x40000, NO_DUMP )
/* there are two empty sockets next to the two following program roms, /* there are two empty sockets next to the two following program roms,
these roms may be missing and this PCB is not working on real hardware */ these roms may be missing and this PCB is not working on real hardware */
ROM_LOAD16_BYTE( "ce91e-b", 0x80000, 0x40000, CRC(0862386e) SHA1(9fcfbcbbc17529de75d5419018e7b1dd90b397c0) ) ROM_LOAD16_BYTE( "ce91e-b", 0x80000, 0x40000, CRC(0862386e) SHA1(9fcfbcbbc17529de75d5419018e7b1dd90b397c0) )
ROM_LOAD16_BYTE( "ce91e-a", 0x80001, 0x40000, CRC(0c83844d) SHA1(4c25ba4a50d62c62789d026e3d304ed1dfb3c248) ) ROM_LOAD16_BYTE( "ce91e-a", 0x80001, 0x40000, CRC(0c83844d) SHA1(4c25ba4a50d62c62789d026e3d304ed1dfb3c248) )
@ -6625,15 +6625,15 @@ ROM_END
ROM_START( sf2unkb ) ROM_START( sf2unkb )
ROM_REGION( CODE_SIZE, "maincpu", 0 ) /* 68000 code */ ROM_REGION( CODE_SIZE, "maincpu", 0 ) /* 68000 code */
/* do not comment this out, this is only for testing purpose /* do not comment this out, this is only for testing purpose
ROM_LOAD16_BYTE( "12.bin", 0x000000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) ) ROM_LOAD16_BYTE( "12.bin", 0x000000, 0x40000, CRC(a258b4d5) SHA1(3433b6493794c98bb35c1b27cc65bb5f13d52e9b) )
ROM_LOAD16_BYTE( "09.bin", 0x000001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) ) ROM_LOAD16_BYTE( "09.bin", 0x000001, 0x40000, CRC(59ccd474) SHA1(7bb28c28ee722435fdbb18eb73e52bd65b419103) )
ROM_LOAD16_BYTE( "11.bin", 0x080000, 0x40000, CRC(82097d63) SHA1(881e7ffb78197f6794b5d41f5c2c87da35e8cb15) ) ROM_LOAD16_BYTE( "11.bin", 0x080000, 0x40000, CRC(82097d63) SHA1(881e7ffb78197f6794b5d41f5c2c87da35e8cb15) )
ROM_LOAD16_BYTE( "10.bin", 0x080001, 0x40000, CRC(0c83844d) SHA1(4c25ba4a50d62c62789d026e3d304ed1dfb3c248) ) ROM_LOAD16_BYTE( "10.bin", 0x080001, 0x40000, CRC(0c83844d) SHA1(4c25ba4a50d62c62789d026e3d304ed1dfb3c248) )
*/ */
ROM_LOAD16_BYTE( "prg part 1.sf2unkb", 0x00000, 0x80000, NO_DUMP ) ROM_LOAD16_BYTE( "prg part 1.sf2unkb", 0x00000, 0x80000, NO_DUMP )
ROM_LOAD16_BYTE( "prg part 2.sf2unkb", 0x00001, 0x80000, NO_DUMP ) ROM_LOAD16_BYTE( "prg part 2.sf2unkb", 0x00001, 0x80000, NO_DUMP )
/* there are two empty sockets next to the two following program roms, /* there are two empty sockets next to the two following program roms,
these roms may be missing and this PCB is not working on real hardware */ these roms may be missing and this PCB is not working on real hardware */
ROM_LOAD16_BYTE( "w-6", 0x100000, 0x20000, CRC(bb4af315) SHA1(75f0827f4f7e9f292add46467f8d4fe19b2514c9) ) ROM_LOAD16_BYTE( "w-6", 0x100000, 0x20000, CRC(bb4af315) SHA1(75f0827f4f7e9f292add46467f8d4fe19b2514c9) )
ROM_LOAD16_BYTE( "w-5", 0x100001, 0x20000, CRC(c02a13eb) SHA1(b807cc495bff3f95d03b061fc629c95f965cb6d8) ) ROM_LOAD16_BYTE( "w-5", 0x100001, 0x20000, CRC(c02a13eb) SHA1(b807cc495bff3f95d03b061fc629c95f965cb6d8) )
@ -6671,8 +6671,8 @@ ROM_START( sf2unkb )
ROM_REGION( 0x40000, "oki", 0 ) /* Samples */ ROM_REGION( 0x40000, "oki", 0 ) /* Samples */
ROM_LOAD( "sample part 1.unkb", 0x20000, 0x20000, NO_DUMP ) ROM_LOAD( "sample part 1.unkb", 0x20000, 0x20000, NO_DUMP )
/* do not comment this out, this is only for testing purpose /* do not comment this out, this is only for testing purpose
ROM_LOAD( "sf2_18.11c", 0x00000, 0x20000, CRC(7f162009) SHA1(346bf42992b4c36c593e21901e22c87ae4a7d86d) ) ROM_LOAD( "sf2_18.11c", 0x00000, 0x20000, CRC(7f162009) SHA1(346bf42992b4c36c593e21901e22c87ae4a7d86d) )
*/ */
ROM_LOAD( "w-7", 0x20000, 0x20000, CRC(beade53f) SHA1(277c397dc12752719ec6b47d2224750bd1c07f79) ) ROM_LOAD( "w-7", 0x20000, 0x20000, CRC(beade53f) SHA1(277c397dc12752719ec6b47d2224750bd1c07f79) )
ROM_END ROM_END
@ -8323,13 +8323,13 @@ ROM_START( sf2amf )
ROM_LOAD16_BYTE( "5.amf", 0x000000, 0x80000, CRC(03991fba) SHA1(6c42bf15248640fdb3e98fb01b0a870649deb410) ) ROM_LOAD16_BYTE( "5.amf", 0x000000, 0x80000, CRC(03991fba) SHA1(6c42bf15248640fdb3e98fb01b0a870649deb410) )
ROM_LOAD16_BYTE( "4.amf", 0x000001, 0x80000, CRC(39f15a1e) SHA1(901c4fea76bf5bff7330ed07ffde54cdccdaa680) ) ROM_LOAD16_BYTE( "4.amf", 0x000001, 0x80000, CRC(39f15a1e) SHA1(901c4fea76bf5bff7330ed07ffde54cdccdaa680) )
/* there are two empty sockets next to the two former program roms, /* there are two empty sockets next to the two former program roms,
these roms may be missing and this PCB is not working on real hardware */ these roms may be missing and this PCB is not working on real hardware */
ROM_LOAD16_BYTE( "prg part 3.amf", 0x100000, 0x40000, NO_DUMP ) ROM_LOAD16_BYTE( "prg part 3.amf", 0x100000, 0x40000, NO_DUMP )
ROM_LOAD16_BYTE( "prg part 4.amf", 0x100001, 0x40000, NO_DUMP ) ROM_LOAD16_BYTE( "prg part 4.amf", 0x100001, 0x40000, NO_DUMP )
/* do not comment this out, this is only for testing purpose /* do not comment this out, this is only for testing purpose
ROM_LOAD16_BYTE( "u221.rom", 0x100000, 0x20000, CRC(64e6e091) SHA1(32ec05db955e538d4ada26d19ee50926f74b684f) ) ROM_LOAD16_BYTE( "u221.rom", 0x100000, 0x20000, CRC(64e6e091) SHA1(32ec05db955e538d4ada26d19ee50926f74b684f) )
ROM_LOAD16_BYTE( "u195.rom", 0x100001, 0x20000, CRC(c95e4443) SHA1(28417dee9ccdfa65b0f4a92aa29b90279fe8cd85) ) ROM_LOAD16_BYTE( "u195.rom", 0x100001, 0x20000, CRC(c95e4443) SHA1(28417dee9ccdfa65b0f4a92aa29b90279fe8cd85) )
*/ */
ROM_REGION( 0x600000, "gfx", 0 ) ROM_REGION( 0x600000, "gfx", 0 )
ROMX_LOAD( "y.c.e.c m.k.r-001", 0x000000, 0x80000, CRC(a258de13) SHA1(2e477948c4c8a2fb7cfdc4a739766bc4a4e01c49), ROM_GROUPWORD | ROM_SKIP(6) ) ROMX_LOAD( "y.c.e.c m.k.r-001", 0x000000, 0x80000, CRC(a258de13) SHA1(2e477948c4c8a2fb7cfdc4a739766bc4a4e01c49), ROM_GROUPWORD | ROM_SKIP(6) )

18
src/mame/drivers/ddenlovr.c
View File

@ -445,8 +445,8 @@ static int blit_draw( running_machine &machine, int src, int sx )
arg_size = fetch_word(src_data, src_len, &bit_addr, 4) + 1; arg_size = fetch_word(src_data, src_len, &bit_addr, 4) + 1;
#ifdef MAME_DEBUG #ifdef MAME_DEBUG
// if (pen_size > 4 || arg_size > 8) // if (pen_size > 4 || arg_size > 8)
// popmessage("warning: pen_size %d arg_size %d", pen_size, arg_size); // popmessage("warning: pen_size %d arg_size %d", pen_size, arg_size);
#endif #endif
// sryudens game bug // sryudens game bug
@ -2513,14 +2513,14 @@ static ADDRESS_MAP_START( kotbinyo_portmap, AS_IO, 8, dynax_state )
AM_RANGE(0x83, 0x84) AM_READ(hanakanz_gfxrom_r) AM_RANGE(0x83, 0x84) AM_READ(hanakanz_gfxrom_r)
AM_RANGE(0xa0, 0xa1) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w) AM_RANGE(0xa0, 0xa1) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w)
AM_RANGE(0xb0, 0xb0) AM_READ_PORT("SYSTEM") AM_RANGE(0xb0, 0xb0) AM_READ_PORT("SYSTEM")
// AM_RANGE(0xb1, 0xb2) AM_READ(hanakanz_keyb_r) // AM_RANGE(0xb1, 0xb2) AM_READ(hanakanz_keyb_r)
AM_RANGE(0xb1, 0xb1) AM_READ_PORT("KEYB0") AM_RANGE(0xb1, 0xb1) AM_READ_PORT("KEYB0")
AM_RANGE(0xb2, 0xb2) AM_READ_PORT("KEYB1") AM_RANGE(0xb2, 0xb2) AM_READ_PORT("KEYB1")
AM_RANGE(0xb3, 0xb3) AM_WRITE(hanakanz_coincounter_w) AM_RANGE(0xb3, 0xb3) AM_WRITE(hanakanz_coincounter_w)
// AM_RANGE(0xb4, 0xb4) AM_WRITE(hanakanz_keyb_w) // AM_RANGE(0xb4, 0xb4) AM_WRITE(hanakanz_keyb_w)
AM_RANGE(0xb6, 0xb6) AM_READ(hanakanz_rand_r) AM_RANGE(0xb6, 0xb6) AM_READ(hanakanz_rand_r)
AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("oki", okim6295_device, read, write) AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("oki", okim6295_device, read, write)
// AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write) // AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -2537,14 +2537,14 @@ static ADDRESS_MAP_START( kotbinsp_portmap, AS_IO, 8, dynax_state )
AM_RANGE(0x83, 0x84) AM_READ(hanakanz_gfxrom_r) AM_RANGE(0x83, 0x84) AM_READ(hanakanz_gfxrom_r)
AM_RANGE(0xa0, 0xa1) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w) AM_RANGE(0xa0, 0xa1) AM_DEVWRITE_LEGACY("ymsnd", ym2413_w)
AM_RANGE(0x90, 0x90) AM_READ_PORT("SYSTEM") AM_RANGE(0x90, 0x90) AM_READ_PORT("SYSTEM")
// AM_RANGE(0x91, 0x91) AM_READ(hanakanz_keyb_r) // AM_RANGE(0x91, 0x91) AM_READ(hanakanz_keyb_r)
AM_RANGE(0x91, 0x91) AM_READ_PORT("KEYB0") AM_RANGE(0x91, 0x91) AM_READ_PORT("KEYB0")
AM_RANGE(0x92, 0x92) AM_READ_PORT("KEYB1") AM_RANGE(0x92, 0x92) AM_READ_PORT("KEYB1")
AM_RANGE(0x93, 0x93) AM_WRITE(hanakanz_coincounter_w) AM_RANGE(0x93, 0x93) AM_WRITE(hanakanz_coincounter_w)
// AM_RANGE(0x94, 0x94) AM_WRITE(hanakanz_keyb_w) // AM_RANGE(0x94, 0x94) AM_WRITE(hanakanz_keyb_w)
AM_RANGE(0x96, 0x96) AM_READ(hanakanz_rand_r) AM_RANGE(0x96, 0x96) AM_READ(hanakanz_rand_r)
AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("oki", okim6295_device, read, write) AM_RANGE(0xc0, 0xc0) AM_DEVREADWRITE("oki", okim6295_device, read, write)
// AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write) // AM_RANGE(0xe0, 0xef) AM_DEVREADWRITE("rtc", msm6242_device, read, write)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -9133,7 +9133,7 @@ static MACHINE_CONFIG_START( kotbinyo, dynax_state )
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80)
/* devices */ /* devices */
// MCFG_MSM6242_ADD("rtc", hanakanz_rtc_intf) // MCFG_MSM6242_ADD("rtc", hanakanz_rtc_intf)
MACHINE_CONFIG_END MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( kotbinsp, kotbinyo ) static MACHINE_CONFIG_DERIVED( kotbinsp, kotbinyo )

74
src/mame/drivers/dec8.c
View File

@ -2079,10 +2079,10 @@ static MACHINE_CONFIG_START( lastmisn, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1); deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58) // MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */) // MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8) // MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1) // MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART) MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_lastmisn) MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_lastmisn)
@ -2118,7 +2118,7 @@ static MACHINE_CONFIG_START( shackled, dec8_state )
MCFG_CPU_PROGRAM_MAP(ym3526_s_map) MCFG_CPU_PROGRAM_MAP(ym3526_s_map)
/* NMIs are caused by the main CPU */ /* NMIs are caused by the main CPU */
// MCFG_QUANTUM_TIME(attotime::from_hz(100000)) // MCFG_QUANTUM_TIME(attotime::from_hz(100000))
MCFG_QUANTUM_PERFECT_CPU("maincpu") // needs heavy sync, otherwise one of the two CPUs will miss an irq and makes the game to hang MCFG_QUANTUM_PERFECT_CPU("maincpu") // needs heavy sync, otherwise one of the two CPUs will miss an irq and makes the game to hang
/* video hardware */ /* video hardware */
@ -2128,10 +2128,10 @@ static MACHINE_CONFIG_START( shackled, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1); deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58) // MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */) // MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8) // MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1) // MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART) MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_shackled) MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_shackled)
@ -2176,10 +2176,10 @@ static MACHINE_CONFIG_START( gondo, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1); deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58) // MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */) // MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8) // MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1) // MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART) MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_gondo) MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_gondo)
MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8) MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8)
@ -2225,10 +2225,10 @@ static MACHINE_CONFIG_START( garyoret, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1); deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58) // MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */) // MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8) // MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1) // MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART) MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_garyoret) MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_garyoret)
MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8) MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8)
@ -2277,10 +2277,10 @@ static MACHINE_CONFIG_START( ghostb, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1); deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58) // MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */) // MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8) // MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1) // MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART) MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_ghostb) MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_ghostb)
MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8) MCFG_SCREEN_VBLANK_DRIVER(dec8_state, screen_eof_dec8)
@ -2328,10 +2328,10 @@ static MACHINE_CONFIG_START( csilver, dec8_state )
deco_karnovsprites_device::set_gfx_region(*device, 1); deco_karnovsprites_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58) // MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */) // MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8) // MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1) // MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART) MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_lastmisn) MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_lastmisn)
@ -2384,10 +2384,10 @@ static MACHINE_CONFIG_START( oscar, dec8_state )
deco_mxc06_device::set_gfx_region(*device, 1); deco_mxc06_device::set_gfx_region(*device, 1);
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58) // MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */) // MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8) // MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1) // MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART) MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_oscar) MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_oscar)
@ -2426,10 +2426,10 @@ static MACHINE_CONFIG_START( srdarwin, dec8_state )
MCFG_BUFFERED_SPRITERAM8_ADD("spriteram") MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58) // MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */) // MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8) // MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1) // MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART) MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_srdarwin) MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_srdarwin)
@ -2477,10 +2477,10 @@ static MACHINE_CONFIG_START( cobracom, dec8_state )
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
// MCFG_SCREEN_REFRESH_RATE(58) // MCFG_SCREEN_REFRESH_RATE(58)
// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */) // MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(529) /* 58Hz, 529ms Vblank duration */)
// MCFG_SCREEN_SIZE(32*8, 32*8) // MCFG_SCREEN_SIZE(32*8, 32*8)
// MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1) // MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 1*8, 31*8-1)
MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART) MCFG_SCREEN_RAW_PARAMS(DEC8_PIXEL_CLOCK, DEC8_HTOTAL, DEC8_HBEND, DEC8_HBSTART, DEC8_VTOTAL, DEC8_VBEND, DEC8_VBSTART)
MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_cobracom) MCFG_SCREEN_UPDATE_DRIVER(dec8_state, screen_update_cobracom)

32
src/mame/drivers/firebeat.c
View File

@ -108,24 +108,24 @@
- The external Yamaha MIDI sound board is not emulated (no keyboard sounds). - The external Yamaha MIDI sound board is not emulated (no keyboard sounds).
- Notes on how the video is supposed to work from Ville / Ian Patterson: - Notes on how the video is supposed to work from Ville / Ian Patterson:
There are four "display contexts" that are set up via registers 20-4E. They are There are four "display contexts" that are set up via registers 20-4E. They are
basically just raw framebuffers. 40-4E sets the base framebuffer pointer, 30-3E basically just raw framebuffers. 40-4E sets the base framebuffer pointer, 30-3E
sets the size, 20-2E may set the minimum x and y coordinates but I haven't seen sets the size, 20-2E may set the minimum x and y coordinates but I haven't seen
them set to something other than 0 yet. One context is set as the one the RAMDAC them set to something other than 0 yet. One context is set as the one the RAMDAC
outputs to the monitor (not sure how this is selected yet, probably the lower outputs to the monitor (not sure how this is selected yet, probably the lower
bits of register 12). Thestartup test in the popn BIOS checks all of VRAM, so bits of register 12). Thestartup test in the popn BIOS checks all of VRAM, so
it moves the currentdisplay address around so you don't see crazy colors, which it moves the currentdisplay address around so you don't see crazy colors, which
is very helpful in figuring out how this part works. is very helpful in figuring out how this part works.
The other new part is that there are two VRAM write ports, managed by registers The other new part is that there are two VRAM write ports, managed by registers
60+68+70 and 64+6A+74, with status read from the lower bits of reg 7A. Each context 60+68+70 and 64+6A+74, with status read from the lower bits of reg 7A. Each context
can either write to VRAM as currently emulated, or the port can be switched in to can either write to VRAM as currently emulated, or the port can be switched in to
"immediate mode" via registers 68/6A. Immedate mode can be used to run GCU commands "immediate mode" via registers 68/6A. Immedate mode can be used to run GCU commands
at any point during the frame. It's mainly used to call display lists, which is where at any point during the frame. It's mainly used to call display lists, which is where
the display list addresses come from. Some games use it to send other commands, so the display list addresses come from. Some games use it to send other commands, so
it appears to be a 4-dword FIFO or something along those lines. it appears to be a 4-dword FIFO or something along those lines.
*/ */
#include "emu.h" #include "emu.h"

12
src/mame/drivers/goldstar.c
View File

@ -634,8 +634,8 @@ static ADDRESS_MAP_START( megaline_portmap, AS_IO, 8, goldstar_state )
AM_RANGE(0xe0, 0xe0) AM_DEVWRITE("sn3", sn76489_device, write) /* SN76489 #3 */ AM_RANGE(0xe0, 0xe0) AM_DEVWRITE("sn3", sn76489_device, write) /* SN76489 #3 */
AM_RANGE(0x60, 0x60) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w) /* AY8910 control? */ AM_RANGE(0x60, 0x60) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_w) /* AY8910 control? */
AM_RANGE(0x80, 0x80) AM_DEVREADWRITE_LEGACY("aysnd", ay8910_r, ay8910_data_w) /* AY8910 Input? */ AM_RANGE(0x80, 0x80) AM_DEVREADWRITE_LEGACY("aysnd", ay8910_r, ay8910_data_w) /* AY8910 Input? */
// AM_RANGE(0x01, 0x01) AM_DEVREAD_LEGACY("aysnd", ay8910_r) // AM_RANGE(0x01, 0x01) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
// AM_RANGE(0x02, 0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w) // AM_RANGE(0x02, 0x03) AM_DEVWRITE_LEGACY("aysnd", ay8910_data_address_w)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -7012,9 +7012,9 @@ static MACHINE_CONFIG_START( megaline, goldstar_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", goldstar_state, nmi_line_pulse) MCFG_CPU_VBLANK_INT_DRIVER("screen", goldstar_state, nmi_line_pulse)
/* 3x 8255 */ /* 3x 8255 */
// MCFG_I8255A_ADD( "ppi8255_0", lucky8_ppi8255_0_intf ) // MCFG_I8255A_ADD( "ppi8255_0", lucky8_ppi8255_0_intf )
// MCFG_I8255A_ADD( "ppi8255_1", lucky8_ppi8255_1_intf ) // MCFG_I8255A_ADD( "ppi8255_1", lucky8_ppi8255_1_intf )
// MCFG_I8255A_ADD( "ppi8255_2", lucky8_ppi8255_2_intf ) // MCFG_I8255A_ADD( "ppi8255_2", lucky8_ppi8255_2_intf )
/* video hardware */ /* video hardware */
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
@ -7027,7 +7027,7 @@ static MACHINE_CONFIG_START( megaline, goldstar_state )
MCFG_GFXDECODE(megaline) MCFG_GFXDECODE(megaline)
MCFG_PALETTE_LENGTH(256) MCFG_PALETTE_LENGTH(256)
// MCFG_NVRAM_ADD_1FILL("nvram") // MCFG_NVRAM_ADD_1FILL("nvram")
MCFG_VIDEO_START_OVERRIDE(goldstar_state,goldstar) MCFG_VIDEO_START_OVERRIDE(goldstar_state,goldstar)

8
src/mame/drivers/s6a.c
View File

@ -261,8 +261,8 @@ INPUT_CHANGED_MEMBER( s6a_state::audio_nmi )
WRITE8_MEMBER( s6a_state::sol0_w ) WRITE8_MEMBER( s6a_state::sol0_w )
{ {
// if (BIT(data, 4)) // if (BIT(data, 4))
// m_samples->start(2, 5); // outhole // m_samples->start(2, 5); // outhole
} }
WRITE8_MEMBER( s6a_state::sol1_w ) WRITE8_MEMBER( s6a_state::sol1_w )
@ -287,8 +287,8 @@ WRITE8_MEMBER( s6a_state::sol1_w )
m_pias->cb1_w(m_cb1); m_pias->cb1_w(m_cb1);
// if (BIT(data, 5)) // if (BIT(data, 5))
// m_samples->start(0, 6); // knocker // m_samples->start(0, 6); // knocker
} }
static const pia6821_interface pia22_intf = static const pia6821_interface pia22_intf =

16
src/mame/drivers/scramble.c
View File

@ -1789,18 +1789,18 @@ ROM_END
Triple Punch Triple Punch
(C)1982 KKI (C)1982 KKI
board silkscreend PCO-008-01 board silkscreend PCO-008-01
Empty 24 pin socket at 2E Empty 24 pin socket at 2E
Empty 40 pin socket at 0A Empty 40 pin socket at 0A
.2h 2732 stickered TD4 .2h 2732 stickered TD4
.2k 2732 stickered TC3 .2k 2732 stickered TC3
.2l 2732 stickered TE2 .2l 2732 stickered TE2
.2m 2732 stickered TD1 .2m 2732 stickered TD1
.5h 2716 stickered TA7 .5h 2716 stickered TA7
.5f 2716 stickered TA6 .5f 2716 stickered TA6
.6e 82s123 stickered TA .6e 82s123 stickered TA
***************************************************************************/ ***************************************************************************/
ROM_START( triplepa ) ROM_START( triplepa )

74
src/mame/drivers/supercrd.c
View File

@ -34,7 +34,7 @@
ROMs: PRG: 2x 27C512 (IC37, IC51) ROMs: PRG: 2x 27C512 (IC37, IC51)
GFX: 2x 27C512 (IC10, IC11) GFX: 2x 27C512 (IC10, IC11)
BP: 1x N82S147N BP: 1x N82S147N
1x Xtal 16 MHz. 1x Xtal 16 MHz.
1x 8 DIP switches bank. 1x 8 DIP switches bank.
@ -276,9 +276,9 @@ static ADDRESS_MAP_START( supercrd_map, AS_PROGRAM, 8, supercrd_state )
AM_RANGE(0x0000, 0xbfff) AM_ROM AM_RANGE(0x0000, 0xbfff) AM_ROM
AM_RANGE(0xc000, 0xcfff) AM_RAM_WRITE(supercrd_videoram_w) AM_SHARE("videoram") // wrong AM_RANGE(0xc000, 0xcfff) AM_RAM_WRITE(supercrd_videoram_w) AM_SHARE("videoram") // wrong
AM_RANGE(0xd000, 0xdfff) AM_RAM_WRITE(supercrd_colorram_w) AM_SHARE("colorram") // wrong AM_RANGE(0xd000, 0xdfff) AM_RAM_WRITE(supercrd_colorram_w) AM_SHARE("colorram") // wrong
// AM_RANGE(0x0000, 0x0000) AM_RAM AM_SHARE("nvram") // AM_RANGE(0x0000, 0x0000) AM_RAM AM_SHARE("nvram")
// AM_RANGE(0xe000, 0xe000) AM_DEVWRITE("crtc", mc6845_device, address_w) // AM_RANGE(0xe000, 0xe000) AM_DEVWRITE("crtc", mc6845_device, address_w)
// AM_RANGE(0xe001, 0xe001) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w) // AM_RANGE(0xe001, 0xe001) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -401,16 +401,16 @@ GFXDECODE_END
//static const mc6845_interface mc6845_intf = //static const mc6845_interface mc6845_intf =
//{ //{
// "screen", /* screen we are acting on */ // "screen", /* screen we are acting on */
// 4, /* number of pixels per video memory address */ // 4, /* number of pixels per video memory address */
// NULL, /* before pixel update callback */ // NULL, /* before pixel update callback */
// NULL, /* row update callback */ // NULL, /* row update callback */
// NULL, /* after pixel update callback */ // NULL, /* after pixel update callback */
// DEVCB_NULL, /* callback for display state changes */ // DEVCB_NULL, /* callback for display state changes */
// DEVCB_NULL, /* callback for cursor state changes */ // DEVCB_NULL, /* callback for cursor state changes */
// DEVCB_NULL, /* HSYNC callback */ // DEVCB_NULL, /* HSYNC callback */
// DEVCB_NULL, /* VSYNC callback */ // DEVCB_NULL, /* VSYNC callback */
// NULL /* update address callback */ // NULL /* update address callback */
//}; //};
@ -420,24 +420,24 @@ GFXDECODE_END
//static I8255_INTERFACE (ppi8255_intf_0) //static I8255_INTERFACE (ppi8255_intf_0)
//{ //{
// /* (port) Mode X - description */ // /* (port) Mode X - description */
// DEVCB_UNMAPPED, /* Port A read */ // DEVCB_UNMAPPED, /* Port A read */
// DEVCB_UNMAPPED, /* Port A write */ // DEVCB_UNMAPPED, /* Port A write */
// DEVCB_UNMAPPED, /* Port B read */ // DEVCB_UNMAPPED, /* Port B read */
// DEVCB_UNMAPPED, /* Port B write */ // DEVCB_UNMAPPED, /* Port B write */
// DEVCB_UNMAPPED, /* Port C read */ // DEVCB_UNMAPPED, /* Port C read */
// DEVCB_UNMAPPED /* Port C write */ // DEVCB_UNMAPPED /* Port C write */
//}; //};
//static I8255_INTERFACE (ppi8255_intf_1) //static I8255_INTERFACE (ppi8255_intf_1)
//{ //{
// /* (port) Mode X - description */ // /* (port) Mode X - description */
// DEVCB_UNMAPPED, /* Port A read */ // DEVCB_UNMAPPED, /* Port A read */
// DEVCB_UNMAPPED, /* Port A write */ // DEVCB_UNMAPPED, /* Port A write */
// DEVCB_UNMAPPED, /* Port B read */ // DEVCB_UNMAPPED, /* Port B read */
// DEVCB_UNMAPPED, /* Port B write */ // DEVCB_UNMAPPED, /* Port B write */
// DEVCB_UNMAPPED, /* Port C read */ // DEVCB_UNMAPPED, /* Port C read */
// DEVCB_UNMAPPED /* Port C write */ // DEVCB_UNMAPPED /* Port C write */
//}; //};
/************************** /**************************
@ -449,10 +449,10 @@ static MACHINE_CONFIG_START( supercrd, supercrd_state )
MCFG_CPU_ADD("maincpu", Z80, MASTER_CLOCK/8) /* 2MHz, guess */ MCFG_CPU_ADD("maincpu", Z80, MASTER_CLOCK/8) /* 2MHz, guess */
MCFG_CPU_PROGRAM_MAP(supercrd_map) MCFG_CPU_PROGRAM_MAP(supercrd_map)
// MCFG_NVRAM_ADD_0FILL("nvram") // MCFG_NVRAM_ADD_0FILL("nvram")
// MCFG_I8255_ADD( "ppi8255_0", ppi8255_intf_0 ) // MCFG_I8255_ADD( "ppi8255_0", ppi8255_intf_0 )
// MCFG_I8255_ADD( "ppi8255_1", ppi8255_intf_1 ) // MCFG_I8255_ADD( "ppi8255_1", ppi8255_intf_1 )
/* video hardware */ /* video hardware */
@ -469,12 +469,12 @@ static MACHINE_CONFIG_START( supercrd, supercrd_state )
MCFG_PALETTE_INIT_OVERRIDE(supercrd_state, supercrd) MCFG_PALETTE_INIT_OVERRIDE(supercrd_state, supercrd)
MCFG_VIDEO_START_OVERRIDE(supercrd_state, supercrd) MCFG_VIDEO_START_OVERRIDE(supercrd_state, supercrd)
// MCFG_MC6845_ADD("crtc", MC6845, MASTER_CLOCK/8, mc6845_intf) // MCFG_MC6845_ADD("crtc", MC6845, MASTER_CLOCK/8, mc6845_intf)
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono") MCFG_SPEAKER_STANDARD_MONO("mono")
// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75) // MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
MACHINE_CONFIG_END MACHINE_CONFIG_END
@ -488,10 +488,10 @@ ROM_START( supercrd )
ROM_LOAD( "supca_417_ce2.ic51", 0x10000, 0x08000, CRC(36415f73) SHA1(9881b88991f034d79260502289432a7318aa1647) ) // wrong ROM_LOAD( "supca_417_ce2.ic51", 0x10000, 0x08000, CRC(36415f73) SHA1(9881b88991f034d79260502289432a7318aa1647) ) // wrong
ROM_IGNORE( 0x8000) ROM_IGNORE( 0x8000)
// ROM_LOAD( "supca_417_ce1.ic37", 0x0000, 0x8000, CRC(b67f7d38) SHA1(eaf8f24d476185d4744858afcbf0005362f49cab) ) // ROM_LOAD( "supca_417_ce1.ic37", 0x0000, 0x8000, CRC(b67f7d38) SHA1(eaf8f24d476185d4744858afcbf0005362f49cab) )
// ROM_CONTINUE( 0x0000, 0x8000) // ROM_CONTINUE( 0x0000, 0x8000)
// ROM_LOAD( "supca_417_ce2.ic51", 0x8000, 0x8000, CRC(36415f73) SHA1(9881b88991f034d79260502289432a7318aa1647) ) // ROM_LOAD( "supca_417_ce2.ic51", 0x8000, 0x8000, CRC(36415f73) SHA1(9881b88991f034d79260502289432a7318aa1647) )
// ROM_IGNORE( 0x8000) // ROM_IGNORE( 0x8000)
ROM_REGION( 0x20000, "gfxtemp", 0 ) ROM_REGION( 0x20000, "gfxtemp", 0 )
ROM_LOAD( "supca_410_zg2.ic11", 0x00000, 0x10000, CRC(a4646dc6) SHA1(638ad334bb4f1430381474ddfaa1029cb4d13916) ) ROM_LOAD( "supca_410_zg2.ic11", 0x00000, 0x10000, CRC(a4646dc6) SHA1(638ad334bb4f1430381474ddfaa1029cb4d13916) )

2
src/mame/drivers/zn.c
View File

@ -422,7 +422,7 @@ static void zn_driver_init( running_machine &machine )
{ {
state->m_znsec0->init( zn_config_table[ n_game ].p_n_mainsec ); state->m_znsec0->init( zn_config_table[ n_game ].p_n_mainsec );
state->m_znsec1->init( zn_config_table[ n_game ].p_n_gamesec ); state->m_znsec1->init( zn_config_table[ n_game ].p_n_gamesec );
// psx_sio_install_handler( machine, 0, sio_pad_handler ); // psx_sio_install_handler( machine, 0, sio_pad_handler );
break; break;
} }
n_game++; n_game++;

6
src/mame/machine/scramble.c
View File

@ -637,7 +637,7 @@ WRITE8_MEMBER(scramble_state::harem_decrypt_clk_w)
m_harem_decrypt_mode = ((m_harem_decrypt_mode >> 1) | ((m_harem_decrypt_bit & 1) << 3)) & 0x0f; m_harem_decrypt_mode = ((m_harem_decrypt_mode >> 1) | ((m_harem_decrypt_bit & 1) << 3)) & 0x0f;
m_harem_decrypt_count++; m_harem_decrypt_count++;
// logerror("%s: decrypt mode = %02x, count = %x\n", machine().describe_context(), m_harem_decrypt_mode, m_harem_decrypt_count); // logerror("%s: decrypt mode = %02x, count = %x\n", machine().describe_context(), m_harem_decrypt_mode, m_harem_decrypt_count);
} }
m_harem_decrypt_clk = data; m_harem_decrypt_clk = data;
@ -658,7 +658,7 @@ WRITE8_MEMBER(scramble_state::harem_decrypt_clk_w)
membank("rombank")->set_base (m_harem_decrypted_data + 0x2000 * bank); membank("rombank")->set_base (m_harem_decrypted_data + 0x2000 * bank);
membank("rombank")->set_base_decrypted (m_harem_decrypted_opcodes + 0x2000 * bank); membank("rombank")->set_base_decrypted (m_harem_decrypted_opcodes + 0x2000 * bank);
// logerror("%s: decrypt mode = %02x (bank %x) active\n", machine().describe_context(), m_harem_decrypt_mode, bank); // logerror("%s: decrypt mode = %02x (bank %x) active\n", machine().describe_context(), m_harem_decrypt_mode, bank);
m_harem_decrypt_mode = 0; m_harem_decrypt_mode = 0;
m_harem_decrypt_count = 0; m_harem_decrypt_count = 0;
@ -670,7 +670,7 @@ WRITE8_MEMBER(scramble_state::harem_decrypt_rst_w)
m_harem_decrypt_mode = 0; m_harem_decrypt_mode = 0;
m_harem_decrypt_count = 0; m_harem_decrypt_count = 0;
// logerror("%s: decrypt mode reset\n", machine().describe_context()); // logerror("%s: decrypt mode reset\n", machine().describe_context());
} }
DRIVER_INIT_MEMBER(scramble_state,harem) DRIVER_INIT_MEMBER(scramble_state,harem)

2
src/mame/machine/zndip.c
View File

@ -41,7 +41,7 @@ void zndip_device::data_in( int data, int mask )
{ {
int dip = m_data_handler(); int dip = m_data_handler();
int bit = ( ( dip >> m_bit ) & 1 ); int bit = ( ( dip >> m_bit ) & 1 );
// verboselog( machine, 2, "read dip %02x -> %02x\n", n_data, bit * PSX_SIO_IN_DATA ); // verboselog( machine, 2, "read dip %02x -> %02x\n", n_data, bit * PSX_SIO_IN_DATA );
data_out( bit * PSX_SIO_IN_DATA, PSX_SIO_IN_DATA ); data_out( bit * PSX_SIO_IN_DATA, PSX_SIO_IN_DATA );
m_bit++; m_bit++;
m_bit &= 7; m_bit &= 7;

2
src/mame/mame.lst
View File

@ -5042,7 +5042,7 @@ meltybld // 2005.08 Melty Blood Act Cadenza (Rev C)
ggxxsla // 2005.09 Guilty Gear XX Slash (Rev A) ggxxsla // 2005.09 Guilty Gear XX Slash (Rev A)
radirgy // 2005.10 Radirgy radirgy // 2005.10 Radirgy
undefeat // 2005.10 Under Defeat undefeat // 2005.10 Under Defeat
radirgya // 2005.12 Radirgy (Rev A) radirgya // 2005.12 Radirgy (Rev A)
// 2005.?? Dragon Treasure 3 (Rev A) // 2005.?? Dragon Treasure 3 (Rev A)
// 2005.?? ExZeus // 2005.?? ExZeus
// 2005.?? Mushiking The King Of Beetles II ENG // 2005.?? Mushiking The King Of Beetles II ENG

2
src/mame/video/galaxold.c
View File

@ -790,7 +790,7 @@ VIDEO_START_MEMBER(galaxold_state,harem)
{ {
video_start_common(machine()); video_start_common(machine());
m_bg_tilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(galaxold_state::harem_get_tile_info),this),TILEMAP_SCAN_ROWS,8,8,32,32); m_bg_tilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(galaxold_state::harem_get_tile_info),this),TILEMAP_SCAN_ROWS,8,8,32,32);
// m_bg_tilemap->set_transparent_pen(0); // opaque tilemap to get sky and sand colors // m_bg_tilemap->set_transparent_pen(0); // opaque tilemap to get sky and sand colors
m_bg_tilemap->set_scroll_cols(32); m_bg_tilemap->set_scroll_cols(32);

4
src/mame/video/konicdev.c
View File

@ -10321,10 +10321,10 @@ void k001604_draw_back_layer( device_t *device, bitmap_rgb32 &bitmap, const rect
x = (x + 320) * 256; x = (x + 320) * 256;
y = (y + 208) * 256; y = (y + 208) * 256;
// xx = (xx); // xx = (xx);
xy = (-xy); xy = (-xy);
yx = (-yx); yx = (-yx);
// yy = (yy); // yy = (yy);
if ((k001604->reg[0x6c / 4] & (0x08 >> layer)) != 0) if ((k001604->reg[0x6c / 4] & (0x08 >> layer)) != 0)
{ {

2
src/mame/video/vastar.c
View File

@ -130,7 +130,7 @@ static void draw_sprites(running_machine &machine, bitmap_ind16 &bitmap,const re
UINT8 *spriteram_3 = state->m_spriteram3; UINT8 *spriteram_3 = state->m_spriteram3;
int offs; int offs;
// for (offs = 0; offs < 0x40; offs += 2) // for (offs = 0; offs < 0x40; offs += 2)
for (offs = 0x40-2; offs >=0; offs -= 2) for (offs = 0x40-2; offs >=0; offs -= 2)
{ {
int code, sx, sy, color, flipx, flipy; int code, sx, sy, color, flipx, flipy;

2
src/mame/video/vsystem_spr2.c
View File

@ -16,7 +16,7 @@
// Pipe Dream // Pipe Dream
// there were lots of comments saying drivers using the // there were lots of comments saying drivers using the
// static const UINT8 zoomtable[16] = { 0,7,14,20,25,30,34,38,42,46,49,52,54,57,59,61 }; // static const UINT8 zoomtable[16] = { 0,7,14,20,25,30,34,38,42,46,49,52,54,57,59,61 };
// table for zooming needed upgrading, are we sure this isn't one of the // table for zooming needed upgrading, are we sure this isn't one of the
// differences between this sprite chip and the one in vsystem_spr.c, pspikes zooming is very rough // differences between this sprite chip and the one in vsystem_spr.c, pspikes zooming is very rough

10
src/mess/drivers/a7800.c
View File

@ -10,13 +10,13 @@
added PAL machine description added PAL machine description
changed clock to be precise changed clock to be precise
2012/10/25 Robert Tuccitto NTSC Color Generator utilized for 2012/10/25 Robert Tuccitto NTSC Color Generator utilized for
color palette with hue shift/start color palette with hue shift/start
based on observation of several based on observation of several
systems across multiple displays systems across multiple displays
2012/11/09 Robert Tuccitto Fixed 3 degree hue begin point 2012/11/09 Robert Tuccitto Fixed 3 degree hue begin point
miscalculation of color palette miscalculation of color palette
***************************************************************************/ ***************************************************************************/

148
src/mess/drivers/adam.c
View File

@ -626,18 +626,18 @@ WRITE8_MEMBER( adam_state::mioc_w )
{ {
/* /*
bit description bit description
0 Lower memory option 0 0 Lower memory option 0
1 Lower memory option 1 1 Lower memory option 1
2 Upper memory option 0 2 Upper memory option 0
3 Upper memory option 1 3 Upper memory option 1
4 4
5 5
6 6
7 7
*/ */
m_mioc = data; m_mioc = data;
} }
@ -666,18 +666,18 @@ WRITE8_MEMBER( adam_state::adamnet_w )
{ {
/* /*
bit description bit description
0 Network reset 0 Network reset
1 EOS enable 1 EOS enable
2 2
3 3
4 4
5 5
6 6
7 7
*/ */
if (BIT(m_an, 0) && !BIT(data, 0)) if (BIT(m_an, 0) && !BIT(data, 0))
{ {
@ -698,18 +698,18 @@ WRITE8_MEMBER( adam_state::m6801_p1_w )
{ {
/* /*
bit description bit description
0 BA8 0 BA8
1 BA9 1 BA9
2 BA10 2 BA10
3 BA11 3 BA11
4 BA12 4 BA12
5 BA13 5 BA13
6 BA14 6 BA14
7 BA15 7 BA15
*/ */
m_ba = (data << 8) | (m_ba & 0xff); m_ba = (data << 8) | (m_ba & 0xff);
} }
@ -723,15 +723,15 @@ READ8_MEMBER( adam_state::m6801_p2_r )
{ {
/* /*
bit description bit description
0 M6801 mode bit 0 0 M6801 mode bit 0
1 M6801 mode bit 1 1 M6801 mode bit 1
2 M6801 mode bit 2 2 M6801 mode bit 2
3 NET RXD 3 NET RXD
4 4
*/ */
UINT8 data = M6801_MODE_7; UINT8 data = M6801_MODE_7;
@ -750,15 +750,15 @@ WRITE8_MEMBER( adam_state::m6801_p2_w )
{ {
/* /*
bit description bit description
0 _DMA 0 _DMA
1 1
2 _BWR 2 _BWR
3 3
4 NET TXD 4 NET TXD
*/ */
// DMA // DMA
m_dma = BIT(data, 0); m_dma = BIT(data, 0);
@ -779,18 +779,18 @@ READ8_MEMBER( adam_state::m6801_p3_r )
{ {
/* /*
bit description bit description
0 BD0 0 BD0
1 BD1 1 BD1
2 BD2 2 BD2
3 BD3 3 BD3
4 BD4 4 BD4
5 BD5 5 BD5
6 BD6 6 BD6
7 BD7 7 BD7
*/ */
return m_data_out; return m_data_out;
} }
@ -804,18 +804,18 @@ WRITE8_MEMBER( adam_state::m6801_p3_w )
{ {
/* /*
bit description bit description
0 BD0 0 BD0
1 BD1 1 BD1
2 BD2 2 BD2
3 BD3 3 BD3
4 BD4 4 BD4
5 BD5 5 BD5
6 BD6 6 BD6
7 BD7 7 BD7
*/ */
m_data_in = data; m_data_in = data;
} }
@ -829,18 +829,18 @@ WRITE8_MEMBER( adam_state::m6801_p4_w )
{ {
/* /*
bit description bit description
0 BA0 0 BA0
1 BA1 1 BA1
2 BA2 2 BA2
3 BA3 3 BA3
4 BA4 4 BA4
5 BA5 5 BA5
6 BA6 6 BA6
7 BA7 7 BA7
*/ */
m_ba = (m_ba & 0xff00) | data; m_ba = (m_ba & 0xff00) | data;
} }

16
src/mess/drivers/alphasma.c
View File

@ -4,10 +4,10 @@
08/28/2012 Skeleton driver 08/28/2012 Skeleton driver
TODO: TODO:
- define video HW capabilities - define video HW capabilities
- "Addr. Bus RAM error" string read, presumably memory mapped RAM at 0x8000 - "Addr. Bus RAM error" string read, presumably memory mapped RAM at 0x8000
is actually a r/w bank register. is actually a r/w bank register.
****************************************************************************/ ****************************************************************************/
@ -30,7 +30,7 @@ public:
virtual void machine_start(); virtual void machine_start();
virtual void palette_init(); virtual void palette_init();
// virtual UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); // virtual UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
}; };
@ -41,8 +41,8 @@ static ADDRESS_MAP_START(alphasmart_mem, AS_PROGRAM, 8, alphasmart_state)
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START(alphasmart_io, AS_IO, 8, alphasmart_state) static ADDRESS_MAP_START(alphasmart_io, AS_IO, 8, alphasmart_state)
// AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_DEVREADWRITE("hd44780", hd44780_device, control_read, control_write) // AM_RANGE(MC68HC11_IO_PORTA, MC68HC11_IO_PORTA) AM_DEVREADWRITE("hd44780", hd44780_device, control_read, control_write)
// AM_RANGE(MC68HC11_IO_PORTD, MC68HC11_IO_PORTD) AM_DEVREADWRITE("hd44780", hd44780_device, data_read, data_write) // AM_RANGE(MC68HC11_IO_PORTD, MC68HC11_IO_PORTD) AM_DEVREADWRITE("hd44780", hd44780_device, data_read, data_write)
ADDRESS_MAP_END ADDRESS_MAP_END
/* Input ports */ /* Input ports */
@ -79,7 +79,7 @@ static MACHINE_CONFIG_START( alphasmart, alphasmart_state )
MCFG_CPU_PROGRAM_MAP(alphasmart_mem) MCFG_CPU_PROGRAM_MAP(alphasmart_mem)
MCFG_CPU_IO_MAP(alphasmart_io) MCFG_CPU_IO_MAP(alphasmart_io)
MCFG_CPU_CONFIG(alphasmart_hc11_config) MCFG_CPU_CONFIG(alphasmart_hc11_config)
// MCFG_CPU_PERIODIC_INT_DRIVER(alphasmart_state, irq0_line_hold, 50) // MCFG_CPU_PERIODIC_INT_DRIVER(alphasmart_state, irq0_line_hold, 50)
MCFG_HD44780_ADD("hd44780", alphasmart_4line_display) MCFG_HD44780_ADD("hd44780", alphasmart_4line_display)

2
src/mess/drivers/altos5.c
View File

@ -1,6 +1,6 @@
/*************************************************************************** /***************************************************************************
Altos 5-15 Altos 5-15
****************************************************************************/ ****************************************************************************/

150
src/mess/drivers/apc.c
View File

@ -1,50 +1,50 @@
/*************************************************************************** /***************************************************************************
Advanced Personal Computer (c) 1982 NEC Advanced Personal Computer (c) 1982 NEC
preliminary driver by Angelo Salese preliminary driver by Angelo Salese
TODO: TODO:
- video emulation - video emulation
- Floppy device - Floppy device
- keyboard - keyboard
- Understand interrupt sources - Understand interrupt sources
- NMI seems valid, dumps a x86 stack to vram? - NMI seems valid, dumps a x86 stack to vram?
- Unknown RTC device type; - Unknown RTC device type;
- What are exactly APU and MPU devices? They sounds scary ... - What are exactly APU and MPU devices? They sounds scary ...
- DMA hook-ups - DMA hook-ups
- serial ports - serial ports
- parallel ports - parallel ports
- Extract info regarding Hard Disk functionality - Extract info regarding Hard Disk functionality
- Various unknown ports - Various unknown ports
- What kind of external ROM actually maps at 0xa****? - What kind of external ROM actually maps at 0xa****?
============================================================================ ============================================================================
front ^ front ^
| |
card card
---- ----
69PFCU 7220 PFCU1R 2764 69PFCU 7220 PFCU1R 2764
69PTS 7220 69PTS 7220
- -
69PFB2 8086/8087 DFBU2J PFBU2L 2732 69PFB2 8086/8087 DFBU2J PFBU2L 2732
69SNB RAM 69SNB RAM
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
i/o memory map (preliminary): i/o memory map (preliminary):
0x00 - 0x1f DMA 0x00 - 0x1f DMA
0x20 - 0x23 i8259 master 0x20 - 0x23 i8259 master
0x28 - 0x2f i8259 slave (even), pit8253 (odd) 0x28 - 0x2f i8259 slave (even), pit8253 (odd)
0x30 - 0x37 serial i8251, even #1 / odd #2 0x30 - 0x37 serial i8251, even #1 / odd #2
0x38 - 0x3f DMA segments 0x38 - 0x3f DMA segments
0x40 - 0x43 upd7220, even chr / odd bitmap 0x40 - 0x43 upd7220, even chr / odd bitmap
0x48 - 0x4f keyboard 0x48 - 0x4f keyboard
0x50 - 0x53 upd765 0x50 - 0x53 upd765
0x58 rtc 0x58 rtc
0x5a - 0x5e APU 0x5a - 0x5e APU
0x60 MPU (melody) 0x60 MPU (melody)
0x61 - 0x67 (Mirror of pit8253?) 0x61 - 0x67 (Mirror of pit8253?)
0x68 - 0x6f parallel port 0x68 - 0x6f parallel port
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
0xfe3c2: checks if the floppy has a valid string for booting (either "CP/M-86" 0xfe3c2: checks if the floppy has a valid string for booting (either "CP/M-86"
@ -172,33 +172,33 @@ static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
int xi,yi; int xi,yi;
int x; int x;
UINT8 char_size; UINT8 char_size;
// UINT8 interlace_on; // UINT8 interlace_on;
// if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off // if(state->m_video_ff[DISPLAY_REG] == 0) //screen is off
// return; // return;
// interlace_on = state->m_video_reg[2] == 0x10; /* TODO: correct? */ // interlace_on = state->m_video_reg[2] == 0x10; /* TODO: correct? */
char_size = 16; char_size = 16;
for(x=0;x<pitch;x++) for(x=0;x<pitch;x++)
{ {
UINT8 tile_data; UINT8 tile_data;
// UINT8 secret,reverse,u_line,v_line; // UINT8 secret,reverse,u_line,v_line;
UINT8 color; UINT8 color;
UINT8 tile,attr,pen; UINT8 tile,attr,pen;
UINT32 tile_addr; UINT32 tile_addr;
// tile_addr = addr+(x*(state->m_video_ff[WIDTH40_REG]+1)); // tile_addr = addr+(x*(state->m_video_ff[WIDTH40_REG]+1));
tile_addr = addr+(x*(1)); tile_addr = addr+(x*(1));
tile = state->m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0x007f; tile = state->m_video_ram_1[(tile_addr*2+1) & 0x1fff] & 0x007f;
attr = (state->m_video_ram_1[(tile_addr*2 & 0x1fff) | 0x2000] & 0x00ff); attr = (state->m_video_ram_1[(tile_addr*2 & 0x1fff) | 0x2000] & 0x00ff);
// secret = (attr & 1) ^ 1; // secret = (attr & 1) ^ 1;
//blink = attr & 2; //blink = attr & 2;
// reverse = attr & 4; // reverse = attr & 4;
// u_line = attr & 8; // u_line = attr & 8;
// v_line = attr & 0x10; // v_line = attr & 0x10;
color = (attr & 0xe0) >> 5; color = (attr & 0xe0) >> 5;
for(yi=0;yi<lr;yi++) for(yi=0;yi<lr;yi++)
@ -207,19 +207,19 @@ static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
{ {
int res_x,res_y; int res_x,res_y;
// res_x = (x*8+xi) * (state->m_video_ff[WIDTH40_REG]+1); // res_x = (x*8+xi) * (state->m_video_ff[WIDTH40_REG]+1);
res_x = (x*8+xi) * (1); res_x = (x*8+xi) * (1);
res_y = y*lr+yi; res_y = y*lr+yi;
if(res_x > 640 || res_y > char_size*25) //TODO if(res_x > 640 || res_y > char_size*25) //TODO
continue; continue;
// tile_data = secret ? 0 : (state->m_char_rom[tile*char_size+interlace_on*0x800+yi]); // tile_data = secret ? 0 : (state->m_char_rom[tile*char_size+interlace_on*0x800+yi]);
tile_data = (state->m_char_rom[tile+yi*0x80]); tile_data = (state->m_char_rom[tile+yi*0x80]);
// if(reverse) { tile_data^=0xff; } // if(reverse) { tile_data^=0xff; }
// if(u_line && yi == 7) { tile_data = 0xff; } // if(u_line && yi == 7) { tile_data = 0xff; }
// if(v_line) { tile_data|=8; } // if(v_line) { tile_data|=8; }
if(cursor_on && cursor_addr == tile_addr) if(cursor_on && cursor_addr == tile_addr)
tile_data^=0xff; tile_data^=0xff;
@ -232,13 +232,13 @@ static UPD7220_DRAW_TEXT_LINE( hgdc_draw_text )
if(pen) if(pen)
bitmap.pix16(res_y, res_x) = pen; bitmap.pix16(res_y, res_x) = pen;
// if(state->m_video_ff[WIDTH40_REG]) // if(state->m_video_ff[WIDTH40_REG])
// { // {
// if(res_x+1 > 640 || res_y > char_size*25) //TODO // if(res_x+1 > 640 || res_y > char_size*25) //TODO
// continue; // continue;
// bitmap.pix16(res_y, res_x+1) = pen; // bitmap.pix16(res_y, res_x+1) = pen;
// } // }
} }
} }
} }
@ -387,7 +387,7 @@ WRITE8_MEMBER(apc_state::apc_dma_w)
static ADDRESS_MAP_START( apc_map, AS_PROGRAM, 16, apc_state ) static ADDRESS_MAP_START( apc_map, AS_PROGRAM, 16, apc_state )
AM_RANGE(0x00000, 0x9ffff) AM_RAM AM_RANGE(0x00000, 0x9ffff) AM_RAM
// AM_RANGE(0xa0000, 0xaffff) space for an external ROM // AM_RANGE(0xa0000, 0xaffff) space for an external ROM
AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("ipl", 0) AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_REGION("ipl", 0)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -396,18 +396,18 @@ static ADDRESS_MAP_START( apc_io, AS_IO, 16, apc_state )
AM_RANGE(0x00, 0x1f) AM_READWRITE8(apc_dma_r, apc_dma_w,0xff00) AM_RANGE(0x00, 0x1f) AM_READWRITE8(apc_dma_r, apc_dma_w,0xff00)
AM_RANGE(0x20, 0x23) AM_DEVREADWRITE8_LEGACY("pic8259_master", pic8259_r, pic8259_w, 0x00ff) // i8259 AM_RANGE(0x20, 0x23) AM_DEVREADWRITE8_LEGACY("pic8259_master", pic8259_r, pic8259_w, 0x00ff) // i8259
AM_RANGE(0x28, 0x2f) AM_READWRITE8(apc_port_28_r, apc_port_28_w, 0xffff) AM_RANGE(0x28, 0x2f) AM_READWRITE8(apc_port_28_r, apc_port_28_w, 0xffff)
// 0x30, 0x37 serial port 0/1 (i8251) (even/odd) // 0x30, 0x37 serial port 0/1 (i8251) (even/odd)
AM_RANGE(0x38, 0x3f) AM_WRITE8(apc_dma_segments_w,0x00ff) AM_RANGE(0x38, 0x3f) AM_WRITE8(apc_dma_segments_w,0x00ff)
AM_RANGE(0x40, 0x43) AM_READWRITE8(apc_gdc_r, apc_gdc_w, 0xffff) AM_RANGE(0x40, 0x43) AM_READWRITE8(apc_gdc_r, apc_gdc_w, 0xffff)
// 0x46 UPD7220 reset interrupt // 0x46 UPD7220 reset interrupt
AM_RANGE(0x48, 0x4f) AM_READWRITE8(apc_kbd_r, apc_kbd_w, 0x00ff) AM_RANGE(0x48, 0x4f) AM_READWRITE8(apc_kbd_r, apc_kbd_w, 0x00ff)
AM_RANGE(0x50, 0x53) AM_DEVICE8("upd765", upd765a_device, map, 0x00ff ) // upd765 AM_RANGE(0x50, 0x53) AM_DEVICE8("upd765", upd765a_device, map, 0x00ff ) // upd765
// 0x5a APU data (Arithmetic Processing Unit!) // 0x5a APU data (Arithmetic Processing Unit!)
// 0x5e APU status/command // 0x5e APU status/command
AM_RANGE(0x60, 0x67) AM_READWRITE8(apc_port_60_r, apc_port_60_w, 0xffff) AM_RANGE(0x60, 0x67) AM_READWRITE8(apc_port_60_r, apc_port_60_w, 0xffff)
// 0x60 Melody Processing Unit // 0x60 Melody Processing Unit
// AM_RANGE(0x68, 0x6f) i8255 , printer port (A: status (R) B: data (W) C: command (W)) // AM_RANGE(0x68, 0x6f) i8255 , printer port (A: status (R) B: data (W) C: command (W))
// AM_DEVREADWRITE8("upd7220_btm", upd7220_device, read, write, 0x00ff) // AM_DEVREADWRITE8("upd7220_btm", upd7220_device, read, write, 0x00ff)
ADDRESS_MAP_END ADDRESS_MAP_END
static INPUT_PORTS_START( apc ) static INPUT_PORTS_START( apc )
@ -468,15 +468,15 @@ INPUT_PORTS_END
void apc_state::fdc_drq(bool state) void apc_state::fdc_drq(bool state)
{ {
// printf("%02x DRQ\n",state); // printf("%02x DRQ\n",state);
// i8237_dreq0_w(m_dma, state); // i8237_dreq0_w(m_dma, state);
m_dmac->dreq1_w(state); m_dmac->dreq1_w(state);
} }
void apc_state::fdc_irq(bool state) void apc_state::fdc_irq(bool state)
{ {
// printf("IRQ %d\n",state); // printf("IRQ %d\n",state);
pic8259_ir3_w(machine().device("pic8259_slave"), state); pic8259_ir3_w(machine().device("pic8259_slave"), state);
} }
@ -628,7 +628,7 @@ WRITE_LINE_MEMBER(apc_state::apc_dma_hrq_changed)
m_dmac->hack_w(state); m_dmac->hack_w(state);
// printf("%02x HLDA\n",state); // printf("%02x HLDA\n",state);
} }
WRITE_LINE_MEMBER( apc_state::apc_tc_w ) WRITE_LINE_MEMBER( apc_state::apc_tc_w )
@ -655,7 +655,7 @@ WRITE8_MEMBER(apc_state::apc_dma_write_byte)
address_space &program = m_maincpu->space(AS_PROGRAM); address_space &program = m_maincpu->space(AS_PROGRAM);
offs_t addr = (m_dma_offset[m_dack] << 16) | offset; offs_t addr = (m_dma_offset[m_dack] << 16) | offset;
// printf("%08x %02x\n",addr,data); // printf("%08x %02x\n",addr,data);
program.write_byte(addr, data); program.write_byte(addr, data);
} }
@ -673,7 +673,7 @@ WRITE_LINE_MEMBER(apc_state::apc_dack3_w){ /*printf("%02x 3\n",state);*/ set_dma
READ8_MEMBER(apc_state::test_r) READ8_MEMBER(apc_state::test_r)
{ {
// printf("2dd DACK R\n"); // printf("2dd DACK R\n");
return m_fdc->dma_r(); return m_fdc->dma_r();
} }
@ -767,8 +767,8 @@ ROM_START( apc )
ROM_LOAD16_BYTE( "pfbu2j.bin", 0x00000, 0x001000, CRC(86970df5) SHA1(be59c5dad3bd8afc21e9f2f1404553d4371978be) ) ROM_LOAD16_BYTE( "pfbu2j.bin", 0x00000, 0x001000, CRC(86970df5) SHA1(be59c5dad3bd8afc21e9f2f1404553d4371978be) )
ROM_LOAD16_BYTE( "pfbu2l.bin", 0x00001, 0x001000, CRC(38df2e70) SHA1(a37ccaea00c2b290610d354de08b489fa897ec48) ) ROM_LOAD16_BYTE( "pfbu2l.bin", 0x00001, 0x001000, CRC(38df2e70) SHA1(a37ccaea00c2b290610d354de08b489fa897ec48) )
// ROM_REGION( 0x10000, "file", ROMREGION_ERASE00 ) // ROM_REGION( 0x10000, "file", ROMREGION_ERASE00 )
// ROM_LOAD( "sioapc.o", 0, 0x10000, CRC(1) SHA1(1) ) // ROM_LOAD( "sioapc.o", 0, 0x10000, CRC(1) SHA1(1) )
ROM_REGION( 0x2000, "gfx", ROMREGION_ERASE00 ) ROM_REGION( 0x2000, "gfx", ROMREGION_ERASE00 )
ROM_LOAD("pfcu1r.bin", 0x000000, 0x002000, CRC(683efa94) SHA1(43157984a1746b2e448f3236f571011af9a3aa73) ) ROM_LOAD("pfcu1r.bin", 0x000000, 0x002000, CRC(683efa94) SHA1(43157984a1746b2e448f3236f571011af9a3aa73) )

2
src/mess/drivers/apple3.c
View File

@ -72,7 +72,7 @@ static MACHINE_CONFIG_START( apple3, apple3_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", M6502, 2000000) /* 2 MHz */ MCFG_CPU_ADD("maincpu", M6502, 2000000) /* 2 MHz */
MCFG_CPU_PROGRAM_MAP(apple3_map) MCFG_CPU_PROGRAM_MAP(apple3_map)
// MCFG_CPU_CONFIG( apple3_m6502_interface ) // MCFG_CPU_CONFIG( apple3_m6502_interface )
MCFG_CPU_PERIODIC_INT_DRIVER(apple3_state, apple3_interrupt, 192) MCFG_CPU_PERIODIC_INT_DRIVER(apple3_state, apple3_interrupt, 192)
MCFG_QUANTUM_TIME(attotime::from_hz(60)) MCFG_QUANTUM_TIME(attotime::from_hz(60))

56
src/mess/drivers/bw2.c
View File

@ -367,16 +367,16 @@ WRITE8_MEMBER( bw2_state::ppi_pa_w )
{ {
/* /*
PA0 KB0 Keyboard line select 0 PA0 KB0 Keyboard line select 0
PA1 KB1 Keyboard line select 1 PA1 KB1 Keyboard line select 1
PA2 KB2 Keyboard line select 2 PA2 KB2 Keyboard line select 2
PA3 KB3 Keyboard line select 3 PA3 KB3 Keyboard line select 3
PA4 /DS0 Drive select 0 PA4 /DS0 Drive select 0
PA5 /DS1 Drive select 1 PA5 /DS1 Drive select 1
PA6 Select RS232 connector PA6 Select RS232 connector
PA7 /STROBE to centronics printer PA7 /STROBE to centronics printer
*/ */
// keyboard // keyboard
m_kb = data & 0x0f; m_kb = data & 0x0f;
@ -398,16 +398,16 @@ READ8_MEMBER( bw2_state::ppi_pb_r )
{ {
/* /*
PB0 Keyboard column status of selected line PB0 Keyboard column status of selected line
PB1 Keyboard column status of selected line PB1 Keyboard column status of selected line
PB2 Keyboard column status of selected line PB2 Keyboard column status of selected line
PB3 Keyboard column status of selected line PB3 Keyboard column status of selected line
PB4 Keyboard column status of selected line PB4 Keyboard column status of selected line
PB5 Keyboard column status of selected line PB5 Keyboard column status of selected line
PB6 Keyboard column status of selected line PB6 Keyboard column status of selected line
PB7 Keyboard column status of selected line PB7 Keyboard column status of selected line
*/ */
static const char *const rownames[] = { "Y0", "Y1", "Y2", "Y3", "Y4", "Y5", "Y6", "Y7", "Y8", "Y9" }; static const char *const rownames[] = { "Y0", "Y1", "Y2", "Y3", "Y4", "Y5", "Y6", "Y7", "Y8", "Y9" };
@ -425,12 +425,12 @@ WRITE8_MEMBER( bw2_state::ppi_pc_w )
{ {
/* /*
PC0 Memory bank select PC0 Memory bank select
PC1 Memory bank select PC1 Memory bank select
PC2 Memory bank select PC2 Memory bank select
PC3 Not connected PC3 Not connected
*/ */
m_bank = data & 0x07; m_bank = data & 0x07;
} }
@ -439,12 +439,12 @@ READ8_MEMBER( bw2_state::ppi_pc_r )
{ {
/* /*
PC4 BUSY from centronics printer PC4 BUSY from centronics printer
PC5 M/FDBK motor feedback PC5 M/FDBK motor feedback
PC6 RLSD Carrier detect from RS232 PC6 RLSD Carrier detect from RS232
PC7 /PROT Write protected disk PC7 /PROT Write protected disk
*/ */
UINT8 data = 0; UINT8 data = 0;

196
src/mess/drivers/ng_aes.c
View File

@ -92,7 +92,7 @@ static UINT8* CDEmuReadQChannel(int NeoCDSectorLBA)
if(neocd.cd == NULL) // no cd is there, bail out if(neocd.cd == NULL) // no cd is there, bail out
return QChannelData; return QChannelData;
// NeoCDSectorLBA // NeoCDSectorLBA
switch (CDEmuStatus) { switch (CDEmuStatus) {
case reading: case reading:
case playing: { case playing: {
@ -252,12 +252,12 @@ static void NeoSetTextSlot(INT32 nSlot)
static void MapVectorTable(bool bMapBoardROM) static void MapVectorTable(bool bMapBoardROM)
{ {
/* /*
if (!bMapBoardROM && Neo68KROMActive) { if (!bMapBoardROM && Neo68KROMActive) {
SekMapMemory(Neo68KFix[nNeoActiveSlot], 0x000000, 0x0003FF, SM_ROM); SekMapMemory(Neo68KFix[nNeoActiveSlot], 0x000000, 0x0003FF, SM_ROM);
} else { } else {
SekMapMemory(NeoVectorActive, 0x000000, 0x0003FF, SM_ROM); SekMapMemory(NeoVectorActive, 0x000000, 0x0003FF, SM_ROM);
} }
*/ */
} }
@ -404,26 +404,26 @@ public:
void ng_aes_state::SekWriteWord(UINT32 a, UINT16 d) void ng_aes_state::SekWriteWord(UINT32 a, UINT16 d)
{ {
// printf("write word %08x %04x\n", a, d); // printf("write word %08x %04x\n", a, d);
curr_space->write_word(a,d); curr_space->write_word(a,d);
} }
void ng_aes_state::SekWriteByte(UINT32 a, UINT8 d) void ng_aes_state::SekWriteByte(UINT32 a, UINT8 d)
{ {
// printf("write byte %08x %02x\n", a, d); // printf("write byte %08x %02x\n", a, d);
curr_space->write_byte(a,d); curr_space->write_byte(a,d);
} }
UINT32 ng_aes_state::SekReadByte(UINT32 a) UINT32 ng_aes_state::SekReadByte(UINT32 a)
{ {
// printf("read byte %08x\n", a); // printf("read byte %08x\n", a);
return curr_space->read_byte(a); return curr_space->read_byte(a);
} }
UINT32 ng_aes_state::SekReadWord(UINT32 a) UINT32 ng_aes_state::SekReadWord(UINT32 a)
{ {
// printf("read WORD %08x\n", a); // printf("read WORD %08x\n", a);
return curr_space->read_word(a); return curr_space->read_word(a);
} }
@ -947,10 +947,10 @@ void ng_aes_state::NeoCDReadSector()
if ((nff0002 & 0x0500)) { if ((nff0002 & 0x0500)) {
if (NeoCDAssyStatus == 1 && bNeoCDLoadSector) { if (NeoCDAssyStatus == 1 && bNeoCDLoadSector) {
// if (LC8951RegistersW[10] & 0x80) { // if (LC8951RegistersW[10] & 0x80) {
NeoCDSectorLBA++; NeoCDSectorLBA++;
NeoCDSectorLBA = CDEmuLoadSector(NeoCDSectorLBA, NeoCDSectorData + 4) -1; NeoCDSectorLBA = CDEmuLoadSector(NeoCDSectorLBA, NeoCDSectorData + 4) -1;
// } // }
if (LC8951RegistersW[10] & 0x80) { if (LC8951RegistersW[10] & 0x80) {
LC8951UpdateHeader(); LC8951UpdateHeader();
@ -960,17 +960,17 @@ void ng_aes_state::NeoCDReadSector()
LC8951RegistersR[14] = 0x10; // STAT2 LC8951RegistersR[14] = 0x10; // STAT2
LC8951RegistersR[15] = 0; // STAT3 LC8951RegistersR[15] = 0; // STAT3
// bprintf(PRINT_IMPORTANT, _T(" Sector %08i (%02i:%02i:%02i) read\n"), NeoCDSectorLBA, NeoCDSectorMin, NeoCDSectorSec, NeoCDSectorFrm); // bprintf(PRINT_IMPORTANT, _T(" Sector %08i (%02i:%02i:%02i) read\n"), NeoCDSectorLBA, NeoCDSectorMin, NeoCDSectorSec, NeoCDSectorFrm);
// CDZ protection hack? (error correction on the CDC should correct this?) // CDZ protection hack? (error correction on the CDC should correct this?)
#if 1 #if 1
if (NeoCDSectorData[4 + 64] == 'g' && !strncmp(NeoCDSectorData + 4, "Copyright by SNK", 16)) { if (NeoCDSectorData[4 + 64] == 'g' && !strncmp(NeoCDSectorData + 4, "Copyright by SNK", 16)) {
// printf(PRINT_ERROR, _T(" simulated CDZ protection error\n")); // printf(PRINT_ERROR, _T(" simulated CDZ protection error\n"));
// bprintf(PRINT_ERROR, _T(" %.70hs\n"), NeoCDSectorData + 4); // bprintf(PRINT_ERROR, _T(" %.70hs\n"), NeoCDSectorData + 4);
NeoCDSectorData[4 + 64] = 'f'; NeoCDSectorData[4 + 64] = 'f';
// LC8951RegistersR[12] = 0x00; // STAT0 // LC8951RegistersR[12] = 0x00; // STAT0
} }
#endif #endif
@ -979,12 +979,12 @@ void ng_aes_state::NeoCDReadSector()
LC8951RegistersR[1] &= ~0x20; LC8951RegistersR[1] &= ~0x20;
// bprintf(PRINT_IMPORTANT, _T(" DECI interrupt triggered\n")); // bprintf(PRINT_IMPORTANT, _T(" DECI interrupt triggered\n"));
} }
} }
bNeoCDLoadSector = true; bNeoCDLoadSector = true;
// bNeoCDLoadSector = false; // bNeoCDLoadSector = false;
} }
} }
@ -992,8 +992,8 @@ void ng_aes_state::NeoCDReadSector()
UINT8 ng_aes_state::neogeoReadTransfer(UINT32 sekAddress, int is_byte_transfer) UINT8 ng_aes_state::neogeoReadTransfer(UINT32 sekAddress, int is_byte_transfer)
{ {
// if ((sekAddress & 0x0FFFFF) < 16) // if ((sekAddress & 0x0FFFFF) < 16)
// printf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (byte, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1)); // printf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (byte, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
sekAddress ^= 1; sekAddress ^= 1;
@ -1019,11 +1019,11 @@ UINT8 ng_aes_state::neogeoReadTransfer(UINT32 sekAddress, int is_byte_transfer)
void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int is_byte_transfer) void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int is_byte_transfer)
{ {
// if ((sekAddress & 0x0FFFFF) < 16) // if ((sekAddress & 0x0FFFFF) < 16)
// bprintf(PRINT_NORMAL, _T(" - Transfer: 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - Transfer: 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
if (!nTransferWriteEnable) { if (!nTransferWriteEnable) {
// return; // return;
} }
int address; int address;
@ -1040,7 +1040,7 @@ void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int i
if ((address&3)==2) NeoSpriteRAM[address^3] = byteValue; if ((address&3)==2) NeoSpriteRAM[address^3] = byteValue;
if ((address&3)==3) NeoSpriteRAM[address] = byteValue; if ((address&3)==3) NeoSpriteRAM[address] = byteValue;
// NeoCDOBJBankUpdate[nSpriteTransferBank >> 20] = true; // NeoCDOBJBankUpdate[nSpriteTransferBank >> 20] = true;
break; break;
case 1: // ADPCM case 1: // ADPCM
YM2610ADPCMAROM[nNeoActiveSlot][nADPCMTransferBank + ((sekAddress & 0x0FFFFF) >> 1)] = byteValue; YM2610ADPCMAROM[nNeoActiveSlot][nADPCMTransferBank + ((sekAddress & 0x0FFFFF) >> 1)] = byteValue;
@ -1058,7 +1058,7 @@ void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int i
break; break;
case 5: // Text case 5: // Text
NeoTextRAM[(sekAddress & 0x3FFFF) >> 1] = byteValue; NeoTextRAM[(sekAddress & 0x3FFFF) >> 1] = byteValue;
// NeoUpdateTextOne((sekAddress & 0x3FFFF) >> 1, byteValue); // NeoUpdateTextOne((sekAddress & 0x3FFFF) >> 1, byteValue);
break; break;
} }
} }
@ -1067,7 +1067,7 @@ void ng_aes_state::neogeoWriteTransfer(UINT32 sekAddress, UINT8 byteValue, int i
UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress) UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
{ {
// bprintf(PRINT_NORMAL, _T(" - CDROM: 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - CDROM: 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
switch (sekAddress & 0xFFFF) { switch (sekAddress & 0xFFFF) {
@ -1077,10 +1077,10 @@ UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
// LC8951 registers // LC8951 registers
case 0x0100: case 0x0100:
// bprintf(PRINT_NORMAL, _T(" - LC8951 register read (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - LC8951 register read (PC: 0x%06X)\n"), SekGetPC(-1));
return nLC8951Register; return nLC8951Register;
case 0x0102: { case 0x0102: {
// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X read (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X read (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
INT32 reg = LC8951RegistersR[nLC8951Register]; INT32 reg = LC8951RegistersR[nLC8951Register];
@ -1108,7 +1108,7 @@ UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
} }
// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X read (word, PC: 0x%06X)\n"), sekAddress, SekGetPC(-1));
return ~0; return ~0;
} }
@ -1116,20 +1116,20 @@ UINT16 ng_aes_state::neogeoReadWordCDROM(UINT32 sekAddress)
void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue) void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
{ {
// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
int byteValue = wordValue & 0xff; int byteValue = wordValue & 0xff;
switch (sekAddress & 0xFFFE) { switch (sekAddress & 0xFFFE) {
case 0x0002: case 0x0002:
// bprintf(PRINT_IMPORTANT, _T(" - NGCD Interrupt mask -> 0x%04X (PC: 0x%06X)\n"), wordValue, SekGetPC(-1)); // bprintf(PRINT_IMPORTANT, _T(" - NGCD Interrupt mask -> 0x%04X (PC: 0x%06X)\n"), wordValue, SekGetPC(-1));
nff0002 = wordValue; nff0002 = wordValue;
// LC8951RegistersR[1] |= 0x20; // LC8951RegistersR[1] |= 0x20;
//if (nff0002 & 0x0500) //if (nff0002 & 0x0500)
// nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0)); // nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
//else //else
// nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0)); // nNeoCDCyclesIRQPeriod = (INT32)(12000000.0 * nBurnCPUSpeedAdjust / (256.0 * 75.0));
break; break;
@ -1182,7 +1182,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
case 0x007E: case 0x007E:
NeoCDDMAMode = wordValue; NeoCDDMAMode = wordValue;
// bprintf(PRINT_NORMAL, _T(" - DMA controller 0x%2X -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0xFF, wordValue, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - DMA controller 0x%2X -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0xFF, wordValue, SekGetPC(-1));
break; break;
// upload DMA controller program // upload DMA controller program
@ -1195,16 +1195,16 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
case 0x008A: case 0x008A:
case 0x008C: case 0x008C:
case 0x008E: case 0x008E:
// bprintf(PRINT_NORMAL, _T(" - DMA controller program[%02i] -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0x0F, wordValue, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - DMA controller program[%02i] -> 0x%04X (PC: 0x%06X)\n"), sekAddress & 0x0F, wordValue, SekGetPC(-1));
break; break;
// LC8951 registers // LC8951 registers
case 0x0100: case 0x0100:
nLC8951Register = byteValue & 0x0F; nLC8951Register = byteValue & 0x0F;
// bprintf(PRINT_NORMAL, _T(" - LC8951 register -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - LC8951 register -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, SekGetPC(-1));
break; break;
case 0x0102: case 0x0102:
// bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, byteValue, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - LC8951 register 0x%X -> 0x%02X (PC: 0x%06X)\n"), nLC8951Register, byteValue, SekGetPC(-1));
switch (nLC8951Register) { switch (nLC8951Register) {
case 3: // DBCH case 3: // DBCH
LC8951RegistersW[ 3] = byteValue & 0x0F; LC8951RegistersW[ 3] = byteValue & 0x0F;
@ -1217,10 +1217,10 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
LC8951RegistersW[ 7] = ~0x00; LC8951RegistersW[ 7] = ~0x00;
LC8951RegistersR[ 1] &= ~0x40; LC8951RegistersR[ 1] &= ~0x40;
break; break;
// case 10: // case 10:
// LC8951RegistersW[nLC8951Register] = byteValue; // LC8951RegistersW[nLC8951Register] = byteValue;
// bprintf(PRINT_NORMAL, _T(" - CTRL0 -> %02X (PC: 0x%06X)\n"), LC8951RegistersW[nLC8951Register], byteValue, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - CTRL0 -> %02X (PC: 0x%06X)\n"), LC8951RegistersW[nLC8951Register], byteValue, SekGetPC(-1));
// break; // break;
case 11: case 11:
LC8951RegistersW[11] = byteValue; // CTRL1 LC8951RegistersW[11] = byteValue; // CTRL1
LC8951UpdateHeader(); LC8951UpdateHeader();
@ -1235,43 +1235,43 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
break; break;
case 0x0104: case 0x0104:
// bprintf(PRINT_NORMAL, _T(" - NGCD 0xE00000 area -> 0x%02X (PC: 0x%06X)\n"), byteValue, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD 0xE00000 area -> 0x%02X (PC: 0x%06X)\n"), byteValue, SekGetPC(-1));
nActiveTransferArea = byteValue; nActiveTransferArea = byteValue;
break; break;
case 0x0120: case 0x0120:
// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
NeoSetSpriteSlot(1); NeoSetSpriteSlot(1);
memset(NeoCDOBJBankUpdate, 0, sizeof(NeoCDOBJBankUpdate)); memset(NeoCDOBJBankUpdate, 0, sizeof(NeoCDOBJBankUpdate));
break; break;
case 0x0122: case 0x0122:
// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 1 (PC: 0x%06X) %x\n"), SekGetPC(-1), byteValue); // bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 1 (PC: 0x%06X) %x\n"), SekGetPC(-1), byteValue);
break; break;
case 0x0126: case 0x0126:
// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
curr_space->machine().scheduler().synchronize(); curr_space->machine().scheduler().synchronize();
curr_space->machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE); curr_space->machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
break; break;
case 0x0128: case 0x0128:
// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 1 (PC: 0x%06X)\n"), SekGetPC(-1));
NeoSetTextSlot(1); NeoSetTextSlot(1);
break; break;
case 0x0140: case 0x0140:
// bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD OBJ BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
video_reset(); video_reset();
break; break;
case 0x0142: case 0x0142:
// bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD PCM BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
break; break;
case 0x0146: case 0x0146:
// bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD Z80 BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
curr_space->machine().scheduler().synchronize(); curr_space->machine().scheduler().synchronize();
curr_space->machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_HALT, CLEAR_LINE); curr_space->machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
break; break;
case 0x0148: case 0x0148:
// bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD FIX BUSREQ -> 0 (PC: 0x%06X)\n"), SekGetPC(-1));
video_reset(); video_reset();
break; break;
@ -1284,7 +1284,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
break; break;
case 0x016c: case 0x016c:
// bprintf(PRINT_ERROR, _T(" - NGCD port 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1)); // bprintf(PRINT_ERROR, _T(" - NGCD port 0x%06X -> 0x%02X (PC: 0x%06X)\n"), sekAddress, byteValue, SekGetPC(-1));
MapVectorTable(!(byteValue == 0xFF)); MapVectorTable(!(byteValue == 0xFF));
@ -1293,7 +1293,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
break; break;
case 0x016e: case 0x016e:
// bprintf(PRINT_IMPORTANT, _T(" - NGCD 0xE00000 area write access %s (0x%02X, PC: 0x%06X)\n"), byteValue ? _T("enabled") : _T("disabled"), byteValue, SekGetPC(-1)); // bprintf(PRINT_IMPORTANT, _T(" - NGCD 0xE00000 area write access %s (0x%02X, PC: 0x%06X)\n"), byteValue ? _T("enabled") : _T("disabled"), byteValue, SekGetPC(-1));
nTransferWriteEnable = byteValue; nTransferWriteEnable = byteValue;
break; break;
@ -1301,8 +1301,8 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
case 0x0180: { case 0x0180: {
static UINT8 clara = 0; static UINT8 clara = 0;
if (!byteValue && clara) { if (!byteValue && clara) {
// bprintf(PRINT_IMPORTANT, _T(" - NGCD CD communication reset (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_IMPORTANT, _T(" - NGCD CD communication reset (PC: 0x%06X)\n"), SekGetPC(-1));
// NeoCDCommsReset(); // NeoCDCommsReset();
} }
clara = byteValue; clara = byteValue;
break; break;
@ -1310,7 +1310,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
case 0x0182: { case 0x0182: {
static UINT8 clara = 0; static UINT8 clara = 0;
if (!byteValue && clara) { if (!byteValue && clara) {
// bprintf(PRINT_IMPORTANT, _T(" - NGCD Z80 reset (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_IMPORTANT, _T(" - NGCD Z80 reset (PC: 0x%06X)\n"), SekGetPC(-1));
//ZetReset(); //ZetReset();
} }
clara = byteValue; clara = byteValue;
@ -1325,7 +1325,7 @@ void ng_aes_state::neogeoWriteWordCDROM(UINT32 sekAddress, UINT16 wordValue)
default: { default: {
// bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1)); // bprintf(PRINT_NORMAL, _T(" - NGCD port 0x%06X -> 0x%04X (PC: 0x%06X)\n"), sekAddress, wordValue, SekGetPC(-1));
} }
} }
@ -1394,12 +1394,12 @@ void ng_aes_state::NeoCDDoDMA()
// Here, only bus access is used to get a rough approximation -- // Here, only bus access is used to get a rough approximation --
// each read/write takes a single cycle, setup and everything else is ignored. // each read/write takes a single cycle, setup and everything else is ignored.
// bprintf(PRINT_IMPORTANT, _T(" - DMA controller transfer started (PC: 0x%06X)\n"), SekGetPC(-1)); // bprintf(PRINT_IMPORTANT, _T(" - DMA controller transfer started (PC: 0x%06X)\n"), SekGetPC(-1));
switch (NeoCDDMAMode) { switch (NeoCDDMAMode) {
case 0xCFFD: { case 0xCFFD: {
// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 8); // bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 8);
// - DMA controller 0x7E -> 0xCFFD (PC: 0xC07CE2) // - DMA controller 0x7E -> 0xCFFD (PC: 0xC07CE2)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8) // - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
@ -1425,7 +1425,7 @@ void ng_aes_state::NeoCDDoDMA()
} }
case 0xE2DD: { case 0xE2DD: {
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X, skip odd bytes\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4); // bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X, skip odd bytes\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// - DMA controller 0x7E -> 0xE2DD (PC: 0xC0A190) // - DMA controller 0x7E -> 0xE2DD (PC: 0xC0A190)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192) // - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
@ -1450,7 +1450,7 @@ void ng_aes_state::NeoCDDoDMA()
} }
case 0xFC2D: { case 0xFC2D: {
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4); // bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer, skip odd bytes\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// - DMA controller 0x7E -> 0xFC2D (PC: 0xC0A190) // - DMA controller 0x7E -> 0xFC2D (PC: 0xC0A190)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192) // - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
@ -1494,7 +1494,7 @@ void ng_aes_state::NeoCDDoDMA()
// - DMA controller program[14] -> 0xFCF5 (PC: 0xC0A1A0) // - DMA controller program[14] -> 0xFCF5 (PC: 0xC0A1A0)
case 0xFE6D: { case 0xFE6D: {
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2); // bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- 0x%08X - 0x%08X\n"), NeoCDDMAAddress2, NeoCDDMAAddress2 + NeoCDDMACount * 2, NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
// - DMA controller 0x7E -> 0xFE6D (PC: 0xC0FD7A) // - DMA controller 0x7E -> 0xFE6D (PC: 0xC0FD7A)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0FD7C) // - DMA controller program[00] -> 0xFCF5 (PC: 0xC0FD7C)
@ -1516,15 +1516,15 @@ void ng_aes_state::NeoCDDoDMA()
if (NeoCDDMAAddress2 == 0x0800) { if (NeoCDDMAAddress2 == 0x0800) {
// MapVectorTable(false); // MapVectorTable(false);
// bprintf(PRINT_ERROR, _T(" RAM vectors mapped (PC = 0x%08X\n"), SekGetPC(0)); // bprintf(PRINT_ERROR, _T(" RAM vectors mapped (PC = 0x%08X\n"), SekGetPC(0));
// extern INT32 bRunPause; // extern INT32 bRunPause;
// bRunPause = 1; // bRunPause = 1;
} }
break; break;
} }
case 0xFEF5: { case 0xFEF5: {
// bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4); // bprintf(PRINT_NORMAL, _T(" adr : 0x%08X - 0x%08X <- address\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 4);
// - DMA controller 0x7E -> 0xFEF5 (PC: 0xC07CE2) // - DMA controller 0x7E -> 0xFEF5 (PC: 0xC07CE2)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8) // - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
@ -1548,7 +1548,7 @@ if (NeoCDDMAAddress2 == 0x0800) {
} }
case 0xFFC5: { case 0xFFC5: {
// bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2); // bprintf(PRINT_NORMAL, _T(" copy: 0x%08X - 0x%08X <- LC8951 external buffer\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2);
// - DMA controller 0x7E -> 0xFFC5 (PC: 0xC0A190) // - DMA controller 0x7E -> 0xFFC5 (PC: 0xC0A190)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192) // - DMA controller program[00] -> 0xFCF5 (PC: 0xC0A192)
@ -1592,7 +1592,7 @@ if (NeoCDDMAAddress2 == 0x0800) {
// - DMA controller program[14] -> 0x13FC (PC: 0xC0A1A0) // - DMA controller program[14] -> 0x13FC (PC: 0xC0A1A0)
case 0xFFDD: { case 0xFFDD: {
// bprintf(PRINT_NORMAL, _T(" Fill: 0x%08X - 0x%08X <- 0x%04X\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2, NeoCDDMAValue1); // bprintf(PRINT_NORMAL, _T(" Fill: 0x%08X - 0x%08X <- 0x%04X\n"), NeoCDDMAAddress1, NeoCDDMAAddress1 + NeoCDDMACount * 2, NeoCDDMAValue1);
// - DMA controller 0x7E -> 0xFFDD (PC: 0xC07CE2) // - DMA controller 0x7E -> 0xFFDD (PC: 0xC07CE2)
// - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8) // - DMA controller program[00] -> 0xFCF5 (PC: 0xC07CE8)
@ -1637,14 +1637,14 @@ void ng_aes_state::NeoCDProcessCommand()
case 0: case 0:
break; break;
case 1: case 1:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]); // //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
CDEmuStop(); CDEmuStop();
NeoCDAssyStatus = 0x0E; NeoCDAssyStatus = 0x0E;
bNeoCDLoadSector = false; bNeoCDLoadSector = false;
break; break;
case 2: case 2:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]); // //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDCommsStatusFIFO[1] = NeoCDCommsCommandFIFO[3]; NeoCDCommsStatusFIFO[1] = NeoCDCommsCommandFIFO[3];
switch (NeoCDCommsCommandFIFO[3]) { switch (NeoCDCommsCommandFIFO[3]) {
@ -1786,7 +1786,7 @@ void ng_aes_state::NeoCDProcessCommand()
NeoCDSectorLBA -= CD_FRAMES_PREGAP; NeoCDSectorLBA -= CD_FRAMES_PREGAP;
CDEmuStartRead(); CDEmuStartRead();
// LC8951RegistersR[1] |= 0x20; // LC8951RegistersR[1] |= 0x20;
} else { } else {
if (CDEmuGetStatus() == reading) { if (CDEmuGetStatus() == reading) {
@ -1802,22 +1802,22 @@ void ng_aes_state::NeoCDProcessCommand()
break; break;
} }
case 4: case 4:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]); // //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
CDEmuPause(); CDEmuPause();
break; break;
case 5: case 5:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]); // //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
// NeoCDAssyStatus = 9; // NeoCDAssyStatus = 9;
// bNeoCDLoadSector = false; // bNeoCDLoadSector = false;
break; break;
case 6: case 6:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]); // //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDAssyStatus = 4; NeoCDAssyStatus = 4;
bNeoCDLoadSector = false; bNeoCDLoadSector = false;
break; break;
case 7: case 7:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]); // //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDAssyStatus = 1; NeoCDAssyStatus = 1;
bNeoCDLoadSector = true; bNeoCDLoadSector = true;
break; break;
@ -1830,7 +1830,7 @@ void ng_aes_state::NeoCDProcessCommand()
case 13: case 13:
case 14: case 14:
case 15: case 15:
// //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]); // //bprintf(PRINT_ERROR, _T(" CD comms received command %i\n"), NeoCDCommsCommandFIFO[0]);
NeoCDAssyStatus = 9; NeoCDAssyStatus = 9;
bNeoCDLoadSector = false; bNeoCDLoadSector = false;
break; break;
@ -1853,13 +1853,13 @@ void ng_aes_state::NeoCDCommsControl(UINT8 clock, UINT8 send)
printf("has command %02x\n", NeoCDCommsCommandFIFO[0]); printf("has command %02x\n", NeoCDCommsCommandFIFO[0]);
// bprintf(PRINT_NORMAL, _T(" - CD mechanism command receive completed : 0x")); // bprintf(PRINT_NORMAL, _T(" - CD mechanism command receive completed : 0x"));
for (INT32 i = 0; i < 9; i++) { for (INT32 i = 0; i < 9; i++) {
// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsCommandFIFO[i]); // bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsCommandFIFO[i]);
sum += NeoCDCommsCommandFIFO[i]; sum += NeoCDCommsCommandFIFO[i];
} }
sum = ~(sum + 5) & 0x0F; sum = ~(sum + 5) & 0x0F;
// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsCommandFIFO[9], (sum == NeoCDCommsCommandFIFO[9]) ? _T("OK") : _T("NG")); // bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsCommandFIFO[9], (sum == NeoCDCommsCommandFIFO[9]) ? _T("OK") : _T("NG"));
if (sum == NeoCDCommsCommandFIFO[9]) { if (sum == NeoCDCommsCommandFIFO[9]) {
printf("request to process command %02x\n", NeoCDCommsCommandFIFO[0]); printf("request to process command %02x\n", NeoCDCommsCommandFIFO[0]);
@ -1892,21 +1892,21 @@ void ng_aes_state::NeoCDCommsControl(UINT8 clock, UINT8 send)
// status send complete // status send complete
// if (NeoCDCommsStatusFIFO[0] || NeoCDCommsStatusFIFO[1]) { // if (NeoCDCommsStatusFIFO[0] || NeoCDCommsStatusFIFO[1]) {
// INT32 sum = 0; // INT32 sum = 0;
// //
// bprintf(PRINT_NORMAL, _T(" - CD mechanism status send completed : 0x")); // bprintf(PRINT_NORMAL, _T(" - CD mechanism status send completed : 0x"));
// for (INT32 i = 0; i < 9; i++) { // for (INT32 i = 0; i < 9; i++) {
// bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsStatusFIFO[i]); // bprintf(PRINT_NORMAL, _T("%X"), NeoCDCommsStatusFIFO[i]);
// sum += NeoCDCommsStatusFIFO[i]; // sum += NeoCDCommsStatusFIFO[i];
// } // }
// sum = ~(sum + 5) & 0x0F; // sum = ~(sum + 5) & 0x0F;
// bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsStatusFIFO[9], (sum == NeoCDCommsStatusFIFO[9]) ? _T("OK") : _T("NG")); // bprintf(PRINT_NORMAL, _T(" (CS 0x%X, %s)\n"), NeoCDCommsStatusFIFO[9], (sum == NeoCDCommsStatusFIFO[9]) ? _T("OK") : _T("NG"));
// } // }
// if (NeoCDAssyStatus == 0xE) { // if (NeoCDAssyStatus == 0xE) {
// NeoCDAssyStatus = 9; // NeoCDAssyStatus = 9;
// } // }
} }
} }
@ -2426,10 +2426,10 @@ static ADDRESS_MAP_START( neocd_audio_io_map, AS_IO, 8, ng_aes_state )
AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READ(audio_command_r) AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_READ(audio_command_r)
AM_RANGE(0x04, 0x07) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY("ymsnd", ym2610_r, ym2610_w) AM_RANGE(0x04, 0x07) AM_MIRROR(0xff00) AM_DEVREADWRITE_LEGACY("ymsnd", ym2610_r, ym2610_w)
AM_RANGE(0x08, 0x08) AM_MIRROR(0xff00) /* write - NMI enable / acknowledge? (the data written doesn't matter) */ AM_RANGE(0x08, 0x08) AM_MIRROR(0xff00) /* write - NMI enable / acknowledge? (the data written doesn't matter) */
// AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_f000_f7ff_r) // AM_RANGE(0x08, 0x08) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_f000_f7ff_r)
// AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_e000_efff_r) // AM_RANGE(0x09, 0x09) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_e000_efff_r)
// AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_c000_dfff_r) // AM_RANGE(0x0a, 0x0a) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_c000_dfff_r)
// AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_8000_bfff_r) // AM_RANGE(0x0b, 0x0b) AM_MIRROR(0xfff0) AM_MASK(0xfff0) AM_READ(audio_cpu_bank_select_8000_bfff_r)
AM_RANGE(0x0c, 0x0c) AM_MIRROR(0xff00) AM_WRITE(audio_result_w) AM_RANGE(0x0c, 0x0c) AM_MIRROR(0xff00) AM_WRITE(audio_result_w)
AM_RANGE(0x18, 0x18) AM_MIRROR(0xff00) /* write - NMI disable? (the data written doesn't matter) */ AM_RANGE(0x18, 0x18) AM_MIRROR(0xff00) /* write - NMI disable? (the data written doesn't matter) */
ADDRESS_MAP_END ADDRESS_MAP_END

64
src/mess/drivers/pc100.c
View File

@ -2,8 +2,8 @@
NEC PC-100 NEC PC-100
preliminary driver by Angelo Salese preliminary driver by Angelo Salese
Thanks to Carl for the i8259 tip; Thanks to Carl for the i8259 tip;
TODO: TODO:
- floppy support (no images available right now); - floppy support (no images available right now);
@ -20,33 +20,33 @@
F8216: FA cli F8216: FA cli
F8217: 0A E9 or ch,cl F8217: 0A E9 or ch,cl
F8219: 74 15 je 0F8230h F8219: 74 15 je 0F8230h
- Second one is for the vblank irq timing: - Second one is for the vblank irq timing:
F8238: 8B D3 mov dx,bx F8238: 8B D3 mov dx,bx
F823A: 8B D9 mov bx,cx F823A: 8B D9 mov bx,cx
F823C: CF iret F823C: CF iret
F824D: E4 02 in al,2h F824D: E4 02 in al,2h
F824F: 8A E0 mov ah,al F824F: 8A E0 mov ah,al
F8251: B0 EF mov al,0EFh F8251: B0 EF mov al,0EFh
F8253: E6 02 out 2h,al F8253: E6 02 out 2h,al
F8255: BB 00 00 mov bx,0h F8255: BB 00 00 mov bx,0h
F8258: BA 00 00 mov dx,0h F8258: BA 00 00 mov dx,0h
F825B: B9 20 4E mov cx,4E20h F825B: B9 20 4E mov cx,4E20h
F825E: FB sti F825E: FB sti
F825F: E2 FE loop 0F825Fh ;calculates the vblank here F825F: E2 FE loop 0F825Fh ;calculates the vblank here
F8261: FA cli F8261: FA cli
F8262: 8A C4 mov al,ah F8262: 8A C4 mov al,ah
F8264: E6 02 out 2h,al F8264: E6 02 out 2h,al
F8266: 2B D3 sub dx,bx F8266: 2B D3 sub dx,bx
F8268: 81 FA 58 1B cmp dx,1B58h F8268: 81 FA 58 1B cmp dx,1B58h
F826C: 78 06 js 0F8274h ;error if DX is smaller than 0x1b58 F826C: 78 06 js 0F8274h ;error if DX is smaller than 0x1b58
F826E: 81 FA 40 1F cmp dx,1F40h F826E: 81 FA 40 1F cmp dx,1F40h
F8272: 78 0A js 0F827Eh ;error if DX is greater than 0x1f40 F8272: 78 0A js 0F827Eh ;error if DX is greater than 0x1f40
F8274: B1 05 mov cl,5h F8274: B1 05 mov cl,5h
F8276: E8 CB 03 call 0F8644h F8276: E8 CB 03 call 0F8644h
F8279: E8 79 FF call 0F81F5h F8279: E8 79 FF call 0F81F5h
F827C: EB FE jmp 0F827Ch F827C: EB FE jmp 0F827Ch
F827E: B0 FF mov al,0FFh F827E: B0 FF mov al,0FFh
fwiw with current timings, we get DX=0x1f09, enough for passing the test; fwiw with current timings, we get DX=0x1f09, enough for passing the test;
****************************************************************************/ ****************************************************************************/
@ -352,9 +352,9 @@ GFXDECODE_END
WRITE8_MEMBER( pc100_state::rtc_porta_w ) WRITE8_MEMBER( pc100_state::rtc_porta_w )
{ {
/* /*
---- -x-- chip select ---- -x-- chip select
---- --x- read ---- --x- read
---- ---x write ---- ---x write
*/ */
m_rtc->write_w(data & 1); m_rtc->write_w(data & 1);

2
src/mess/drivers/pc9801.c
View File

@ -9,7 +9,7 @@
- proper 8251 uart hook-up on keyboard - proper 8251 uart hook-up on keyboard
- boot is too slow right now, might be due of the floppy / HDD devices - boot is too slow right now, might be due of the floppy / HDD devices
- investigate on POR bit - investigate on POR bit
- Write a PC80S31K device (also used on PC-8801 and PC-88VA, it's the FDC + Z80 sub-system); - Write a PC80S31K device (also used on PC-8801 and PC-88VA, it's the FDC + Z80 sub-system);
TODO (PC-9801RS): TODO (PC-9801RS):
- floppy disk hook-up; - floppy disk hook-up;

68
src/mess/machine/adam_ddp.c
View File

@ -166,18 +166,18 @@ WRITE8_MEMBER( adam_digital_data_pack_device::p1_w )
{ {
/* /*
bit description bit description
0 SPD SEL (0=20 ips, 1=80ips) 0 SPD SEL (0=20 ips, 1=80ips)
1 STOP0 1 STOP0
2 STOP1 2 STOP1
3 _GO FWD 3 _GO FWD
4 _GO REV 4 _GO REV
5 BRAKE 5 BRAKE
6 _WR0 6 _WR0
7 _WR1 7 _WR1
*/ */
if (m_ddp0->exists()) if (m_ddp0->exists())
{ {
@ -211,15 +211,15 @@ READ8_MEMBER( adam_digital_data_pack_device::p2_r )
{ {
/* /*
bit description bit description
0 mode bit 0 0 mode bit 0
1 mode bit 1 / CIP1 1 mode bit 1 / CIP1
2 mode bit 2 2 mode bit 2
3 NET RXD 3 NET RXD
4 4
*/ */
UINT8 data = 0; UINT8 data = 0;
@ -243,15 +243,15 @@ WRITE8_MEMBER( adam_digital_data_pack_device::p2_w )
{ {
/* /*
bit description bit description
0 WRT DATA 0 WRT DATA
1 1
2 TRACK A/B (0=B, 1=A) 2 TRACK A/B (0=B, 1=A)
3 3
4 NET TXD 4 NET TXD
*/ */
if (m_ddp0->exists()) if (m_ddp0->exists())
{ {
@ -278,18 +278,18 @@ READ8_MEMBER( adam_digital_data_pack_device::p4_r )
{ {
/* /*
bit description bit description
0 A8 0 A8
1 A9 1 A9
2 A10 (2114 _S) 2 A10 (2114 _S)
3 MSENSE 0 3 MSENSE 0
4 MSENSE 1 4 MSENSE 1
5 CIP0 5 CIP0
6 RD DATA 0 (always 1) 6 RD DATA 0 (always 1)
7 RD DATA 1 (data from drives ORed together) 7 RD DATA 1 (data from drives ORed together)
*/ */
UINT8 data = 0; UINT8 data = 0;

68
src/mess/machine/adam_fdc.c
View File

@ -215,18 +215,18 @@ READ8_MEMBER( adam_fdc_device::p1_r )
{ {
/* /*
bit description bit description
0 disk in place 0 disk in place
1 1
2 FDC DRQ 2 FDC DRQ
3 3
4 4
5 5
6 6
7 SW3 (0=DS1, 1=DS2) 7 SW3 (0=DS1, 1=DS2)
*/ */
UINT8 data = 0; UINT8 data = 0;
@ -251,18 +251,18 @@ WRITE8_MEMBER( adam_fdc_device::p1_w )
{ {
/* /*
bit description bit description
0 0
1 FDC ENP 1 FDC ENP
2 2
3 FDC _DDEN 3 FDC _DDEN
4 4
5 DRIVE SELECT 5 DRIVE SELECT
6 MOTOR ON 6 MOTOR ON
7 7
*/ */
// write precompensation // write precompensation
//m_fdc->enp_w(BIT(data, 1)); //m_fdc->enp_w(BIT(data, 1));
@ -293,15 +293,15 @@ READ8_MEMBER( adam_fdc_device::p2_r )
{ {
/* /*
bit description bit description
0 mode bit 0 0 mode bit 0
1 mode bit 1 1 mode bit 1
2 mode bit 2 2 mode bit 2
3 NET RXD 3 NET RXD
4 4
*/ */
UINT8 data = M6801_MODE_2; UINT8 data = M6801_MODE_2;
@ -320,15 +320,15 @@ WRITE8_MEMBER( adam_fdc_device::p2_w )
{ {
/* /*
bit description bit description
0 0
1 1
2 2
3 3
4 NET TXD 4 NET TXD
*/ */
m_bus->txd_w(this, BIT(data, 4)); m_bus->txd_w(this, BIT(data, 4));
} }

28
src/mess/machine/adam_ide.c
View File

@ -9,11 +9,11 @@
/* /*
TODO: TODO:
- parallel status port - parallel status port
- memory bank switching port - memory bank switching port
- boot ROM - boot ROM
*/ */
@ -127,18 +127,18 @@ UINT8 powermate_ide_device::adam_bd_r(address_space &space, offs_t offset, UINT8
case 0x40: // Printer status case 0x40: // Printer status
/* /*
bit description bit description
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
*/ */
break; break;
case 0x58: case 0x58:

88
src/mess/machine/adam_kb.c
View File

@ -261,18 +261,18 @@ READ8_MEMBER( adam_keyboard_device::p1_r )
{ {
/* /*
bit description bit description
0 X0 0 X0
1 X1 1 X1
2 X2 2 X2
3 X3 3 X3
4 X4 4 X4
5 X5 5 X5
6 X6 6 X6
7 X7 7 X7
*/ */
UINT8 data = 0xff; UINT8 data = 0xff;
@ -302,15 +302,15 @@ READ8_MEMBER( adam_keyboard_device::p2_r )
{ {
/* /*
bit description bit description
0 mode bit 0 0 mode bit 0
1 mode bit 1 1 mode bit 1
2 mode bit 2 2 mode bit 2
3 NET RXD 3 NET RXD
4 4
*/ */
UINT8 data = M6801_MODE_7; UINT8 data = M6801_MODE_7;
@ -329,15 +329,15 @@ WRITE8_MEMBER( adam_keyboard_device::p2_w )
{ {
/* /*
bit description bit description
0 0
1 1
2 2
3 3
4 NET TXD 4 NET TXD
*/ */
m_bus->txd_w(this, BIT(data, 4)); m_bus->txd_w(this, BIT(data, 4));
} }
@ -361,18 +361,18 @@ WRITE8_MEMBER( adam_keyboard_device::p3_w )
{ {
/* /*
bit description bit description
0 Y0 0 Y0
1 Y1 1 Y1
2 Y2 2 Y2
3 Y3 3 Y3
4 Y4 4 Y4
5 Y5 5 Y5
6 Y6 6 Y6
7 Y7 7 Y7
*/ */
m_key_y = (m_key_y & 0x1f00) | data; m_key_y = (m_key_y & 0x1f00) | data;
} }
@ -396,18 +396,18 @@ WRITE8_MEMBER( adam_keyboard_device::p4_w )
{ {
/* /*
bit description bit description
0 Y8 0 Y8
1 Y9 1 Y9
2 Y10 2 Y10
3 Y11 3 Y11
4 Y12 4 Y12
5 5
6 6
7 7
*/ */
m_key_y = ((data & 0x1f) << 8) | (m_key_y & 0xff); m_key_y = ((data & 0x1f) << 8) | (m_key_y & 0xff);
} }

88
src/mess/machine/adam_prn.c
View File

@ -136,18 +136,18 @@ WRITE8_MEMBER( adam_printer_device::p1_w )
{ {
/* /*
bit description bit description
0 M2 phase D 0 M2 phase D
1 M2 phase B 1 M2 phase B
2 M2 phase C 2 M2 phase C
3 M2 phase A 3 M2 phase A
4 M3 phase B 4 M3 phase B
5 M3 phase D 5 M3 phase D
6 M3 phase A 6 M3 phase A
7 M3 phase C 7 M3 phase C
*/ */
} }
@ -159,15 +159,15 @@ READ8_MEMBER( adam_printer_device::p2_r )
{ {
/* /*
bit description bit description
0 mode bit 0 0 mode bit 0
1 mode bit 1 1 mode bit 1
2 mode bit 2 2 mode bit 2
3 NET RXD 3 NET RXD
4 NET TXD 4 NET TXD
*/ */
UINT8 data = M6801_MODE_7; UINT8 data = M6801_MODE_7;
@ -186,15 +186,15 @@ WRITE8_MEMBER( adam_printer_device::p2_w )
{ {
/* /*
bit description bit description
0 mode bit 0 0 mode bit 0
1 mode bit 1 1 mode bit 1
2 mode bit 2 2 mode bit 2
3 NET RXD 3 NET RXD
4 NET TXD 4 NET TXD
*/ */
m_bus->txd_w(this, BIT(data, 4)); m_bus->txd_w(this, BIT(data, 4));
} }
@ -218,18 +218,18 @@ READ8_MEMBER( adam_printer_device::p4_r )
{ {
/* /*
bit description bit description
0 0
1 1
2 2
3 3
4 left margin 4 left margin
5 platen detent 5 platen detent
6 wheel home 6 wheel home
7 self-test 7 self-test
*/ */
return 0x80; return 0x80;
} }
@ -243,16 +243,16 @@ WRITE8_MEMBER( adam_printer_device::p4_w )
{ {
/* /*
bit description bit description
0 print hammer solenoid 0 print hammer solenoid
1 ribbon advance solenoid 1 ribbon advance solenoid
2 platen motor advance 2 platen motor advance
3 platen motor break 3 platen motor break
4 4
5 5
6 6
7 7
*/ */
} }

28
src/mess/machine/adam_spi.c
View File

@ -134,15 +134,15 @@ READ8_MEMBER( adam_spi_device::p2_r )
{ {
/* /*
bit description bit description
0 mode bit 0 0 mode bit 0
1 mode bit 1 1 mode bit 1
2 mode bit 2 2 mode bit 2
3 NET RXD 3 NET RXD
4 4
*/ */
UINT8 data = M6801_MODE_7; UINT8 data = M6801_MODE_7;
@ -161,15 +161,15 @@ WRITE8_MEMBER( adam_spi_device::p2_w )
{ {
/* /*
bit description bit description
0 0
1 1
2 2
3 3
4 NET TXD 4 NET TXD
*/ */
m_bus->txd_w(this, BIT(data, 4)); m_bus->txd_w(this, BIT(data, 4));
} }

2
src/version.c
View File

@ -38,4 +38,4 @@
***************************************************************************/ ***************************************************************************/
extern const char build_version[]; extern const char build_version[];
const char build_version[] = "0.147u2 ("__DATE__")"; const char build_version[] = "0.147u3 ("__DATE__")";