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https://github.com/holub/mame
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dp8344: Disable side effects with certain opcodes; implement halt on reset (nw)
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AJR
parent
02d79dc882
commit
88238e2d61
@ -305,6 +305,8 @@ void dp8344_device::device_reset()
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// Reset Remote Interface Configuration Register
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m_ric = m_auto_start ? 0x03 : 0x01;
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m_hib = false;
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if (!m_auto_start)
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suspend(SUSPEND_REASON_HALT, true);
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// Reset execution state
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m_nmi_pending = false;
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@ -799,13 +801,12 @@ void dp8344_device::data_stack_push(u8 data)
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u8 dp8344_device::data_stack_pop()
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{
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// TBD: do test instructions (BIT, CMP, JRMK, etc.) suppress side effects as with RTR and ECR?
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m_dsp = (m_dsp - 1) & 0xf;
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return m_ds[m_dsp];
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}
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//**************************************************************************
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// TRANSCEIVER OPERATION
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//**************************************************************************
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@ -943,16 +944,20 @@ void dp8344_device::receive_fifo_push(u8 data)
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// receive_fifo_pop - read from RTR
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//-------------------------------------------------
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u8 dp8344_device::receive_fifo_pop()
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u8 dp8344_device::receive_fifo_pop(bool test)
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{
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// Clear Receive FIFO Full, DEME, Auto-Response and Poll/Acknowledge bits in NCF
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m_ncf &= 0xb0;
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if (!test)
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{
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// Clear Receive FIFO Full, DEME, Auto-Response and Poll/Acknowledge bits in NCF
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m_ncf &= 0xb0;
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// Clear Data Available flag in TSR
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m_tsr &= 0xf7;
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if ((m_icr & 0xc0) == 0xc0)
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set_receiver_interrupt(false);
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// Clear Data Available flag in TSR
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m_tsr &= 0xf7;
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if ((m_icr & 0xc0) == 0xc0)
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set_receiver_interrupt(false);
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}
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// TODO
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return 0;
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}
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@ -984,29 +989,32 @@ void dp8344_device::set_receiver_error(u8 code)
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// get_error_code - read from ECR
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//-------------------------------------------------
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u8 dp8344_device::get_error_code()
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u8 dp8344_device::get_error_code(bool test)
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{
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u8 code = m_ecr;
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// Clear Error Code Register and Receiver Error flag in NCF
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m_ecr = 0x00;
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m_ncf &= 0xdf;
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// Update interrupt status if RE interrupt selected
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switch (m_icr & 0xc0)
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if (!test)
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{
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case 0x00:
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// Interrupt on RFF
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set_receiver_interrupt(BIT(m_ncf, 6));
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break;
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// Clear Error Code Register and Receiver Error flag in NCF
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m_ecr = 0x00;
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m_ncf &= 0xdf;
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case 0x40:
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// Interrupt on DAV
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set_receiver_interrupt(BIT(m_tsr, 3));
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break;
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// Update interrupt status if RE interrupt selected
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switch (m_icr & 0xc0)
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{
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case 0x00:
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// Interrupt on RFF
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set_receiver_interrupt(BIT(m_ncf, 6));
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break;
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default:
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break;
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case 0x40:
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// Interrupt on DAV
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set_receiver_interrupt(BIT(m_tsr, 3));
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break;
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default:
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break;
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}
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}
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return code;
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@ -1106,7 +1114,7 @@ void dp8344_device::clear_network_command_flag(u8 data)
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// read_register - read from source register
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//-------------------------------------------------
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u8 dp8344_device::read_register(unsigned reg)
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u8 dp8344_device::read_register(unsigned reg, bool test)
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{
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switch (reg)
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{
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@ -1136,7 +1144,7 @@ u8 dp8344_device::read_register(unsigned reg)
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case 4: // GP0 (main) or Receive/Transmit Register and/or Error Code Register (alternate)
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if (m_bb)
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return BIT(m_tcr, 6) ? get_error_code() : receive_fifo_pop();
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return BIT(m_tcr, 6) ? get_error_code(test) : receive_fifo_pop(test);
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else
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return m_gp_main[0];
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@ -1522,7 +1530,7 @@ dp8344_device::inst_state dp8344_device::decode_instruction()
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{
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if (m_latched_instr < 0x8000)
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{
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m_source_data = read_register(m_latched_instr & 0x000f);
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m_source_data = read_register(m_latched_instr & 0x000f, (m_latched_instr & 0x7000) == 0x3000);
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if ((m_latched_instr & 0xf000) == 0x1000)
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{
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// MOVE to indexed data memory
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@ -1538,7 +1546,7 @@ dp8344_device::inst_state dp8344_device::decode_instruction()
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else if ((m_latched_instr & 0xf800) == 0x8000)
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{
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// JRMK
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m_source_data = read_register(m_latched_instr & 0x001f);
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m_source_data = read_register(m_latched_instr & 0x001f, true);
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return TX1_JRMK;
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}
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else if ((m_latched_instr & 0xfc00) == 0x8800)
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@ -1551,7 +1559,7 @@ dp8344_device::inst_state dp8344_device::decode_instruction()
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else if ((m_latched_instr & 0xfc00) == 0x8c00)
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{
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// LJMP or LCALL, conditional
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m_source_data = read_register(m_latched_instr & 0x001f);
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m_source_data = read_register(m_latched_instr & 0x001f, true);
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instruction_wait();
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return T2_ABSOLUTE;
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}
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@ -1564,7 +1572,7 @@ dp8344_device::inst_state dp8344_device::decode_instruction()
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else if ((m_latched_instr >= 0xa000 && m_latched_instr < 0xae00) || (m_latched_instr & 0xfc00) == 0xc000)
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{
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if ((m_latched_instr & 0xfe00) != 0xc000)
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m_source_data = read_register(m_latched_instr & 0x001f);
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m_source_data = read_register(m_latched_instr & 0x001f, false);
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switch (m_latched_instr & 0x0180)
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{
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case 0x0000:
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@ -1619,7 +1627,7 @@ dp8344_device::inst_state dp8344_device::decode_instruction()
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{
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// MOVE to or from accumulator-indexed data memory
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if (BIT(m_latched_instr, 7))
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m_source_data = read_register(m_latched_instr & 0x001f);
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m_source_data = read_register(m_latched_instr & 0x001f, false);
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m_data_address = m_ir[(m_latched_instr & 0x0060) >> 5] + read_accumulator();
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return BIT(m_latched_instr, 7) ? TX_WRITE : TX_READ;
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}
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@ -1645,7 +1653,7 @@ dp8344_device::inst_state dp8344_device::decode_instruction()
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else if ((m_latched_instr & 0xff80) == 0xcd80)
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{
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// JMP, register-based
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m_source_data = read_register(m_latched_instr & 0x001f);
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m_source_data = read_register(m_latched_instr & 0x001f, true);
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return TX1_JMP;
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}
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else if ((m_latched_instr & 0xff00) == 0xce00)
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@ -1678,7 +1686,7 @@ dp8344_device::inst_state dp8344_device::decode_instruction()
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}
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else
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{
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m_source_data = read_register(m_latched_instr & 0x001f);
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m_source_data = read_register(m_latched_instr & 0x001f, false);
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instruction_wait();
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return T2_STORE;
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}
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@ -124,13 +124,13 @@ private:
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void transmitter_idle();
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void receiver_active();
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void receive_fifo_push(u8 data);
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u8 receive_fifo_pop();
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u8 receive_fifo_pop(bool test);
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void set_receiver_error(u8 code);
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u8 get_error_code();
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u8 get_error_code(bool test);
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void set_transceiver_command(u8 data);
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void set_transceiver_mode(u8 data);
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void clear_network_command_flag(u8 data);
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u8 read_register(unsigned reg);
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u8 read_register(unsigned reg, bool test);
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u8 read_accumulator() const;
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void write_register(unsigned reg, u8 data);
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void prefetch_instruction();
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@ -82,6 +82,7 @@ void is48x_state::is482(machine_config &config)
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m_maincpu->set_addrmap(AS_IO, &is48x_state::io_map);
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DP8344B(config, m_bcp, 18.867_MHz_XTAL); // DP8344BV
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m_bcp->set_auto_start(false);
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m_bcp->set_addrmap(AS_PROGRAM, &is48x_state::bcp_inst_map);
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m_bcp->set_addrmap(AS_DATA, &is48x_state::bcp_data_map);
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