mirror of
https://github.com/holub/mame
synced 2025-04-25 17:56:43 +03:00
Fixed redundant logerror parameters and trailing spaces
This commit is contained in:
Joakim Larsson Edstrom
parent
63ac06861f
commit
889f958365
@ -28,8 +28,8 @@
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#define VERBOSE 0
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#define LOGPRINT(x) do { if (VERBOSE) logerror x; } while (0)
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#define LOG(x)
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#define LOGR(x)
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#define LOG(x)
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#define LOGR(x)
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#define LOGINT(x) LOGPRINT(x)
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#define LOGSETUP(x) LOGPRINT(x)
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#if VERBOSE == 2
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@ -502,7 +502,7 @@ UINT8 fga002_device::do_fga002reg_istim0_r()
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}
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/*
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/*
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* FGA-002 interrupt support
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*/
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void fga002_device::do_fga002reg_localiack_w(UINT8 data)
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@ -522,14 +522,14 @@ void fga002_device::do_fga002reg_localiack_w(UINT8 data)
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UINT8 fga002_device::do_fga002reg_localiack_r()
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{
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UINT8 ret = m_fga002[FGA_LOCALIACK];
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UINT8 ret = m_fga002[FGA_LOCALIACK];
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LOGINT(("%s() <- %02x\n", FUNCNAME, ret));
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return ret;
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}
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UINT8 fga002_device::do_fga002reg_ctl3_r()
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{
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UINT8 ret = m_fga002[FGA_CTL3];
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UINT8 ret = m_fga002[FGA_CTL3];
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LOGINT(("%s() <- %02x\n", FUNCNAME, ret));
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return ret;
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}
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@ -571,8 +571,8 @@ UINT8 fga002_device::do_fga002reg_islocal7_r(){ UINT8 ret = m_fga002[FGA_ISLOCAL
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void fga002_device::islocal_w(int status, int vector, int control, int data)
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{
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m_fga002[status] = m_fga002[control] & REG_ICR_EDGE ? 0x80 : 0x00;
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LOGINT(("%s(%02x)\n", FUNCNAME, m_fga002[status]));
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m_fga002[status] = m_fga002[control] & REG_ICR_EDGE ? 0x80 : 0x00;
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LOGINT(("%s(%02x)\n", FUNCNAME, m_fga002[status]));
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}
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// TODO: support level triggered interrupts, only edge triggered interrupts are supported atm
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@ -587,18 +587,18 @@ void fga002_device::do_fga002reg_islocal7_w(UINT8 data){ LOGINT(("%s\n", FUNCNA
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// Local IRQ callbacks
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// TODO: support level triggered interrupts, ICR bit 6, only edge triggered interrupts are supported atm
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// TODO: support programmable assertion levels ICR bit 5, a call to this function assumes assertion atm
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// TODO: support programmable assertion levels ICR bit 5, a call to this function assumes assertion atm
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void fga002_device::lirq_w(int status, int vector, int control, int state)
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{
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LOGINT((" - %s\n", state == ASSERT_LINE ? "Asserted" : "Cleared"));
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if (state == ASSERT_LINE)
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{
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m_fga002[status] &= ~REG_ISLOCAL_IRQ;
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m_fga002[status] &= ~REG_ISLOCAL_IRQ;
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trigger_interrupt(vector);
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}
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else
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else
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{
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m_fga002[status] |= REG_ISLOCAL_IRQ;
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m_fga002[status] |= REG_ISLOCAL_IRQ;
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}
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}
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@ -93,7 +93,7 @@ DONE (x) (p=partly) NMOS CMOS
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#define LOGTX(x)
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#define LOGRX(x)
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#define LOGSETUP(x)
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#define LOGINT(x) LOGPRINT(x)
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#define LOGINT(x) LOGPRINT(x)
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#if VERBOSE > 1
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#define logerror printf
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@ -404,7 +404,7 @@ READ8_MEMBER( duscc_device::iack )
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void duscc_device::check_interrupts()
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{
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LOGINT(("%s %s()\n",tag(), FUNCNAME));
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int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE;
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int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE;
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// "If no interrupt is pending, an H'FF' is output when reading the IVRM."
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if (state == CLEAR_LINE)
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@ -457,7 +457,7 @@ UINT8 duscc_device::modify_vector(UINT8 vec, int index, UINT8 src)
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if ((m_icr & REG_ICR_VEC_MOD) != 0) // Affect vector?
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{
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// Modify vector according to "Vector Include Status" bit (REG_ICR_V2V4_MOD)
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if ((m_icr & REG_ICR_V2V4_MOD) != 0)
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if ((m_icr & REG_ICR_V2V4_MOD) != 0)
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{ // Affect V2-V4
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LOGINT((" - Affect V2-V4 with status"));
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vec &= 0x07 << 3;
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@ -479,7 +479,7 @@ UINT8 duscc_device::modify_vector(UINT8 vec, int index, UINT8 src)
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This group of registers define mechanisms for communications between the DUSCC and the processor and contain the device status
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information. Four registers, available for each channel, and four common device registers comprise this group which consists of
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the following:
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1. Interrupt Enable Register (IERA/B). - checked by trigger_interrupt
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1. Interrupt Enable Register (IERA/B). - checked by trigger_interrupt
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2. Receiver Status Register (RSRA/B).
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3. Transmitter and Receiver Status Register (TRSRA/B).
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4. Input and Counter/timer Status Register (ICTSRA/B).
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@ -978,7 +978,7 @@ void duscc_channel::tra_callback()
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else
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{
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LOG((LLFORMAT " %s() \"%s \"Channel %c Failed to transmit \n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index));
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logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, m_owner->tag(), 'A' + m_index);
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logerror("%s Channel %c Failed to transmit\n", FUNCNAME, 'A' + m_index);
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}
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}
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@ -1299,15 +1299,15 @@ UINT8 duscc_channel::do_dusccreg_ictsr_r()
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receiver' command is invoked.
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*/
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UINT8 duscc_channel::do_dusccreg_gsr_r()
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{
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{
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static UINT8 old_gsr = 0;
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if (m_uart->m_gsr != old_gsr) LOG(("%s <- %02x\n", FUNCNAME, m_uart->m_gsr));
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old_gsr = m_uart->m_gsr;
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return m_uart->m_gsr;
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old_gsr = m_uart->m_gsr;
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return m_uart->m_gsr;
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}
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UINT8 duscc_channel::do_dusccreg_ier_r()
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{
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{
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LOGINT(("%s <- %02x\n", FUNCNAME, m_ier));
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return (UINT8) m_ier;
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}
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@ -1912,7 +1912,7 @@ void duscc_channel::do_dusccreg_omr_w(UINT8 data)
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*/
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void duscc_channel::do_dusccreg_pcr_w(UINT8 data)
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{
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LOG(("%c %s(%02x)\n", 'A' + m_index, FUNCNAME, data));
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LOG(("%c %s(%02x)\n", 'A' + m_index, FUNCNAME, data));
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m_pcr = data;
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LOG(("- The X2/IDCN pin is %s\n", m_index == duscc_device::CHANNEL_B ? "ignored for channel B" :
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((m_pcr & REG_PCR_X2_IDC) ? "crystal input" : "daisy chain interrupt output")));
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@ -1956,7 +1956,7 @@ void duscc_channel::do_dusccreg_ccr_w(UINT8 data)
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int rate;
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m_ccr = data;
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LOG(("%c %s(%02x)\n", 'A' + m_index, FUNCNAME, data));
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LOG(("%c %s(%02x)\n", 'A' + m_index, FUNCNAME, data));
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switch(m_ccr)
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{
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// TRANSMITTER COMMANDS
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@ -2113,8 +2113,8 @@ void duscc_channel::do_dusccreg_txfifo_w(UINT8 data)
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before reading the character data from RxFIFO. For block status, the status register is initially cleared and then read after the
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message is received. Asserted status bits can be programmed to generate an interrupt (see Interrupt Enable Register).*/
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void duscc_channel::do_dusccreg_rsr_w(UINT8 data)
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{
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LOG(("%c %s(%02x)\n", 'A' + m_index, FUNCNAME, data));
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{
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LOG(("%c %s(%02x)\n", 'A' + m_index, FUNCNAME, data));
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m_rsr &= ~data; // Clear only bits which are 1:s
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return;
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}
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@ -2163,7 +2163,7 @@ void duscc_channel::do_dusccreg_gsr_w(UINT8 data)
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This register controls whether the assertion of bits in the channel's status registers causes an interrupt to be generated. An additional
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condition for an interrupt to be generated is that the channel's master interrupt enabled bit, ICR[O] or ICR[1], be asserted.*/
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void duscc_channel::do_dusccreg_ier_w(UINT8 data)
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{
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{
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LOGINT(("%c %s(%02x)\n", 'A' + m_index, FUNCNAME, data));
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if (REG_IER_DCD_CTS & (data ^ m_ier)) LOGINT(("- DCD/CTS interrups %s\n", (data & REG_IER_DCD_CTS) ? "enabled" : "disabled" ));
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if (REG_IER_TXRDY & (data ^ m_ier)) LOGINT(("- TXRDY interrupts %s\n", (data & REG_IER_TXRDY) ? "enabled" : "disabled" ));
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@ -2264,7 +2264,7 @@ UINT8 duscc_channel::read(offs_t &offset)
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// CDUSCC Extended registers - requires A7 to be set through REG_SEA
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case REG_CID: data = do_dusccreg_cid_r(); break;
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default:
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logerror(" \"%s\" %s: %c : Unsupported RRx register:%02x\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg);
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logerror("%s: %c : Unsupported RRx register:%02x\n", FUNCNAME, 'A' + m_index, reg);
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}
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LOGR(("%s \"%s\": %c : Register R%d read '%02x'\n", FUNCNAME, m_owner->tag(), 'A' + m_index, reg, data));
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@ -2323,7 +2323,7 @@ void duscc_channel::write(UINT8 data, offs_t &offset)
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case REG_TELR: LOG(("REG_TELR\n")); break;
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default:
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logerror(" \"%s\" %s: %c : Unsupported WRx register:%02x(%02x)\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg, data);
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logerror("%s: %c : Unsupported WRx register:%02x(%02x)\n", FUNCNAME, 'A' + m_index, reg, data);
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}
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}
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@ -143,33 +143,33 @@
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*
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* PIT #1 hardware wiring
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* ----------------------------------------------------------
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* PA0-PA3 Rotary Switch 1 input
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* PA4-PA7 Rotary Switch 2 input
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* H1-H4 User I/O via optional B5 or optional 5-row VME P2 connector
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* PB0-PB2 Floppy Disk Drive Control output
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* PB3-PB4 Floppy Disk Drive Control input
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* PB5 Floppy Disk Drive Control output
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* PB6-PB7 DMAC control
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* PC0,PC1 User I/O via optional B5 or optional 5-row VME P2 connector
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* PC4,PC7 User I/O via optional B5 or optional 5-row VME P2 connector
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* PC2 Reserved
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* PC3 Timer interrupt request
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* PC5 Port Interrupt Request
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* PC6 68882 FPCP Sense
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* PA0-PA3 Rotary Switch 1 input
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* PA4-PA7 Rotary Switch 2 input
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* H1-H4 User I/O via optional B5 or optional 5-row VME P2 connector
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* PB0-PB2 Floppy Disk Drive Control output
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* PB3-PB4 Floppy Disk Drive Control input
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* PB5 Floppy Disk Drive Control output
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* PB6-PB7 DMAC control
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* PC0,PC1 User I/O via optional B5 or optional 5-row VME P2 connector
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* PC4,PC7 User I/O via optional B5 or optional 5-row VME P2 connector
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* PC2 Reserved
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* PC3 Timer interrupt request
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* PC5 Port Interrupt Request
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* PC6 68882 FPCP Sense
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*
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* PIT #2 hardware setup wiring
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* ----------------------------------------------------------
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* PA0-PA7 User I/O via optional B5 or optional 5-row VME P2 connector
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* H1-H4 User I/O via optional B5 or optional 5-row VME P2 connector
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* PB0-PB2 Memory Size
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* PB3-PB7 Board ID
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* PC0-PC1 Hardware ID
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* PC2 Status of write protection for (default and optional) Boot PROMs
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* PC3 Timer Interrupt request
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* PC4 Status of write protection for SYSTEM-Flash Memory
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* PC5 DMA control
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* PC6 Flash programming voltage control
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* PC7 Reserved
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* PA0-PA7 User I/O via optional B5 or optional 5-row VME P2 connector
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* H1-H4 User I/O via optional B5 or optional 5-row VME P2 connector
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* PB0-PB2 Memory Size
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* PB3-PB7 Board ID
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* PC0-PC1 Hardware ID
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* PC2 Status of write protection for (default and optional) Boot PROMs
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* PC3 Timer Interrupt request
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* PC4 Status of write protection for SYSTEM-Flash Memory
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* PC5 DMA control
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* PC6 Flash programming voltage control
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* PC7 Reserved
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*
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* DMAC Channel Assignments
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* ----------------------------------------------------------
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@ -202,7 +202,7 @@
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#define LOG(x)
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#define LOGR(x)
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#define LOGSETUP(x)
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#define LOGINT(x) LOGPRINT(x)
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#define LOGINT(x) LOGPRINT(x)
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#if VERBOSE >= 2
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#define logerror printf
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#endif
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@ -392,7 +392,7 @@ READ8_MEMBER (fccpu30_state::rotary_rd){
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// PIT#1 Port B TODO: implement floppy and dma control
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READ8_MEMBER (fccpu30_state::flop_dmac_r){
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LOG(("%s\n", FUNCNAME));
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return 0xff;
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return 0xff;
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}
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WRITE8_MEMBER (fccpu30_state::flop_dmac_w){
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@ -403,7 +403,7 @@ WRITE8_MEMBER (fccpu30_state::flop_dmac_w){
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// TODO: Connect PC0, PC1, PC4 and PC7 to B5 and/or P2 connector
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READ8_MEMBER (fccpu30_state::pit1c_r){
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LOG(("%s\n", FUNCNAME));
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return 0xff;
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return 0xff;
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}
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WRITE8_MEMBER (fccpu30_state::pit1c_w){
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@ -414,7 +414,7 @@ WRITE8_MEMBER (fccpu30_state::pit1c_w){
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READ8_MEMBER (fccpu30_state::pit2a_r){
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LOG(("%s\n", FUNCNAME));
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logerror("Unsupported user i/o on PIT2 port A detected\n");
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return 0xff;
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return 0xff;
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}
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WRITE8_MEMBER (fccpu30_state::pit2a_w){
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@ -448,7 +448,7 @@ READ8_MEMBER (fccpu30_state::board_mem_id_rd){
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// PIT#2 Port C TODO: implement timer interrupt, DMA i/o, memory control and Hardware ID
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READ8_MEMBER (fccpu30_state::pit2c_r){
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LOG(("%s\n", FUNCNAME));
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return 0xff;
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return 0xff;
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}
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WRITE8_MEMBER (fccpu30_state::pit2c_w){
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@ -486,7 +486,7 @@ WRITE_LINE_MEMBER(fccpu30_state::fga_irq_callback)
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update_irq_to_maincpu();
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}
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void fccpu30_state::update_irq_to_maincpu()
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void fccpu30_state::update_irq_to_maincpu()
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{
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LOGINT(("%s()\n", FUNCNAME));
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LOGINT((" - fga_irq_level: %02x\n", fga_irq_level));
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@ -546,7 +546,7 @@ static MACHINE_CONFIG_START (fccpu30, fccpu30_state)
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MCFG_DUSCC_OUT_DTRA_CB(DEVWRITELINE(RS232P4_TAG, rs232_port_device, write_dtr))
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MCFG_DUSCC_OUT_RTSA_CB(DEVWRITELINE(RS232P4_TAG, rs232_port_device, write_rts))
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/* DUSCC1 interrupt signal REQN is connected to LOCAL IRQ4 of the FGA-002 and level is programmable */
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MCFG_DUSCC_OUT_INT_CB(DEVWRITELINE("fga002", fga002_device, lirq4_w))
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MCFG_DUSCC_OUT_INT_CB(DEVWRITELINE("fga002", fga002_device, lirq4_w))
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MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
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/* Port 2 on Port A */
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@ -558,7 +558,7 @@ static MACHINE_CONFIG_START (fccpu30, fccpu30_state)
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MCFG_DUSCC_OUT_DTRB_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_dtr))
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MCFG_DUSCC_OUT_RTSB_CB(DEVWRITELINE(RS232P3_TAG, rs232_port_device, write_rts))
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/* DUSCC2 interrupt signal REQN is connected to LOCAL IRQ5 of the FGA-002 and level is programmable */
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MCFG_DUSCC_OUT_INT_CB(DEVWRITELINE("fga002", fga002_device, lirq5_w))
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MCFG_DUSCC_OUT_INT_CB(DEVWRITELINE("fga002", fga002_device, lirq5_w))
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MCFG_RS232_PORT_ADD (RS232P1_TAG, default_rs232_devices, nullptr)
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MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, rxb_w))
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@ -642,19 +642,19 @@ ROM_END
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* :pit2 Reg -> 70 CNTRL - Current value of timer low byte
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* :pit1 Reg 10 <- e0 TCR - PC3 is TOUT, PC7 is I/O, Interrupts enabled, PC2 is I/O, CLK and x32 prescaler, Preload timer on 0 (zero), Timer disabled
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* :pit1 Reg 00 <- 20 PGCR -
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* :pit1 Reg 01 <- 08 PSRR -
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* :pit1 Reg 06 <- c0 PACR -
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* :pit1 Reg 00 <- 20 PGCR -
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* :pit1 Reg 01 <- 08 PSRR -
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* :pit1 Reg 06 <- c0 PACR -
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* :pit1 Reg 02 <- 00 PADDR -
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* :pit1 Reg 07 <- c0 PBCR -
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* :pit1 Reg 09 <- 00 PBDR -
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* :pit1 Reg 09 <- 00 PBDR -
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* :pit1 Reg 03 <- 00 PBDDR -
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* :pit1 Reg 0c <- 17 PCDR -
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* :pit1 Reg 04 <- 17 PCDDR -
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* :pit1 Reg 0c <- 17 PCDR -
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* :pit1 Reg 04 <- 17 PCDDR -
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* :pit1 Reg 15 <- e2 CPRL -
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* :pit1 Reg 14 <- 04 CPRM -
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* :pit1 Reg 13 <- 00 CPRH -
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* :pit1 Reg 11 <- f2 TIVR -
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* :pit1 Reg 11 <- f2 TIVR -
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* :pit1 Reg 10 <- 41 TCR - PC3 is SQW at TOUT, PC7 is I/O, PC2 is I/O, CLK and x32 prescaler, Preload timer on 0 (zero), Timer enabled
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* :pit2 Reg 10 <- e2 PC3 is TOUT, PC7 is I/O, Interrupts enabled, PC2 is timer enable/disable, CLK and prescaler, Preload timer on 0 (zero), Timer disabled
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@ -673,7 +673,7 @@ ROM_END
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* DUSCC #1 channel A setup 1 sequence FGA-002 firmware (polled i/o)
|
||||
* A Reg 0f <- 00 - reset Tx Command
|
||||
* A Reg 0f <- 40 - reset Rx Command
|
||||
* A Reg 0f <- 40 - reset Rx Command
|
||||
* A Reg 00 <- 07 - Async mode
|
||||
* A Reg 01 <- 38 - Normal polled or interrupt mode, no DMA
|
||||
* A Reg 04 <- 7f - Tx 8 bits, CTS and RTS, 1 STOP bit
|
||||
@ -714,8 +714,8 @@ ROM_END
|
||||
* Repeated setup for channel B
|
||||
*
|
||||
* FGA setup
|
||||
void fga002_device::do_fga002reg_icrtim0_w(UINT8)(00)
|
||||
void fga002_device::do_fga002reg_ctl3_w(UINT8)(0c)
|
||||
void fga002_device::do_fga002reg_icrtim0_w(UINT8)(00)
|
||||
void fga002_device::do_fga002reg_ctl3_w(UINT8)(0c)
|
||||
void fga002_device::do_fga002reg_icrlocal0_w(UINT8)(00)
|
||||
void fga002_device::do_fga002reg_icrlocal1_w(UINT8)(00)
|
||||
void fga002_device::do_fga002reg_icrlocal2_w(UINT8)(00)
|
||||
@ -725,42 +725,40 @@ void fga002_device::do_fga002reg_icrlocal5_w(UINT8)(00)
|
||||
void fga002_device::do_fga002reg_icrlocal6_w(UINT8)(00)
|
||||
void fga002_device::do_fga002reg_icrlocal7_w(UINT8)(00)
|
||||
|
||||
* A Reg 10 <- 20
|
||||
* A Reg 10 <- 20
|
||||
UINT8 duscc_channel::do_dusccreg_rxfifo_r()
|
||||
- RX rp:0 wp:1 sz:4
|
||||
- RX reading out data:6e 'n'
|
||||
- RX rp:0 wp:1 sz:4
|
||||
- RX reading out data:6e 'n'
|
||||
|
||||
|
||||
UINT8 duscc_channel::do_dusccreg_rxfifo_r()
|
||||
- RX rp:1 wp:2 sz:4
|
||||
- RX reading out data:6e 'n'
|
||||
* A Reg 10 <- 6e
|
||||
* A Reg 10 <- 0d
|
||||
* A Reg 10 <- 0a
|
||||
UINT8 duscc_channel::do_dusccreg_rxfifo_r()
|
||||
- RX rp:1 wp:2 sz:4
|
||||
- RX reading out data:6e 'n'
|
||||
* A Reg 10 <- 6e
|
||||
* A Reg 10 <- 0d
|
||||
* A Reg 10 <- 0a
|
||||
void fga002_device::do_fga002reg_icrlocal2_w(UINT8)(4d)
|
||||
void fga002_device::do_fga002reg_icrlocal4_w(UINT8)(1c)
|
||||
* A Reg 0f <- 00
|
||||
* A Reg 0f <- 40
|
||||
* A Reg 00 <- 07
|
||||
* A Reg 01 <- 38
|
||||
* A Reg 04 <- 7f
|
||||
* A Reg 06 <- 1b
|
||||
* A Reg 0b <- e1
|
||||
* A Reg 0e <- 27
|
||||
* A Reg 07 <- 2d
|
||||
* A Reg 05 <- 3d
|
||||
* A Reg 1c <- 10
|
||||
void duscc_channel::do_dusccreg_ier_w(UINT8)(10)
|
||||
- RXRDY interrupts enabled
|
||||
:duscc void duscc_device::check_interrupts()()
|
||||
:duscc virtual int duscc_device::z80daisy_irq_state() A:[00][00][00][00] B:[00][00][00][00] Interrupt State 00
|
||||
void fga002_device::trigger_interrupt(UINT8)(34)
|
||||
Interrupt Level 4, caused by ICR 1c with vector 34
|
||||
void fga002_device::check_interrupts()()
|
||||
:fga002 virtual int fga002_device::z80daisy_irq_state() Level 0-7:[00][00] [00][00] [01][00] [00][00]
|
||||
* A Reg 0f <- 00
|
||||
* A Reg 0f <- 40
|
||||
* A Reg 00 <- 07
|
||||
* A Reg 01 <- 38
|
||||
* A Reg 04 <- 7f
|
||||
* A Reg 06 <- 1b
|
||||
* A Reg 0b <- e1
|
||||
* A Reg 0e <- 27
|
||||
* A Reg 07 <- 2d
|
||||
* A Reg 05 <- 3d
|
||||
* A Reg 1c <- 10
|
||||
void duscc_channel::do_dusccreg_ier_w(UINT8)(10)
|
||||
- RXRDY interrupts enabled
|
||||
:duscc void duscc_device::check_interrupts()()
|
||||
:duscc virtual int duscc_device::z80daisy_irq_state() A:[00][00][00][00] B:[00][00][00][00] Interrupt State 00
|
||||
void fga002_device::trigger_interrupt(UINT8)(34)
|
||||
Interrupt Level 4, caused by ICR 1c with vector 34
|
||||
void fga002_device::check_interrupts()()
|
||||
:fga002 virtual int fga002_device::z80daisy_irq_state() Level 0-7:[00][00] [00][00] [01][00] [00][00]
|
||||
void fccpu30_state::fga_irq_callback(int)(01)
|
||||
void fga002_device::check_interrupts()()
|
||||
|
||||
void fga002_device::check_interrupts()()
|
||||
*/
|
||||
|
||||
/* Driver */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user