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Fixed redundant logerror parameters and trailing spaces

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This commit is contained in:
Joakim Larsson Edstrom 2016-09-07 16:25:32 +02:00
parent 63ac06861f
commit 889f958365
4 changed files with 98 additions and 100 deletions
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6
src/devices/machine/scnxx562.cpp
View File

@ -978,7 +978,7 @@ void duscc_channel::tra_callback()
else else
{ {
LOG((LLFORMAT " %s() \"%s \"Channel %c Failed to transmit \n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index)); LOG((LLFORMAT " %s() \"%s \"Channel %c Failed to transmit \n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index));
logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, m_owner->tag(), 'A' + m_index); logerror("%s Channel %c Failed to transmit\n", FUNCNAME, 'A' + m_index);
} }
} }
@ -2264,7 +2264,7 @@ UINT8 duscc_channel::read(offs_t &offset)
// CDUSCC Extended registers - requires A7 to be set through REG_SEA // CDUSCC Extended registers - requires A7 to be set through REG_SEA
case REG_CID: data = do_dusccreg_cid_r(); break; case REG_CID: data = do_dusccreg_cid_r(); break;
default: default:
logerror(" \"%s\" %s: %c : Unsupported RRx register:%02x\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg); logerror("%s: %c : Unsupported RRx register:%02x\n", FUNCNAME, 'A' + m_index, reg);
} }
LOGR(("%s \"%s\": %c : Register R%d read '%02x'\n", FUNCNAME, m_owner->tag(), 'A' + m_index, reg, data)); LOGR(("%s \"%s\": %c : Register R%d read '%02x'\n", FUNCNAME, m_owner->tag(), 'A' + m_index, reg, data));
@ -2323,7 +2323,7 @@ void duscc_channel::write(UINT8 data, offs_t &offset)
case REG_TELR: LOG(("REG_TELR\n")); break; case REG_TELR: LOG(("REG_TELR\n")); break;
default: default:
logerror(" \"%s\" %s: %c : Unsupported WRx register:%02x(%02x)\n", m_owner->tag(), FUNCNAME, 'A' + m_index, reg, data); logerror("%s: %c : Unsupported WRx register:%02x(%02x)\n", FUNCNAME, 'A' + m_index, reg, data);
} }
} }

50
src/mame/drivers/fccpu30.cpp
View File

@ -143,33 +143,33 @@
* *
* PIT #1 hardware wiring * PIT #1 hardware wiring
* ---------------------------------------------------------- * ----------------------------------------------------------
* PA0-PA3 Rotary Switch 1 input * PA0-PA3 Rotary Switch 1 input
* PA4-PA7 Rotary Switch 2 input * PA4-PA7 Rotary Switch 2 input
* H1-H4 User I/O via optional B5 or optional 5-row VME P2 connector * H1-H4 User I/O via optional B5 or optional 5-row VME P2 connector
* PB0-PB2 Floppy Disk Drive Control output * PB0-PB2 Floppy Disk Drive Control output
* PB3-PB4 Floppy Disk Drive Control input * PB3-PB4 Floppy Disk Drive Control input
* PB5 Floppy Disk Drive Control output * PB5 Floppy Disk Drive Control output
* PB6-PB7 DMAC control * PB6-PB7 DMAC control
* PC0,PC1 User I/O via optional B5 or optional 5-row VME P2 connector * PC0,PC1 User I/O via optional B5 or optional 5-row VME P2 connector
* PC4,PC7 User I/O via optional B5 or optional 5-row VME P2 connector * PC4,PC7 User I/O via optional B5 or optional 5-row VME P2 connector
* PC2 Reserved * PC2 Reserved
* PC3 Timer interrupt request * PC3 Timer interrupt request
* PC5 Port Interrupt Request * PC5 Port Interrupt Request
* PC6 68882 FPCP Sense * PC6 68882 FPCP Sense
* *
* PIT #2 hardware setup wiring * PIT #2 hardware setup wiring
* ---------------------------------------------------------- * ----------------------------------------------------------
* PA0-PA7 User I/O via optional B5 or optional 5-row VME P2 connector * PA0-PA7 User I/O via optional B5 or optional 5-row VME P2 connector
* H1-H4 User I/O via optional B5 or optional 5-row VME P2 connector * H1-H4 User I/O via optional B5 or optional 5-row VME P2 connector
* PB0-PB2 Memory Size * PB0-PB2 Memory Size
* PB3-PB7 Board ID * PB3-PB7 Board ID
* PC0-PC1 Hardware ID * PC0-PC1 Hardware ID
* PC2 Status of write protection for (default and optional) Boot PROMs * PC2 Status of write protection for (default and optional) Boot PROMs
* PC3 Timer Interrupt request * PC3 Timer Interrupt request
* PC4 Status of write protection for SYSTEM-Flash Memory * PC4 Status of write protection for SYSTEM-Flash Memory
* PC5 DMA control * PC5 DMA control
* PC6 Flash programming voltage control * PC6 Flash programming voltage control
* PC7 Reserved * PC7 Reserved
* *
* DMAC Channel Assignments * DMAC Channel Assignments
* ---------------------------------------------------------- * ----------------------------------------------------------
@ -730,7 +730,6 @@ UINT8 duscc_channel::do_dusccreg_rxfifo_r()
- RX rp:0 wp:1 sz:4 - RX rp:0 wp:1 sz:4
- RX reading out data:6e 'n' - RX reading out data:6e 'n'
UINT8 duscc_channel::do_dusccreg_rxfifo_r() UINT8 duscc_channel::do_dusccreg_rxfifo_r()
- RX rp:1 wp:2 sz:4 - RX rp:1 wp:2 sz:4
- RX reading out data:6e 'n' - RX reading out data:6e 'n'
@ -760,7 +759,6 @@ void fga002_device::check_interrupts()()
:fga002 virtual int fga002_device::z80daisy_irq_state() Level 0-7:[00][00] [00][00] [01][00] [00][00] :fga002 virtual int fga002_device::z80daisy_irq_state() Level 0-7:[00][00] [00][00] [01][00] [00][00]
void fccpu30_state::fga_irq_callback(int)(01) void fccpu30_state::fga_irq_callback(int)(01)
void fga002_device::check_interrupts()() void fga002_device::check_interrupts()()
*/ */
/* Driver */ /* Driver */