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dsp56k.c : Remove globals from dsp56k cpu core. [AtariAce]

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This commit is contained in:
Andrew Gardner 2010-08-10 05:25:22 +00:00
parent a3e4397af7
commit 88bbeda462
5 changed files with 70 additions and 66 deletions
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14
src/emu/cpu/dsp56k/dsp56k.c
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@ -45,13 +45,6 @@ using namespace DSP56K;
static CPU_RESET( dsp56k ); static CPU_RESET( dsp56k );
/***************************************************************************
ONBOARD MEMORY
***************************************************************************/
UINT16 *dsp56k_peripheral_ram;
UINT16 *dsp56k_program_ram;
/*************************************************************************** /***************************************************************************
COMPONENT FUNCTIONALITY COMPONENT FUNCTIONALITY
***************************************************************************/ ***************************************************************************/
@ -78,7 +71,8 @@ static DIRECT_UPDATE_HANDLER( dsp56k_direct_handler )
{ {
if (address >= (0x0000<<1) && address <= (0x07ff<<1)) if (address >= (0x0000<<1) && address <= (0x07ff<<1))
{ {
direct->raw = direct->decrypted = (UINT8 *)(dsp56k_program_ram - (0x0000<<1)); dsp56k_core* cpustate = get_safe_token(space->cpu);
direct->raw = direct->decrypted = (UINT8 *)(cpustate->program_ram - (0x0000<<1));
return ~0; return ~0;
} }
@ -374,13 +368,13 @@ extern CPU_DISASSEMBLE( dsp56k );
* Internal Memory Maps * Internal Memory Maps
****************************************************************************/ ****************************************************************************/
static ADDRESS_MAP_START( dsp56156_program_map, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( dsp56156_program_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x0000,0x07ff) AM_RAM AM_BASE(&dsp56k_program_ram) /* 1-5 */ AM_RANGE(0x0000,0x07ff) AM_READWRITE(DSP56K::program_r, DSP56K::program_w) /* 1-5 */
// AM_RANGE(0x2f00,0x2fff) AM_ROM /* 1-5 PROM reserved memory. Is this the right spot for it? */ // AM_RANGE(0x2f00,0x2fff) AM_ROM /* 1-5 PROM reserved memory. Is this the right spot for it? */
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( dsp56156_x_data_map, ADDRESS_SPACE_DATA, 16 ) static ADDRESS_MAP_START( dsp56156_x_data_map, ADDRESS_SPACE_DATA, 16 )
AM_RANGE(0x0000,0x07ff) AM_RAM /* 1-5 */ AM_RANGE(0x0000,0x07ff) AM_RAM /* 1-5 */
AM_RANGE(0xffc0,0xffff) AM_READWRITE(peripheral_register_r, peripheral_register_w) AM_BASE(&dsp56k_peripheral_ram) /* 1-5 On-chip peripheral registers memory mapped in data space */ AM_RANGE(0xffc0,0xffff) AM_READWRITE(DSP56K::peripheral_register_r, DSP56K::peripheral_register_w) /* 1-5 On-chip peripheral registers memory mapped in data space */
ADDRESS_MAP_END ADDRESS_MAP_END

3
src/emu/cpu/dsp56k/dsp56k.h
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@ -235,6 +235,9 @@ typedef struct
legacy_cpu_device *device; legacy_cpu_device *device;
const address_space *program; const address_space *program;
const address_space *data; const address_space *data;
UINT16 peripheral_ram[0x40];
UINT16 program_ram[0x800];
} dsp56k_core; } dsp56k_core;

38
src/emu/cpu/dsp56k/dsp56mem.c
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@ -4,9 +4,6 @@
#include "dsp56mem.h" #include "dsp56mem.h"
#include "dsp56pcu.h" #include "dsp56pcu.h"
extern UINT16 *dsp56k_peripheral_ram;
extern UINT16 *dsp56k_program_ram;
namespace DSP56K namespace DSP56K
{ {
@ -301,9 +298,9 @@ void RXDF_bit_set(dsp56k_core* cpustate, UINT8 value)
void dsp56k_host_interface_reset(dsp56k_core* cpustate) void dsp56k_host_interface_reset(dsp56k_core* cpustate)
{ {
// Hook up the CPU-side pointers properly. // Hook up the CPU-side pointers properly.
cpustate->HI.hcr = &dsp56k_peripheral_ram[A2O(0xffc4)]; cpustate->HI.hcr = &cpustate->peripheral_ram[A2O(0xffc4)];
cpustate->HI.hsr = &dsp56k_peripheral_ram[A2O(0xffe4)]; cpustate->HI.hsr = &cpustate->peripheral_ram[A2O(0xffe4)];
cpustate->HI.htrx = &dsp56k_peripheral_ram[A2O(0xffe5)]; cpustate->HI.htrx = &cpustate->peripheral_ram[A2O(0xffe5)];
// The Bootstrap hack is initialized to write to address 0x0000 // The Bootstrap hack is initialized to write to address 0x0000
cpustate->HI.bootstrap_offset = 0x0000; cpustate->HI.bootstrap_offset = 0x0000;
@ -486,7 +483,17 @@ void dsp56k_io_reset(dsp56k_core* cpustate)
external_p_wait_states_set(cpustate, 0x1f); external_p_wait_states_set(cpustate, 0x1f);
} }
} // namespace DSP56K READ16_HANDLER( program_r )
{
dsp56k_core* cpustate = get_safe_token(space->cpu);
return cpustate->program_ram[offset];
}
WRITE16_HANDLER( program_w )
{
dsp56k_core* cpustate = get_safe_token(space->cpu);
cpustate->program_ram[offset] = data;
}
/* Work */ /* Work */
READ16_HANDLER( peripheral_register_r ) READ16_HANDLER( peripheral_register_r )
@ -621,7 +628,7 @@ READ16_HANDLER( peripheral_register_r )
} }
// Its primary behavior is RAM // Its primary behavior is RAM
return dsp56k_peripheral_ram[offset]; return cpustate->peripheral_ram[offset];
} }
WRITE16_HANDLER( peripheral_register_w ) WRITE16_HANDLER( peripheral_register_w )
@ -629,7 +636,7 @@ WRITE16_HANDLER( peripheral_register_w )
dsp56k_core* cpustate = get_safe_token(space->cpu); dsp56k_core* cpustate = get_safe_token(space->cpu);
// Its primary behavior is RAM // Its primary behavior is RAM
// COMBINE_DATA(&dsp56k_peripheral_ram[offset]); // COMBINE_DATA(&cpustate->peripheral_ram[offset]);
// (printf) logerror("Peripheral write 0x%04x = %04x\n", O2A(offset), data); // (printf) logerror("Peripheral write 0x%04x = %04x\n", O2A(offset), data);
@ -779,6 +786,7 @@ WRITE16_HANDLER( peripheral_register_w )
} }
} }
} // namespace DSP56K
/* These two functions are exposed to the outside world */ /* These two functions are exposed to the outside world */
/* They represent the host side of the dsp56k's host interface */ /* They represent the host side of the dsp56k's host interface */
@ -840,8 +848,8 @@ void dsp56k_host_interface_write(running_device* device, UINT8 offset, UINT8 dat
// HACK // HACK
if (cpustate->bootstrap_mode == BOOTSTRAP_HI) if (cpustate->bootstrap_mode == BOOTSTRAP_HI)
{ {
dsp56k_program_ram[cpustate->HI.bootstrap_offset] &= 0x00ff; cpustate->program_ram[cpustate->HI.bootstrap_offset] &= 0x00ff;
dsp56k_program_ram[cpustate->HI.bootstrap_offset] |= (data << 8); cpustate->program_ram[cpustate->HI.bootstrap_offset] |= (data << 8);
break; /* Probably the right thing to do, given this is a hack */ break; /* Probably the right thing to do, given this is a hack */
} }
@ -856,8 +864,8 @@ void dsp56k_host_interface_write(running_device* device, UINT8 offset, UINT8 dat
// HACK // HACK
if (cpustate->bootstrap_mode == BOOTSTRAP_HI) if (cpustate->bootstrap_mode == BOOTSTRAP_HI)
{ {
dsp56k_program_ram[cpustate->HI.bootstrap_offset] &= 0xff00; cpustate->program_ram[cpustate->HI.bootstrap_offset] &= 0xff00;
dsp56k_program_ram[cpustate->HI.bootstrap_offset] |= data; cpustate->program_ram[cpustate->HI.bootstrap_offset] |= data;
cpustate->HI.bootstrap_offset++; cpustate->HI.bootstrap_offset++;
if (cpustate->HI.bootstrap_offset == 0x800) if (cpustate->HI.bootstrap_offset == 0x800)
@ -947,8 +955,8 @@ UINT8 dsp56k_host_interface_read(running_device* device, UINT8 offset)
/* MISC*/ /* MISC*/
UINT16 dsp56k_get_peripheral_memory(running_device* device, UINT16 addr) UINT16 dsp56k_get_peripheral_memory(running_device* device, UINT16 addr)
{ {
// TODO // THIS COMES BACK dsp56k_core* cpustate = get_safe_token(device); dsp56k_core* cpustate = get_safe_token(device);
return dsp56k_peripheral_ram[A2O(addr)]; return cpustate->peripheral_ram[A2O(addr)];
} }

76
src/emu/cpu/dsp56k/dsp56mem.h
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@ -18,41 +18,41 @@ void mem_reset(dsp56k_core* cpustate);
#define O2A(a) (a+0xffc0) #define O2A(a) (a+0xffc0)
// The memory 'registers' // The memory 'registers'
#define PBC (dsp56k_peripheral_ram[A2O(0xffc0)]) #define PBC (cpustate->peripheral_ram[A2O(0xffc0)])
#define PCC (dsp56k_peripheral_ram[A2O(0xffc1)]) #define PCC (cpustate->peripheral_ram[A2O(0xffc1)])
#define PBDDR (dsp56k_peripheral_ram[A2O(0xffc2)]) #define PBDDR (cpustate->peripheral_ram[A2O(0xffc2)])
#define PCDDR (dsp56k_peripheral_ram[A2O(0xffc3)]) #define PCDDR (cpustate->peripheral_ram[A2O(0xffc3)])
#define HCR (dsp56k_peripheral_ram[A2O(0xffc4)]) #define HCR (cpustate->peripheral_ram[A2O(0xffc4)])
#define COCR (dsp56k_peripheral_ram[A2O(0xffc8)]) #define COCR (cpustate->peripheral_ram[A2O(0xffc8)])
#define CRASSI0 (dsp56k_peripheral_ram[A2O(0xffd0)]) #define CRASSI0 (cpustate->peripheral_ram[A2O(0xffd0)])
#define CRBSSI0 (dsp56k_peripheral_ram[A2O(0xffd1)]) #define CRBSSI0 (cpustate->peripheral_ram[A2O(0xffd1)])
#define CRASSI1 (dsp56k_peripheral_ram[A2O(0xffd8)]) #define CRASSI1 (cpustate->peripheral_ram[A2O(0xffd8)])
#define CRBSSI1 (dsp56k_peripheral_ram[A2O(0xffd9)]) #define CRBSSI1 (cpustate->peripheral_ram[A2O(0xffd9)])
#define PLCR (dsp56k_peripheral_ram[A2O(0xffdc)]) #define PLCR (cpustate->peripheral_ram[A2O(0xffdc)])
#define BCR (dsp56k_peripheral_ram[A2O(0xffde)]) #define BCR (cpustate->peripheral_ram[A2O(0xffde)])
#define IPR (dsp56k_peripheral_ram[A2O(0xffdf)]) #define IPR (cpustate->peripheral_ram[A2O(0xffdf)])
#define PBD (dsp56k_peripheral_ram[A2O(0xffe2)]) #define PBD (cpustate->peripheral_ram[A2O(0xffe2)])
#define PCD (dsp56k_peripheral_ram[A2O(0xffe3)]) #define PCD (cpustate->peripheral_ram[A2O(0xffe3)])
#define HSR (dsp56k_peripheral_ram[A2O(0xffe4)]) #define HSR (cpustate->peripheral_ram[A2O(0xffe4)])
#define HTXHRX (dsp56k_peripheral_ram[A2O(0xffe5)]) #define HTXHRX (cpustate->peripheral_ram[A2O(0xffe5)])
#define COSR (dsp56k_peripheral_ram[A2O(0xffe8)]) #define COSR (cpustate->peripheral_ram[A2O(0xffe8)])
#define CRXCTX (dsp56k_peripheral_ram[A2O(0xffe9)]) #define CRXCTX (cpustate->peripheral_ram[A2O(0xffe9)])
#define TCR (dsp56k_peripheral_ram[A2O(0xffec)]) #define TCR (cpustate->peripheral_ram[A2O(0xffec)])
#define TCTR (dsp56k_peripheral_ram[A2O(0xffed)]) #define TCTR (cpustate->peripheral_ram[A2O(0xffed)])
#define TCPR (dsp56k_peripheral_ram[A2O(0xffee)]) #define TCPR (cpustate->peripheral_ram[A2O(0xffee)])
#define TPR (dsp56k_peripheral_ram[A2O(0xffef)]) #define TPR (cpustate->peripheral_ram[A2O(0xffef)])
#define TSRSSI0 (dsp56k_peripheral_ram[A2O(0xfff0)]) #define TSRSSI0 (cpustate->peripheral_ram[A2O(0xfff0)])
#define TRXSSI0 (dsp56k_peripheral_ram[A2O(0xfff1)]) #define TRXSSI0 (cpustate->peripheral_ram[A2O(0xfff1)])
#define RSMA0 (dsp56k_peripheral_ram[A2O(0xfff2)]) #define RSMA0 (cpustate->peripheral_ram[A2O(0xfff2)])
#define RSMB0 (dsp56k_peripheral_ram[A2O(0xfff3)]) #define RSMB0 (cpustate->peripheral_ram[A2O(0xfff3)])
#define TSMA0 (dsp56k_peripheral_ram[A2O(0xfff4)]) #define TSMA0 (cpustate->peripheral_ram[A2O(0xfff4)])
#define TSMB0 (dsp56k_peripheral_ram[A2O(0xfff5)]) #define TSMB0 (cpustate->peripheral_ram[A2O(0xfff5)])
#define TSRSSI1 (dsp56k_peripheral_ram[A2O(0xfff8)]) #define TSRSSI1 (cpustate->peripheral_ram[A2O(0xfff8)])
#define TRXSSI1 (dsp56k_peripheral_ram[A2O(0xfff9)]) #define TRXSSI1 (cpustate->peripheral_ram[A2O(0xfff9)])
#define RSMA1 (dsp56k_peripheral_ram[A2O(0xfffa)]) #define RSMA1 (cpustate->peripheral_ram[A2O(0xfffa)])
#define RSMB1 (dsp56k_peripheral_ram[A2O(0xfffb)]) #define RSMB1 (cpustate->peripheral_ram[A2O(0xfffb)])
#define TSMA1 (dsp56k_peripheral_ram[A2O(0xfffc)]) #define TSMA1 (cpustate->peripheral_ram[A2O(0xfffc)])
#define TSMB1 (dsp56k_peripheral_ram[A2O(0xfffd)]) #define TSMB1 (cpustate->peripheral_ram[A2O(0xfffd)])
/* Interrupt priority register (IPR) bits */ /* Interrupt priority register (IPR) bits */
void IPR_set(dsp56k_core* cpustate, UINT16 value); void IPR_set(dsp56k_core* cpustate, UINT16 value);
@ -235,9 +235,11 @@ void PCDDR_set(dsp56k_core* cpustate, UINT16 value);
/* Port C Dtaa Register (PCD) */ /* Port C Dtaa Register (PCD) */
void PCD_set(dsp56k_core* cpustate, UINT16 value); void PCD_set(dsp56k_core* cpustate, UINT16 value);
} // namespace DSP56K
READ16_HANDLER( peripheral_register_r ); READ16_HANDLER( peripheral_register_r );
WRITE16_HANDLER( peripheral_register_w ); WRITE16_HANDLER( peripheral_register_w );
READ16_HANDLER( program_r );
WRITE16_HANDLER( program_w );
} // namespace DSP56K
#endif #endif

5
src/emu/cpu/dsp56k/dsp56pcu.c
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@ -1,9 +1,6 @@
#include "dsp56pcu.h" #include "dsp56pcu.h"
#include "dsp56mem.h" #include "dsp56mem.h"
extern UINT16 *dsp56k_peripheral_ram;
extern UINT16 *dsp56k_program_ram;
namespace DSP56K namespace DSP56K
{ {
@ -149,7 +146,7 @@ void pcu_reset(dsp56k_core* cpustate)
/* P:$cfff -> Internal P:$07ff high byte */ /* P:$cfff -> Internal P:$07ff high byte */
UINT8 mem_value_low = memory_read_byte_16le(cpustate->program, mem_offset); /* TODO: IS THIS READING RIGHT? */ UINT8 mem_value_low = memory_read_byte_16le(cpustate->program, mem_offset); /* TODO: IS THIS READING RIGHT? */
UINT8 mem_value_high = memory_read_byte_16be(cpustate->program, mem_offset); UINT8 mem_value_high = memory_read_byte_16be(cpustate->program, mem_offset);
dsp56k_program_ram[i] = (mem_value_high << 8) || mem_value_low; cpustate->program_ram[i] = (mem_value_high << 8) || mem_value_low;
} }
/* HACK - Set the PC to 0x0000 as per the boot ROM. */ /* HACK - Set the PC to 0x0000 as per the boot ROM. */