mirror of
https://github.com/holub/mame
synced 2025-06-03 03:16:30 +03:00
-sbus: Fixed a minor typo in the description of the Artecon serial/parallel board, nw
-sparc: Added stubbed-out IFLUSH instruction to fix illegal instruction exceptions in SunOS 4.1.4 installer. [Ryan Holtz] -nscsi: Added optional verbose logging of data transfers. [Ryan Holtz] -timekpr: Switched to use the new logmacro system. [Ryan Holtz] -sun4c: Can now successfully install SunOS 4.1.4. [Ryan Holtz] * Hooked up auxiliary I/O port. * Hooked up bus timeout on unmapped RAM ranges, per documentation. * Changed FDC type to i82072, per documentation. * Silenced a ton of logging. * Reworked IRQ handling and added support for software interrupts.
This commit is contained in:
mooglyguy
parent
dfcf8538f7
commit
88dce5bbb3
@ -30,7 +30,7 @@ void sbus_cards(device_slot_interface &device)
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device.option_add("turbogxp", SBUS_TURBOGXP); /* Sun TurboGX+ 8-bit color display board */
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device.option_add("sunpc", SBUS_SUNPC); /* Sun SunPC 5x86 Accelerator board */
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device.option_add("hme", SBUS_HME); /* Sun SunSwift 10/100 + Fast Wide SCSI "Colossus" board */
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device.option_add("sb300p", SBUS_SB300P); /* Artecon CB300P 3-serial/4-parallel board */
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device.option_add("sb300p", SBUS_SB300P); /* Artecon CB300P 3-serial/1-parallel board */
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}
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DEFINE_DEVICE_TYPE(SBUS_SLOT, sbus_slot_device, "sbus_slot", "Sun SBus Slot")
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@ -184,9 +184,12 @@ void mb86901_device::device_start()
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m_alu_op3_assigned[OP3_WRTBR] = true;
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m_alu_op3_assigned[OP3_FPOP1] = true;
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m_alu_op3_assigned[OP3_FPOP2] = true;
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m_alu_op3_assigned[OP3_CPOP1] = true;
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m_alu_op3_assigned[OP3_CPOP2] = true;
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m_alu_op3_assigned[OP3_JMPL] = true;
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m_alu_op3_assigned[OP3_RETT] = true;
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m_alu_op3_assigned[OP3_TICC] = true;
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m_alu_op3_assigned[OP3_IFLUSH] = true;
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m_alu_op3_assigned[OP3_SAVE] = true;
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m_alu_op3_assigned[OP3_RESTORE] = true;
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#if SPARCV8
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@ -198,8 +201,6 @@ void mb86901_device::device_start()
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m_alu_op3_assigned[OP3_SMULCC] = true;
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m_alu_op3_assigned[OP3_UDIVCC] = true;
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m_alu_op3_assigned[OP3_SDIVCC] = true;
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m_alu_op3_assigned[OP3_CPOP1] = true;
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m_alu_op3_assigned[OP3_CPOP2] = true;
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#endif
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m_program = &space(AS_PROGRAM);
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@ -1489,6 +1490,10 @@ void mb86901_device::execute_group2(uint32_t op)
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execute_ticc(op);
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break;
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case OP3_IFLUSH:
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// Ignored
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break;
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case OP3_SAVE:
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case OP3_RESTORE:
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execute_saverestore(op);
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@ -2941,7 +2946,7 @@ void mb86901_device::execute_step()
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m_execute_mode = 0;
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m_error_mode = 0;
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m_reset_mode = 1;
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printf("Entering reset mode\n");
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//printf("Entering reset mode\n");
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return;
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}
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else if ((PSR & PSR_ET_MASK) && (m_bp_irl == 15 || m_bp_irl > ((PSR & PSR_PIL_MASK) >> PSR_PIL_SHIFT)))
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@ -3028,7 +3033,7 @@ void mb86901_device::reset_step()
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m_execute_mode = 1;
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m_trap = 1;
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m_reset_trap = 1;
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printf("m_bp_reset_in is false, resetting\n");
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//printf("m_bp_reset_in is false, resetting\n");
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}
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}
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@ -208,6 +208,7 @@
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#define OP3_JMPL 56
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#define OP3_RETT 57
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#define OP3_TICC 58
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#define OP3_IFLUSH 59
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#define OP3_SAVE 60
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#define OP3_RESTORE 61
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@ -6,8 +6,9 @@
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#define LOG_GENERAL (1U << 0)
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#define LOG_STATE (1U << 1)
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#define LOG_CONTROL (1U << 2)
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#define LOG_DATA (1U << 3)
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//#define VERBOSE (LOG_GENERAL | LOG_STATE | LOG_CONTROL)
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//#define VERBOSE (LOG_GENERAL | LOG_STATE | LOG_CONTROL | LOG_DATA)
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#define VERBOSE (LOG_GENERAL)
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#include "logmacro.h"
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@ -465,6 +466,7 @@ uint8_t nscsi_full_device::scsi_get_data(int id, int pos)
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{
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switch(id) {
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case SBUF_MAIN:
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LOGMASKED(LOG_DATA, "scsi_get_data MAIN, id:%d pos:%d data:%02x %c\n", id, pos, scsi_cmdbuf[pos], scsi_cmdbuf[pos] >= 0x20 && scsi_cmdbuf[pos] < 0x7f ? (char)scsi_cmdbuf[pos] : ' ');
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return scsi_cmdbuf[pos];
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case SBUF_SENSE:
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return scsi_sense_buffer[pos];
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@ -477,6 +479,7 @@ void nscsi_full_device::scsi_put_data(int id, int pos, uint8_t data)
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{
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switch(id) {
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case SBUF_MAIN:
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LOGMASKED(LOG_DATA, "nscsi_bus: scsi_put_data MAIN, id:%d pos:%d data:%02x %c\n", id, pos, data, data >= 0x20 && data < 0x7f ? (char)data : ' ');
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scsi_cmdbuf[pos] = data;
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break;
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case SBUF_SENSE:
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@ -6,6 +6,7 @@
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#define LOG_GENERAL (1U << 0)
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#define LOG_COMMAND (1U << 1)
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#define LOG_DATA (1U << 2)
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#define VERBOSE (LOG_GENERAL)
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@ -60,21 +61,30 @@ MACHINE_CONFIG_END
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uint8_t nscsi_harddisk_device::scsi_get_data(int id, int pos)
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{
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uint8_t data = 0;
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if(id != 2)
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return nscsi_full_device::scsi_get_data(id, pos);
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int clba = lba + pos / bytes_per_sector;
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if(clba != cur_lba) {
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cur_lba = clba;
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if(!hard_disk_read(harddisk, cur_lba, block)) {
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LOG("HD READ ERROR !\n");
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memset(block, 0, sizeof(block));
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}
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{
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data = nscsi_full_device::scsi_get_data(id, pos);
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}
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return block[pos % bytes_per_sector];
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else
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{
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int clba = lba + pos / bytes_per_sector;
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if(clba != cur_lba) {
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cur_lba = clba;
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if(!hard_disk_read(harddisk, cur_lba, block)) {
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LOG("HD READ ERROR !\n");
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memset(block, 0, sizeof(block));
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}
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}
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data = block[pos % bytes_per_sector];
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}
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LOGMASKED(LOG_DATA, "nscsi_hd: scsi_get_data, id:%d pos:%d data:%02x %c\n", id, pos, data, data >= 0x20 && data < 0x7f ? (char)data : ' ');
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return data;
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}
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void nscsi_harddisk_device::scsi_put_data(int id, int pos, uint8_t data)
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{
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LOGMASKED(LOG_DATA, "nscsi_hd: scsi_put_data, id:%d pos:%d data:%02x %c\n", id, pos, data, data >= 0x20 && data < 0x7f ? (char)data : ' ');
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if(id != 2) {
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nscsi_full_device::scsi_put_data(id, pos, data);
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return;
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@ -18,6 +18,12 @@
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#include "machine/timekpr.h"
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#include "machine/timehelp.h"
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#define LOG_GENERAL (1U << 0)
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#define LOG_TICKS (1U << 1)
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#define VERBOSE (0)
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#include "logmacro.h"
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// device type definition
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DEFINE_DEVICE_TYPE(M48T02, m48t02_device, "m48t02", "M48T02 Timekeeper")
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DEFINE_DEVICE_TYPE(M48T35, m48t35_device, "m48t35", "M48T35 Timekeeper")
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@ -274,7 +280,7 @@ void timekeeper_device::counters_from_ram()
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void timekeeper_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
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{
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logerror("Tick\n");
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LOGMASKED(LOG_TICKS, "Tick\n");
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if( ( m_seconds & SECONDS_ST ) != 0 ||
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( m_control & CONTROL_W ) != 0 )
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{
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@ -370,7 +376,7 @@ WRITE8_MEMBER(timekeeper_device::watchdog_write)
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WRITE8_MEMBER( timekeeper_device::write )
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{
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logerror("timekeeper_device::write: %04x = %02x\n", offset, data);
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LOGMASKED(LOG_GENERAL, "timekeeper_device::write: %04x = %02x\n", offset, data);
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if( offset == m_offset_control )
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{
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if( ( m_control & CONTROL_W ) != 0 &&
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@ -429,7 +435,7 @@ READ8_MEMBER( timekeeper_device::read )
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m_reset_cb(CLEAR_LINE);
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m_irq_cb(CLEAR_LINE);
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}
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logerror("timekeeper_device::read: %04x (%02x)\n", offset, result);
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LOGMASKED(LOG_GENERAL, "timekeeper_device::read: %04x (%02x)\n", offset, result);
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return result;
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}
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@ -490,6 +490,13 @@
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#define DMA_BYTE_COUNT (2)
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#define DMA_XTAL (25_MHz_XTAL)
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#define AUXIO_DENSITY (0x20)
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#define AUXIO_DISK_CHG (0x10)
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#define AUXIO_DRIVE_SEL (0x08)
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#define AUXIO_TC (0x04)
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#define AUXIO_EJECT (0x02)
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#define AUXIO_LED (0x01)
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namespace
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{
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const sparc_disassembler::asi_desc_map::value_type sun4_asi_desc[] = {
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@ -542,6 +549,7 @@ public:
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, m_scc1(*this, SCC1_TAG)
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, m_scc2(*this, SCC2_TAG)
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, m_fdc(*this, FDC_TAG)
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, m_floppy(*this, FDC_TAG":0")
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, m_lance(*this, LANCE_TAG)
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, m_scsibus(*this, "scsibus")
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, m_scsi(*this, "scsibus:7:ncr53c90a")
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@ -579,6 +587,8 @@ private:
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DECLARE_WRITE32_MEMBER( sun4c_mmu_w );
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DECLARE_READ32_MEMBER( ram_r );
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DECLARE_WRITE32_MEMBER( ram_w );
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DECLARE_READ32_MEMBER( timeout_r );
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DECLARE_WRITE32_MEMBER( timeout_w );
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DECLARE_READ32_MEMBER( ss1_sl0_id );
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DECLARE_READ32_MEMBER( timer_r );
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DECLARE_WRITE32_MEMBER( timer_w );
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@ -586,6 +596,8 @@ private:
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DECLARE_WRITE8_MEMBER( irq_w );
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DECLARE_READ8_MEMBER( fdc_r );
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DECLARE_WRITE8_MEMBER( fdc_w );
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DECLARE_READ8_MEMBER( auxio_r );
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DECLARE_WRITE8_MEMBER( auxio_w );
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DECLARE_READ32_MEMBER( dma_r );
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DECLARE_WRITE32_MEMBER( dma_w );
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DECLARE_READ32_MEMBER( lance_dma_r ); // TODO: Should be 16 bits
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@ -598,6 +610,8 @@ private:
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DECLARE_WRITE_LINE_MEMBER( scc1_int );
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DECLARE_WRITE_LINE_MEMBER( scc2_int );
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DECLARE_WRITE_LINE_MEMBER( fdc_irq );
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DECLARE_FLOPPY_FORMATS( floppy_formats );
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void ncr53c90a(device_t *device);
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@ -622,7 +636,8 @@ private:
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required_device<z80scc_device> m_scc1;
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required_device<z80scc_device> m_scc2;
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required_device<n82077aa_device> m_fdc;
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required_device<i82072_device> m_fdc;
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required_device<floppy_connector> m_floppy;
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required_device<am79c90_device> m_lance;
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required_device<nscsi_bus_device> m_scsibus;
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required_device<ncr53c90a_device> m_scsi;
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@ -636,6 +651,7 @@ private:
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uint32_t *m_rom_ptr;
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uint32_t m_context;
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uint8_t m_system_enable;
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uint8_t m_auxio;
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uint32_t m_buserr[4];
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uint32_t m_counter[4];
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uint32_t m_dma[4];
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@ -643,13 +659,15 @@ private:
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bool m_dma_tc_read;
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uint32_t m_dma_pack_register;
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int m_scsi_irq;
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int m_fdc_irq;
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uint32_t *m_ram_ptr;
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uint8_t m_segmap[16][4096];
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uint32_t m_pagemap[16384];
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uint32_t m_cachetags[0x4000];
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uint32_t m_cachedata[0x4000];
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uint32_t m_ram_size, m_ram_size_words;
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uint32_t m_ram_size;
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uint32_t m_ram_size_words;
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uint8_t m_ctx_mask; // SS2 is sun4c but has 16 contexts; most have 8
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uint8_t m_pmeg_mask; // SS2 is sun4c but has 16384 PTEs; most have 8192
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uint8_t m_irq_reg; // IRQ control
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@ -706,7 +724,7 @@ uint32_t sun4_state::read_insn_data_4c(uint8_t asi, address_space &space, uint32
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return m_type1space->read32(space, tmp, mem_mask);
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default:
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printf("sun4c: access to memory type not defined in sun4c\n");
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logerror("sun4c: access to memory type not defined in sun4c\n");
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m_maincpu->set_mae();
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m_buserr[0] = 0x20;
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m_buserr[1] = offset << 2;
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@ -717,7 +735,7 @@ uint32_t sun4_state::read_insn_data_4c(uint8_t asi, address_space &space, uint32
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{
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if (!machine().side_effects_disabled())
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{
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printf("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
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logerror("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
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m_maincpu->set_mae();
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m_buserr[0] |= 0x80; // invalid PTE
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m_buserr[0] &= ~0x8000; // read
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@ -752,7 +770,7 @@ void sun4_state::write_insn_data_4c(uint8_t asi, address_space &space, uint32_t
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{
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if ((!(m_pagemap[entry] & PM_WRITEMASK)) || ((m_pagemap[entry] & PM_SYSMASK) && !(asi & 1)))
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{
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printf("sun4c: write protect MMU error (PC=%x)\n", m_maincpu->pc());
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logerror("sun4c: write protect MMU error (PC=%x)\n", m_maincpu->pc());
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m_buserr[0] |= 0x8040; // write, protection error
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m_buserr[1] = offset<<2;
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m_maincpu->set_mae();
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@ -777,7 +795,7 @@ void sun4_state::write_insn_data_4c(uint8_t asi, address_space &space, uint32_t
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m_type1space->write32(space, tmp, data, mem_mask);
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return;
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default:
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printf("sun4c: access to memory type not defined\n");
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logerror("sun4c: access to memory type not defined\n");
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m_maincpu->set_mae();
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m_buserr[0] = 0x8020;
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m_buserr[1] = offset << 2;
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@ -786,7 +804,7 @@ void sun4_state::write_insn_data_4c(uint8_t asi, address_space &space, uint32_t
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}
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else
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{
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printf("sun4c: INVALID PTE entry %d %08x accessed! data=%08x vaddr=%x PC=%x\n", entry, m_pagemap[entry], data, offset <<2, m_maincpu->pc());
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logerror("sun4c: INVALID PTE entry %d %08x accessed! data=%08x vaddr=%x PC=%x\n", entry, m_pagemap[entry], data, offset <<2, m_maincpu->pc());
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m_maincpu->set_mae();
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m_buserr[0] |= 0x8080; // write cycle, invalid PTE
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m_buserr[1] = offset<<2;
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@ -861,7 +879,7 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
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case 0: // IDPROM - TODO: SPARCstation-1 does not have an ID prom and a timeout should occur.
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default:
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printf("sun4c: ASI 2 space unhandled read @ %x (PC=%x)\n", offset<<2, m_maincpu->pc());
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logerror("sun4c: ASI 2 space unhandled read @ %x (PC=%x)\n", offset<<2, m_maincpu->pc());
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return 0;
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}
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break;
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@ -894,11 +912,11 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
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return read_insn_data_4c(asi, space, offset, mem_mask);
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default:
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if (!machine().side_effects_disabled()) printf("sun4c: ASI %d unhandled read @ %x (PC=%x)\n", asi, offset<<2, m_maincpu->pc());
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if (!machine().side_effects_disabled()) logerror("sun4c: ASI %d unhandled read @ %x (PC=%x)\n", asi, offset<<2, m_maincpu->pc());
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return 0;
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}
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printf("sun4c: read asi %d byte offset %x, PC = %x\n", asi, offset << 2, m_maincpu->pc());
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logerror("sun4c: read asi %d byte offset %x, PC = %x\n", asi, offset << 2, m_maincpu->pc());
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return 0;
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}
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@ -939,7 +957,7 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w )
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return;
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case 6: // bus error
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printf("%08x to bus error @ %x, mask %08x\n", data, offset, mem_mask);
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logerror("%08x to bus error @ %x, mask %08x\n", data, offset, mem_mask);
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m_buserr[offset & 0xf] = data;
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return;
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@ -964,7 +982,7 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w )
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case 0: // IDPROM
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default:
|
||||
printf("sun4c: ASI 2 space unhandled write %x @ %x (mask %08x, PC=%x, shift %x)\n", data, offset<<2, mem_mask, m_maincpu->pc(), offset>>26);
|
||||
logerror("sun4c: ASI 2 space unhandled write %x @ %x (mask %08x, PC=%x, shift %x)\n", data, offset<<2, mem_mask, m_maincpu->pc(), offset>>26);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
@ -1003,7 +1021,7 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w )
|
||||
return;
|
||||
}
|
||||
|
||||
printf("sun4c: %08x to asi %d byte offset %x, PC = %x, mask = %08x\n", data, asi, offset << 2, m_maincpu->pc(), mem_mask);
|
||||
logerror("sun4c: %08x to asi %d byte offset %x, PC = %x, mask = %08x\n", data, asi, offset << 2, m_maincpu->pc(), mem_mask);
|
||||
}
|
||||
|
||||
// -----------------------------------------------------------------
|
||||
@ -1038,7 +1056,7 @@ uint32_t sun4_state::read_insn_data(uint8_t asi, address_space &space, uint32_t
|
||||
return m_type1space->read32(space, tmp, mem_mask);
|
||||
|
||||
default:
|
||||
printf("sun4: access to unhandled memory type\n");
|
||||
logerror("sun4: access to unhandled memory type\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
@ -1046,7 +1064,7 @@ uint32_t sun4_state::read_insn_data(uint8_t asi, address_space &space, uint32_t
|
||||
{
|
||||
if (!machine().side_effects_disabled())
|
||||
{
|
||||
printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
|
||||
logerror("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
|
||||
m_maincpu->set_mae();
|
||||
m_buserr[0] |= 0x80; // invalid PTE
|
||||
m_buserr[0] &= ~0x8000; // read
|
||||
@ -1098,13 +1116,13 @@ void sun4_state::write_insn_data(uint8_t asi, address_space &space, uint32_t off
|
||||
return;
|
||||
|
||||
default:
|
||||
printf("sun4: access to memory type not defined in sun4c\n");
|
||||
logerror("sun4: access to memory type not defined in sun4c\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("sun4: INVALID PTE entry %d %08x accessed! data=%08x vaddr=%x PC=%x\n", entry, m_pagemap[entry], data, offset <<2, m_maincpu->pc());
|
||||
logerror("sun4: INVALID PTE entry %d %08x accessed! data=%08x vaddr=%x PC=%x\n", entry, m_pagemap[entry], data, offset <<2, m_maincpu->pc());
|
||||
//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
|
||||
//m_buserr[0] = 0x8; // invalid PTE
|
||||
//m_buserr[1] = offset<<2;
|
||||
@ -1160,7 +1178,7 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
|
||||
|
||||
case 0:
|
||||
default:
|
||||
printf("sun4: ASI 2 space unhandled read @ %x (PC=%x)\n", offset<<2, m_maincpu->pc());
|
||||
logerror("sun4: ASI 2 space unhandled read @ %x (PC=%x)\n", offset<<2, m_maincpu->pc());
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
@ -1196,11 +1214,11 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
|
||||
return read_insn_data(asi, space, offset, mem_mask);
|
||||
|
||||
default:
|
||||
if (!machine().side_effects_disabled()) printf("sun4: ASI %d unhandled read @ %x (PC=%x)\n", asi, offset<<2, m_maincpu->pc());
|
||||
if (!machine().side_effects_disabled()) logerror("sun4: ASI %d unhandled read @ %x (PC=%x)\n", asi, offset<<2, m_maincpu->pc());
|
||||
return 0;
|
||||
}
|
||||
|
||||
printf("sun4: read asi %d byte offset %x, PC = %x\n", asi, offset << 2, m_maincpu->pc());
|
||||
logerror("sun4: read asi %d byte offset %x, PC = %x\n", asi, offset << 2, m_maincpu->pc());
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1279,7 +1297,7 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
|
||||
|
||||
case 0: // IDPROM
|
||||
default:
|
||||
printf("sun4: ASI 2 space unhandled write %x @ %x (mask %08x, PC=%x)\n", data, offset<<2, mem_mask, m_maincpu->pc());
|
||||
logerror("sun4: ASI 2 space unhandled write %x @ %x (mask %08x, PC=%x)\n", data, offset<<2, mem_mask, m_maincpu->pc());
|
||||
return;
|
||||
}
|
||||
break;
|
||||
@ -1395,9 +1413,11 @@ void sun4_state::machine_reset()
|
||||
{
|
||||
m_context = 0;
|
||||
m_system_enable = 0;
|
||||
m_auxio = 0xc0;
|
||||
m_irq_reg = 0;
|
||||
m_scc1_int = m_scc2_int = 0;
|
||||
m_scsi_irq = 0;
|
||||
m_fdc_irq = 0;
|
||||
m_dma_irq = false;
|
||||
m_dma_tc_read = false;
|
||||
m_dma_pack_register = 0;
|
||||
@ -1433,6 +1453,21 @@ void sun4_state::machine_start()
|
||||
m_reset_timer->adjust(attotime::never);
|
||||
}
|
||||
|
||||
READ32_MEMBER( sun4_state::timeout_r )
|
||||
{
|
||||
m_buserr[0] = 0x20; // read timeout
|
||||
m_buserr[1] = 0x04000000 + (offset << 2);
|
||||
m_maincpu->set_mae();
|
||||
return ~0;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( sun4_state::timeout_w )
|
||||
{
|
||||
m_buserr[0] = 0x8020; // write timeout
|
||||
m_buserr[1] = 0x04000000 + (offset << 2);
|
||||
m_maincpu->set_mae();
|
||||
}
|
||||
|
||||
READ32_MEMBER( sun4_state::ram_r )
|
||||
{
|
||||
//printf("ram_r: @ %08x (mask %08x)\n", offset<<2, mem_mask);
|
||||
@ -1511,6 +1546,7 @@ WRITE32_MEMBER( sun4_state::ram_w )
|
||||
void sun4_state::type0space_map(address_map &map)
|
||||
{
|
||||
map(0x00000000, 0x03ffffff).rw(FUNC(sun4_state::ram_r), FUNC(sun4_state::ram_w));
|
||||
map(0x04000000, 0x0fffffff).rw(FUNC(sun4_state::timeout_r), FUNC(sun4_state::timeout_w));
|
||||
}
|
||||
|
||||
void sun4_state::type1space_map(address_map &map)
|
||||
@ -1522,6 +1558,7 @@ void sun4_state::type1space_map(address_map &map)
|
||||
map(0x05000000, 0x05000003).rw(FUNC(sun4_state::irq_r), FUNC(sun4_state::irq_w));
|
||||
map(0x06000000, 0x0607ffff).rom().region("user1", 0);
|
||||
map(0x07200000, 0x07200003).rw(FUNC(sun4_state::fdc_r), FUNC(sun4_state::fdc_w));
|
||||
map(0x07400003, 0x07400003).rw(FUNC(sun4_state::auxio_r), FUNC(sun4_state::auxio_w));
|
||||
map(0x08000000, 0x08000003).r(FUNC(sun4_state::ss1_sl0_id)); // slot 0 contains SCSI/DMA/Ethernet
|
||||
map(0x08400000, 0x0840000f).rw(FUNC(sun4_state::dma_r), FUNC(sun4_state::dma_w));
|
||||
map(0x08800000, 0x0880002f).m(m_scsi, FUNC(ncr53c90a_device::map)).umask32(0xff000000);
|
||||
@ -1549,11 +1586,9 @@ READ8_MEMBER( sun4_state::fdc_r )
|
||||
{
|
||||
case 0: // Main Status (R)
|
||||
return m_fdc->msr_r(space, 0, 0xff);
|
||||
break;
|
||||
|
||||
case 1: // FIFO Data Port (R)
|
||||
return m_fdc->fifo_r(space, 0, 0xff);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
@ -1579,6 +1614,27 @@ WRITE8_MEMBER( sun4_state::fdc_w )
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER( sun4_state::auxio_r )
|
||||
{
|
||||
logerror("%s: auxio_r: %02x\n", machine().describe_context(), m_auxio);
|
||||
return m_auxio;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( sun4_state::auxio_w )
|
||||
{
|
||||
logerror("%s: auxio_w: %02x, drive_sel:%d tc:%d eject:%d LED:%d\n", machine().describe_context(), data, BIT(data, 3), BIT(data, 2), BIT(data, 1), BIT(data, 0));
|
||||
m_auxio = (m_auxio & 0xf0) | (data & 0x0f);
|
||||
if (!(m_auxio & AUXIO_DRIVE_SEL))
|
||||
{
|
||||
m_auxio &= ~(AUXIO_DENSITY | AUXIO_DISK_CHG);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_auxio |= AUXIO_DISK_CHG; // Report no disk inserted
|
||||
m_fdc->tc_w(data & AUXIO_TC);
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER( sun4_state::irq_r )
|
||||
{
|
||||
return m_irq_reg;
|
||||
@ -1586,18 +1642,45 @@ READ8_MEMBER( sun4_state::irq_r )
|
||||
|
||||
WRITE8_MEMBER( sun4_state::irq_w )
|
||||
{
|
||||
printf("%02x to IRQ\n", data);
|
||||
|
||||
const uint8_t old_irq = m_irq_reg;
|
||||
m_irq_reg = data;
|
||||
const uint8_t changed = old_irq ^ data;
|
||||
|
||||
m_maincpu->set_input_line(SPARC_IRQ12, ((m_scc1_int || m_scc2_int) && (m_irq_reg & 0x01)) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (!(m_irq_reg & 0x01))
|
||||
m_maincpu->set_input_line(SPARC_NMI, CLEAR_LINE);
|
||||
logerror("%02x to IRQ, %02x changed\n", data, changed);
|
||||
|
||||
if (!changed)
|
||||
return;
|
||||
|
||||
if (BIT(changed, 0))
|
||||
{
|
||||
if (BIT(m_irq_reg, 7) && BIT(m_counter[2] | m_counter[3], 31))
|
||||
m_maincpu->set_input_line(SPARC_IRQ14, BIT(data, 0) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(m_irq_reg, 5) && BIT(m_counter[0] | m_counter[1], 31))
|
||||
m_maincpu->set_input_line(SPARC_IRQ10, BIT(data, 0) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(m_irq_reg, 3))
|
||||
m_maincpu->set_input_line(SPARC_IRQ6, BIT(data, 0) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(m_irq_reg, 2))
|
||||
m_maincpu->set_input_line(SPARC_IRQ4, BIT(data, 0) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(m_irq_reg, 1))
|
||||
m_maincpu->set_input_line(SPARC_IRQ1, BIT(data, 0) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
else if (BIT(m_irq_reg, 0))
|
||||
{
|
||||
if (BIT(changed, 7) && BIT(m_counter[2] | m_counter[3], 31))
|
||||
m_maincpu->set_input_line(SPARC_IRQ14, BIT(m_irq_reg, 7) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(changed, 5) && BIT(m_counter[0] | m_counter[1], 31))
|
||||
m_maincpu->set_input_line(SPARC_IRQ10, BIT(m_irq_reg, 5) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(changed, 3))
|
||||
m_maincpu->set_input_line(SPARC_IRQ6, BIT(m_irq_reg, 3) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(changed, 2))
|
||||
m_maincpu->set_input_line(SPARC_IRQ4, BIT(m_irq_reg, 2) ? ASSERT_LINE : CLEAR_LINE);
|
||||
if (BIT(changed, 1))
|
||||
m_maincpu->set_input_line(SPARC_IRQ1, BIT(m_irq_reg, 1) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( sun4_state::scc1_int )
|
||||
{
|
||||
logerror("scc1\n");
|
||||
m_scc1_int = state;
|
||||
|
||||
m_maincpu->set_input_line(SPARC_IRQ12, ((m_scc1_int || m_scc2_int) && (m_irq_reg & 0x01)) ? ASSERT_LINE : CLEAR_LINE);
|
||||
@ -1605,7 +1688,6 @@ WRITE_LINE_MEMBER( sun4_state::scc1_int )
|
||||
|
||||
WRITE_LINE_MEMBER( sun4_state::scc2_int )
|
||||
{
|
||||
logerror("scc2\n");
|
||||
m_scc2_int = state;
|
||||
|
||||
m_maincpu->set_input_line(SPARC_IRQ12, ((m_scc1_int || m_scc2_int) && (m_irq_reg & 0x01)) ? ASSERT_LINE : CLEAR_LINE);
|
||||
@ -1623,7 +1705,6 @@ void sun4_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
|
||||
start_timer(0);
|
||||
if ((m_irq_reg & 0x21) == 0x21)
|
||||
{
|
||||
logerror("t0\n");
|
||||
m_maincpu->set_input_line(SPARC_IRQ10, ASSERT_LINE);
|
||||
//printf("Taking INT10\n");
|
||||
}
|
||||
@ -1637,7 +1718,6 @@ void sun4_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
|
||||
//m_c1_timer->adjust(attotime::never);
|
||||
if ((m_irq_reg & 0x81) == 0x81)
|
||||
{
|
||||
logerror("t1\n");
|
||||
m_maincpu->set_input_line(SPARC_IRQ14, ASSERT_LINE);
|
||||
//printf("Taking INT14\n");
|
||||
}
|
||||
@ -1646,7 +1726,7 @@ void sun4_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
|
||||
case TIMER_RESET:
|
||||
m_reset_timer->adjust(attotime::never);
|
||||
m_maincpu->set_input_line(SPARC_RESET, CLEAR_LINE);
|
||||
printf("Clearing reset line\n");
|
||||
//printf("Clearing reset line\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -1665,7 +1745,6 @@ READ32_MEMBER( sun4_state::timer_r )
|
||||
//printf("Read timer limit 0 (%08x) @ %x, mask %08x\n", ret, m_maincpu->pc(), mem_mask);
|
||||
m_counter[0] &= ~0x80000000;
|
||||
m_counter[1] &= ~0x80000000;
|
||||
logerror("tc0\n");
|
||||
m_maincpu->set_input_line(SPARC_IRQ10, CLEAR_LINE);
|
||||
}
|
||||
|
||||
@ -1678,7 +1757,6 @@ READ32_MEMBER( sun4_state::timer_r )
|
||||
//printf("Read timer limit 1 (%08x) @ %x, mask %08x\n", ret, m_maincpu->pc(), mem_mask);
|
||||
m_counter[2] &= ~0x80000000;
|
||||
m_counter[3] &= ~0x80000000;
|
||||
logerror("tc1\n");
|
||||
m_maincpu->set_input_line(SPARC_IRQ14, CLEAR_LINE);
|
||||
}
|
||||
return ret;
|
||||
@ -1947,6 +2025,17 @@ WRITE_LINE_MEMBER( sun4_state::scsi_drq )
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( sun4_state::fdc_irq )
|
||||
{
|
||||
int old_irq = m_fdc_irq;
|
||||
m_fdc_irq = state;
|
||||
if (old_irq != m_fdc_irq)
|
||||
{
|
||||
logerror("fdc_irq %d\n", state);
|
||||
m_maincpu->set_input_line(SPARC_IRQ11, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
READ32_MEMBER( sun4_state::lance_dma_r )
|
||||
{
|
||||
if (m_arch == ARCH_SUN4)
|
||||
@ -2015,8 +2104,10 @@ MACHINE_CONFIG_START(sun4_state::sun4)
|
||||
|
||||
M48T02(config, TIMEKEEPER_TAG, 0);
|
||||
|
||||
MCFG_N82077AA_ADD(FDC_TAG, n82077aa_device::MODE_PS2)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:0", sun_floppies, "35hd", sun4_state::floppy_formats)
|
||||
I82072(config, m_fdc, 24_MHz_XTAL);
|
||||
m_fdc->set_ready_line_connected(false);
|
||||
m_fdc->intrq_wr_callback().set(FUNC(sun4_state::fdc_irq));
|
||||
FLOPPY_CONNECTOR(config, m_floppy, sun_floppies, "35hd", sun4_state::floppy_formats);
|
||||
|
||||
// MMU Type 0 device space
|
||||
ADDRESS_MAP_BANK(config, m_type0space).set_map(&sun4_state::type0space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
|
||||
@ -2075,8 +2166,10 @@ MACHINE_CONFIG_START(sun4_state::sun4c)
|
||||
|
||||
M48T02(config, TIMEKEEPER_TAG, 0);
|
||||
|
||||
MCFG_N82077AA_ADD(FDC_TAG, n82077aa_device::MODE_PS2)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:0", sun_floppies, "35hd", sun4_state::floppy_formats)
|
||||
I82072(config, m_fdc, 24_MHz_XTAL);
|
||||
m_fdc->set_ready_line_connected(false);
|
||||
m_fdc->intrq_wr_callback().set(FUNC(sun4_state::fdc_irq));
|
||||
FLOPPY_CONNECTOR(config, m_floppy, sun_floppies, "35hd", sun4_state::floppy_formats);
|
||||
|
||||
// MMU Type 0 device space
|
||||
ADDRESS_MAP_BANK(config, m_type0space).set_map(&sun4_state::type0space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user