mirror of
https://github.com/holub/mame
synced 2025-04-23 17:00:53 +03:00
minx.c: Get rid of pointers to member functions (nw)
This commit is contained in:
Wilbert Pol
parent
309361d038
commit
8911a52216
@ -177,14 +177,11 @@ UINT16 minx_cpu_device::rdop16()
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void minx_cpu_device::execute_run()
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{
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// UINT32 oldpc;
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UINT8 op;
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do
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{
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m_curpc = GET_MINX_PC;
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debugger_instruction_hook(this, m_curpc);
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// oldpc = GET_MINX_PC;
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if ( m_interrupt_pending )
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{
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@ -210,9 +207,7 @@ void minx_cpu_device::execute_run()
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}
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else
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{
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op = rdop();
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(this->*insnminx[op])();
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m_icount -= insnminx_cycles[op];
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execute_one();
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}
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} while ( m_icount > 0 );
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}
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@ -102,785 +102,12 @@ private:
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void JMP( UINT16 arg );
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void CALL( UINT16 arg );
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void minx_00();
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void minx_01();
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void minx_02();
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void minx_03();
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void minx_04();
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void minx_05();
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void minx_06();
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void minx_07();
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void minx_08();
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void minx_09();
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void minx_0A();
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void minx_0B();
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void minx_0C();
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void minx_0D();
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void minx_0E();
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void minx_0F();
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void minx_10();
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void minx_11();
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void minx_12();
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void minx_13();
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void minx_14();
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void minx_15();
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void minx_16();
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void minx_17();
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void minx_18();
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void minx_19();
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void minx_1A();
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void minx_1B();
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void minx_1C();
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void minx_1D();
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void minx_1E();
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void minx_1F();
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void minx_20();
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void minx_21();
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void minx_22();
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void minx_23();
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void minx_24();
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void minx_25();
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void minx_26();
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void minx_27();
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void minx_28();
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void minx_29();
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void minx_2A();
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void minx_2B();
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void minx_2C();
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void minx_2D();
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void minx_2E();
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void minx_2F();
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void minx_30();
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void minx_31();
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void minx_32();
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void minx_33();
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void minx_34();
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void minx_35();
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void minx_36();
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void minx_37();
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void minx_38();
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void minx_39();
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void minx_3A();
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void minx_3B();
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void minx_3C();
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void minx_3D();
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void minx_3E();
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void minx_3F();
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void minx_40();
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void minx_41();
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void minx_42();
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void minx_43();
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void minx_44();
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void minx_45();
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void minx_46();
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void minx_47();
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void minx_48();
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void minx_49();
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void minx_4A();
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void minx_4B();
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void minx_4C();
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void minx_4D();
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void minx_4E();
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void minx_4F();
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void minx_50();
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void minx_51();
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void minx_52();
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void minx_53();
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void minx_54();
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void minx_55();
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void minx_56();
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void minx_57();
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void minx_58();
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void minx_59();
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void minx_5A();
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void minx_5B();
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void minx_5C();
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void minx_5D();
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void minx_5E();
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void minx_5F();
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void minx_60();
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void minx_61();
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void minx_62();
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void minx_63();
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void minx_64();
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void minx_65();
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void minx_66();
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void minx_67();
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void minx_68();
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void minx_69();
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void minx_6A();
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void minx_6B();
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void minx_6C();
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void minx_6D();
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void minx_6E();
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void minx_6F();
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void minx_70();
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void minx_71();
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void minx_72();
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void minx_73();
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void minx_74();
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void minx_75();
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void minx_76();
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void minx_77();
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void minx_78();
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void minx_79();
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void minx_7A();
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void minx_7B();
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void minx_7C();
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void minx_7D();
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void minx_7E();
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void minx_7F();
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void minx_80();
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void minx_81();
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void minx_82();
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void minx_83();
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void minx_84();
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void minx_85();
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void minx_86();
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void minx_87();
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void minx_88();
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void minx_89();
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void minx_8A();
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void minx_8B();
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void minx_8C();
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void minx_8D();
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void minx_8E();
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void minx_8F();
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void minx_90();
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void minx_91();
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void minx_92();
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void minx_93();
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void minx_94();
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void minx_95();
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void minx_96();
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void minx_97();
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void minx_98();
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void minx_99();
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void minx_9A();
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void minx_9B();
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void minx_9C();
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void minx_9D();
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void minx_9E();
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void minx_9F();
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void minx_A0();
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void minx_A1();
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void minx_A2();
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void minx_A3();
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void minx_A4();
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void minx_A5();
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void minx_A6();
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void minx_A7();
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void minx_A8();
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void minx_A9();
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void minx_AA();
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void minx_AB();
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void minx_AC();
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void minx_AD();
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void minx_AE();
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void minx_AF();
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void minx_B0();
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void minx_B1();
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void minx_B2();
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void minx_B3();
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void minx_B4();
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void minx_B5();
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void minx_B6();
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void minx_B7();
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void minx_B8();
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void minx_B9();
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void minx_BA();
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void minx_BB();
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void minx_BC();
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void minx_BD();
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void minx_BE();
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void minx_BF();
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void minx_C0();
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void minx_C1();
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void minx_C2();
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void minx_C3();
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void minx_C4();
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void minx_C5();
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void minx_C6();
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void minx_C7();
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void minx_C8();
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void minx_C9();
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void minx_CA();
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void minx_CB();
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void minx_CC();
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void minx_CD();
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void minx_CE();
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void minx_CF();
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void minx_D0();
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void minx_D1();
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void minx_D2();
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void minx_D3();
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void minx_D4();
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void minx_D5();
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void minx_D6();
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void minx_D7();
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void minx_D8();
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void minx_D9();
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void minx_DA();
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void minx_DB();
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void minx_DC();
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void minx_DD();
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void minx_DE();
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void minx_DF();
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void minx_E0();
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void minx_E1();
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void minx_E2();
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void minx_E3();
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void minx_E4();
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void minx_E5();
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void minx_E6();
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void minx_E7();
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void minx_E8();
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void minx_E9();
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void minx_EA();
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void minx_EB();
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void minx_EC();
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void minx_ED();
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void minx_EE();
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void minx_EF();
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void minx_F0();
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void minx_F1();
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void minx_F2();
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void minx_F3();
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void minx_F4();
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void minx_F5();
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void minx_F6();
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void minx_F7();
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void minx_F8();
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void minx_F9();
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void minx_FA();
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void minx_FB();
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void minx_FC();
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void minx_FD();
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void minx_FE();
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void minx_FF();
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void execute_one();
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void execute_one_ce();
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void execute_one_cf();
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void minx_CE_00();
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void minx_CE_01();
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void minx_CE_02();
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void minx_CE_03();
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void minx_CE_04();
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void minx_CE_05();
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void minx_CE_06();
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void minx_CE_07();
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void minx_CE_08();
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void minx_CE_09();
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void minx_CE_0A();
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void minx_CE_0B();
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void minx_CE_0C();
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void minx_CE_0D();
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void minx_CE_0E();
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void minx_CE_0F();
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void minx_CE_10();
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void minx_CE_11();
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void minx_CE_12();
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void minx_CE_13();
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void minx_CE_14();
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void minx_CE_15();
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void minx_CE_16();
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void minx_CE_17();
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void minx_CE_18();
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void minx_CE_19();
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void minx_CE_1A();
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void minx_CE_1B();
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void minx_CE_1C();
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void minx_CE_1D();
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void minx_CE_1E();
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void minx_CE_1F();
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void minx_CE_20();
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void minx_CE_21();
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void minx_CE_22();
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void minx_CE_23();
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void minx_CE_24();
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void minx_CE_25();
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void minx_CE_26();
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void minx_CE_27();
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void minx_CE_28();
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void minx_CE_29();
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void minx_CE_2A();
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void minx_CE_2B();
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void minx_CE_2C();
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void minx_CE_2D();
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void minx_CE_2E();
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void minx_CE_2F();
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void minx_CE_30();
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void minx_CE_31();
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void minx_CE_32();
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void minx_CE_33();
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void minx_CE_34();
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void minx_CE_35();
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void minx_CE_36();
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void minx_CE_37();
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void minx_CE_38();
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void minx_CE_39();
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void minx_CE_3A();
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void minx_CE_3B();
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void minx_CE_3C();
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void minx_CE_3D();
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void minx_CE_3E();
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void minx_CE_3F();
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void minx_CE_40();
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void minx_CE_41();
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void minx_CE_42();
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void minx_CE_43();
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void minx_CE_44();
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void minx_CE_45();
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void minx_CE_46();
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void minx_CE_47();
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void minx_CE_48();
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void minx_CE_49();
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void minx_CE_4A();
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void minx_CE_4B();
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void minx_CE_4C();
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void minx_CE_4D();
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void minx_CE_4E();
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void minx_CE_4F();
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void minx_CE_50();
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void minx_CE_51();
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void minx_CE_52();
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void minx_CE_53();
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void minx_CE_54();
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void minx_CE_55();
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void minx_CE_56();
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void minx_CE_57();
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void minx_CE_58();
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void minx_CE_59();
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void minx_CE_5A();
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void minx_CE_5B();
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void minx_CE_5C();
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void minx_CE_5D();
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void minx_CE_5E();
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void minx_CE_5F();
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void minx_CE_60();
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void minx_CE_61();
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void minx_CE_62();
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void minx_CE_63();
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void minx_CE_64();
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void minx_CE_65();
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void minx_CE_66();
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void minx_CE_67();
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void minx_CE_68();
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void minx_CE_69();
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void minx_CE_6A();
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void minx_CE_6B();
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void minx_CE_6C();
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void minx_CE_6D();
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void minx_CE_6E();
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void minx_CE_6F();
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void minx_CE_70();
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void minx_CE_71();
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void minx_CE_72();
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void minx_CE_73();
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void minx_CE_74();
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void minx_CE_75();
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void minx_CE_76();
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void minx_CE_77();
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void minx_CE_78();
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void minx_CE_79();
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void minx_CE_7A();
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void minx_CE_7B();
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void minx_CE_7C();
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void minx_CE_7D();
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void minx_CE_7E();
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void minx_CE_7F();
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void minx_CE_80();
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void minx_CE_81();
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void minx_CE_82();
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void minx_CE_83();
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void minx_CE_84();
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void minx_CE_85();
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void minx_CE_86();
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void minx_CE_87();
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void minx_CE_88();
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void minx_CE_89();
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void minx_CE_8A();
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void minx_CE_8B();
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void minx_CE_8C();
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void minx_CE_8D();
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void minx_CE_8E();
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void minx_CE_8F();
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void minx_CE_90();
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void minx_CE_91();
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void minx_CE_92();
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void minx_CE_93();
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void minx_CE_94();
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void minx_CE_95();
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void minx_CE_96();
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void minx_CE_97();
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void minx_CE_98();
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void minx_CE_99();
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void minx_CE_9A();
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void minx_CE_9B();
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void minx_CE_9C();
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void minx_CE_9D();
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void minx_CE_9E();
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void minx_CE_9F();
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void minx_CE_A0();
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void minx_CE_A1();
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void minx_CE_A2();
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void minx_CE_A3();
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void minx_CE_A4();
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void minx_CE_A5();
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void minx_CE_A6();
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void minx_CE_A7();
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void minx_CE_A8();
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void minx_CE_A9();
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void minx_CE_AA();
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void minx_CE_AB();
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void minx_CE_AC();
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void minx_CE_AD();
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void minx_CE_AE();
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void minx_CE_AF();
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void minx_CE_B0();
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void minx_CE_B1();
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void minx_CE_B2();
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void minx_CE_B3();
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void minx_CE_B4();
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void minx_CE_B5();
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void minx_CE_B6();
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void minx_CE_B7();
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void minx_CE_B8();
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void minx_CE_B9();
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void minx_CE_BA();
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void minx_CE_BB();
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void minx_CE_BC();
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void minx_CE_BD();
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void minx_CE_BE();
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void minx_CE_BF();
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void minx_CE_C0();
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void minx_CE_C1();
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void minx_CE_C2();
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void minx_CE_C3();
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void minx_CE_C4();
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void minx_CE_C5();
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void minx_CE_C6();
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void minx_CE_C7();
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void minx_CE_C8();
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void minx_CE_C9();
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void minx_CE_CA();
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void minx_CE_CB();
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void minx_CE_CC();
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void minx_CE_CD();
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void minx_CE_CE();
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void minx_CE_CF();
|
||||
void minx_CE_D0();
|
||||
void minx_CE_D1();
|
||||
void minx_CE_D2();
|
||||
void minx_CE_D3();
|
||||
void minx_CE_D4();
|
||||
void minx_CE_D5();
|
||||
void minx_CE_D6();
|
||||
void minx_CE_D7();
|
||||
void minx_CE_D8();
|
||||
void minx_CE_D9();
|
||||
void minx_CE_DA();
|
||||
void minx_CE_DB();
|
||||
void minx_CE_DC();
|
||||
void minx_CE_DD();
|
||||
void minx_CE_DE();
|
||||
void minx_CE_DF();
|
||||
void minx_CE_E0();
|
||||
void minx_CE_E1();
|
||||
void minx_CE_E2();
|
||||
void minx_CE_E3();
|
||||
void minx_CE_E4();
|
||||
void minx_CE_E5();
|
||||
void minx_CE_E6();
|
||||
void minx_CE_E7();
|
||||
void minx_CE_E8();
|
||||
void minx_CE_E9();
|
||||
void minx_CE_EA();
|
||||
void minx_CE_EB();
|
||||
void minx_CE_EC();
|
||||
void minx_CE_ED();
|
||||
void minx_CE_EE();
|
||||
void minx_CE_EF();
|
||||
void minx_CE_F0();
|
||||
void minx_CE_F1();
|
||||
void minx_CE_F2();
|
||||
void minx_CE_F3();
|
||||
void minx_CE_F4();
|
||||
void minx_CE_F5();
|
||||
void minx_CE_F6();
|
||||
void minx_CE_F7();
|
||||
void minx_CE_F8();
|
||||
void minx_CE_F9();
|
||||
void minx_CE_FA();
|
||||
void minx_CE_FB();
|
||||
void minx_CE_FC();
|
||||
void minx_CE_FD();
|
||||
void minx_CE_FE();
|
||||
void minx_CE_FF();
|
||||
|
||||
void minx_CF_00();
|
||||
void minx_CF_01();
|
||||
void minx_CF_02();
|
||||
void minx_CF_03();
|
||||
void minx_CF_04();
|
||||
void minx_CF_05();
|
||||
void minx_CF_06();
|
||||
void minx_CF_07();
|
||||
void minx_CF_08();
|
||||
void minx_CF_09();
|
||||
void minx_CF_0A();
|
||||
void minx_CF_0B();
|
||||
void minx_CF_0C();
|
||||
void minx_CF_0D();
|
||||
void minx_CF_0E();
|
||||
void minx_CF_0F();
|
||||
void minx_CF_10();
|
||||
void minx_CF_11();
|
||||
void minx_CF_12();
|
||||
void minx_CF_13();
|
||||
void minx_CF_14();
|
||||
void minx_CF_15();
|
||||
void minx_CF_16();
|
||||
void minx_CF_17();
|
||||
void minx_CF_18();
|
||||
void minx_CF_19();
|
||||
void minx_CF_1A();
|
||||
void minx_CF_1B();
|
||||
void minx_CF_1C();
|
||||
void minx_CF_1D();
|
||||
void minx_CF_1E();
|
||||
void minx_CF_1F();
|
||||
void minx_CF_20();
|
||||
void minx_CF_21();
|
||||
void minx_CF_22();
|
||||
void minx_CF_23();
|
||||
void minx_CF_24();
|
||||
void minx_CF_25();
|
||||
void minx_CF_26();
|
||||
void minx_CF_27();
|
||||
void minx_CF_28();
|
||||
void minx_CF_29();
|
||||
void minx_CF_2A();
|
||||
void minx_CF_2B();
|
||||
void minx_CF_2C();
|
||||
void minx_CF_2D();
|
||||
void minx_CF_2E();
|
||||
void minx_CF_2F();
|
||||
void minx_CF_30();
|
||||
void minx_CF_31();
|
||||
void minx_CF_32();
|
||||
void minx_CF_33();
|
||||
void minx_CF_34();
|
||||
void minx_CF_35();
|
||||
void minx_CF_36();
|
||||
void minx_CF_37();
|
||||
void minx_CF_38();
|
||||
void minx_CF_39();
|
||||
void minx_CF_3A();
|
||||
void minx_CF_3B();
|
||||
void minx_CF_3C();
|
||||
void minx_CF_3D();
|
||||
void minx_CF_3E();
|
||||
void minx_CF_3F();
|
||||
void minx_CF_40();
|
||||
void minx_CF_41();
|
||||
void minx_CF_42();
|
||||
void minx_CF_43();
|
||||
void minx_CF_44();
|
||||
void minx_CF_45();
|
||||
void minx_CF_46();
|
||||
void minx_CF_47();
|
||||
void minx_CF_48();
|
||||
void minx_CF_49();
|
||||
void minx_CF_4A();
|
||||
void minx_CF_4B();
|
||||
void minx_CF_4C();
|
||||
void minx_CF_4D();
|
||||
void minx_CF_4E();
|
||||
void minx_CF_4F();
|
||||
void minx_CF_50();
|
||||
void minx_CF_51();
|
||||
void minx_CF_52();
|
||||
void minx_CF_53();
|
||||
void minx_CF_54();
|
||||
void minx_CF_55();
|
||||
void minx_CF_56();
|
||||
void minx_CF_57();
|
||||
void minx_CF_58();
|
||||
void minx_CF_59();
|
||||
void minx_CF_5A();
|
||||
void minx_CF_5B();
|
||||
void minx_CF_5C();
|
||||
void minx_CF_5D();
|
||||
void minx_CF_5E();
|
||||
void minx_CF_5F();
|
||||
void minx_CF_60();
|
||||
void minx_CF_61();
|
||||
void minx_CF_62();
|
||||
void minx_CF_63();
|
||||
void minx_CF_64();
|
||||
void minx_CF_65();
|
||||
void minx_CF_66();
|
||||
void minx_CF_67();
|
||||
void minx_CF_68();
|
||||
void minx_CF_69();
|
||||
void minx_CF_6A();
|
||||
void minx_CF_6B();
|
||||
void minx_CF_6C();
|
||||
void minx_CF_6D();
|
||||
void minx_CF_6E();
|
||||
void minx_CF_6F();
|
||||
void minx_CF_70();
|
||||
void minx_CF_71();
|
||||
void minx_CF_72();
|
||||
void minx_CF_73();
|
||||
void minx_CF_74();
|
||||
void minx_CF_75();
|
||||
void minx_CF_76();
|
||||
void minx_CF_77();
|
||||
void minx_CF_78();
|
||||
void minx_CF_79();
|
||||
void minx_CF_7A();
|
||||
void minx_CF_7B();
|
||||
void minx_CF_7C();
|
||||
void minx_CF_7D();
|
||||
void minx_CF_7E();
|
||||
void minx_CF_7F();
|
||||
void minx_CF_80();
|
||||
void minx_CF_81();
|
||||
void minx_CF_82();
|
||||
void minx_CF_83();
|
||||
void minx_CF_84();
|
||||
void minx_CF_85();
|
||||
void minx_CF_86();
|
||||
void minx_CF_87();
|
||||
void minx_CF_88();
|
||||
void minx_CF_89();
|
||||
void minx_CF_8A();
|
||||
void minx_CF_8B();
|
||||
void minx_CF_8C();
|
||||
void minx_CF_8D();
|
||||
void minx_CF_8E();
|
||||
void minx_CF_8F();
|
||||
void minx_CF_90();
|
||||
void minx_CF_91();
|
||||
void minx_CF_92();
|
||||
void minx_CF_93();
|
||||
void minx_CF_94();
|
||||
void minx_CF_95();
|
||||
void minx_CF_96();
|
||||
void minx_CF_97();
|
||||
void minx_CF_98();
|
||||
void minx_CF_99();
|
||||
void minx_CF_9A();
|
||||
void minx_CF_9B();
|
||||
void minx_CF_9C();
|
||||
void minx_CF_9D();
|
||||
void minx_CF_9E();
|
||||
void minx_CF_9F();
|
||||
void minx_CF_A0();
|
||||
void minx_CF_A1();
|
||||
void minx_CF_A2();
|
||||
void minx_CF_A3();
|
||||
void minx_CF_A4();
|
||||
void minx_CF_A5();
|
||||
void minx_CF_A6();
|
||||
void minx_CF_A7();
|
||||
void minx_CF_A8();
|
||||
void minx_CF_A9();
|
||||
void minx_CF_AA();
|
||||
void minx_CF_AB();
|
||||
void minx_CF_AC();
|
||||
void minx_CF_AD();
|
||||
void minx_CF_AE();
|
||||
void minx_CF_AF();
|
||||
void minx_CF_B0();
|
||||
void minx_CF_B1();
|
||||
void minx_CF_B2();
|
||||
void minx_CF_B3();
|
||||
void minx_CF_B4();
|
||||
void minx_CF_B5();
|
||||
void minx_CF_B6();
|
||||
void minx_CF_B7();
|
||||
void minx_CF_B8();
|
||||
void minx_CF_B9();
|
||||
void minx_CF_BA();
|
||||
void minx_CF_BB();
|
||||
void minx_CF_BC();
|
||||
void minx_CF_BD();
|
||||
void minx_CF_BE();
|
||||
void minx_CF_BF();
|
||||
void minx_CF_C0();
|
||||
void minx_CF_C1();
|
||||
void minx_CF_C2();
|
||||
void minx_CF_C3();
|
||||
void minx_CF_C4();
|
||||
void minx_CF_C5();
|
||||
void minx_CF_C6();
|
||||
void minx_CF_C7();
|
||||
void minx_CF_C8();
|
||||
void minx_CF_C9();
|
||||
void minx_CF_CA();
|
||||
void minx_CF_CB();
|
||||
void minx_CF_CC();
|
||||
void minx_CF_CD();
|
||||
void minx_CF_CE();
|
||||
void minx_CF_CF();
|
||||
void minx_CF_D0();
|
||||
void minx_CF_D1();
|
||||
void minx_CF_D2();
|
||||
void minx_CF_D3();
|
||||
void minx_CF_D4();
|
||||
void minx_CF_D5();
|
||||
void minx_CF_D6();
|
||||
void minx_CF_D7();
|
||||
void minx_CF_D8();
|
||||
void minx_CF_D9();
|
||||
void minx_CF_DA();
|
||||
void minx_CF_DB();
|
||||
void minx_CF_DC();
|
||||
void minx_CF_DD();
|
||||
void minx_CF_DE();
|
||||
void minx_CF_DF();
|
||||
void minx_CF_E0();
|
||||
void minx_CF_E1();
|
||||
void minx_CF_E2();
|
||||
void minx_CF_E3();
|
||||
void minx_CF_E4();
|
||||
void minx_CF_E5();
|
||||
void minx_CF_E6();
|
||||
void minx_CF_E7();
|
||||
void minx_CF_E8();
|
||||
void minx_CF_E9();
|
||||
void minx_CF_EA();
|
||||
void minx_CF_EB();
|
||||
void minx_CF_EC();
|
||||
void minx_CF_ED();
|
||||
void minx_CF_EE();
|
||||
void minx_CF_EF();
|
||||
void minx_CF_F0();
|
||||
void minx_CF_F1();
|
||||
void minx_CF_F2();
|
||||
void minx_CF_F3();
|
||||
void minx_CF_F4();
|
||||
void minx_CF_F5();
|
||||
void minx_CF_F6();
|
||||
void minx_CF_F7();
|
||||
void minx_CF_F8();
|
||||
void minx_CF_F9();
|
||||
void minx_CF_FA();
|
||||
void minx_CF_FB();
|
||||
void minx_CF_FC();
|
||||
void minx_CF_FD();
|
||||
void minx_CF_FE();
|
||||
void minx_CF_FF();
|
||||
|
||||
typedef void (minx_cpu_device::*op_func)();
|
||||
static const op_func insnminx[256];
|
||||
static const int insnminx_cycles[256];
|
||||
|
||||
static const op_func insnminx_CE[256];
|
||||
static const int insnminx_cycles_CE[256];
|
||||
|
||||
static const op_func insnminx_CF[256];
|
||||
static const int insnminx_cycles_CF[256];
|
||||
|
||||
};
|
||||
|
||||
@ -360,3 +360,4 @@ void minx_cpu_device::CALL( UINT16 arg )
|
||||
#define AD2_Y8 UINT32 addr2 = ( m_YI << 16 ) | ( m_Y + rdop() )
|
||||
#define AD2_XL UINT32 addr2 = ( m_XI << 16 ) | ( m_X + ( m_HL & 0x00FF ) )
|
||||
#define AD2_YL UINT32 addr2 = ( m_YI << 16 ) | ( m_Y + ( m_HL & 0x00FF ) )
|
||||
|
||||
|
||||
@ -1,312 +1,542 @@
|
||||
#undef OP
|
||||
#define OP(nn) void minx_cpu_device::minx_CE_##nn()
|
||||
|
||||
OP(00) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(01) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(02) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(03) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(04) { AD1_IHL; WR( addr1, ADD8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
OP(05) { AD1_IHL; WR( addr1, ADD8( RD( addr1 ), rdop() ) ); }
|
||||
OP(06) { AD1_IHL; AD2_XIX; WR( addr1, ADD8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
OP(07) { AD1_IHL; AD2_YIY; WR( addr1, ADD8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
OP(08) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(09) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(0A) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(0B) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(0C) { AD1_IHL; WR( addr1, ADDC8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
OP(0D) { AD1_IHL; WR( addr1, ADDC8( RD( addr1 ), rdop() ) ); }
|
||||
OP(0E) { AD1_IHL; AD2_XIX; WR( addr1, ADDC8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
OP(0F) { AD1_IHL; AD2_YIY; WR( addr1, ADDC8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
void minx_cpu_device::execute_one_ce()
|
||||
{
|
||||
const UINT8 opcode = rdop();
|
||||
|
||||
OP(10) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(11) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(12) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(13) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(14) { AD1_IHL; WR( addr1, SUB8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
OP(15) { AD1_IHL; WR( addr1, SUB8( RD( addr1 ), rdop() ) ); }
|
||||
OP(16) { AD1_IHL; AD2_XIX; WR( addr1, SUB8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
OP(17) { AD1_IHL; AD2_YIY; WR( addr1, SUB8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
OP(18) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(19) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(1A) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(1B) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(1C) { AD1_IHL; WR( addr1, SUBC8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
OP(1D) { AD1_IHL; WR( addr1, SUBC8( RD( addr1 ), rdop() ) ); }
|
||||
OP(1E) { AD1_IHL; AD2_XIX; WR( addr1, SUBC8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
OP(1F) { AD1_IHL; AD2_YIY; WR( addr1, SUBC8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
switch (opcode)
|
||||
{
|
||||
case 0x00: { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x01: { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x02: { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x03: { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x04: { AD1_IHL; WR( addr1, ADD8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
break;
|
||||
case 0x05: { AD1_IHL; WR( addr1, ADD8( RD( addr1 ), rdop() ) ); }
|
||||
break;
|
||||
case 0x06: { AD1_IHL; AD2_XIX; WR( addr1, ADD8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
case 0x07: { AD1_IHL; AD2_YIY; WR( addr1, ADD8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
case 0x08: { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x09: { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x0A: { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x0B: { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x0C: { AD1_IHL; WR( addr1, ADDC8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
break;
|
||||
case 0x0D: { AD1_IHL; WR( addr1, ADDC8( RD( addr1 ), rdop() ) ); }
|
||||
break;
|
||||
case 0x0E: { AD1_IHL; AD2_XIX; WR( addr1, ADDC8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
case 0x0F: { AD1_IHL; AD2_YIY; WR( addr1, ADDC8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
|
||||
OP(20) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(21) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(22) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(23) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(24) { AD1_IHL; WR( addr1, AND8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
OP(25) { AD1_IHL; WR( addr1, AND8( RD( addr1 ), rdop() ) ); }
|
||||
OP(26) { AD1_IHL; AD2_XIX; WR( addr1, AND8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
OP(27) { AD1_IHL; AD2_YIY; WR( addr1, AND8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
OP(28) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(29) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(2A) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(2B) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(2C) { AD1_IHL; WR( addr1, OR8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
OP(2D) { AD1_IHL; WR( addr1, OR8( RD( addr1 ), rdop() ) ); }
|
||||
OP(2E) { AD1_IHL; AD2_XIX; WR( addr1, OR8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
OP(2F) { AD1_IHL; AD2_YIY; WR( addr1, OR8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
case 0x10: { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x11: { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x12: { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x13: { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x14: { AD1_IHL; WR( addr1, SUB8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
break;
|
||||
case 0x15: { AD1_IHL; WR( addr1, SUB8( RD( addr1 ), rdop() ) ); }
|
||||
break;
|
||||
case 0x16: { AD1_IHL; AD2_XIX; WR( addr1, SUB8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
case 0x17: { AD1_IHL; AD2_YIY; WR( addr1, SUB8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
case 0x18: { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x19: { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x1A: { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x1B: { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x1C: { AD1_IHL; WR( addr1, SUBC8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
break;
|
||||
case 0x1D: { AD1_IHL; WR( addr1, SUBC8( RD( addr1 ), rdop() ) ); }
|
||||
break;
|
||||
case 0x1E: { AD1_IHL; AD2_XIX; WR( addr1, SUBC8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
case 0x1F: { AD1_IHL; AD2_YIY; WR( addr1, SUBC8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
|
||||
OP(30) { AD2_X8; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(31) { AD2_Y8; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(32) { AD2_XL; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(33) { AD2_YL; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(34) { AD1_IHL; SUB8( RD( addr1 ), ( m_BA & 0x00FF ) ); }
|
||||
OP(35) { AD1_IHL; SUB8( RD( addr1 ), rdop() ); }
|
||||
OP(36) { AD1_IHL; AD2_XIX; SUB8( RD( addr1 ), RD( addr2 ) ); }
|
||||
OP(37) { AD1_IHL; AD2_YIY; SUB8( RD( addr1 ), RD( addr2 ) ); }
|
||||
OP(38) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(39) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(3A) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(3B) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(3C) { AD1_IHL; WR( addr1, XOR8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
OP(3D) { AD1_IHL; WR( addr1, XOR8( RD( addr1 ), rdop() ) ); }
|
||||
OP(3E) { AD1_IHL; AD2_XIX; WR( addr1, XOR8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
OP(3F) { AD1_IHL; AD2_YIY; WR( addr1, XOR8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
case 0x20: { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x21: { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x22: { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x23: { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x24: { AD1_IHL; WR( addr1, AND8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
break;
|
||||
case 0x25: { AD1_IHL; WR( addr1, AND8( RD( addr1 ), rdop() ) ); }
|
||||
break;
|
||||
case 0x26: { AD1_IHL; AD2_XIX; WR( addr1, AND8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
case 0x27: { AD1_IHL; AD2_YIY; WR( addr1, AND8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
case 0x28: { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x29: { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x2A: { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x2B: { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x2C: { AD1_IHL; WR( addr1, OR8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
break;
|
||||
case 0x2D: { AD1_IHL; WR( addr1, OR8( RD( addr1 ), rdop() ) ); }
|
||||
break;
|
||||
case 0x2E: { AD1_IHL; AD2_XIX; WR( addr1, OR8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
case 0x2F: { AD1_IHL; AD2_YIY; WR( addr1, OR8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
|
||||
OP(40) { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(41) { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(42) { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(43) { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(44) { AD1_X8; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
OP(45) { AD1_Y8; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
OP(46) { AD1_XL; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
OP(47) { AD1_YL; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
OP(48) { AD2_X8; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(49) { AD2_Y8; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(4A) { AD2_XL; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(4B) { AD2_YL; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(4C) { AD1_X8; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
OP(4D) { AD1_Y8; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
OP(4E) { AD1_XL; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
OP(4F) { AD1_YL; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
case 0x30: { AD2_X8; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x31: { AD2_Y8; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x32: { AD2_XL; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x33: { AD2_YL; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x34: { AD1_IHL; SUB8( RD( addr1 ), ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x35: { AD1_IHL; SUB8( RD( addr1 ), rdop() ); }
|
||||
break;
|
||||
case 0x36: { AD1_IHL; AD2_XIX; SUB8( RD( addr1 ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x37: { AD1_IHL; AD2_YIY; SUB8( RD( addr1 ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x38: { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x39: { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x3A: { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x3B: { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x3C: { AD1_IHL; WR( addr1, XOR8( RD( addr1 ), ( m_BA & 0x00FF ) ) ); }
|
||||
break;
|
||||
case 0x3D: { AD1_IHL; WR( addr1, XOR8( RD( addr1 ), rdop() ) ); }
|
||||
break;
|
||||
case 0x3E: { AD1_IHL; AD2_XIX; WR( addr1, XOR8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
case 0x3F: { AD1_IHL; AD2_YIY; WR( addr1, XOR8( RD( addr1 ), RD( addr2 ) ) ); }
|
||||
break;
|
||||
|
||||
OP(50) { AD2_X8; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(51) { AD2_Y8; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(52) { AD2_XL; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(53) { AD2_YL; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(54) { AD1_X8; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
OP(55) { AD1_Y8; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
OP(56) { AD1_XL; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
OP(57) { AD1_YL; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
OP(58) { AD2_X8; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(59) { AD2_Y8; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(5A) { AD2_XL; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(5B) { AD2_YL; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(5C) { AD1_X8; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
OP(5D) { AD1_Y8; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
OP(5E) { AD1_XL; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
OP(5F) { AD1_YL; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
case 0x40: { AD2_X8; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x41: { AD2_Y8; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x42: { AD2_XL; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x43: { AD2_YL; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x44: { AD1_X8; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x45: { AD1_Y8; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x46: { AD1_XL; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x47: { AD1_YL; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x48: { AD2_X8; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x49: { AD2_Y8; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x4A: { AD2_XL; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x4B: { AD2_YL; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x4C: { AD1_X8; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x4D: { AD1_Y8; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x4E: { AD1_XL; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x4F: { AD1_YL; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
|
||||
OP(60) { AD1_IHL; AD2_X8; WR( addr1, RD( addr2 ) ); }
|
||||
OP(61) { AD1_IHL; AD2_Y8; WR( addr1, RD( addr2 ) ); }
|
||||
OP(62) { AD1_IHL; AD2_XL; WR( addr1, RD( addr2 ) ); }
|
||||
OP(63) { AD1_IHL; AD2_YL; WR( addr1, RD( addr2 ) ); }
|
||||
OP(64) { /* illegal operation? */ }
|
||||
OP(65) { /* illegal operation? */ }
|
||||
OP(66) { /* illegal operation? */ }
|
||||
OP(67) { /* illegal operation? */ }
|
||||
OP(68) { AD1_XIX; AD2_X8; WR( addr1, RD( addr2 ) ); }
|
||||
OP(69) { AD1_XIX; AD2_Y8; WR( addr1, RD( addr2 ) ); }
|
||||
OP(6A) { AD1_XIX; AD2_XL; WR( addr1, RD( addr2 ) ); }
|
||||
OP(6B) { AD1_XIX; AD2_YL; WR( addr1, RD( addr2 ) ); }
|
||||
OP(6C) { /* illegal operation? */ }
|
||||
OP(6D) { /* illegal operation? */ }
|
||||
OP(6E) { /* illegal operation? */ }
|
||||
OP(6F) { /* illegal operation? */ }
|
||||
case 0x50: { AD2_X8; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x51: { AD2_Y8; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x52: { AD2_XL; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x53: { AD2_YL; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x54: { AD1_X8; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x55: { AD1_Y8; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x56: { AD1_XL; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x57: { AD1_YL; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x58: { AD2_X8; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x59: { AD2_Y8; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x5A: { AD2_XL; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x5B: { AD2_YL; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x5C: { AD1_X8; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
break;
|
||||
case 0x5D: { AD1_Y8; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
break;
|
||||
case 0x5E: { AD1_XL; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
break;
|
||||
case 0x5F: { AD1_YL; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
break;
|
||||
|
||||
OP(70) { /* illegal operation? */ }
|
||||
OP(71) { /* illegal operation? */ }
|
||||
OP(72) { /* illegal operation? */ }
|
||||
OP(73) { /* illegal operation? */ }
|
||||
OP(74) { /* illegal operation? */ }
|
||||
OP(75) { /* illegal operation? */ }
|
||||
OP(76) { /* illegal operation? */ }
|
||||
OP(77) { /* illegal operation? */ }
|
||||
OP(78) { AD1_YIY; AD2_X8; WR( addr1, RD( addr2 ) ); }
|
||||
OP(79) { AD1_YIY; AD2_Y8; WR( addr1, RD( addr2 ) ); }
|
||||
OP(7A) { AD1_YIY; AD2_XL; WR( addr1, RD( addr2 ) ); }
|
||||
OP(7B) { AD1_YIY; AD2_YL; WR( addr1, RD( addr2 ) ); }
|
||||
OP(7C) { /* illegal operation? */ }
|
||||
OP(7D) { /* illegal operation? */ }
|
||||
OP(7E) { /* illegal operation? */ }
|
||||
OP(7F) { /* illegal operation? */ }
|
||||
case 0x60: { AD1_IHL; AD2_X8; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x61: { AD1_IHL; AD2_Y8; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x62: { AD1_IHL; AD2_XL; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x63: { AD1_IHL; AD2_YL; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x64: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x65: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x66: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x67: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x68: { AD1_XIX; AD2_X8; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x69: { AD1_XIX; AD2_Y8; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x6A: { AD1_XIX; AD2_XL; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x6B: { AD1_XIX; AD2_YL; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x6C: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x6D: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x6E: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x6F: { /* illegal operation? */ }
|
||||
break;
|
||||
|
||||
OP(80) { m_BA = ( m_BA & 0xFF00 ) | SAL8( m_BA & 0x00FF ); }
|
||||
OP(81) { m_BA = ( m_BA & 0x00FF ) | ( SAL8( m_BA >> 8 )<< 8 ); }
|
||||
OP(82) { AD1_IN8; WR( addr1, SAL8( RD( addr1 ) ) ); }
|
||||
OP(83) { AD1_IHL; WR( addr1, SAL8( RD( addr1 ) ) ); }
|
||||
OP(84) { m_BA = ( m_BA & 0xFF00 ) | SHL8( m_BA & 0x00FF ); }
|
||||
OP(85) { m_BA = ( m_BA & 0x00FF ) | ( SHL8( m_BA >> 8 ) << 8 ); }
|
||||
OP(86) { AD1_IN8; WR( addr1, SHL8( RD( addr1 ) ) ); }
|
||||
OP(87) { AD1_IHL; WR( addr1, SHL8( RD( addr1 ) ) ); }
|
||||
OP(88) { m_BA = ( m_BA & 0xFF00 ) | SAR8( m_BA & 0x00FF ); }
|
||||
OP(89) { m_BA = ( m_BA & 0x00FF ) | ( SAR8( m_BA >> 8 ) << 8 ); }
|
||||
OP(8A) { AD1_IN8; WR( addr1, SAR8( RD( addr1 ) ) ); }
|
||||
OP(8B) { AD1_IHL; WR( addr1, SAR8( RD( addr1 ) ) ); }
|
||||
OP(8C) { m_BA = ( m_BA & 0xFF00 ) | SHR8( m_BA & 0x00FF ); }
|
||||
OP(8D) { m_BA = ( m_BA & 0x00FF ) | ( SHR8( m_BA >> 8 ) << 8 ); }
|
||||
OP(8E) { AD1_IN8; WR( addr1, SHR8( RD( addr1 ) ) ); }
|
||||
OP(8F) { AD1_IHL; WR( addr1, SHR8( RD( addr1 ) ) ); }
|
||||
case 0x70: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x71: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x72: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x73: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x74: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x75: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x76: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x77: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x78: { AD1_YIY; AD2_X8; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x79: { AD1_YIY; AD2_Y8; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x7A: { AD1_YIY; AD2_XL; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x7B: { AD1_YIY; AD2_YL; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x7C: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x7D: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x7E: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x7F: { /* illegal operation? */ }
|
||||
break;
|
||||
|
||||
OP(90) { m_BA = ( m_BA & 0xFF00 ) | ROLC8( m_BA & 0x00FF ); }
|
||||
OP(91) { m_BA = ( m_BA & 0x00FF ) | ( ROLC8( m_BA >> 8 ) << 8 ); }
|
||||
OP(92) { AD1_IN8; WR( addr1, ROLC8( RD( addr1 ) ) ); }
|
||||
OP(93) { AD1_IHL; WR( addr1, ROLC8( RD( addr1 ) ) ); }
|
||||
OP(94) { m_BA = ( m_BA & 0xFF00 ) | ROL8( m_BA & 0x00FF ); }
|
||||
OP(95) { m_BA = ( m_BA & 0x00FF ) | ( ROL8( m_BA >> 8 ) << 8 ); }
|
||||
OP(96) { AD1_IN8; WR( addr1, ROL8( RD( addr1 ) ) ); }
|
||||
OP(97) { AD1_IHL; WR( addr1, ROL8( RD( addr1 ) ) ); }
|
||||
OP(98) { m_BA = ( m_BA & 0xFF00 ) | RORC8( m_BA & 0x00FF ); }
|
||||
OP(99) { m_BA = ( m_BA & 0x00FF ) | ( RORC8( m_BA >> 8 ) << 8 ); }
|
||||
OP(9A) { AD1_IN8; WR( addr1, RORC8( RD( addr1 ) ) ); }
|
||||
OP(9B) { AD1_IHL; WR( addr1, RORC8( RD( addr1 ) ) ); }
|
||||
OP(9C) { m_BA = ( m_BA & 0xFF00 ) | ROR8( m_BA & 0x00FF ); }
|
||||
OP(9D) { m_BA = ( m_BA & 0x00FF ) | ( ROR8( m_BA >> 8 ) << 8 ); }
|
||||
OP(9E) { AD1_IN8; WR( addr1, ROR8( RD( addr1 ) ) ); }
|
||||
OP(9F) { AD1_IHL; WR( addr1, ROR8( RD( addr1 ) ) ); }
|
||||
case 0x80: { m_BA = ( m_BA & 0xFF00 ) | SAL8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0x81: { m_BA = ( m_BA & 0x00FF ) | ( SAL8( m_BA >> 8 )<< 8 ); }
|
||||
break;
|
||||
case 0x82: { AD1_IN8; WR( addr1, SAL8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x83: { AD1_IHL; WR( addr1, SAL8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x84: { m_BA = ( m_BA & 0xFF00 ) | SHL8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0x85: { m_BA = ( m_BA & 0x00FF ) | ( SHL8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x86: { AD1_IN8; WR( addr1, SHL8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x87: { AD1_IHL; WR( addr1, SHL8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x88: { m_BA = ( m_BA & 0xFF00 ) | SAR8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0x89: { m_BA = ( m_BA & 0x00FF ) | ( SAR8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x8A: { AD1_IN8; WR( addr1, SAR8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x8B: { AD1_IHL; WR( addr1, SAR8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x8C: { m_BA = ( m_BA & 0xFF00 ) | SHR8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0x8D: { m_BA = ( m_BA & 0x00FF ) | ( SHR8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x8E: { AD1_IN8; WR( addr1, SHR8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x8F: { AD1_IHL; WR( addr1, SHR8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
|
||||
OP(A0) { m_BA = ( m_BA & 0xFF00 ) | NOT8( m_BA & 0x00FF ); }
|
||||
OP(A1) { m_BA = ( m_BA & 0x00FF ) | ( NOT8( m_BA >> 8 ) << 8 ); }
|
||||
OP(A2) { AD1_IN8; WR( addr1, NOT8( RD( addr1 ) ) ); }
|
||||
OP(A3) { AD1_IHL; WR( addr1, NOT8( RD( addr1 ) ) ); }
|
||||
OP(A4) { m_BA = ( m_BA & 0xFF00 ) | NEG8( m_BA & 0x00FF ); }
|
||||
OP(A5) { m_BA = ( m_BA & 0x00FF ) | ( NEG8( m_BA >> 8 ) << 8 ); }
|
||||
OP(A6) { AD1_IN8; WR( addr1, NEG8( RD( addr1 ) ) ); }
|
||||
OP(A7) { AD1_IHL; WR( addr1, NEG8( RD( addr1 ) ) ); }
|
||||
OP(A8) { m_BA = ( ( m_BA & 0x0080 ) ? ( 0xFF00 | m_BA ) : ( m_BA & 0x00FF ) ); }
|
||||
OP(A9) { /* illegal operation? */ }
|
||||
OP(AA) { /* illegal operation? */ }
|
||||
OP(AB) { /* illegal operation? */ }
|
||||
OP(AC) { /* illegal operation? */ }
|
||||
OP(AD) { /* illegal operation? */ }
|
||||
OP(AE) { /* HALT */ m_halted = 1; }
|
||||
OP(AF) { }
|
||||
case 0x90: { m_BA = ( m_BA & 0xFF00 ) | ROLC8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0x91: { m_BA = ( m_BA & 0x00FF ) | ( ROLC8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x92: { AD1_IN8; WR( addr1, ROLC8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x93: { AD1_IHL; WR( addr1, ROLC8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x94: { m_BA = ( m_BA & 0xFF00 ) | ROL8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0x95: { m_BA = ( m_BA & 0x00FF ) | ( ROL8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x96: { AD1_IN8; WR( addr1, ROL8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x97: { AD1_IHL; WR( addr1, ROL8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x98: { m_BA = ( m_BA & 0xFF00 ) | RORC8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0x99: { m_BA = ( m_BA & 0x00FF ) | ( RORC8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x9A: { AD1_IN8; WR( addr1, RORC8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x9B: { AD1_IHL; WR( addr1, RORC8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x9C: { m_BA = ( m_BA & 0xFF00 ) | ROR8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0x9D: { m_BA = ( m_BA & 0x00FF ) | ( ROR8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x9E: { AD1_IN8; WR( addr1, ROR8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x9F: { AD1_IHL; WR( addr1, ROR8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
|
||||
OP(B0) { m_BA = ( m_BA & 0x00FF ) | ( AND8( ( m_BA >> 8 ), rdop() ) << 8 ); }
|
||||
OP(B1) { m_HL = ( m_HL & 0xFF00 ) | AND8( ( m_HL & 0x00FF ), rdop() ); }
|
||||
OP(B2) { m_HL = ( m_HL & 0x00FF ) | ( AND8( ( m_HL >> 8 ), rdop() ) << 8 ); }
|
||||
OP(B3) { /* illegal operation? */ }
|
||||
OP(B4) { m_BA = ( m_BA & 0x00FF ) | ( OR8( ( m_BA >> 8 ), rdop() ) << 8 ); }
|
||||
OP(B5) { m_HL = ( m_HL & 0xFF00 ) | OR8( ( m_HL & 0x00FF ), rdop() ); }
|
||||
OP(B6) { m_HL = ( m_HL & 0x00FF ) | ( OR8( ( m_HL >> 8 ), rdop() ) << 8 ); }
|
||||
OP(B7) { /* illegal operation? */ }
|
||||
OP(B8) { m_BA = ( m_BA & 0x00FF ) | ( XOR8( ( m_BA >> 8 ), rdop() ) << 8 ); }
|
||||
OP(B9) { m_HL = ( m_HL & 0xFF00 ) | XOR8( ( m_HL & 0x00FF ), rdop() ); }
|
||||
OP(BA) { m_HL = ( m_HL & 0x00FF ) | ( XOR8( ( m_HL >> 8 ), rdop() ) << 8 ); }
|
||||
OP(BB) { /* illegal operation? */ }
|
||||
OP(BC) { SUB8( ( m_BA >> 8 ), rdop() ); }
|
||||
OP(BD) { SUB8( ( m_HL & 0x00FF), rdop() ); }
|
||||
OP(BE) { SUB8( ( m_HL >> 8 ), rdop() ); }
|
||||
OP(BF) { SUB8( m_N, rdop() ); }
|
||||
case 0xA0: { m_BA = ( m_BA & 0xFF00 ) | NOT8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0xA1: { m_BA = ( m_BA & 0x00FF ) | ( NOT8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0xA2: { AD1_IN8; WR( addr1, NOT8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0xA3: { AD1_IHL; WR( addr1, NOT8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0xA4: { m_BA = ( m_BA & 0xFF00 ) | NEG8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0xA5: { m_BA = ( m_BA & 0x00FF ) | ( NEG8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0xA6: { AD1_IN8; WR( addr1, NEG8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0xA7: { AD1_IHL; WR( addr1, NEG8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0xA8: { m_BA = ( ( m_BA & 0x0080 ) ? ( 0xFF00 | m_BA ) : ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0xA9: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xAA: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xAB: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xAC: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xAD: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xAE: { /* HALT */ m_halted = 1; }
|
||||
break;
|
||||
case 0xAF: { }
|
||||
break;
|
||||
|
||||
OP(C0) { m_BA = ( m_BA & 0xFF00 ) | m_N; }
|
||||
OP(C1) { m_BA = ( m_BA & 0xFF00 ) | m_F; }
|
||||
OP(C2) { m_N = ( m_BA & 0x00FF ); }
|
||||
OP(C3) { m_F = ( m_BA & 0x00FF ); }
|
||||
OP(C4) { m_U = rdop(); }
|
||||
OP(C5) { m_I = rdop(); }
|
||||
OP(C6) { m_XI = rdop(); }
|
||||
OP(C7) { m_YI = rdop(); }
|
||||
OP(C8) { m_BA = ( m_BA & 0xFF00 ) | m_V; }
|
||||
OP(C9) { m_BA = ( m_BA & 0xFF00 ) | m_I; }
|
||||
OP(CA) { m_BA = ( m_BA & 0xFF00 ) | m_XI; }
|
||||
OP(CB) { m_BA = ( m_BA & 0xFF00 ) | m_YI; }
|
||||
OP(CC) { m_U = ( m_BA & 0x00FF ); }
|
||||
OP(CD) { m_I = ( m_BA & 0x00FF ); }
|
||||
OP(CE) { m_XI = ( m_BA & 0x00FF ); }
|
||||
OP(CF) { m_YI = ( m_BA & 0x00FF ); }
|
||||
case 0xB0: { m_BA = ( m_BA & 0x00FF ) | ( AND8( ( m_BA >> 8 ), rdop() ) << 8 ); }
|
||||
break;
|
||||
case 0xB1: { m_HL = ( m_HL & 0xFF00 ) | AND8( ( m_HL & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0xB2: { m_HL = ( m_HL & 0x00FF ) | ( AND8( ( m_HL >> 8 ), rdop() ) << 8 ); }
|
||||
break;
|
||||
case 0xB3: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xB4: { m_BA = ( m_BA & 0x00FF ) | ( OR8( ( m_BA >> 8 ), rdop() ) << 8 ); }
|
||||
break;
|
||||
case 0xB5: { m_HL = ( m_HL & 0xFF00 ) | OR8( ( m_HL & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0xB6: { m_HL = ( m_HL & 0x00FF ) | ( OR8( ( m_HL >> 8 ), rdop() ) << 8 ); }
|
||||
break;
|
||||
case 0xB7: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xB8: { m_BA = ( m_BA & 0x00FF ) | ( XOR8( ( m_BA >> 8 ), rdop() ) << 8 ); }
|
||||
break;
|
||||
case 0xB9: { m_HL = ( m_HL & 0xFF00 ) | XOR8( ( m_HL & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0xBA: { m_HL = ( m_HL & 0x00FF ) | ( XOR8( ( m_HL >> 8 ), rdop() ) << 8 ); }
|
||||
break;
|
||||
case 0xBB: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xBC: { SUB8( ( m_BA >> 8 ), rdop() ); }
|
||||
break;
|
||||
case 0xBD: { SUB8( ( m_HL & 0x00FF), rdop() ); }
|
||||
break;
|
||||
case 0xBE: { SUB8( ( m_HL >> 8 ), rdop() ); }
|
||||
break;
|
||||
case 0xBF: { SUB8( m_N, rdop() ); }
|
||||
break;
|
||||
|
||||
OP(D0) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(D1) { AD2_I16; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(D2) { AD2_I16; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(D3) { AD2_I16; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(D4) { AD1_I16; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
OP(D5) { AD1_I16; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
OP(D6) { AD1_I16; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
OP(D7) { AD1_I16; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
OP(D8) { m_HL = ( m_HL & 0x00FF ) * ( m_BA & 0x00FF ); }
|
||||
OP(D9) { int d = m_HL / ( m_BA & 0x00FF ); m_HL = ( ( m_HL - ( ( m_BA & 0x00FF ) * d ) ) << 8 ) | d; }
|
||||
OP(DA) { /* illegal operation? */ }
|
||||
OP(DB) { /* illegal operation? */ }
|
||||
OP(DC) { /* illegal operation? */ }
|
||||
OP(DD) { /* illegal operation? */ }
|
||||
OP(DE) { /* illegal operation? */ }
|
||||
OP(DF) { /* illegal operation? */ }
|
||||
case 0xC0: { m_BA = ( m_BA & 0xFF00 ) | m_N; }
|
||||
break;
|
||||
case 0xC1: { m_BA = ( m_BA & 0xFF00 ) | m_F; }
|
||||
break;
|
||||
case 0xC2: { m_N = ( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0xC3: { m_F = ( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0xC4: { m_U = rdop(); }
|
||||
break;
|
||||
case 0xC5: { m_I = rdop(); }
|
||||
break;
|
||||
case 0xC6: { m_XI = rdop(); }
|
||||
break;
|
||||
case 0xC7: { m_YI = rdop(); }
|
||||
break;
|
||||
case 0xC8: { m_BA = ( m_BA & 0xFF00 ) | m_V; }
|
||||
break;
|
||||
case 0xC9: { m_BA = ( m_BA & 0xFF00 ) | m_I; }
|
||||
break;
|
||||
case 0xCA: { m_BA = ( m_BA & 0xFF00 ) | m_XI; }
|
||||
break;
|
||||
case 0xCB: { m_BA = ( m_BA & 0xFF00 ) | m_YI; }
|
||||
break;
|
||||
case 0xCC: { m_U = ( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0xCD: { m_I = ( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0xCE: { m_XI = ( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0xCF: { m_YI = ( m_BA & 0x00FF ); }
|
||||
break;
|
||||
|
||||
OP(E0) { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E1) { INT8 d8 = rdop(); if ( ( m_F & FLAG_Z ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E2) { INT8 d8 = rdop(); if ( !( m_F & FLAG_Z ) && ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E3) { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E4) { INT8 d8 = rdop(); if ( ( m_F & FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E5) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E6) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_S ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E7) { INT8 d8 = rdop(); if ( ( m_F & FLAG_S ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E8) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X0 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E9) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X1 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(EA) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X2 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(EB) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_DZ ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(EC) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X0 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(ED) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X1 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(EE) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X2 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(EF) { INT8 d8 = rdop(); if ( ( m_E & EXEC_DZ ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
case 0xD0: { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0xD1: { AD2_I16; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0xD2: { AD2_I16; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0xD3: { AD2_I16; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0xD4: { AD1_I16; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0xD5: { AD1_I16; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0xD6: { AD1_I16; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
break;
|
||||
case 0xD7: { AD1_I16; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
break;
|
||||
case 0xD8: { m_HL = ( m_HL & 0x00FF ) * ( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0xD9: { int d = m_HL / ( m_BA & 0x00FF ); m_HL = ( ( m_HL - ( ( m_BA & 0x00FF ) * d ) ) << 8 ) | d; }
|
||||
break;
|
||||
case 0xDA: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xDB: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xDC: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xDD: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xDE: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xDF: { /* illegal operation? */ }
|
||||
break;
|
||||
|
||||
OP(F0) { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(F1) { INT8 d8 = rdop(); if ( ( m_F & FLAG_Z ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(F2) { INT8 d8 = rdop(); if ( !( m_F & FLAG_Z ) && ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(F3) { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { CALL( m_PC + d8 - 1 ); } }
|
||||
OP(F4) { INT8 d8 = rdop(); if ( ( m_F & FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(F5) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(F6) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_S ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(F7) { INT8 d8 = rdop(); if ( ( m_F & FLAG_S ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(F8) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X0 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(F9) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X1 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(FA) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X2 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(FB) { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_DZ ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(FC) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X0 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(FD) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X1 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(FE) { INT8 d8 = rdop(); if ( ( m_E & EXEC_X2 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(FF) { INT8 d8 = rdop(); if ( ( m_E & EXEC_DZ ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
case 0xE0: { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE1: { INT8 d8 = rdop(); if ( ( m_F & FLAG_Z ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE2: { INT8 d8 = rdop(); if ( !( m_F & FLAG_Z ) && ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE3: { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE4: { INT8 d8 = rdop(); if ( ( m_F & FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE5: { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_O ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE6: { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_S ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE7: { INT8 d8 = rdop(); if ( ( m_F & FLAG_S ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE8: { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X0 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE9: { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X1 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xEA: { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X2 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xEB: { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_DZ ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xEC: { INT8 d8 = rdop(); if ( ( m_E & EXEC_X0 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xED: { INT8 d8 = rdop(); if ( ( m_E & EXEC_X1 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xEE: { INT8 d8 = rdop(); if ( ( m_E & EXEC_X2 ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xEF: { INT8 d8 = rdop(); if ( ( m_E & EXEC_DZ ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
|
||||
case 0xF0: { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xF1: { INT8 d8 = rdop(); if ( ( m_F & FLAG_Z ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xF2: { INT8 d8 = rdop(); if ( !( m_F & FLAG_Z ) && ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xF3: { INT8 d8 = rdop(); if ( ( ( m_F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( m_F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { CALL( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xF4: { INT8 d8 = rdop(); if ( ( m_F & FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xF5: { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_O ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xF6: { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_S ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xF7: { INT8 d8 = rdop(); if ( ( m_F & FLAG_S ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xF8: { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X0 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xF9: { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X1 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xFA: { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_X2 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xFB: { INT8 d8 = rdop(); if ( ! ( m_E & EXEC_DZ ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xFC: { INT8 d8 = rdop(); if ( ( m_E & EXEC_X0 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xFD: { INT8 d8 = rdop(); if ( ( m_E & EXEC_X1 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xFE: { INT8 d8 = rdop(); if ( ( m_E & EXEC_X2 ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xFF: { INT8 d8 = rdop(); if ( ( m_E & EXEC_DZ ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
}
|
||||
|
||||
m_icount -= insnminx_cycles_CE[opcode];
|
||||
}
|
||||
|
||||
const minx_cpu_device::op_func minx_cpu_device::insnminx_CE[256] = {
|
||||
&minx_cpu_device::minx_CE_00, &minx_cpu_device::minx_CE_01, &minx_cpu_device::minx_CE_02, &minx_cpu_device::minx_CE_03, &minx_cpu_device::minx_CE_04, &minx_cpu_device::minx_CE_05, &minx_cpu_device::minx_CE_06, &minx_cpu_device::minx_CE_07,
|
||||
&minx_cpu_device::minx_CE_08, &minx_cpu_device::minx_CE_09, &minx_cpu_device::minx_CE_0A, &minx_cpu_device::minx_CE_0B, &minx_cpu_device::minx_CE_0C, &minx_cpu_device::minx_CE_0D, &minx_cpu_device::minx_CE_0E, &minx_cpu_device::minx_CE_0F,
|
||||
&minx_cpu_device::minx_CE_10, &minx_cpu_device::minx_CE_11, &minx_cpu_device::minx_CE_12, &minx_cpu_device::minx_CE_13, &minx_cpu_device::minx_CE_14, &minx_cpu_device::minx_CE_15, &minx_cpu_device::minx_CE_16, &minx_cpu_device::minx_CE_17,
|
||||
&minx_cpu_device::minx_CE_18, &minx_cpu_device::minx_CE_19, &minx_cpu_device::minx_CE_1A, &minx_cpu_device::minx_CE_1B, &minx_cpu_device::minx_CE_1C, &minx_cpu_device::minx_CE_1D, &minx_cpu_device::minx_CE_1E, &minx_cpu_device::minx_CE_1F,
|
||||
&minx_cpu_device::minx_CE_20, &minx_cpu_device::minx_CE_21, &minx_cpu_device::minx_CE_22, &minx_cpu_device::minx_CE_23, &minx_cpu_device::minx_CE_24, &minx_cpu_device::minx_CE_25, &minx_cpu_device::minx_CE_26, &minx_cpu_device::minx_CE_27,
|
||||
&minx_cpu_device::minx_CE_28, &minx_cpu_device::minx_CE_29, &minx_cpu_device::minx_CE_2A, &minx_cpu_device::minx_CE_2B, &minx_cpu_device::minx_CE_2C, &minx_cpu_device::minx_CE_2D, &minx_cpu_device::minx_CE_2E, &minx_cpu_device::minx_CE_2F,
|
||||
&minx_cpu_device::minx_CE_30, &minx_cpu_device::minx_CE_31, &minx_cpu_device::minx_CE_32, &minx_cpu_device::minx_CE_33, &minx_cpu_device::minx_CE_34, &minx_cpu_device::minx_CE_35, &minx_cpu_device::minx_CE_36, &minx_cpu_device::minx_CE_37,
|
||||
&minx_cpu_device::minx_CE_38, &minx_cpu_device::minx_CE_39, &minx_cpu_device::minx_CE_3A, &minx_cpu_device::minx_CE_3B, &minx_cpu_device::minx_CE_3C, &minx_cpu_device::minx_CE_3D, &minx_cpu_device::minx_CE_3E, &minx_cpu_device::minx_CE_3F,
|
||||
&minx_cpu_device::minx_CE_40, &minx_cpu_device::minx_CE_41, &minx_cpu_device::minx_CE_42, &minx_cpu_device::minx_CE_43, &minx_cpu_device::minx_CE_44, &minx_cpu_device::minx_CE_45, &minx_cpu_device::minx_CE_46, &minx_cpu_device::minx_CE_47,
|
||||
&minx_cpu_device::minx_CE_48, &minx_cpu_device::minx_CE_49, &minx_cpu_device::minx_CE_4A, &minx_cpu_device::minx_CE_4B, &minx_cpu_device::minx_CE_4C, &minx_cpu_device::minx_CE_4D, &minx_cpu_device::minx_CE_4E, &minx_cpu_device::minx_CE_4F,
|
||||
&minx_cpu_device::minx_CE_50, &minx_cpu_device::minx_CE_51, &minx_cpu_device::minx_CE_52, &minx_cpu_device::minx_CE_53, &minx_cpu_device::minx_CE_54, &minx_cpu_device::minx_CE_55, &minx_cpu_device::minx_CE_56, &minx_cpu_device::minx_CE_57,
|
||||
&minx_cpu_device::minx_CE_58, &minx_cpu_device::minx_CE_59, &minx_cpu_device::minx_CE_5A, &minx_cpu_device::minx_CE_5B, &minx_cpu_device::minx_CE_5C, &minx_cpu_device::minx_CE_5D, &minx_cpu_device::minx_CE_5E, &minx_cpu_device::minx_CE_5F,
|
||||
&minx_cpu_device::minx_CE_60, &minx_cpu_device::minx_CE_61, &minx_cpu_device::minx_CE_62, &minx_cpu_device::minx_CE_63, &minx_cpu_device::minx_CE_64, &minx_cpu_device::minx_CE_65, &minx_cpu_device::minx_CE_66, &minx_cpu_device::minx_CE_67,
|
||||
&minx_cpu_device::minx_CE_68, &minx_cpu_device::minx_CE_69, &minx_cpu_device::minx_CE_6A, &minx_cpu_device::minx_CE_6B, &minx_cpu_device::minx_CE_6C, &minx_cpu_device::minx_CE_6D, &minx_cpu_device::minx_CE_6E, &minx_cpu_device::minx_CE_6F,
|
||||
&minx_cpu_device::minx_CE_70, &minx_cpu_device::minx_CE_71, &minx_cpu_device::minx_CE_72, &minx_cpu_device::minx_CE_73, &minx_cpu_device::minx_CE_74, &minx_cpu_device::minx_CE_75, &minx_cpu_device::minx_CE_76, &minx_cpu_device::minx_CE_77,
|
||||
&minx_cpu_device::minx_CE_78, &minx_cpu_device::minx_CE_79, &minx_cpu_device::minx_CE_7A, &minx_cpu_device::minx_CE_7B, &minx_cpu_device::minx_CE_7C, &minx_cpu_device::minx_CE_7D, &minx_cpu_device::minx_CE_7E, &minx_cpu_device::minx_CE_7F,
|
||||
&minx_cpu_device::minx_CE_80, &minx_cpu_device::minx_CE_81, &minx_cpu_device::minx_CE_82, &minx_cpu_device::minx_CE_83, &minx_cpu_device::minx_CE_84, &minx_cpu_device::minx_CE_85, &minx_cpu_device::minx_CE_86, &minx_cpu_device::minx_CE_87,
|
||||
&minx_cpu_device::minx_CE_88, &minx_cpu_device::minx_CE_89, &minx_cpu_device::minx_CE_8A, &minx_cpu_device::minx_CE_8B, &minx_cpu_device::minx_CE_8C, &minx_cpu_device::minx_CE_8D, &minx_cpu_device::minx_CE_8E, &minx_cpu_device::minx_CE_8F,
|
||||
&minx_cpu_device::minx_CE_90, &minx_cpu_device::minx_CE_91, &minx_cpu_device::minx_CE_92, &minx_cpu_device::minx_CE_93, &minx_cpu_device::minx_CE_94, &minx_cpu_device::minx_CE_95, &minx_cpu_device::minx_CE_96, &minx_cpu_device::minx_CE_97,
|
||||
&minx_cpu_device::minx_CE_98, &minx_cpu_device::minx_CE_99, &minx_cpu_device::minx_CE_9A, &minx_cpu_device::minx_CE_9B, &minx_cpu_device::minx_CE_9C, &minx_cpu_device::minx_CE_9D, &minx_cpu_device::minx_CE_9E, &minx_cpu_device::minx_CE_9F,
|
||||
&minx_cpu_device::minx_CE_A0, &minx_cpu_device::minx_CE_A1, &minx_cpu_device::minx_CE_A2, &minx_cpu_device::minx_CE_A3, &minx_cpu_device::minx_CE_A4, &minx_cpu_device::minx_CE_A5, &minx_cpu_device::minx_CE_A6, &minx_cpu_device::minx_CE_A7,
|
||||
&minx_cpu_device::minx_CE_A8, &minx_cpu_device::minx_CE_A9, &minx_cpu_device::minx_CE_AA, &minx_cpu_device::minx_CE_AB, &minx_cpu_device::minx_CE_AC, &minx_cpu_device::minx_CE_AD, &minx_cpu_device::minx_CE_AE, &minx_cpu_device::minx_CE_AF,
|
||||
&minx_cpu_device::minx_CE_B0, &minx_cpu_device::minx_CE_B1, &minx_cpu_device::minx_CE_B2, &minx_cpu_device::minx_CE_B3, &minx_cpu_device::minx_CE_B4, &minx_cpu_device::minx_CE_B5, &minx_cpu_device::minx_CE_B6, &minx_cpu_device::minx_CE_B7,
|
||||
&minx_cpu_device::minx_CE_B8, &minx_cpu_device::minx_CE_B9, &minx_cpu_device::minx_CE_BA, &minx_cpu_device::minx_CE_BB, &minx_cpu_device::minx_CE_BC, &minx_cpu_device::minx_CE_BD, &minx_cpu_device::minx_CE_BE, &minx_cpu_device::minx_CE_BF,
|
||||
&minx_cpu_device::minx_CE_C0, &minx_cpu_device::minx_CE_C1, &minx_cpu_device::minx_CE_C2, &minx_cpu_device::minx_CE_C3, &minx_cpu_device::minx_CE_C4, &minx_cpu_device::minx_CE_C5, &minx_cpu_device::minx_CE_C6, &minx_cpu_device::minx_CE_C7,
|
||||
&minx_cpu_device::minx_CE_C8, &minx_cpu_device::minx_CE_C9, &minx_cpu_device::minx_CE_CA, &minx_cpu_device::minx_CE_CB, &minx_cpu_device::minx_CE_CC, &minx_cpu_device::minx_CE_CD, &minx_cpu_device::minx_CE_CE, &minx_cpu_device::minx_CE_CF,
|
||||
&minx_cpu_device::minx_CE_D0, &minx_cpu_device::minx_CE_D1, &minx_cpu_device::minx_CE_D2, &minx_cpu_device::minx_CE_D3, &minx_cpu_device::minx_CE_D4, &minx_cpu_device::minx_CE_D5, &minx_cpu_device::minx_CE_D6, &minx_cpu_device::minx_CE_D7,
|
||||
&minx_cpu_device::minx_CE_D8, &minx_cpu_device::minx_CE_D9, &minx_cpu_device::minx_CE_DA, &minx_cpu_device::minx_CE_DB, &minx_cpu_device::minx_CE_DC, &minx_cpu_device::minx_CE_DD, &minx_cpu_device::minx_CE_DE, &minx_cpu_device::minx_CE_DF,
|
||||
&minx_cpu_device::minx_CE_E0, &minx_cpu_device::minx_CE_E1, &minx_cpu_device::minx_CE_E2, &minx_cpu_device::minx_CE_E3, &minx_cpu_device::minx_CE_E4, &minx_cpu_device::minx_CE_E5, &minx_cpu_device::minx_CE_E6, &minx_cpu_device::minx_CE_E7,
|
||||
&minx_cpu_device::minx_CE_E8, &minx_cpu_device::minx_CE_E9, &minx_cpu_device::minx_CE_EA, &minx_cpu_device::minx_CE_EB, &minx_cpu_device::minx_CE_EC, &minx_cpu_device::minx_CE_ED, &minx_cpu_device::minx_CE_EE, &minx_cpu_device::minx_CE_EF,
|
||||
&minx_cpu_device::minx_CE_F0, &minx_cpu_device::minx_CE_F1, &minx_cpu_device::minx_CE_F2, &minx_cpu_device::minx_CE_F3, &minx_cpu_device::minx_CE_F4, &minx_cpu_device::minx_CE_F5, &minx_cpu_device::minx_CE_F6, &minx_cpu_device::minx_CE_F7,
|
||||
&minx_cpu_device::minx_CE_F8, &minx_cpu_device::minx_CE_F9, &minx_cpu_device::minx_CE_FA, &minx_cpu_device::minx_CE_FB, &minx_cpu_device::minx_CE_FC, &minx_cpu_device::minx_CE_FD, &minx_cpu_device::minx_CE_FE, &minx_cpu_device::minx_CE_FF
|
||||
};
|
||||
|
||||
const int minx_cpu_device::insnminx_cycles_CE[256] = {
|
||||
16, 16, 16, 16, 16, 20, 20, 20, 16, 16, 16, 16, 16, 20, 20, 20,
|
||||
|
||||
@ -1,312 +1,542 @@
|
||||
#undef OP
|
||||
#define OP(nn) void minx_cpu_device::minx_CF_##nn()
|
||||
|
||||
OP(00) { m_BA = ADD16( m_BA, m_BA ); }
|
||||
OP(01) { m_BA = ADD16( m_BA, m_HL ); }
|
||||
OP(02) { m_BA = ADD16( m_BA, m_X ); }
|
||||
OP(03) { m_BA = ADD16( m_BA, m_Y ); }
|
||||
OP(04) { m_BA = ADDC16( m_BA, m_BA ); }
|
||||
OP(05) { m_BA = ADDC16( m_BA, m_HL ); }
|
||||
OP(06) { m_BA = ADDC16( m_BA, m_X ); }
|
||||
OP(07) { m_BA = ADDC16( m_BA, m_Y ); }
|
||||
OP(08) { m_BA = SUB16( m_BA, m_BA ); }
|
||||
OP(09) { m_BA = SUB16( m_BA, m_HL ); }
|
||||
OP(0A) { m_BA = SUB16( m_BA, m_X ); }
|
||||
OP(0B) { m_BA = SUB16( m_BA, m_Y ); }
|
||||
OP(0C) { m_BA = SUBC16( m_BA, m_BA ); }
|
||||
OP(0D) { m_BA = SUBC16( m_BA, m_HL ); }
|
||||
OP(0E) { m_BA = SUBC16( m_BA, m_X ); }
|
||||
OP(0F) { m_BA = SUBC16( m_BA, m_Y ); }
|
||||
void minx_cpu_device::execute_one_cf()
|
||||
{
|
||||
const UINT8 opcode = rdop();
|
||||
|
||||
OP(10) { /* illegal instruction? */ }
|
||||
OP(11) { /* illegal instruction? */ }
|
||||
OP(12) { /* illegal instruction? */ }
|
||||
OP(13) { /* illegal instruction? */ }
|
||||
OP(14) { /* illegal instruction? */ }
|
||||
OP(15) { /* illegal instruction? */ }
|
||||
OP(16) { /* illegal instruction? */ }
|
||||
OP(17) { /* illegal instruction? */ }
|
||||
OP(18) { SUB16( m_BA, m_BA ); }
|
||||
OP(19) { SUB16( m_BA, m_HL ); }
|
||||
OP(1A) { SUB16( m_BA, m_X ); }
|
||||
OP(1B) { SUB16( m_BA, m_Y ); }
|
||||
OP(1C) { /* illegal instruction? */ }
|
||||
OP(1D) { /* illegal instruction? */ }
|
||||
OP(1E) { /* illegal instruction? */ }
|
||||
OP(1F) { /* illegal instruction? */ }
|
||||
switch (opcode)
|
||||
{
|
||||
case 0x00: { m_BA = ADD16( m_BA, m_BA ); }
|
||||
break;
|
||||
case 0x01: { m_BA = ADD16( m_BA, m_HL ); }
|
||||
break;
|
||||
case 0x02: { m_BA = ADD16( m_BA, m_X ); }
|
||||
break;
|
||||
case 0x03: { m_BA = ADD16( m_BA, m_Y ); }
|
||||
break;
|
||||
case 0x04: { m_BA = ADDC16( m_BA, m_BA ); }
|
||||
break;
|
||||
case 0x05: { m_BA = ADDC16( m_BA, m_HL ); }
|
||||
break;
|
||||
case 0x06: { m_BA = ADDC16( m_BA, m_X ); }
|
||||
break;
|
||||
case 0x07: { m_BA = ADDC16( m_BA, m_Y ); }
|
||||
break;
|
||||
case 0x08: { m_BA = SUB16( m_BA, m_BA ); }
|
||||
break;
|
||||
case 0x09: { m_BA = SUB16( m_BA, m_HL ); }
|
||||
break;
|
||||
case 0x0A: { m_BA = SUB16( m_BA, m_X ); }
|
||||
break;
|
||||
case 0x0B: { m_BA = SUB16( m_BA, m_Y ); }
|
||||
break;
|
||||
case 0x0C: { m_BA = SUBC16( m_BA, m_BA ); }
|
||||
break;
|
||||
case 0x0D: { m_BA = SUBC16( m_BA, m_HL ); }
|
||||
break;
|
||||
case 0x0E: { m_BA = SUBC16( m_BA, m_X ); }
|
||||
break;
|
||||
case 0x0F: { m_BA = SUBC16( m_BA, m_Y ); }
|
||||
break;
|
||||
|
||||
OP(20) { m_HL = ADD16( m_HL, m_BA ); }
|
||||
OP(21) { m_HL = ADD16( m_HL, m_HL ); }
|
||||
OP(22) { m_HL = ADD16( m_HL, m_X ); }
|
||||
OP(23) { m_HL = ADD16( m_HL, m_Y ); }
|
||||
OP(24) { m_HL = ADDC16( m_HL, m_BA ); }
|
||||
OP(25) { m_HL = ADDC16( m_HL, m_HL ); }
|
||||
OP(26) { m_HL = ADDC16( m_HL, m_X ); }
|
||||
OP(27) { m_HL = ADDC16( m_HL, m_Y ); }
|
||||
OP(28) { m_HL = SUB16( m_HL, m_BA ); }
|
||||
OP(29) { m_HL = SUB16( m_HL, m_HL ); }
|
||||
OP(2A) { m_HL = SUB16( m_HL, m_X ); }
|
||||
OP(2B) { m_HL = SUB16( m_HL, m_Y ); }
|
||||
OP(2C) { m_HL = SUBC16( m_HL, m_BA ); }
|
||||
OP(2D) { m_HL = SUBC16( m_HL, m_HL ); }
|
||||
OP(2E) { m_HL = SUBC16( m_HL, m_X ); }
|
||||
OP(2F) { m_HL = SUBC16( m_HL, m_Y ); }
|
||||
case 0x10: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x11: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x12: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x13: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x14: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x15: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x16: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x17: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x18: { SUB16( m_BA, m_BA ); }
|
||||
break;
|
||||
case 0x19: { SUB16( m_BA, m_HL ); }
|
||||
break;
|
||||
case 0x1A: { SUB16( m_BA, m_X ); }
|
||||
break;
|
||||
case 0x1B: { SUB16( m_BA, m_Y ); }
|
||||
break;
|
||||
case 0x1C: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x1D: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x1E: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x1F: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(30) { /* illegal instruction? */ }
|
||||
OP(31) { /* illegal instruction? */ }
|
||||
OP(32) { /* illegal instruction? */ }
|
||||
OP(33) { /* illegal instruction? */ }
|
||||
OP(34) { /* illegal instruction? */ }
|
||||
OP(35) { /* illegal instruction? */ }
|
||||
OP(36) { /* illegal instruction? */ }
|
||||
OP(37) { /* illegal instruction? */ }
|
||||
OP(38) { SUB16( m_HL, m_BA ); }
|
||||
OP(39) { SUB16( m_HL, m_HL ); }
|
||||
OP(3A) { SUB16( m_HL, m_X ); }
|
||||
OP(3B) { SUB16( m_HL, m_Y ); }
|
||||
OP(3C) { /* illegal instruction? */ }
|
||||
OP(3D) { /* illegal instruction? */ }
|
||||
OP(3E) { /* illegal instruction? */ }
|
||||
OP(3F) { /* illegal instruction? */ }
|
||||
case 0x20: { m_HL = ADD16( m_HL, m_BA ); }
|
||||
break;
|
||||
case 0x21: { m_HL = ADD16( m_HL, m_HL ); }
|
||||
break;
|
||||
case 0x22: { m_HL = ADD16( m_HL, m_X ); }
|
||||
break;
|
||||
case 0x23: { m_HL = ADD16( m_HL, m_Y ); }
|
||||
break;
|
||||
case 0x24: { m_HL = ADDC16( m_HL, m_BA ); }
|
||||
break;
|
||||
case 0x25: { m_HL = ADDC16( m_HL, m_HL ); }
|
||||
break;
|
||||
case 0x26: { m_HL = ADDC16( m_HL, m_X ); }
|
||||
break;
|
||||
case 0x27: { m_HL = ADDC16( m_HL, m_Y ); }
|
||||
break;
|
||||
case 0x28: { m_HL = SUB16( m_HL, m_BA ); }
|
||||
break;
|
||||
case 0x29: { m_HL = SUB16( m_HL, m_HL ); }
|
||||
break;
|
||||
case 0x2A: { m_HL = SUB16( m_HL, m_X ); }
|
||||
break;
|
||||
case 0x2B: { m_HL = SUB16( m_HL, m_Y ); }
|
||||
break;
|
||||
case 0x2C: { m_HL = SUBC16( m_HL, m_BA ); }
|
||||
break;
|
||||
case 0x2D: { m_HL = SUBC16( m_HL, m_HL ); }
|
||||
break;
|
||||
case 0x2E: { m_HL = SUBC16( m_HL, m_X ); }
|
||||
break;
|
||||
case 0x2F: { m_HL = SUBC16( m_HL, m_Y ); }
|
||||
break;
|
||||
|
||||
OP(40) { m_X = ADD16( m_X, m_BA ); }
|
||||
OP(41) { m_X = ADD16( m_X, m_HL ); }
|
||||
OP(42) { m_Y = ADD16( m_Y, m_BA ); }
|
||||
OP(43) { m_Y = ADD16( m_Y, m_HL ); }
|
||||
OP(44) { m_SP = ADD16( m_SP, m_BA ); }
|
||||
OP(45) { m_SP = ADD16( m_SP, m_HL ); }
|
||||
OP(46) { /* illegal instruction? */ }
|
||||
OP(47) { /* illegal instruction? */ }
|
||||
OP(48) { m_X = SUB16( m_X, m_BA ); }
|
||||
OP(49) { m_X = SUB16( m_X, m_HL ); }
|
||||
OP(4A) { m_Y = SUB16( m_Y, m_BA ); }
|
||||
OP(4B) { m_Y = SUB16( m_Y, m_HL ); }
|
||||
OP(4C) { m_SP = SUB16( m_SP, m_BA ); }
|
||||
OP(4D) { m_SP = SUB16( m_SP, m_HL ); }
|
||||
OP(4E) { /* illegal instruction? */ }
|
||||
OP(4F) { /* illegal instruction? */ }
|
||||
case 0x30: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x31: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x32: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x33: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x34: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x35: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x36: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x37: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x38: { SUB16( m_HL, m_BA ); }
|
||||
break;
|
||||
case 0x39: { SUB16( m_HL, m_HL ); }
|
||||
break;
|
||||
case 0x3A: { SUB16( m_HL, m_X ); }
|
||||
break;
|
||||
case 0x3B: { SUB16( m_HL, m_Y ); }
|
||||
break;
|
||||
case 0x3C: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x3D: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x3E: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x3F: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(50) { /* illegal instruction? */ }
|
||||
OP(51) { /* illegal instruction? */ }
|
||||
OP(52) { /* illegal instruction? */ }
|
||||
OP(53) { /* illegal instruction? */ }
|
||||
OP(54) { /* illegal instruction? */ }
|
||||
OP(55) { /* illegal instruction? */ }
|
||||
OP(56) { /* illegal instruction? */ }
|
||||
OP(57) { /* illegal instruction? */ }
|
||||
OP(58) { /* illegal instruction? */ }
|
||||
OP(59) { /* illegal instruction? */ }
|
||||
OP(5A) { /* illegal instruction? */ }
|
||||
OP(5B) { /* illegal instruction? */ }
|
||||
OP(5C) { SUB16( m_SP, m_BA ); }
|
||||
OP(5D) { SUB16( m_SP, m_HL ); }
|
||||
OP(5E) { /* illegal instruction? */ }
|
||||
OP(5F) { /* illegal instruction? */ }
|
||||
case 0x40: { m_X = ADD16( m_X, m_BA ); }
|
||||
break;
|
||||
case 0x41: { m_X = ADD16( m_X, m_HL ); }
|
||||
break;
|
||||
case 0x42: { m_Y = ADD16( m_Y, m_BA ); }
|
||||
break;
|
||||
case 0x43: { m_Y = ADD16( m_Y, m_HL ); }
|
||||
break;
|
||||
case 0x44: { m_SP = ADD16( m_SP, m_BA ); }
|
||||
break;
|
||||
case 0x45: { m_SP = ADD16( m_SP, m_HL ); }
|
||||
break;
|
||||
case 0x46: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x47: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x48: { m_X = SUB16( m_X, m_BA ); }
|
||||
break;
|
||||
case 0x49: { m_X = SUB16( m_X, m_HL ); }
|
||||
break;
|
||||
case 0x4A: { m_Y = SUB16( m_Y, m_BA ); }
|
||||
break;
|
||||
case 0x4B: { m_Y = SUB16( m_Y, m_HL ); }
|
||||
break;
|
||||
case 0x4C: { m_SP = SUB16( m_SP, m_BA ); }
|
||||
break;
|
||||
case 0x4D: { m_SP = SUB16( m_SP, m_HL ); }
|
||||
break;
|
||||
case 0x4E: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x4F: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(60) { ADDC16( m_BA, rdop16() ); /* ??? */ }
|
||||
OP(61) { ADDC16( m_HL, rdop16() ); /* ??? */ }
|
||||
OP(62) { ADDC16( m_X, rdop16() ); /* ??? */ }
|
||||
OP(63) { ADDC16( m_Y, rdop16() ); /* ??? */ }
|
||||
OP(64) { /* illegal instruction? */ }
|
||||
OP(65) { /* illegal instruction? */ }
|
||||
OP(66) { /* illegal instruction? */ }
|
||||
OP(67) { /* illegal instruction? */ }
|
||||
OP(68) { m_SP = ADD16( m_SP, rdop16() ); }
|
||||
OP(69) { /* illegal instruction? */ }
|
||||
OP(6A) { m_SP = SUB16( m_SP, rdop16() ); }
|
||||
OP(6B) { /* illegal instruction? */ }
|
||||
OP(6C) { SUB16( m_SP, rdop16() ); }
|
||||
OP(6D) { /* illegal instruction? */ }
|
||||
OP(6E) { m_SP = rdop16(); }
|
||||
OP(6F) { /* illegal instruction? */ }
|
||||
case 0x50: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x51: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x52: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x53: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x54: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x55: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x56: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x57: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x58: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x59: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x5A: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x5B: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x5C: { SUB16( m_SP, m_BA ); }
|
||||
break;
|
||||
case 0x5D: { SUB16( m_SP, m_HL ); }
|
||||
break;
|
||||
case 0x5E: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x5F: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(70) { UINT8 ofs8 = rdop(); m_BA = rd16( m_SP + ofs8 ); }
|
||||
OP(71) { UINT8 ofs8 = rdop(); m_HL = rd16( m_SP + ofs8 ); }
|
||||
OP(72) { UINT8 ofs8 = rdop(); m_X = rd16( m_SP + ofs8 ); }
|
||||
OP(73) { UINT8 ofs8 = rdop(); m_Y = rd16( m_SP + ofs8 ); }
|
||||
OP(74) { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_BA ); }
|
||||
OP(75) { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_HL ); }
|
||||
OP(76) { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_X ); }
|
||||
OP(77) { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_Y ); }
|
||||
OP(78) { AD2_I16; m_SP = rd16( addr2 ); }
|
||||
OP(79) { /* illegal instruction? */ }
|
||||
OP(7A) { /* illegal instruction? */ }
|
||||
OP(7B) { /* illegal instruction? */ }
|
||||
OP(7C) { AD1_I16; wr16( addr1, m_SP ); }
|
||||
OP(7D) { /* illegal instruction? */ }
|
||||
OP(7E) { /* illegal instruction? */ }
|
||||
OP(7F) { /* illegal instruction? */ }
|
||||
case 0x60: { ADDC16( m_BA, rdop16() ); /* ??? */ }
|
||||
break;
|
||||
case 0x61: { ADDC16( m_HL, rdop16() ); /* ??? */ }
|
||||
break;
|
||||
case 0x62: { ADDC16( m_X, rdop16() ); /* ??? */ }
|
||||
break;
|
||||
case 0x63: { ADDC16( m_Y, rdop16() ); /* ??? */ }
|
||||
break;
|
||||
case 0x64: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x65: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x66: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x67: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x68: { m_SP = ADD16( m_SP, rdop16() ); }
|
||||
break;
|
||||
case 0x69: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x6A: { m_SP = SUB16( m_SP, rdop16() ); }
|
||||
break;
|
||||
case 0x6B: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x6C: { SUB16( m_SP, rdop16() ); }
|
||||
break;
|
||||
case 0x6D: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x6E: { m_SP = rdop16(); }
|
||||
break;
|
||||
case 0x6F: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(80) { /* illegal instruction? */ }
|
||||
OP(81) { /* illegal instruction? */ }
|
||||
OP(82) { /* illegal instruction? */ }
|
||||
OP(83) { /* illegal instruction? */ }
|
||||
OP(84) { /* illegal instruction? */ }
|
||||
OP(85) { /* illegal instruction? */ }
|
||||
OP(86) { /* illegal instruction? */ }
|
||||
OP(87) { /* illegal instruction? */ }
|
||||
OP(88) { /* illegal instruction? */ }
|
||||
OP(89) { /* illegal instruction? */ }
|
||||
OP(8A) { /* illegal instruction? */ }
|
||||
OP(8B) { /* illegal instruction? */ }
|
||||
OP(8C) { /* illegal instruction? */ }
|
||||
OP(8D) { /* illegal instruction? */ }
|
||||
OP(8E) { /* illegal instruction? */ }
|
||||
OP(8F) { /* illegal instruction? */ }
|
||||
case 0x70: { UINT8 ofs8 = rdop(); m_BA = rd16( m_SP + ofs8 ); }
|
||||
break;
|
||||
case 0x71: { UINT8 ofs8 = rdop(); m_HL = rd16( m_SP + ofs8 ); }
|
||||
break;
|
||||
case 0x72: { UINT8 ofs8 = rdop(); m_X = rd16( m_SP + ofs8 ); }
|
||||
break;
|
||||
case 0x73: { UINT8 ofs8 = rdop(); m_Y = rd16( m_SP + ofs8 ); }
|
||||
break;
|
||||
case 0x74: { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_BA ); }
|
||||
break;
|
||||
case 0x75: { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_HL ); }
|
||||
break;
|
||||
case 0x76: { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_X ); }
|
||||
break;
|
||||
case 0x77: { UINT8 ofs8 = rdop(); wr16( m_SP + ofs8, m_Y ); }
|
||||
break;
|
||||
case 0x78: { AD2_I16; m_SP = rd16( addr2 ); }
|
||||
break;
|
||||
case 0x79: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x7A: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x7B: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x7C: { AD1_I16; wr16( addr1, m_SP ); }
|
||||
break;
|
||||
case 0x7D: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x7E: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x7F: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(90) { /* illegal instruction? */ }
|
||||
OP(91) { /* illegal instruction? */ }
|
||||
OP(92) { /* illegal instruction? */ }
|
||||
OP(93) { /* illegal instruction? */ }
|
||||
OP(94) { /* illegal instruction? */ }
|
||||
OP(95) { /* illegal instruction? */ }
|
||||
OP(96) { /* illegal instruction? */ }
|
||||
OP(97) { /* illegal instruction? */ }
|
||||
OP(98) { /* illegal instruction? */ }
|
||||
OP(99) { /* illegal instruction? */ }
|
||||
OP(9A) { /* illegal instruction? */ }
|
||||
OP(9B) { /* illegal instruction? */ }
|
||||
OP(9C) { /* illegal instruction? */ }
|
||||
OP(9D) { /* illegal instruction? */ }
|
||||
OP(9E) { /* illegal instruction? */ }
|
||||
OP(9F) { /* illegal instruction? */ }
|
||||
case 0x80: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x81: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x82: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x83: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x84: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x85: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x86: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x87: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x88: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x89: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x8A: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x8B: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x8C: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x8D: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x8E: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x8F: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(A0) { /* illegal instruction? */ }
|
||||
OP(A1) { /* illegal instruction? */ }
|
||||
OP(A2) { /* illegal instruction? */ }
|
||||
OP(A3) { /* illegal instruction? */ }
|
||||
OP(A4) { /* illegal instruction? */ }
|
||||
OP(A5) { /* illegal instruction? */ }
|
||||
OP(A6) { /* illegal instruction? */ }
|
||||
OP(A7) { /* illegal instruction? */ }
|
||||
OP(A8) { /* illegal instruction? */ }
|
||||
OP(A9) { /* illegal instruction? */ }
|
||||
OP(AA) { /* illegal instruction? */ }
|
||||
OP(AB) { /* illegal instruction? */ }
|
||||
OP(AC) { /* illegal instruction? */ }
|
||||
OP(AD) { /* illegal instruction? */ }
|
||||
OP(AE) { /* illegal instruction? */ }
|
||||
OP(AF) { /* illegal instruction? */ }
|
||||
case 0x90: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x91: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x92: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x93: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x94: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x95: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x96: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x97: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x98: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x99: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x9A: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x9B: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x9C: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x9D: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x9E: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0x9F: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(B0) { PUSH8( m_BA & 0x00FF ); }
|
||||
OP(B1) { PUSH8( m_BA >> 8 ); }
|
||||
OP(B2) { PUSH8( m_HL & 0x00FF ); }
|
||||
OP(B3) { PUSH8( m_HL >> 8 ); }
|
||||
OP(B4) { m_BA = ( m_BA & 0xFF00 ) | POP8(); }
|
||||
OP(B5) { m_BA = ( m_BA & 0x00FF ) | ( POP8() << 8 ); }
|
||||
OP(B6) { m_HL = ( m_HL & 0xFF00 ) | POP8(); }
|
||||
OP(B7) { m_HL = ( m_HL & 0x00FF ) | ( POP8() << 8 ); }
|
||||
OP(B8) { PUSH16( m_BA ); PUSH16( m_HL ); PUSH16( m_X ); PUSH16( m_Y ); PUSH8( m_N ); }
|
||||
OP(B9) { PUSH16( m_BA ); PUSH16( m_HL ); PUSH16( m_X ); PUSH16( m_Y ); PUSH8( m_N ); PUSH8( m_I ); PUSH8( m_XI ); PUSH8( m_YI ); }
|
||||
OP(BA) { /* illegal instruction? */ }
|
||||
OP(BB) { /* illegal instruction? */ }
|
||||
OP(BC) { m_N = POP8(); m_Y = POP16(); m_X = POP16(); m_HL = POP16(); m_BA = POP16(); }
|
||||
OP(BD) { m_YI = POP8(); m_XI = POP8(); m_I = POP8(); m_N = POP8(); m_Y = POP16(); m_X = POP16(); m_HL = POP16(); m_BA = POP16(); }
|
||||
OP(BE) { /* illegal instruction? */ }
|
||||
OP(BF) { /* illegal instruction? */ }
|
||||
case 0xA0: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xA1: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xA2: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xA3: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xA4: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xA5: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xA6: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xA7: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xA8: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xA9: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xAA: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xAB: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xAC: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xAD: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xAE: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xAF: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(C0) { AD2_IHL; m_BA = rd16( addr2 ); }
|
||||
OP(C1) { AD2_IHL; m_HL = rd16( addr2 ); }
|
||||
OP(C2) { AD2_IHL; m_X = rd16( addr2 ); }
|
||||
OP(C3) { AD2_IHL; m_Y = rd16( addr2 ); }
|
||||
OP(C4) { AD1_IHL; wr16( addr1, m_BA ); }
|
||||
OP(C5) { AD1_IHL; wr16( addr1, m_HL ); }
|
||||
OP(C6) { AD1_IHL; wr16( addr1, m_X ); }
|
||||
OP(C7) { AD1_IHL; wr16( addr1, m_Y ); }
|
||||
OP(C8) { /* illegal instruction? */ }
|
||||
OP(C9) { /* illegal instruction? */ }
|
||||
OP(CA) { /* illegal instruction? */ }
|
||||
OP(CB) { /* illegal instruction? */ }
|
||||
OP(CC) { /* illegal instruction? */ }
|
||||
OP(CD) { /* illegal instruction? */ }
|
||||
OP(CE) { /* illegal instruction? */ }
|
||||
OP(CF) { /* illegal instruction? */ }
|
||||
case 0xB0: { PUSH8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0xB1: { PUSH8( m_BA >> 8 ); }
|
||||
break;
|
||||
case 0xB2: { PUSH8( m_HL & 0x00FF ); }
|
||||
break;
|
||||
case 0xB3: { PUSH8( m_HL >> 8 ); }
|
||||
break;
|
||||
case 0xB4: { m_BA = ( m_BA & 0xFF00 ) | POP8(); }
|
||||
break;
|
||||
case 0xB5: { m_BA = ( m_BA & 0x00FF ) | ( POP8() << 8 ); }
|
||||
break;
|
||||
case 0xB6: { m_HL = ( m_HL & 0xFF00 ) | POP8(); }
|
||||
break;
|
||||
case 0xB7: { m_HL = ( m_HL & 0x00FF ) | ( POP8() << 8 ); }
|
||||
break;
|
||||
case 0xB8: { PUSH16( m_BA ); PUSH16( m_HL ); PUSH16( m_X ); PUSH16( m_Y ); PUSH8( m_N ); }
|
||||
break;
|
||||
case 0xB9: { PUSH16( m_BA ); PUSH16( m_HL ); PUSH16( m_X ); PUSH16( m_Y ); PUSH8( m_N ); PUSH8( m_I ); PUSH8( m_XI ); PUSH8( m_YI ); }
|
||||
break;
|
||||
case 0xBA: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xBB: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xBC: { m_N = POP8(); m_Y = POP16(); m_X = POP16(); m_HL = POP16(); m_BA = POP16(); }
|
||||
break;
|
||||
case 0xBD: { m_YI = POP8(); m_XI = POP8(); m_I = POP8(); m_N = POP8(); m_Y = POP16(); m_X = POP16(); m_HL = POP16(); m_BA = POP16(); }
|
||||
break;
|
||||
case 0xBE: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xBF: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(D0) { AD2_XIX; m_BA = rd16( addr2 ); }
|
||||
OP(D1) { AD2_XIX; m_HL = rd16( addr2 ); }
|
||||
OP(D2) { AD2_XIX; m_X = rd16( addr2 ); }
|
||||
OP(D3) { AD2_XIX; m_Y = rd16( addr2 ); }
|
||||
OP(D4) { AD1_XIX; wr16( addr1, m_BA ); }
|
||||
OP(D5) { AD1_XIX; wr16( addr1, m_HL ); }
|
||||
OP(D6) { AD1_XIX; wr16( addr1, m_X ); }
|
||||
OP(D7) { AD1_XIX; wr16( addr1, m_Y ); }
|
||||
OP(D8) { AD2_YIY; m_BA = rd16( addr2 ); }
|
||||
OP(D9) { AD2_YIY; m_HL = rd16( addr2 ); }
|
||||
OP(DA) { AD2_YIY; m_X = rd16( addr2 ); }
|
||||
OP(DB) { AD2_YIY; m_Y = rd16( addr2 ); }
|
||||
OP(DC) { AD1_YIY; wr16( addr1, m_BA ); }
|
||||
OP(DD) { AD1_YIY; wr16( addr1, m_HL ); }
|
||||
OP(DE) { AD1_YIY; wr16( addr1, m_X ); }
|
||||
OP(DF) { AD1_YIY; wr16( addr1, m_Y ); }
|
||||
case 0xC0: { AD2_IHL; m_BA = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xC1: { AD2_IHL; m_HL = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xC2: { AD2_IHL; m_X = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xC3: { AD2_IHL; m_Y = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xC4: { AD1_IHL; wr16( addr1, m_BA ); }
|
||||
break;
|
||||
case 0xC5: { AD1_IHL; wr16( addr1, m_HL ); }
|
||||
break;
|
||||
case 0xC6: { AD1_IHL; wr16( addr1, m_X ); }
|
||||
break;
|
||||
case 0xC7: { AD1_IHL; wr16( addr1, m_Y ); }
|
||||
break;
|
||||
case 0xC8: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xC9: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xCA: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xCB: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xCC: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xCD: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xCE: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xCF: { /* illegal instruction? */ }
|
||||
break;
|
||||
|
||||
OP(E0) { } //{ m_BA = m_BA; }
|
||||
OP(E1) { m_BA = m_HL; }
|
||||
OP(E2) { m_BA = m_X; }
|
||||
OP(E3) { m_BA = m_Y; }
|
||||
OP(E4) { m_HL = m_BA; }
|
||||
OP(E5) { } //{ m_HL = m_HL; }
|
||||
OP(E6) { m_HL = m_X; }
|
||||
OP(E7) { m_HL = m_Y; }
|
||||
OP(E8) { m_X = m_BA; }
|
||||
OP(E9) { m_X = m_HL; }
|
||||
OP(EA) { } //{ m_X = m_X; }
|
||||
OP(EB) { m_X = m_Y; }
|
||||
OP(EC) { m_Y = m_BA; }
|
||||
OP(ED) { m_Y = m_HL; }
|
||||
OP(EE) { m_Y = m_X; }
|
||||
OP(EF) { } //{ m_Y = m_Y; }
|
||||
case 0xD0: { AD2_XIX; m_BA = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xD1: { AD2_XIX; m_HL = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xD2: { AD2_XIX; m_X = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xD3: { AD2_XIX; m_Y = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xD4: { AD1_XIX; wr16( addr1, m_BA ); }
|
||||
break;
|
||||
case 0xD5: { AD1_XIX; wr16( addr1, m_HL ); }
|
||||
break;
|
||||
case 0xD6: { AD1_XIX; wr16( addr1, m_X ); }
|
||||
break;
|
||||
case 0xD7: { AD1_XIX; wr16( addr1, m_Y ); }
|
||||
break;
|
||||
case 0xD8: { AD2_YIY; m_BA = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xD9: { AD2_YIY; m_HL = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xDA: { AD2_YIY; m_X = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xDB: { AD2_YIY; m_Y = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xDC: { AD1_YIY; wr16( addr1, m_BA ); }
|
||||
break;
|
||||
case 0xDD: { AD1_YIY; wr16( addr1, m_HL ); }
|
||||
break;
|
||||
case 0xDE: { AD1_YIY; wr16( addr1, m_X ); }
|
||||
break;
|
||||
case 0xDF: { AD1_YIY; wr16( addr1, m_Y ); }
|
||||
break;
|
||||
|
||||
OP(F0) { m_SP = m_BA; }
|
||||
OP(F1) { m_SP = m_HL; }
|
||||
OP(F2) { m_SP = m_X; }
|
||||
OP(F3) { m_SP = m_Y; }
|
||||
OP(F4) { m_HL = m_SP; }
|
||||
OP(F5) { m_HL = m_PC; }
|
||||
OP(F6) { /* illegal instruction? */ }
|
||||
OP(F7) { /* illegal instruction? */ }
|
||||
OP(F8) { m_BA = m_SP; }
|
||||
OP(F9) { m_BA = m_PC; }
|
||||
OP(FA) { m_X = m_SP; }
|
||||
OP(FB) { /* illegal instruction? */ }
|
||||
OP(FC) { /* illegal instruction? */ }
|
||||
OP(FD) { /* illegal instruction? */ }
|
||||
OP(FE) { m_Y = m_SP; }
|
||||
OP(FF) { /* illegal instruction? */ }
|
||||
case 0xE0: { } //{ m_BA = m_BA; }
|
||||
break;
|
||||
case 0xE1: { m_BA = m_HL; }
|
||||
break;
|
||||
case 0xE2: { m_BA = m_X; }
|
||||
break;
|
||||
case 0xE3: { m_BA = m_Y; }
|
||||
break;
|
||||
case 0xE4: { m_HL = m_BA; }
|
||||
break;
|
||||
case 0xE5: { } //{ m_HL = m_HL; }
|
||||
break;
|
||||
case 0xE6: { m_HL = m_X; }
|
||||
break;
|
||||
case 0xE7: { m_HL = m_Y; }
|
||||
break;
|
||||
case 0xE8: { m_X = m_BA; }
|
||||
break;
|
||||
case 0xE9: { m_X = m_HL; }
|
||||
break;
|
||||
case 0xEA: { } //{ m_X = m_X; }
|
||||
break;
|
||||
case 0xEB: { m_X = m_Y; }
|
||||
break;
|
||||
case 0xEC: { m_Y = m_BA; }
|
||||
break;
|
||||
case 0xED: { m_Y = m_HL; }
|
||||
break;
|
||||
case 0xEE: { m_Y = m_X; }
|
||||
break;
|
||||
case 0xEF: { } //{ m_Y = m_Y; }
|
||||
break;
|
||||
|
||||
case 0xF0: { m_SP = m_BA; }
|
||||
break;
|
||||
case 0xF1: { m_SP = m_HL; }
|
||||
break;
|
||||
case 0xF2: { m_SP = m_X; }
|
||||
break;
|
||||
case 0xF3: { m_SP = m_Y; }
|
||||
break;
|
||||
case 0xF4: { m_HL = m_SP; }
|
||||
break;
|
||||
case 0xF5: { m_HL = m_PC; }
|
||||
break;
|
||||
case 0xF6: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xF7: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xF8: { m_BA = m_SP; }
|
||||
break;
|
||||
case 0xF9: { m_BA = m_PC; }
|
||||
break;
|
||||
case 0xFA: { m_X = m_SP; }
|
||||
break;
|
||||
case 0xFB: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xFC: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xFD: { /* illegal instruction? */ }
|
||||
break;
|
||||
case 0xFE: { m_Y = m_SP; }
|
||||
break;
|
||||
case 0xFF: { /* illegal instruction? */ }
|
||||
break;
|
||||
}
|
||||
|
||||
m_icount -= insnminx_cycles_CF[opcode];
|
||||
}
|
||||
|
||||
const minx_cpu_device::op_func minx_cpu_device::insnminx_CF[256] = {
|
||||
&minx_cpu_device::minx_CF_00, &minx_cpu_device::minx_CF_01, &minx_cpu_device::minx_CF_02, &minx_cpu_device::minx_CF_03, &minx_cpu_device::minx_CF_04, &minx_cpu_device::minx_CF_05, &minx_cpu_device::minx_CF_06, &minx_cpu_device::minx_CF_07,
|
||||
&minx_cpu_device::minx_CF_08, &minx_cpu_device::minx_CF_09, &minx_cpu_device::minx_CF_0A, &minx_cpu_device::minx_CF_0B, &minx_cpu_device::minx_CF_0C, &minx_cpu_device::minx_CF_0D, &minx_cpu_device::minx_CF_0E, &minx_cpu_device::minx_CF_0F,
|
||||
&minx_cpu_device::minx_CF_10, &minx_cpu_device::minx_CF_11, &minx_cpu_device::minx_CF_12, &minx_cpu_device::minx_CF_13, &minx_cpu_device::minx_CF_14, &minx_cpu_device::minx_CF_15, &minx_cpu_device::minx_CF_16, &minx_cpu_device::minx_CF_17,
|
||||
&minx_cpu_device::minx_CF_18, &minx_cpu_device::minx_CF_19, &minx_cpu_device::minx_CF_1A, &minx_cpu_device::minx_CF_1B, &minx_cpu_device::minx_CF_1C, &minx_cpu_device::minx_CF_1D, &minx_cpu_device::minx_CF_1E, &minx_cpu_device::minx_CF_1F,
|
||||
&minx_cpu_device::minx_CF_20, &minx_cpu_device::minx_CF_21, &minx_cpu_device::minx_CF_22, &minx_cpu_device::minx_CF_23, &minx_cpu_device::minx_CF_24, &minx_cpu_device::minx_CF_25, &minx_cpu_device::minx_CF_26, &minx_cpu_device::minx_CF_27,
|
||||
&minx_cpu_device::minx_CF_28, &minx_cpu_device::minx_CF_29, &minx_cpu_device::minx_CF_2A, &minx_cpu_device::minx_CF_2B, &minx_cpu_device::minx_CF_2C, &minx_cpu_device::minx_CF_2D, &minx_cpu_device::minx_CF_2E, &minx_cpu_device::minx_CF_2F,
|
||||
&minx_cpu_device::minx_CF_30, &minx_cpu_device::minx_CF_31, &minx_cpu_device::minx_CF_32, &minx_cpu_device::minx_CF_33, &minx_cpu_device::minx_CF_34, &minx_cpu_device::minx_CF_35, &minx_cpu_device::minx_CF_36, &minx_cpu_device::minx_CF_37,
|
||||
&minx_cpu_device::minx_CF_38, &minx_cpu_device::minx_CF_39, &minx_cpu_device::minx_CF_3A, &minx_cpu_device::minx_CF_3B, &minx_cpu_device::minx_CF_3C, &minx_cpu_device::minx_CF_3D, &minx_cpu_device::minx_CF_3E, &minx_cpu_device::minx_CF_3F,
|
||||
&minx_cpu_device::minx_CF_40, &minx_cpu_device::minx_CF_41, &minx_cpu_device::minx_CF_42, &minx_cpu_device::minx_CF_43, &minx_cpu_device::minx_CF_44, &minx_cpu_device::minx_CF_45, &minx_cpu_device::minx_CF_46, &minx_cpu_device::minx_CF_47,
|
||||
&minx_cpu_device::minx_CF_48, &minx_cpu_device::minx_CF_49, &minx_cpu_device::minx_CF_4A, &minx_cpu_device::minx_CF_4B, &minx_cpu_device::minx_CF_4C, &minx_cpu_device::minx_CF_4D, &minx_cpu_device::minx_CF_4E, &minx_cpu_device::minx_CF_4F,
|
||||
&minx_cpu_device::minx_CF_50, &minx_cpu_device::minx_CF_51, &minx_cpu_device::minx_CF_52, &minx_cpu_device::minx_CF_53, &minx_cpu_device::minx_CF_54, &minx_cpu_device::minx_CF_55, &minx_cpu_device::minx_CF_56, &minx_cpu_device::minx_CF_57,
|
||||
&minx_cpu_device::minx_CF_58, &minx_cpu_device::minx_CF_59, &minx_cpu_device::minx_CF_5A, &minx_cpu_device::minx_CF_5B, &minx_cpu_device::minx_CF_5C, &minx_cpu_device::minx_CF_5D, &minx_cpu_device::minx_CF_5E, &minx_cpu_device::minx_CF_5F,
|
||||
&minx_cpu_device::minx_CF_60, &minx_cpu_device::minx_CF_61, &minx_cpu_device::minx_CF_62, &minx_cpu_device::minx_CF_63, &minx_cpu_device::minx_CF_64, &minx_cpu_device::minx_CF_65, &minx_cpu_device::minx_CF_66, &minx_cpu_device::minx_CF_67,
|
||||
&minx_cpu_device::minx_CF_68, &minx_cpu_device::minx_CF_69, &minx_cpu_device::minx_CF_6A, &minx_cpu_device::minx_CF_6B, &minx_cpu_device::minx_CF_6C, &minx_cpu_device::minx_CF_6D, &minx_cpu_device::minx_CF_6E, &minx_cpu_device::minx_CF_6F,
|
||||
&minx_cpu_device::minx_CF_70, &minx_cpu_device::minx_CF_71, &minx_cpu_device::minx_CF_72, &minx_cpu_device::minx_CF_73, &minx_cpu_device::minx_CF_74, &minx_cpu_device::minx_CF_75, &minx_cpu_device::minx_CF_76, &minx_cpu_device::minx_CF_77,
|
||||
&minx_cpu_device::minx_CF_78, &minx_cpu_device::minx_CF_79, &minx_cpu_device::minx_CF_7A, &minx_cpu_device::minx_CF_7B, &minx_cpu_device::minx_CF_7C, &minx_cpu_device::minx_CF_7D, &minx_cpu_device::minx_CF_7E, &minx_cpu_device::minx_CF_7F,
|
||||
&minx_cpu_device::minx_CF_80, &minx_cpu_device::minx_CF_81, &minx_cpu_device::minx_CF_82, &minx_cpu_device::minx_CF_83, &minx_cpu_device::minx_CF_84, &minx_cpu_device::minx_CF_85, &minx_cpu_device::minx_CF_86, &minx_cpu_device::minx_CF_87,
|
||||
&minx_cpu_device::minx_CF_88, &minx_cpu_device::minx_CF_89, &minx_cpu_device::minx_CF_8A, &minx_cpu_device::minx_CF_8B, &minx_cpu_device::minx_CF_8C, &minx_cpu_device::minx_CF_8D, &minx_cpu_device::minx_CF_8E, &minx_cpu_device::minx_CF_8F,
|
||||
&minx_cpu_device::minx_CF_90, &minx_cpu_device::minx_CF_91, &minx_cpu_device::minx_CF_92, &minx_cpu_device::minx_CF_93, &minx_cpu_device::minx_CF_94, &minx_cpu_device::minx_CF_95, &minx_cpu_device::minx_CF_96, &minx_cpu_device::minx_CF_97,
|
||||
&minx_cpu_device::minx_CF_98, &minx_cpu_device::minx_CF_99, &minx_cpu_device::minx_CF_9A, &minx_cpu_device::minx_CF_9B, &minx_cpu_device::minx_CF_9C, &minx_cpu_device::minx_CF_9D, &minx_cpu_device::minx_CF_9E, &minx_cpu_device::minx_CF_9F,
|
||||
&minx_cpu_device::minx_CF_A0, &minx_cpu_device::minx_CF_A1, &minx_cpu_device::minx_CF_A2, &minx_cpu_device::minx_CF_A3, &minx_cpu_device::minx_CF_A4, &minx_cpu_device::minx_CF_A5, &minx_cpu_device::minx_CF_A6, &minx_cpu_device::minx_CF_A7,
|
||||
&minx_cpu_device::minx_CF_A8, &minx_cpu_device::minx_CF_A9, &minx_cpu_device::minx_CF_AA, &minx_cpu_device::minx_CF_AB, &minx_cpu_device::minx_CF_AC, &minx_cpu_device::minx_CF_AD, &minx_cpu_device::minx_CF_AE, &minx_cpu_device::minx_CF_AF,
|
||||
&minx_cpu_device::minx_CF_B0, &minx_cpu_device::minx_CF_B1, &minx_cpu_device::minx_CF_B2, &minx_cpu_device::minx_CF_B3, &minx_cpu_device::minx_CF_B4, &minx_cpu_device::minx_CF_B5, &minx_cpu_device::minx_CF_B6, &minx_cpu_device::minx_CF_B7,
|
||||
&minx_cpu_device::minx_CF_B8, &minx_cpu_device::minx_CF_B9, &minx_cpu_device::minx_CF_BA, &minx_cpu_device::minx_CF_BB, &minx_cpu_device::minx_CF_BC, &minx_cpu_device::minx_CF_BD, &minx_cpu_device::minx_CF_BE, &minx_cpu_device::minx_CF_BF,
|
||||
&minx_cpu_device::minx_CF_C0, &minx_cpu_device::minx_CF_C1, &minx_cpu_device::minx_CF_C2, &minx_cpu_device::minx_CF_C3, &minx_cpu_device::minx_CF_C4, &minx_cpu_device::minx_CF_C5, &minx_cpu_device::minx_CF_C6, &minx_cpu_device::minx_CF_C7,
|
||||
&minx_cpu_device::minx_CF_C8, &minx_cpu_device::minx_CF_C9, &minx_cpu_device::minx_CF_CA, &minx_cpu_device::minx_CF_CB, &minx_cpu_device::minx_CF_CC, &minx_cpu_device::minx_CF_CD, &minx_cpu_device::minx_CF_CE, &minx_cpu_device::minx_CF_CF,
|
||||
&minx_cpu_device::minx_CF_D0, &minx_cpu_device::minx_CF_D1, &minx_cpu_device::minx_CF_D2, &minx_cpu_device::minx_CF_D3, &minx_cpu_device::minx_CF_D4, &minx_cpu_device::minx_CF_D5, &minx_cpu_device::minx_CF_D6, &minx_cpu_device::minx_CF_D7,
|
||||
&minx_cpu_device::minx_CF_D8, &minx_cpu_device::minx_CF_D9, &minx_cpu_device::minx_CF_DA, &minx_cpu_device::minx_CF_DB, &minx_cpu_device::minx_CF_DC, &minx_cpu_device::minx_CF_DD, &minx_cpu_device::minx_CF_DE, &minx_cpu_device::minx_CF_DF,
|
||||
&minx_cpu_device::minx_CF_E0, &minx_cpu_device::minx_CF_E1, &minx_cpu_device::minx_CF_E2, &minx_cpu_device::minx_CF_E3, &minx_cpu_device::minx_CF_E4, &minx_cpu_device::minx_CF_E5, &minx_cpu_device::minx_CF_E6, &minx_cpu_device::minx_CF_E7,
|
||||
&minx_cpu_device::minx_CF_E8, &minx_cpu_device::minx_CF_E9, &minx_cpu_device::minx_CF_EA, &minx_cpu_device::minx_CF_EB, &minx_cpu_device::minx_CF_EC, &minx_cpu_device::minx_CF_ED, &minx_cpu_device::minx_CF_EE, &minx_cpu_device::minx_CF_EF,
|
||||
&minx_cpu_device::minx_CF_F0, &minx_cpu_device::minx_CF_F1, &minx_cpu_device::minx_CF_F2, &minx_cpu_device::minx_CF_F3, &minx_cpu_device::minx_CF_F4, &minx_cpu_device::minx_CF_F5, &minx_cpu_device::minx_CF_F6, &minx_cpu_device::minx_CF_F7,
|
||||
&minx_cpu_device::minx_CF_F8, &minx_cpu_device::minx_CF_F9, &minx_cpu_device::minx_CF_FA, &minx_cpu_device::minx_CF_FB, &minx_cpu_device::minx_CF_FC, &minx_cpu_device::minx_CF_FD, &minx_cpu_device::minx_CF_FE, &minx_cpu_device::minx_CF_FF
|
||||
};
|
||||
|
||||
const int minx_cpu_device::insnminx_cycles_CF[256] = {
|
||||
16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
|
||||
|
||||
@ -1,312 +1,542 @@
|
||||
#undef OP
|
||||
#define OP(nn) void minx_cpu_device::minx_##nn()
|
||||
|
||||
OP(00) { m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
OP(01) { m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
OP(02) { m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
OP(03) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(04) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(05) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(06) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(07) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(08) { m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
OP(09) { m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
OP(0A) { m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
OP(0B) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(0C) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(0D) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(0E) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(0F) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
void minx_cpu_device::execute_one()
|
||||
{
|
||||
const UINT8 opcode = rdop();
|
||||
|
||||
OP(10) { m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
OP(11) { m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
OP(12) { m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
OP(13) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(14) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(15) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(16) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(17) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(18) { m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
OP(19) { m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
OP(1A) { m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
OP(1B) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(1C) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(1D) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(1E) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(1F) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
switch (opcode)
|
||||
{
|
||||
case 0x00: { m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
break;
|
||||
case 0x01: { m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x02: { m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0x03: { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x04: { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x05: { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x06: { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x07: { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | ADD8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x08: { m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
break;
|
||||
case 0x09: { m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x0A: { m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0x0B: { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x0C: { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x0D: { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x0E: { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x0F: { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | ADDC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
|
||||
OP(20) { m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
OP(21) { m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
OP(22) { m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
OP(23) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(24) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(25) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(26) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(27) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(28) { m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
OP(29) { m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
OP(2A) { m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
OP(2B) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(2C) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(2D) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(2E) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(2F) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
case 0x10: { m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
break;
|
||||
case 0x11: { m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x12: { m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0x13: { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x14: { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x15: { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x16: { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x17: { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x18: { m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
break;
|
||||
case 0x19: { m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x1A: { m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0x1B: { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x1C: { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x1D: { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x1E: { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x1F: { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | SUBC8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
|
||||
OP(30) { SUB8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
OP(31) { SUB8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
OP(32) { SUB8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
OP(33) { AD2_IHL; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(34) { AD2_IN8; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(35) { AD2_I16; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(36) { AD2_XIX; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(37) { AD2_YIY; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(38) { m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
OP(39) { m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
OP(3A) { m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
OP(3B) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(3C) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(3D) { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(3E) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
OP(3F) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
case 0x20: { m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
break;
|
||||
case 0x21: { m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x22: { m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0x23: { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x24: { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x25: { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x26: { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x27: { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | AND8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x28: { m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
break;
|
||||
case 0x29: { m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x2A: { m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0x2B: { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x2C: { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x2D: { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x2E: { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x2F: { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | OR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
|
||||
OP(40) { m_BA = ( m_BA & 0xFF00 ) | ( m_BA & 0x00FF); }
|
||||
OP(41) { m_BA = ( m_BA & 0xFF00 ) | ( m_BA >> 8 ); }
|
||||
OP(42) { m_BA = ( m_BA & 0xFF00 ) | ( m_HL & 0x00FF); }
|
||||
OP(43) { m_BA = ( m_BA & 0xFF00 ) | ( m_HL >> 8 ); }
|
||||
OP(44) { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(45) { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(46) { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(47) { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(48) { m_BA = ( m_BA & 0x00FF ) | ( ( m_BA & 0x00FF) << 8 ); }
|
||||
OP(49) { m_BA = ( m_BA & 0x00FF ) | ( ( m_BA >> 8 ) << 8 ); }
|
||||
OP(4A) { m_BA = ( m_BA & 0x00FF ) | ( ( m_HL & 0x00FF) << 8 ); }
|
||||
OP(4B) { m_BA = ( m_BA & 0x00FF ) | ( ( m_HL >> 8 ) << 8 ); }
|
||||
OP(4C) { AD2_IN8; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(4D) { AD2_IHL; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(4E) { AD2_XIX; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(4F) { AD2_YIY; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
case 0x30: { SUB8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
break;
|
||||
case 0x31: { SUB8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x32: { SUB8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0x33: { AD2_IHL; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x34: { AD2_IN8; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x35: { AD2_I16; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x36: { AD2_XIX; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x37: { AD2_YIY; SUB8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x38: { m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), ( m_BA & 0xFF ) ); }
|
||||
break;
|
||||
case 0x39: { m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x3A: { m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), rdop() ); }
|
||||
break;
|
||||
case 0x3B: { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x3C: { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x3D: { AD2_I16; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x3E: { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x3F: { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | XOR8( ( m_BA & 0x00FF ), RD( addr2 ) ); }
|
||||
break;
|
||||
|
||||
OP(50) { m_HL = ( m_HL & 0xFF00 ) | ( m_BA & 0x00FF); }
|
||||
OP(51) { m_HL = ( m_HL & 0xFF00 ) | ( m_BA >> 8 ); }
|
||||
OP(52) { m_HL = ( m_HL & 0xFF00 ) | ( m_HL & 0x00FF); }
|
||||
OP(53) { m_HL = ( m_HL & 0xFF00 ) | ( m_HL >> 8 ); }
|
||||
OP(54) { AD2_IN8; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(55) { AD2_IHL; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(56) { AD2_XIX; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(57) { AD2_YIY; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
OP(58) { m_HL = ( m_HL & 0x00FF ) | ( ( m_BA & 0x00FF) << 8 ); }
|
||||
OP(59) { m_HL = ( m_HL & 0x00FF ) | ( ( m_BA >> 8 ) << 8 ); }
|
||||
OP(5A) { m_HL = ( m_HL & 0x00FF ) | ( ( m_HL & 0x00FF) << 8 ); }
|
||||
OP(5B) { m_HL = ( m_HL & 0x00FF ) | ( ( m_HL >> 8 ) << 8 ); }
|
||||
OP(5C) { AD2_IN8; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(5D) { AD2_IHL; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(5E) { AD2_XIX; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
OP(5F) { AD2_YIY; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
case 0x40: { m_BA = ( m_BA & 0xFF00 ) | ( m_BA & 0x00FF); }
|
||||
break;
|
||||
case 0x41: { m_BA = ( m_BA & 0xFF00 ) | ( m_BA >> 8 ); }
|
||||
break;
|
||||
case 0x42: { m_BA = ( m_BA & 0xFF00 ) | ( m_HL & 0x00FF); }
|
||||
break;
|
||||
case 0x43: { m_BA = ( m_BA & 0xFF00 ) | ( m_HL >> 8 ); }
|
||||
break;
|
||||
case 0x44: { AD2_IN8; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x45: { AD2_IHL; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x46: { AD2_XIX; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x47: { AD2_YIY; m_BA = ( m_BA & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x48: { m_BA = ( m_BA & 0x00FF ) | ( ( m_BA & 0x00FF) << 8 ); }
|
||||
break;
|
||||
case 0x49: { m_BA = ( m_BA & 0x00FF ) | ( ( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x4A: { m_BA = ( m_BA & 0x00FF ) | ( ( m_HL & 0x00FF) << 8 ); }
|
||||
break;
|
||||
case 0x4B: { m_BA = ( m_BA & 0x00FF ) | ( ( m_HL >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x4C: { AD2_IN8; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x4D: { AD2_IHL; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x4E: { AD2_XIX; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x4F: { AD2_YIY; m_BA = ( m_BA & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
|
||||
OP(60) { AD1_XIX; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
OP(61) { AD1_XIX; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
OP(62) { AD1_XIX; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
OP(63) { AD1_XIX; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
OP(64) { AD1_XIX; AD2_IN8; WR( addr1, RD( addr2 ) ); }
|
||||
OP(65) { AD1_XIX; AD2_IHL; WR( addr1, RD( addr2 ) ); }
|
||||
OP(66) { AD1_XIX; AD2_XIX; WR( addr1, RD( addr2 ) ); }
|
||||
OP(67) { AD1_XIX; AD2_YIY; WR( addr1, RD( addr2 ) ); }
|
||||
OP(68) { AD1_IHL; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
OP(69) { AD1_IHL; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
OP(6A) { AD1_IHL; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
OP(6B) { AD1_IHL; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
OP(6C) { AD1_IHL; AD2_IN8; WR( addr1, RD( addr2 ) ); }
|
||||
OP(6D) { AD1_IHL; AD2_IHL; WR( addr1, RD( addr2 ) ); }
|
||||
OP(6E) { AD1_IHL; AD2_XIX; WR( addr1, RD( addr2 ) ); }
|
||||
OP(6F) { AD1_IHL; AD2_YIY; WR( addr1, RD( addr2 ) ); }
|
||||
case 0x50: { m_HL = ( m_HL & 0xFF00 ) | ( m_BA & 0x00FF); }
|
||||
break;
|
||||
case 0x51: { m_HL = ( m_HL & 0xFF00 ) | ( m_BA >> 8 ); }
|
||||
break;
|
||||
case 0x52: { m_HL = ( m_HL & 0xFF00 ) | ( m_HL & 0x00FF); }
|
||||
break;
|
||||
case 0x53: { m_HL = ( m_HL & 0xFF00 ) | ( m_HL >> 8 ); }
|
||||
break;
|
||||
case 0x54: { AD2_IN8; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x55: { AD2_IHL; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x56: { AD2_XIX; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x57: { AD2_YIY; m_HL = ( m_HL & 0xFF00 ) | RD( addr2 ); }
|
||||
break;
|
||||
case 0x58: { m_HL = ( m_HL & 0x00FF ) | ( ( m_BA & 0x00FF) << 8 ); }
|
||||
break;
|
||||
case 0x59: { m_HL = ( m_HL & 0x00FF ) | ( ( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x5A: { m_HL = ( m_HL & 0x00FF ) | ( ( m_HL & 0x00FF) << 8 ); }
|
||||
break;
|
||||
case 0x5B: { m_HL = ( m_HL & 0x00FF ) | ( ( m_HL >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x5C: { AD2_IN8; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x5D: { AD2_IHL; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x5E: { AD2_XIX; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
case 0x5F: { AD2_YIY; m_HL = ( m_HL & 0x00FF ) | ( RD( addr2 ) << 8 ); }
|
||||
break;
|
||||
|
||||
OP(70) { AD1_YIY; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
OP(71) { AD1_YIY; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
OP(72) { AD1_YIY; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
OP(73) { AD1_YIY; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
OP(74) { AD1_YIY; AD2_IN8; WR( addr1, RD( addr2 ) ); }
|
||||
OP(75) { AD1_YIY; AD2_IHL; WR( addr1, RD( addr2 ) ); }
|
||||
OP(76) { AD1_YIY; AD2_XIX; WR( addr1, RD( addr2 ) ); }
|
||||
OP(77) { AD1_YIY; AD2_YIY; WR( addr1, RD( addr2 ) ); }
|
||||
OP(78) { AD1_IN8; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
OP(79) { AD1_IN8; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
OP(7A) { AD1_IN8; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
OP(7B) { AD1_IN8; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
OP(7C) { /* illegal operation? */ }
|
||||
OP(7D) { AD1_IN8; AD2_IHL; WR( addr1, RD( addr2 ) ); }
|
||||
OP(7E) { AD1_IN8; AD2_XIX; WR( addr1, RD( addr2 ) ); }
|
||||
OP(7F) { AD1_IN8; AD2_YIY; WR( addr1, RD( addr2 ) ); }
|
||||
case 0x60: { AD1_XIX; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x61: { AD1_XIX; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x62: { AD1_XIX; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x63: { AD1_XIX; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
break;
|
||||
case 0x64: { AD1_XIX; AD2_IN8; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x65: { AD1_XIX; AD2_IHL; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x66: { AD1_XIX; AD2_XIX; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x67: { AD1_XIX; AD2_YIY; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x68: { AD1_IHL; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x69: { AD1_IHL; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x6A: { AD1_IHL; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x6B: { AD1_IHL; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
break;
|
||||
case 0x6C: { AD1_IHL; AD2_IN8; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x6D: { AD1_IHL; AD2_IHL; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x6E: { AD1_IHL; AD2_XIX; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x6F: { AD1_IHL; AD2_YIY; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
|
||||
OP(80) { m_BA = ( m_BA & 0xFF00 ) | INC8( m_BA & 0x00FF ); }
|
||||
OP(81) { m_BA = ( m_BA & 0x00FF ) | ( INC8( m_BA >> 8 ) << 8 ); }
|
||||
OP(82) { m_HL = ( m_HL & 0xFF00 ) | INC8( m_HL & 0x00FF ); }
|
||||
OP(83) { m_HL = ( m_HL & 0x00FF ) | ( INC8( m_HL >> 8 ) << 8 ); }
|
||||
OP(84) { m_N = INC8( m_N ); }
|
||||
OP(85) { AD1_IN8; WR( addr1, INC8( RD( addr1 ) ) ); }
|
||||
OP(86) { AD1_IHL; WR( addr1, INC8( RD( addr1 ) ) ); }
|
||||
OP(87) { m_SP = INC16( m_SP ); }
|
||||
OP(88) { m_BA = ( m_BA & 0xFF00 ) | DEC8( m_BA & 0x00FF ); }
|
||||
OP(89) { m_BA = ( m_BA & 0x00FF ) | ( DEC8( m_BA >> 8 ) << 8 ); }
|
||||
OP(8A) { m_HL = ( m_HL & 0xFF00 ) | DEC8( m_HL & 0x00FF ); }
|
||||
OP(8B) { m_HL = ( m_HL & 0x00FF ) | ( DEC8( m_HL >> 8 ) << 8 ); }
|
||||
OP(8C) { m_N = DEC8( m_N ); }
|
||||
OP(8D) { AD1_IN8; WR( addr1, DEC8( RD( addr1 ) ) ); }
|
||||
OP(8E) { AD1_IHL; WR( addr1, DEC8( RD( addr1 ) ) ); }
|
||||
OP(8F) { m_SP = DEC8( m_SP ); }
|
||||
case 0x70: { AD1_YIY; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x71: { AD1_YIY; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x72: { AD1_YIY; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x73: { AD1_YIY; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
break;
|
||||
case 0x74: { AD1_YIY; AD2_IN8; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x75: { AD1_YIY; AD2_IHL; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x76: { AD1_YIY; AD2_XIX; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x77: { AD1_YIY; AD2_YIY; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x78: { AD1_IN8; WR( addr1, ( m_BA & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x79: { AD1_IN8; WR( addr1, ( m_BA >> 8 ) ); }
|
||||
break;
|
||||
case 0x7A: { AD1_IN8; WR( addr1, ( m_HL & 0x00FF ) ); }
|
||||
break;
|
||||
case 0x7B: { AD1_IN8; WR( addr1, ( m_HL >> 8 ) ); }
|
||||
break;
|
||||
case 0x7C: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0x7D: { AD1_IN8; AD2_IHL; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x7E: { AD1_IN8; AD2_XIX; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
case 0x7F: { AD1_IN8; AD2_YIY; WR( addr1, RD( addr2 ) ); }
|
||||
break;
|
||||
|
||||
OP(90) { m_BA = INC16( m_BA ); }
|
||||
OP(91) { m_HL = INC16( m_HL ); }
|
||||
OP(92) { m_X = INC16( m_X ); }
|
||||
OP(93) { m_Y = INC16( m_Y ); }
|
||||
OP(94) { m_F = ( AND8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z;}
|
||||
OP(95) { AD1_IHL; m_F = ( AND8( RD( addr1 ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
|
||||
OP(96) { m_F = ( AND8( ( m_BA & 0x00FF ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
|
||||
OP(97) { m_F = ( AND8( ( m_BA >> 8 ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
|
||||
OP(98) { m_BA = DEC16( m_BA ); }
|
||||
OP(99) { m_HL = DEC16( m_HL ); }
|
||||
OP(9A) { m_X = DEC16( m_X ); }
|
||||
OP(9B) { m_Y = DEC16( m_Y ); }
|
||||
OP(9C) { m_F = m_F & rdop(); }
|
||||
OP(9D) { m_F = m_F | rdop(); }
|
||||
OP(9E) { m_F = m_F ^ rdop(); }
|
||||
OP(9F) { m_F = rdop(); }
|
||||
case 0x80: { m_BA = ( m_BA & 0xFF00 ) | INC8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0x81: { m_BA = ( m_BA & 0x00FF ) | ( INC8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x82: { m_HL = ( m_HL & 0xFF00 ) | INC8( m_HL & 0x00FF ); }
|
||||
break;
|
||||
case 0x83: { m_HL = ( m_HL & 0x00FF ) | ( INC8( m_HL >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x84: { m_N = INC8( m_N ); }
|
||||
break;
|
||||
case 0x85: { AD1_IN8; WR( addr1, INC8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x86: { AD1_IHL; WR( addr1, INC8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x87: { m_SP = INC16( m_SP ); }
|
||||
break;
|
||||
case 0x88: { m_BA = ( m_BA & 0xFF00 ) | DEC8( m_BA & 0x00FF ); }
|
||||
break;
|
||||
case 0x89: { m_BA = ( m_BA & 0x00FF ) | ( DEC8( m_BA >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x8A: { m_HL = ( m_HL & 0xFF00 ) | DEC8( m_HL & 0x00FF ); }
|
||||
break;
|
||||
case 0x8B: { m_HL = ( m_HL & 0x00FF ) | ( DEC8( m_HL >> 8 ) << 8 ); }
|
||||
break;
|
||||
case 0x8C: { m_N = DEC8( m_N ); }
|
||||
break;
|
||||
case 0x8D: { AD1_IN8; WR( addr1, DEC8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x8E: { AD1_IHL; WR( addr1, DEC8( RD( addr1 ) ) ); }
|
||||
break;
|
||||
case 0x8F: { m_SP = DEC8( m_SP ); }
|
||||
break;
|
||||
|
||||
OP(A0) { PUSH16( m_BA ); }
|
||||
OP(A1) { PUSH16( m_HL ); }
|
||||
OP(A2) { PUSH16( m_X ); }
|
||||
OP(A3) { PUSH16( m_Y ); }
|
||||
OP(A4) { PUSH8( m_N ); }
|
||||
OP(A5) { PUSH8( m_I ); }
|
||||
OP(A6) { PUSH8( m_XI ); PUSH8( m_YI ); }
|
||||
OP(A7) { PUSH8( m_F ); }
|
||||
OP(A8) { m_BA = POP16(); }
|
||||
OP(A9) { m_HL = POP16();}
|
||||
OP(AA) { m_X = POP16(); }
|
||||
OP(AB) { m_Y = POP16(); }
|
||||
OP(AC) { m_N = POP8(); }
|
||||
OP(AD) { m_I = POP8(); }
|
||||
OP(AE) { m_YI = POP8(); m_XI = POP8(); }
|
||||
OP(AF) { m_F = POP8(); }
|
||||
case 0x90: { m_BA = INC16( m_BA ); }
|
||||
break;
|
||||
case 0x91: { m_HL = INC16( m_HL ); }
|
||||
break;
|
||||
case 0x92: { m_X = INC16( m_X ); }
|
||||
break;
|
||||
case 0x93: { m_Y = INC16( m_Y ); }
|
||||
break;
|
||||
case 0x94: { m_F = ( AND8( ( m_BA & 0x00FF ), ( m_BA >> 8 ) ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z;}
|
||||
break;
|
||||
case 0x95: { AD1_IHL; m_F = ( AND8( RD( addr1 ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
|
||||
break;
|
||||
case 0x96: { m_F = ( AND8( ( m_BA & 0x00FF ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
|
||||
break;
|
||||
case 0x97: { m_F = ( AND8( ( m_BA >> 8 ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
|
||||
break;
|
||||
case 0x98: { m_BA = DEC16( m_BA ); }
|
||||
break;
|
||||
case 0x99: { m_HL = DEC16( m_HL ); }
|
||||
break;
|
||||
case 0x9A: { m_X = DEC16( m_X ); }
|
||||
break;
|
||||
case 0x9B: { m_Y = DEC16( m_Y ); }
|
||||
break;
|
||||
case 0x9C: { m_F = m_F & rdop(); }
|
||||
break;
|
||||
case 0x9D: { m_F = m_F | rdop(); }
|
||||
break;
|
||||
case 0x9E: { m_F = m_F ^ rdop(); }
|
||||
break;
|
||||
case 0x9F: { m_F = rdop(); }
|
||||
break;
|
||||
|
||||
OP(B0) { UINT8 op = rdop(); m_BA = ( m_BA & 0xFF00 ) | op; }
|
||||
OP(B1) { UINT8 op = rdop(); m_BA = ( m_BA & 0x00FF ) | ( op << 8 ); }
|
||||
OP(B2) { UINT8 op = rdop(); m_HL = ( m_HL & 0xFF00 ) | op; }
|
||||
OP(B3) { UINT8 op = rdop(); m_HL = ( m_HL & 0x00FF ) | ( op << 8 ); }
|
||||
OP(B4) { UINT8 op = rdop(); m_N = op; }
|
||||
OP(B5) { AD1_IHL; UINT8 op = rdop(); WR( addr1, op); }
|
||||
OP(B6) { AD1_XIX; UINT8 op = rdop(); WR( addr1, op ); }
|
||||
OP(B7) { AD1_YIY; UINT8 op = rdop(); WR( addr1, op ); }
|
||||
OP(B8) { AD2_I16; m_BA = rd16( addr2 ); }
|
||||
OP(B9) { AD2_I16; m_HL = rd16( addr2 ); }
|
||||
OP(BA) { AD2_I16; m_X = rd16( addr2 ); }
|
||||
OP(BB) { AD2_I16; m_Y = rd16( addr2 ); }
|
||||
OP(BC) { AD1_I16; wr16( addr1, m_BA ); }
|
||||
OP(BD) { AD1_I16; wr16( addr1, m_HL ); }
|
||||
OP(BE) { AD1_I16; wr16( addr1, m_X ); }
|
||||
OP(BF) { AD1_I16; wr16( addr1, m_Y ); }
|
||||
case 0xA0: { PUSH16( m_BA ); }
|
||||
break;
|
||||
case 0xA1: { PUSH16( m_HL ); }
|
||||
break;
|
||||
case 0xA2: { PUSH16( m_X ); }
|
||||
break;
|
||||
case 0xA3: { PUSH16( m_Y ); }
|
||||
break;
|
||||
case 0xA4: { PUSH8( m_N ); }
|
||||
break;
|
||||
case 0xA5: { PUSH8( m_I ); }
|
||||
break;
|
||||
case 0xA6: { PUSH8( m_XI ); PUSH8( m_YI ); }
|
||||
break;
|
||||
case 0xA7: { PUSH8( m_F ); }
|
||||
break;
|
||||
case 0xA8: { m_BA = POP16(); }
|
||||
break;
|
||||
case 0xA9: { m_HL = POP16();}
|
||||
break;
|
||||
case 0xAA: { m_X = POP16(); }
|
||||
break;
|
||||
case 0xAB: { m_Y = POP16(); }
|
||||
break;
|
||||
case 0xAC: { m_N = POP8(); }
|
||||
break;
|
||||
case 0xAD: { m_I = POP8(); }
|
||||
break;
|
||||
case 0xAE: { m_YI = POP8(); m_XI = POP8(); }
|
||||
break;
|
||||
case 0xAF: { m_F = POP8(); }
|
||||
break;
|
||||
|
||||
OP(C0) { m_BA = ADD16( m_BA, rdop16() ); }
|
||||
OP(C1) { m_HL = ADD16( m_HL, rdop16() ); }
|
||||
OP(C2) { m_X = ADD16( m_X, rdop16() ); }
|
||||
OP(C3) { m_Y = ADD16( m_Y, rdop16() ); }
|
||||
OP(C4) { m_BA = rdop16(); }
|
||||
OP(C5) { m_HL = rdop16(); }
|
||||
OP(C6) { m_X = rdop16(); }
|
||||
OP(C7) { m_Y = rdop16(); }
|
||||
OP(C8) { UINT16 t = m_BA; m_BA = m_HL; m_HL = t; }
|
||||
OP(C9) { UINT16 t = m_BA; m_BA = m_X; m_X = t; }
|
||||
OP(CA) { UINT16 t = m_BA; m_BA = m_Y; m_Y = t; }
|
||||
OP(CB) { UINT16 t = m_BA; m_BA = m_SP; m_SP = t; }
|
||||
OP(CC) { m_BA = ( m_BA >> 8 ) | ( ( m_BA & 0x00FF ) << 8 ); }
|
||||
OP(CD) { UINT8 t; AD2_IHL; t = RD( addr2 ); WR( addr2, ( m_BA & 0x00FF ) ); m_BA = ( m_BA & 0xFF00 ) | t; }
|
||||
OP(CE) { UINT8 op = rdop(); (this->*insnminx_CE[op])(); m_icount -= insnminx_cycles_CE[op]; }
|
||||
OP(CF) { UINT8 op = rdop(); (this->*insnminx_CF[op])(); m_icount -= insnminx_cycles_CF[op]; }
|
||||
case 0xB0: { UINT8 op = rdop(); m_BA = ( m_BA & 0xFF00 ) | op; }
|
||||
break;
|
||||
case 0xB1: { UINT8 op = rdop(); m_BA = ( m_BA & 0x00FF ) | ( op << 8 ); }
|
||||
break;
|
||||
case 0xB2: { UINT8 op = rdop(); m_HL = ( m_HL & 0xFF00 ) | op; }
|
||||
break;
|
||||
case 0xB3: { UINT8 op = rdop(); m_HL = ( m_HL & 0x00FF ) | ( op << 8 ); }
|
||||
break;
|
||||
case 0xB4: { UINT8 op = rdop(); m_N = op; }
|
||||
break;
|
||||
case 0xB5: { AD1_IHL; UINT8 op = rdop(); WR( addr1, op); }
|
||||
break;
|
||||
case 0xB6: { AD1_XIX; UINT8 op = rdop(); WR( addr1, op ); }
|
||||
break;
|
||||
case 0xB7: { AD1_YIY; UINT8 op = rdop(); WR( addr1, op ); }
|
||||
break;
|
||||
case 0xB8: { AD2_I16; m_BA = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xB9: { AD2_I16; m_HL = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xBA: { AD2_I16; m_X = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xBB: { AD2_I16; m_Y = rd16( addr2 ); }
|
||||
break;
|
||||
case 0xBC: { AD1_I16; wr16( addr1, m_BA ); }
|
||||
break;
|
||||
case 0xBD: { AD1_I16; wr16( addr1, m_HL ); }
|
||||
break;
|
||||
case 0xBE: { AD1_I16; wr16( addr1, m_X ); }
|
||||
break;
|
||||
case 0xBF: { AD1_I16; wr16( addr1, m_Y ); }
|
||||
break;
|
||||
|
||||
OP(D0) { m_BA = SUB16( m_BA, rdop16() ); }
|
||||
OP(D1) { m_HL = SUB16( m_HL, rdop16() ); }
|
||||
OP(D2) { m_X = SUB16( m_X, rdop16() ); }
|
||||
OP(D3) { m_Y = SUB16( m_Y, rdop16() ); }
|
||||
OP(D4) { SUB16( m_BA, rdop16() ); }
|
||||
OP(D5) { SUB16( m_HL, rdop16() ); }
|
||||
OP(D6) { SUB16( m_X, rdop16() ); }
|
||||
OP(D7) { SUB16( m_Y, rdop16() ); }
|
||||
OP(D8) { AD1_IN8; WR( addr1, AND8( RD( addr1 ), rdop() ) ); }
|
||||
OP(D9) { AD1_IN8; WR( addr1, OR8( RD( addr1 ), rdop() ) ); }
|
||||
OP(DA) { AD1_IN8; WR( addr1, XOR8( RD( addr1 ), rdop() ) ); }
|
||||
OP(DB) { AD1_IN8; SUB8( RD( addr1 ), rdop() ); }
|
||||
OP(DC) { AD1_IN8; m_F = ( AND8( RD( addr1 ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
|
||||
OP(DD) { AD1_IN8; WR( addr1, rdop() ); }
|
||||
OP(DE) { m_BA = ( m_BA & 0xFF00 ) | ( ( m_BA & 0x000F ) | ( ( m_BA & 0x0F00 ) >> 4 ) ); }
|
||||
OP(DF) { m_BA = ( ( m_BA & 0x0080 ) ? 0xFF00 : 0x0000 ) | ( m_BA & 0x000F ); }
|
||||
case 0xC0: { m_BA = ADD16( m_BA, rdop16() ); }
|
||||
break;
|
||||
case 0xC1: { m_HL = ADD16( m_HL, rdop16() ); }
|
||||
break;
|
||||
case 0xC2: { m_X = ADD16( m_X, rdop16() ); }
|
||||
break;
|
||||
case 0xC3: { m_Y = ADD16( m_Y, rdop16() ); }
|
||||
break;
|
||||
case 0xC4: { m_BA = rdop16(); }
|
||||
break;
|
||||
case 0xC5: { m_HL = rdop16(); }
|
||||
break;
|
||||
case 0xC6: { m_X = rdop16(); }
|
||||
break;
|
||||
case 0xC7: { m_Y = rdop16(); }
|
||||
break;
|
||||
case 0xC8: { UINT16 t = m_BA; m_BA = m_HL; m_HL = t; }
|
||||
break;
|
||||
case 0xC9: { UINT16 t = m_BA; m_BA = m_X; m_X = t; }
|
||||
break;
|
||||
case 0xCA: { UINT16 t = m_BA; m_BA = m_Y; m_Y = t; }
|
||||
break;
|
||||
case 0xCB: { UINT16 t = m_BA; m_BA = m_SP; m_SP = t; }
|
||||
break;
|
||||
case 0xCC: { m_BA = ( m_BA >> 8 ) | ( ( m_BA & 0x00FF ) << 8 ); }
|
||||
break;
|
||||
case 0xCD: { UINT8 t; AD2_IHL; t = RD( addr2 ); WR( addr2, ( m_BA & 0x00FF ) ); m_BA = ( m_BA & 0xFF00 ) | t; }
|
||||
break;
|
||||
case 0xCE: { execute_one_ce(); }
|
||||
break;
|
||||
case 0xCF: { execute_one_cf(); }
|
||||
break;
|
||||
|
||||
OP(E0) { INT8 d8 = rdop(); if ( m_F & FLAG_C ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(E1) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_C ) ) { CALL( m_PC + d8- 1 ); m_icount -= 12; } }
|
||||
OP(E2) { INT8 d8 = rdop(); if ( m_F & FLAG_Z ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(E3) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_Z ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
OP(E4) { INT8 d8 = rdop(); if ( m_F & FLAG_C ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E5) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_C ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E6) { INT8 d8 = rdop(); if ( m_F & FLAG_Z ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E7) { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_Z ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(E8) { UINT16 d16 = rdop16(); if ( m_F & FLAG_C ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
|
||||
OP(E9) { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_C ) ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
|
||||
OP(EA) { UINT16 d16 = rdop16(); if ( m_F & FLAG_Z ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
|
||||
OP(EB) { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_Z ) ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
|
||||
OP(EC) { UINT16 d16 = rdop16(); if ( m_F & FLAG_C ) { JMP( m_PC + d16 - 1 ); } }
|
||||
OP(ED) { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_C ) ) { JMP( m_PC + d16 - 1 ); } }
|
||||
OP(EE) { UINT16 d16 = rdop16(); if ( m_F & FLAG_Z ) { JMP( m_PC + d16 - 1 ); } }
|
||||
OP(EF) { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_Z ) ) { JMP( m_PC + d16 - 1 ); } }
|
||||
case 0xD0: { m_BA = SUB16( m_BA, rdop16() ); }
|
||||
break;
|
||||
case 0xD1: { m_HL = SUB16( m_HL, rdop16() ); }
|
||||
break;
|
||||
case 0xD2: { m_X = SUB16( m_X, rdop16() ); }
|
||||
break;
|
||||
case 0xD3: { m_Y = SUB16( m_Y, rdop16() ); }
|
||||
break;
|
||||
case 0xD4: { SUB16( m_BA, rdop16() ); }
|
||||
break;
|
||||
case 0xD5: { SUB16( m_HL, rdop16() ); }
|
||||
break;
|
||||
case 0xD6: { SUB16( m_X, rdop16() ); }
|
||||
break;
|
||||
case 0xD7: { SUB16( m_Y, rdop16() ); }
|
||||
break;
|
||||
case 0xD8: { AD1_IN8; WR( addr1, AND8( RD( addr1 ), rdop() ) ); }
|
||||
break;
|
||||
case 0xD9: { AD1_IN8; WR( addr1, OR8( RD( addr1 ), rdop() ) ); }
|
||||
break;
|
||||
case 0xDA: { AD1_IN8; WR( addr1, XOR8( RD( addr1 ), rdop() ) ); }
|
||||
break;
|
||||
case 0xDB: { AD1_IN8; SUB8( RD( addr1 ), rdop() ); }
|
||||
break;
|
||||
case 0xDC: { AD1_IN8; m_F = ( AND8( RD( addr1 ), rdop() ) ) ? m_F & ~FLAG_Z : m_F | FLAG_Z; }
|
||||
break;
|
||||
case 0xDD: { AD1_IN8; WR( addr1, rdop() ); }
|
||||
break;
|
||||
case 0xDE: { m_BA = ( m_BA & 0xFF00 ) | ( ( m_BA & 0x000F ) | ( ( m_BA & 0x0F00 ) >> 4 ) ); }
|
||||
break;
|
||||
case 0xDF: { m_BA = ( ( m_BA & 0x0080 ) ? 0xFF00 : 0x0000 ) | ( m_BA & 0x000F ); }
|
||||
break;
|
||||
|
||||
OP(F0) { INT8 d8 = rdop(); CALL( m_PC + d8 - 1 ); }
|
||||
OP(F1) { INT8 d8 = rdop(); JMP( m_PC + d8 - 1 ); }
|
||||
OP(F2) { UINT16 d16 = rdop16(); CALL( m_PC + d16 - 1 ); }
|
||||
OP(F3) { UINT16 d16 = rdop16(); JMP( m_PC + d16 - 1 ); }
|
||||
OP(F4) { JMP( m_HL ); }
|
||||
OP(F5) { INT8 d8 = rdop(); m_BA = m_BA - 0x0100; if ( m_BA & 0xFF00 ) { JMP( m_PC + d8 - 1 ); } }
|
||||
OP(F6) { m_BA = ( m_BA & 0xFF00 ) | ( ( m_BA & 0x00F0 ) >> 4 ) | ( ( m_BA & 0x000F ) << 4 ); }
|
||||
OP(F7) { UINT8 d; AD1_IHL; d = RD( addr1 ); WR( addr1, ( ( d & 0xF0 ) >> 4 ) | ( ( d & 0x0F ) << 4 ) ); }
|
||||
OP(F8) { m_PC = POP16(); m_V = POP8(); m_U = m_V; }
|
||||
OP(F9) { m_F = POP8(); m_PC = POP16(); m_V = POP8(); m_U = m_V; }
|
||||
OP(FA) { m_PC = POP16() + 2; m_V = POP8(); m_U = m_V; }
|
||||
OP(FB) { AD1_I16; CALL( rd16( addr1 ) ); }
|
||||
OP(FC) { UINT8 i = rdop() & 0xFE; CALL( rd16( i ) ); PUSH8( m_F ); }
|
||||
OP(FD) { UINT8 i = rdop() & 0xFE; JMP( rd16( i ) ); /* PUSH8( m_F );?? */ }
|
||||
OP(FE) { /* illegal operation? */ }
|
||||
OP(FF) { }
|
||||
case 0xE0: { INT8 d8 = rdop(); if ( m_F & FLAG_C ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xE1: { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_C ) ) { CALL( m_PC + d8- 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xE2: { INT8 d8 = rdop(); if ( m_F & FLAG_Z ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xE3: { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_Z ) ) { CALL( m_PC + d8 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xE4: { INT8 d8 = rdop(); if ( m_F & FLAG_C ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE5: { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_C ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE6: { INT8 d8 = rdop(); if ( m_F & FLAG_Z ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE7: { INT8 d8 = rdop(); if ( ! ( m_F & FLAG_Z ) ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xE8: { UINT16 d16 = rdop16(); if ( m_F & FLAG_C ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xE9: { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_C ) ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xEA: { UINT16 d16 = rdop16(); if ( m_F & FLAG_Z ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xEB: { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_Z ) ) { CALL( m_PC + d16 - 1 ); m_icount -= 12; } }
|
||||
break;
|
||||
case 0xEC: { UINT16 d16 = rdop16(); if ( m_F & FLAG_C ) { JMP( m_PC + d16 - 1 ); } }
|
||||
break;
|
||||
case 0xED: { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_C ) ) { JMP( m_PC + d16 - 1 ); } }
|
||||
break;
|
||||
case 0xEE: { UINT16 d16 = rdop16(); if ( m_F & FLAG_Z ) { JMP( m_PC + d16 - 1 ); } }
|
||||
break;
|
||||
case 0xEF: { UINT16 d16 = rdop16(); if ( ! ( m_F & FLAG_Z ) ) { JMP( m_PC + d16 - 1 ); } }
|
||||
break;
|
||||
|
||||
case 0xF0: { INT8 d8 = rdop(); CALL( m_PC + d8 - 1 ); }
|
||||
break;
|
||||
case 0xF1: { INT8 d8 = rdop(); JMP( m_PC + d8 - 1 ); }
|
||||
break;
|
||||
case 0xF2: { UINT16 d16 = rdop16(); CALL( m_PC + d16 - 1 ); }
|
||||
break;
|
||||
case 0xF3: { UINT16 d16 = rdop16(); JMP( m_PC + d16 - 1 ); }
|
||||
break;
|
||||
case 0xF4: { JMP( m_HL ); }
|
||||
break;
|
||||
case 0xF5: { INT8 d8 = rdop(); m_BA = m_BA - 0x0100; if ( m_BA & 0xFF00 ) { JMP( m_PC + d8 - 1 ); } }
|
||||
break;
|
||||
case 0xF6: { m_BA = ( m_BA & 0xFF00 ) | ( ( m_BA & 0x00F0 ) >> 4 ) | ( ( m_BA & 0x000F ) << 4 ); }
|
||||
break;
|
||||
case 0xF7: { UINT8 d; AD1_IHL; d = RD( addr1 ); WR( addr1, ( ( d & 0xF0 ) >> 4 ) | ( ( d & 0x0F ) << 4 ) ); }
|
||||
break;
|
||||
case 0xF8: { m_PC = POP16(); m_V = POP8(); m_U = m_V; }
|
||||
break;
|
||||
case 0xF9: { m_F = POP8(); m_PC = POP16(); m_V = POP8(); m_U = m_V; }
|
||||
break;
|
||||
case 0xFA: { m_PC = POP16() + 2; m_V = POP8(); m_U = m_V; }
|
||||
break;
|
||||
case 0xFB: { AD1_I16; CALL( rd16( addr1 ) ); }
|
||||
break;
|
||||
case 0xFC: { UINT8 i = rdop() & 0xFE; CALL( rd16( i ) ); PUSH8( m_F ); }
|
||||
break;
|
||||
case 0xFD: { UINT8 i = rdop() & 0xFE; JMP( rd16( i ) ); /* PUSH8( m_F );?? */ }
|
||||
break;
|
||||
case 0xFE: { /* illegal operation? */ }
|
||||
break;
|
||||
case 0xFF: { }
|
||||
break;
|
||||
}
|
||||
|
||||
m_icount -= insnminx_cycles[opcode];
|
||||
}
|
||||
|
||||
const minx_cpu_device::op_func minx_cpu_device::insnminx[256] = {
|
||||
&minx_cpu_device::minx_00, &minx_cpu_device::minx_01, &minx_cpu_device::minx_02, &minx_cpu_device::minx_03, &minx_cpu_device::minx_04, &minx_cpu_device::minx_05, &minx_cpu_device::minx_06, &minx_cpu_device::minx_07,
|
||||
&minx_cpu_device::minx_08, &minx_cpu_device::minx_09, &minx_cpu_device::minx_0A, &minx_cpu_device::minx_0B, &minx_cpu_device::minx_0C, &minx_cpu_device::minx_0D, &minx_cpu_device::minx_0E, &minx_cpu_device::minx_0F,
|
||||
&minx_cpu_device::minx_10, &minx_cpu_device::minx_11, &minx_cpu_device::minx_12, &minx_cpu_device::minx_13, &minx_cpu_device::minx_14, &minx_cpu_device::minx_15, &minx_cpu_device::minx_16, &minx_cpu_device::minx_17,
|
||||
&minx_cpu_device::minx_18, &minx_cpu_device::minx_19, &minx_cpu_device::minx_1A, &minx_cpu_device::minx_1B, &minx_cpu_device::minx_1C, &minx_cpu_device::minx_1D, &minx_cpu_device::minx_1E, &minx_cpu_device::minx_1F,
|
||||
&minx_cpu_device::minx_20, &minx_cpu_device::minx_21, &minx_cpu_device::minx_22, &minx_cpu_device::minx_23, &minx_cpu_device::minx_24, &minx_cpu_device::minx_25, &minx_cpu_device::minx_26, &minx_cpu_device::minx_27,
|
||||
&minx_cpu_device::minx_28, &minx_cpu_device::minx_29, &minx_cpu_device::minx_2A, &minx_cpu_device::minx_2B, &minx_cpu_device::minx_2C, &minx_cpu_device::minx_2D, &minx_cpu_device::minx_2E, &minx_cpu_device::minx_2F,
|
||||
&minx_cpu_device::minx_30, &minx_cpu_device::minx_31, &minx_cpu_device::minx_32, &minx_cpu_device::minx_33, &minx_cpu_device::minx_34, &minx_cpu_device::minx_35, &minx_cpu_device::minx_36, &minx_cpu_device::minx_37,
|
||||
&minx_cpu_device::minx_38, &minx_cpu_device::minx_39, &minx_cpu_device::minx_3A, &minx_cpu_device::minx_3B, &minx_cpu_device::minx_3C, &minx_cpu_device::minx_3D, &minx_cpu_device::minx_3E, &minx_cpu_device::minx_3F,
|
||||
&minx_cpu_device::minx_40, &minx_cpu_device::minx_41, &minx_cpu_device::minx_42, &minx_cpu_device::minx_43, &minx_cpu_device::minx_44, &minx_cpu_device::minx_45, &minx_cpu_device::minx_46, &minx_cpu_device::minx_47,
|
||||
&minx_cpu_device::minx_48, &minx_cpu_device::minx_49, &minx_cpu_device::minx_4A, &minx_cpu_device::minx_4B, &minx_cpu_device::minx_4C, &minx_cpu_device::minx_4D, &minx_cpu_device::minx_4E, &minx_cpu_device::minx_4F,
|
||||
&minx_cpu_device::minx_50, &minx_cpu_device::minx_51, &minx_cpu_device::minx_52, &minx_cpu_device::minx_53, &minx_cpu_device::minx_54, &minx_cpu_device::minx_55, &minx_cpu_device::minx_56, &minx_cpu_device::minx_57,
|
||||
&minx_cpu_device::minx_58, &minx_cpu_device::minx_59, &minx_cpu_device::minx_5A, &minx_cpu_device::minx_5B, &minx_cpu_device::minx_5C, &minx_cpu_device::minx_5D, &minx_cpu_device::minx_5E, &minx_cpu_device::minx_5F,
|
||||
&minx_cpu_device::minx_60, &minx_cpu_device::minx_61, &minx_cpu_device::minx_62, &minx_cpu_device::minx_63, &minx_cpu_device::minx_64, &minx_cpu_device::minx_65, &minx_cpu_device::minx_66, &minx_cpu_device::minx_67,
|
||||
&minx_cpu_device::minx_68, &minx_cpu_device::minx_69, &minx_cpu_device::minx_6A, &minx_cpu_device::minx_6B, &minx_cpu_device::minx_6C, &minx_cpu_device::minx_6D, &minx_cpu_device::minx_6E, &minx_cpu_device::minx_6F,
|
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&minx_cpu_device::minx_70, &minx_cpu_device::minx_71, &minx_cpu_device::minx_72, &minx_cpu_device::minx_73, &minx_cpu_device::minx_74, &minx_cpu_device::minx_75, &minx_cpu_device::minx_76, &minx_cpu_device::minx_77,
|
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&minx_cpu_device::minx_78, &minx_cpu_device::minx_79, &minx_cpu_device::minx_7A, &minx_cpu_device::minx_7B, &minx_cpu_device::minx_7C, &minx_cpu_device::minx_7D, &minx_cpu_device::minx_7E, &minx_cpu_device::minx_7F,
|
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&minx_cpu_device::minx_80, &minx_cpu_device::minx_81, &minx_cpu_device::minx_82, &minx_cpu_device::minx_83, &minx_cpu_device::minx_84, &minx_cpu_device::minx_85, &minx_cpu_device::minx_86, &minx_cpu_device::minx_87,
|
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&minx_cpu_device::minx_88, &minx_cpu_device::minx_89, &minx_cpu_device::minx_8A, &minx_cpu_device::minx_8B, &minx_cpu_device::minx_8C, &minx_cpu_device::minx_8D, &minx_cpu_device::minx_8E, &minx_cpu_device::minx_8F,
|
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&minx_cpu_device::minx_90, &minx_cpu_device::minx_91, &minx_cpu_device::minx_92, &minx_cpu_device::minx_93, &minx_cpu_device::minx_94, &minx_cpu_device::minx_95, &minx_cpu_device::minx_96, &minx_cpu_device::minx_97,
|
||||
&minx_cpu_device::minx_98, &minx_cpu_device::minx_99, &minx_cpu_device::minx_9A, &minx_cpu_device::minx_9B, &minx_cpu_device::minx_9C, &minx_cpu_device::minx_9D, &minx_cpu_device::minx_9E, &minx_cpu_device::minx_9F,
|
||||
&minx_cpu_device::minx_A0, &minx_cpu_device::minx_A1, &minx_cpu_device::minx_A2, &minx_cpu_device::minx_A3, &minx_cpu_device::minx_A4, &minx_cpu_device::minx_A5, &minx_cpu_device::minx_A6, &minx_cpu_device::minx_A7,
|
||||
&minx_cpu_device::minx_A8, &minx_cpu_device::minx_A9, &minx_cpu_device::minx_AA, &minx_cpu_device::minx_AB, &minx_cpu_device::minx_AC, &minx_cpu_device::minx_AD, &minx_cpu_device::minx_AE, &minx_cpu_device::minx_AF,
|
||||
&minx_cpu_device::minx_B0, &minx_cpu_device::minx_B1, &minx_cpu_device::minx_B2, &minx_cpu_device::minx_B3, &minx_cpu_device::minx_B4, &minx_cpu_device::minx_B5, &minx_cpu_device::minx_B6, &minx_cpu_device::minx_B7,
|
||||
&minx_cpu_device::minx_B8, &minx_cpu_device::minx_B9, &minx_cpu_device::minx_BA, &minx_cpu_device::minx_BB, &minx_cpu_device::minx_BC, &minx_cpu_device::minx_BD, &minx_cpu_device::minx_BE, &minx_cpu_device::minx_BF,
|
||||
&minx_cpu_device::minx_C0, &minx_cpu_device::minx_C1, &minx_cpu_device::minx_C2, &minx_cpu_device::minx_C3, &minx_cpu_device::minx_C4, &minx_cpu_device::minx_C5, &minx_cpu_device::minx_C6, &minx_cpu_device::minx_C7,
|
||||
&minx_cpu_device::minx_C8, &minx_cpu_device::minx_C9, &minx_cpu_device::minx_CA, &minx_cpu_device::minx_CB, &minx_cpu_device::minx_CC, &minx_cpu_device::minx_CD, &minx_cpu_device::minx_CE, &minx_cpu_device::minx_CF,
|
||||
&minx_cpu_device::minx_D0, &minx_cpu_device::minx_D1, &minx_cpu_device::minx_D2, &minx_cpu_device::minx_D3, &minx_cpu_device::minx_D4, &minx_cpu_device::minx_D5, &minx_cpu_device::minx_D6, &minx_cpu_device::minx_D7,
|
||||
&minx_cpu_device::minx_D8, &minx_cpu_device::minx_D9, &minx_cpu_device::minx_DA, &minx_cpu_device::minx_DB, &minx_cpu_device::minx_DC, &minx_cpu_device::minx_DD, &minx_cpu_device::minx_DE, &minx_cpu_device::minx_DF,
|
||||
&minx_cpu_device::minx_E0, &minx_cpu_device::minx_E1, &minx_cpu_device::minx_E2, &minx_cpu_device::minx_E3, &minx_cpu_device::minx_E4, &minx_cpu_device::minx_E5, &minx_cpu_device::minx_E6, &minx_cpu_device::minx_E7,
|
||||
&minx_cpu_device::minx_E8, &minx_cpu_device::minx_E9, &minx_cpu_device::minx_EA, &minx_cpu_device::minx_EB, &minx_cpu_device::minx_EC, &minx_cpu_device::minx_ED, &minx_cpu_device::minx_EE, &minx_cpu_device::minx_EF,
|
||||
&minx_cpu_device::minx_F0, &minx_cpu_device::minx_F1, &minx_cpu_device::minx_F2, &minx_cpu_device::minx_F3, &minx_cpu_device::minx_F4, &minx_cpu_device::minx_F5, &minx_cpu_device::minx_F6, &minx_cpu_device::minx_F7,
|
||||
&minx_cpu_device::minx_F8, &minx_cpu_device::minx_F9, &minx_cpu_device::minx_FA, &minx_cpu_device::minx_FB, &minx_cpu_device::minx_FC, &minx_cpu_device::minx_FD, &minx_cpu_device::minx_FE, &minx_cpu_device::minx_FF
|
||||
};
|
||||
|
||||
const int minx_cpu_device::insnminx_cycles[256] = {
|
||||
8, 8, 8, 8, 12, 16, 8, 8, 8, 8, 8, 8, 12, 16, 8, 8,
|
||||
@ -329,3 +559,4 @@ const int minx_cpu_device::insnminx_cycles[256] = {
|
||||
8, 8, 8, 8, 8, 8, 8, 8, 12, 12, 12, 12, 12, 12, 12, 12,
|
||||
20, 8, 24, 12, 8, 1, 8, 12, 8, 8, 8, 20, 20, 1, 1, 8
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user