mirror of
https://github.com/holub/mame
synced 2025-05-29 17:13:05 +03:00
Synced asc sound device from MESS (no whatsnew)
R.B. sorry for this, was afraid it could be forgotten to be synced.
This commit is contained in:
Miodrag Milanovic
parent
689a7d16d2
commit
8941018939
@ -7,20 +7,38 @@
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Emulation by R. Belmont
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Registers:
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0x800: VERSION
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0x801: MODE (1=FIFO mode, 2=wavetable mode)
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0x802: CONTROL (bit 0=analog or PWM output, 1=stereo/mono, 7=processing time exceeded)
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0x803: FIFO MODE (bit 7=clear FIFO, bit 1="non-ROM companding", bit 0="ROM companding")
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0x804: FIFO IRQ STATUS (bit 0=ch A 1/2 full, 1=ch A full, 2=ch B 1/2 full, 3=ch B full)
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0x805: WAVETABLE CONTROL (bits 0-3 wavetables 0-3 start)
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0x806: VOLUME (bits 2-4 = 3 bit internal ASC volume, bits 5-7 = volume control sent to Sony sound chip)
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0x807: CLOCK RATE (0 = Mac 22257 Hz, 1 = undefined, 2 = 22050 Hz, 3 = 44100 Hz)
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0x80a: PLAY REC A
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0x80f: TEST (bits 6-7 = digital test, bits 4-5 = analog test)
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0x810: WAVETABLE 0 PHASE (big-endian 8.16 fixed-point, only 24 bits valid)
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0x814: WAVETABLE 0 INCREMENT (big-endian 8.16 fixed-point, only 24 bits valid)
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0x818: WAVETABLE 1 PHASE
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0x81C: WAVETABLE 1 INCREMENT
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0x820: WAVETABLE 2 PHASE
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0x824: WAVETABLE 2 INCREMENT
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0x828: WAVETABLE 3 PHASE
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0x82C: WAVETABLE 3 INCREMENT
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***************************************************************************/
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#include "emu.h"
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#include "streams.h"
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#include "asc.h"
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//**************************************************************************
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// GLOBAL VARIABLES
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//**************************************************************************
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const device_type ASC = asc_device_config::static_alloc_device_config;
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//**************************************************************************
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// DEVICE CONFIGURATION
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//**************************************************************************
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@ -36,6 +54,18 @@ void asc_device_config::static_set_type(device_config *device, int type)
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asc->m_type = type;
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}
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//-------------------------------------------------
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// static_set_type - configuration helper to set
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// the IRQ callback
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//-------------------------------------------------
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void asc_device_config::static_set_irqf(device_config *device, void (*irqf)(running_device *device, int state))
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{
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asc_device_config *asc = downcast<asc_device_config *>(device);
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asc->m_irq_func = irqf;
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}
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//-------------------------------------------------
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// asc_device_config - constructor
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//-------------------------------------------------
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@ -79,7 +109,8 @@ asc_device::asc_device(running_machine &_machine, const asc_device_config &confi
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: device_t(_machine, config),
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device_sound_interface(_machine, config, *this),
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m_config(config),
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m_chip_type(m_config.m_type)
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m_chip_type(m_config.m_type),
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m_irq_cb(m_config.m_irq_func)
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{
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}
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@ -92,6 +123,8 @@ void asc_device::device_start()
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{
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// create the stream
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m_stream = stream_create(this, 0, 2, 22257, this, static_stream_generate);
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memset(m_regs, 0, sizeof(m_regs));
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}
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@ -102,6 +135,17 @@ void asc_device::device_start()
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void asc_device::device_reset()
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{
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stream_update(m_stream);
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memset(m_regs, 0, sizeof(m_regs));
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memset(m_fifo_a, 0, sizeof(m_fifo_a));
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memset(m_fifo_b, 0, sizeof(m_fifo_b));
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memset(m_phase, 0, sizeof(m_phase));
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memset(m_incr, 0, sizeof(m_incr));
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memset(m_fifo_a_wrhalf, 0, sizeof(m_fifo_a_wrhalf));
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memset(m_fifo_b_wrhalf, 0, sizeof(m_fifo_b_wrhalf));
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m_fifo_a_rdptr = m_fifo_b_rdptr = 0;
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m_fifo_a_wrptr = m_fifo_b_wrptr = 0;
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}
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//-------------------------------------------------
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@ -116,8 +160,113 @@ STREAM_UPDATE( asc_device::static_stream_generate )
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void asc_device::stream_generate(stream_sample_t **inputs, stream_sample_t **outputs, int samples)
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{
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// reset the output stream
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memset(outputs[0], 0, samples * sizeof(*outputs[0]));
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stream_sample_t *outL, *outR;
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int i, ch, halt = 0;
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static UINT32 wtoffs[2] = { 0, 0x200 };
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outL = outputs[0];
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outR = outputs[1];
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switch (m_regs[R_MODE-0x800] & 3)
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{
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case 0: // chip off
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for (i = 0; i < samples; i++)
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{
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outL[i] = outR[i] = 0;
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}
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break;
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case 1: // FIFO mode
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if ((m_fifo_a_rdptr == 0) && (!m_fifo_a_wrhalf[0]))
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{
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halt = 1;
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}
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else if ((m_fifo_a_rdptr == 0x200) && (!m_fifo_a_wrhalf[1]))
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{
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halt = 1;
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}
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for (i = 0; i < samples; i++)
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{
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INT8 smpll, smplr;
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if (m_fifo_a_rdptr < 0x200)
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{
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m_fifo_a_wrhalf[0] = 0;
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m_fifo_b_wrhalf[0] = 0;
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}
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else
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{
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m_fifo_a_wrhalf[1] = 0;
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m_fifo_b_wrhalf[1] = 0;
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}
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smpll = (INT8)m_fifo_a[m_fifo_a_rdptr++]^0x80;
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smplr = (INT8)m_fifo_b[m_fifo_b_rdptr++]^0x80;
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if ((m_fifo_a_rdptr == 0x200) || (m_fifo_a_rdptr == 0x400))
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{
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m_regs[R_FIFOSTAT-0x800] |= 1; // fifo A half-empty
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if (m_irq_cb)
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{
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m_irq_cb(this, 1);
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}
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}
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if ((m_fifo_b_rdptr == 0x200) || (m_fifo_b_rdptr == 0x400))
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{
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m_regs[R_FIFOSTAT-0x800] |= 4; // fifo B half-empty
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if (m_irq_cb)
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{
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m_irq_cb(this, 1);
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}
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}
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m_fifo_a_rdptr &= 0x3ff;
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m_fifo_b_rdptr &= 0x3ff;
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outL[i] = smpll * 64;
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outR[i] = smplr * 64;
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}
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if (halt)
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{
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// m_regs[R_MODE-0x800] = 0;
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}
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break;
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case 2: // wavetable mode
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for (i = 0; i < samples; i++)
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{
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INT32 mixL, mixR;
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INT8 smpl;
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mixL = mixR = 0;
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// update channel pointers
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for (ch = 0; ch < 4; ch++)
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{
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m_phase[ch] += m_incr[ch];
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if (ch < 2)
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{
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smpl = (INT8)m_fifo_a[((m_phase[ch]>>16)&0x1ff) + wtoffs[ch&1]];
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}
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else
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{
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smpl = (INT8)m_fifo_b[((m_phase[ch]>>16)&0x1ff) + wtoffs[ch&1]];
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}
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smpl ^= 0x80;
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mixL += smpl*256;
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mixR += smpl*256;
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}
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outL[i] = mixL>>2;
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outR[i] = mixR>>2;
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}
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break;
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}
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}
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//-------------------------------------------------
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@ -126,40 +275,92 @@ void asc_device::stream_generate(stream_sample_t **inputs, stream_sample_t **out
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UINT8 asc_device::read(UINT16 offset)
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{
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UINT8 rv;
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// printf("ASC: read at %x\n", offset);
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// not sure what actually happens when the CPU reads the FIFO...
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if (offset < 0x400)
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{
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return fifo_a[offset];
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return m_fifo_a[offset];
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}
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else if (offset < 0x800)
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{
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return fifo_b[offset-0x400];
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return m_fifo_b[offset-0x400];
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}
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else
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{
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stream_update(m_stream);
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switch (offset)
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{
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case 0x800: // VERSION
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case R_VERSION:
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switch (m_chip_type)
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{
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case ASC_TYPE_ASC:
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return 0;
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case ASC_TYPE_V8:
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case ASC_TYPE_EAGLE:
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case ASC_TYPE_SPICE:
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case ASC_TYPE_VASP:
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return 0xe8;
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case ASC_TYPE_SONORA:
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return 0xbc;
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default:
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return 0;
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default: // return the actual register value
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break;
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}
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break;
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case 0x804: // FIFO Interrupt Status
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case R_MODE:
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switch (m_chip_type)
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{
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case ASC_TYPE_V8:
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case ASC_TYPE_EAGLE:
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case ASC_TYPE_SPICE:
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case ASC_TYPE_VASP:
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return 1;
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default:
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break;
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}
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break;
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case R_CONTROL:
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switch (m_chip_type)
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{
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case ASC_TYPE_V8:
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case ASC_TYPE_EAGLE:
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case ASC_TYPE_SPICE:
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case ASC_TYPE_VASP:
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return 1;
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default:
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break;
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}
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break;
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case R_FIFOSTAT:
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if (m_chip_type == ASC_TYPE_V8)
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{
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return 3;
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rv = 3;
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}
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else
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{
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rv = m_regs[R_FIFOSTAT-0x800];
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}
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// reading this register clears all bits
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m_regs[R_FIFOSTAT-0x800] = 0;
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// reading this clears interrupts?
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if (m_irq_cb)
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{
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m_irq_cb(this, 0);
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}
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return rv;
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break;
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default:
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@ -167,7 +368,39 @@ UINT8 asc_device::read(UINT16 offset)
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}
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}
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return regs[offset-0x800];
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// WT inc/phase registers - rebuild from "live" copies"
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if ((offset >= 0x810) && (offset <= 0x82f))
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{
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m_regs[0x11] = m_phase[0]>>16;
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m_regs[0x12] = m_phase[0]>>8;
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m_regs[0x13] = m_phase[0];
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m_regs[0x15] = m_incr[0]>>16;
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m_regs[0x16] = m_incr[0]>>8;
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m_regs[0x17] = m_incr[0];
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m_regs[0x19] = m_phase[1]>>16;
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m_regs[0x1a] = m_phase[1]>>8;
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m_regs[0x1b] = m_phase[1];
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m_regs[0x1d] = m_incr[1]>>16;
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m_regs[0x1e] = m_incr[1]>>8;
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m_regs[0x1f] = m_incr[1];
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m_regs[0x21] = m_phase[2]>>16;
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m_regs[0x22] = m_phase[2]>>8;
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m_regs[0x23] = m_phase[2];
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m_regs[0x25] = m_incr[2]>>16;
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m_regs[0x26] = m_incr[2]>>8;
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m_regs[0x27] = m_incr[2];
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m_regs[0x29] = m_phase[3]>>16;
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m_regs[0x2a] = m_phase[3]>>8;
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m_regs[0x2b] = m_phase[3];
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m_regs[0x2d] = m_incr[3]>>16;
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m_regs[0x2e] = m_incr[3]>>8;
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m_regs[0x2f] = m_incr[3];
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}
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return m_regs[offset-0x800];
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}
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//-------------------------------------------------
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@ -176,17 +409,212 @@ UINT8 asc_device::read(UINT16 offset)
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void asc_device::write(UINT16 offset, UINT8 data)
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{
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// printf("ASC: write %02x to %x\n", data, offset);
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if (offset < 0x400)
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{
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fifo_a[offset] = data;
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}
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else if (offset < 0x800)
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if (m_regs[R_MODE-0x800] == 1)
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{
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fifo_b[offset-0x400] = data;
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if (m_fifo_a_wrptr < 0x400)
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{
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m_fifo_a_wrhalf[0] = 1;
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}
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else
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{
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regs[offset-0x800] = data;
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m_fifo_a_wrhalf[1] = 1;
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}
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m_fifo_a[m_fifo_a_wrptr++] = data;
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if ((m_fifo_a_wrptr == 0x200) || (m_fifo_a_wrptr == 0x400))
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{
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m_regs[R_FIFOSTAT-0x800] |= 2; // fifo A half-full
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if (m_irq_cb)
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{
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m_irq_cb(this, 1);
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}
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}
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m_fifo_a_wrptr &= 0x3ff;
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}
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else
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{
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m_fifo_a[offset] = data;
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}
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}
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else if (offset < 0x800)
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{
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if (m_regs[R_MODE-0x800] == 1)
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{
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if (m_fifo_b_wrptr < 0x400)
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{
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m_fifo_b_wrhalf[0] = 1;
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}
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else
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{
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m_fifo_b_wrhalf[1] = 1;
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}
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m_fifo_b[m_fifo_b_wrptr++] = data;
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if ((m_fifo_a_wrptr == 0x200) || (m_fifo_a_wrptr == 0x400))
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{
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m_regs[R_FIFOSTAT-0x800] |= 8; // fifo B half-full
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if (m_irq_cb)
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{
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m_irq_cb(this, 1);
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}
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}
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m_fifo_b_wrptr &= 0x3ff;
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}
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else
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{
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m_fifo_b[offset-0x400] = data;
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}
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}
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else
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{
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// printf("ASC: %02x to %x (was %x)\n", data, offset, m_regs[offset-0x800]);
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stream_update(m_stream);
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switch (offset)
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{
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case R_MODE:
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data &= 3; // only bits 0 and 1 can be written
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memset(m_fifo_a_wrhalf, 0, sizeof(m_fifo_a_wrhalf));
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memset(m_fifo_b_wrhalf, 0, sizeof(m_fifo_b_wrhalf));
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m_fifo_a_rdptr = m_fifo_b_rdptr = 0;
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m_fifo_a_wrptr = m_fifo_b_wrptr = 0;
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break;
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case R_WTCONTROL:
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// printf("One-shot wavetable %02x\n", data);
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break;
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case 0x811:
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m_phase[0] &= 0x00ffff;
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m_phase[0] |= data<<16;
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break;
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case 0x812:
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m_phase[0] &= 0xff00ff;
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m_phase[0] |= data<<8;
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break;
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case 0x813:
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m_phase[0] &= 0xffff00;
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m_phase[0] |= data;
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break;
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case 0x815:
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m_incr[0] &= 0x00ffff;
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m_incr[0] |= data<<16;
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break;
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case 0x816:
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m_incr[0] &= 0xff00ff;
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m_incr[0] |= data<<8;
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break;
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case 0x817:
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m_incr[0] &= 0xffff00;
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m_incr[0] |= data;
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break;
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case 0x819:
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m_phase[1] &= 0x00ffff;
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m_phase[1] |= data<<16;
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break;
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case 0x81a:
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m_phase[1] &= 0xff00ff;
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m_phase[1] |= data<<8;
|
||||
break;
|
||||
|
||||
case 0x81b:
|
||||
m_phase[1] &= 0xffff00;
|
||||
m_phase[1] |= data;
|
||||
break;
|
||||
|
||||
case 0x81d:
|
||||
m_incr[1] &= 0x00ffff;
|
||||
m_incr[1] |= data<<16;
|
||||
break;
|
||||
|
||||
case 0x81e:
|
||||
m_incr[1] &= 0xff00ff;
|
||||
m_incr[1] |= data<<8;
|
||||
break;
|
||||
|
||||
case 0x81f:
|
||||
m_incr[1] &= 0xffff00;
|
||||
m_incr[1] |= data;
|
||||
break;
|
||||
|
||||
case 0x821:
|
||||
m_phase[2] &= 0x00ffff;
|
||||
m_phase[2] |= data<<16;
|
||||
break;
|
||||
|
||||
case 0x822:
|
||||
m_phase[2] &= 0xff00ff;
|
||||
m_phase[2] |= data<<8;
|
||||
break;
|
||||
|
||||
case 0x823:
|
||||
m_phase[2] &= 0xffff00;
|
||||
m_phase[2] |= data;
|
||||
break;
|
||||
|
||||
case 0x825:
|
||||
m_incr[2] &= 0x00ffff;
|
||||
m_incr[2] |= data<<16;
|
||||
break;
|
||||
|
||||
case 0x826:
|
||||
m_incr[2] &= 0xff00ff;
|
||||
m_incr[2] |= data<<8;
|
||||
break;
|
||||
|
||||
case 0x827:
|
||||
m_incr[2] &= 0xffff00;
|
||||
m_incr[2] |= data;
|
||||
break;
|
||||
|
||||
case 0x829:
|
||||
m_phase[3] &= 0x00ffff;
|
||||
m_phase[3] |= data<<16;
|
||||
break;
|
||||
|
||||
case 0x82a:
|
||||
m_phase[3] &= 0xff00ff;
|
||||
m_phase[3] |= data<<8;
|
||||
break;
|
||||
|
||||
case 0x82b:
|
||||
m_phase[3] &= 0xffff00;
|
||||
m_phase[3] |= data;
|
||||
break;
|
||||
|
||||
case 0x82d:
|
||||
m_incr[3] &= 0x00ffff;
|
||||
m_incr[3] |= data<<16;
|
||||
break;
|
||||
|
||||
case 0x82e:
|
||||
m_incr[3] &= 0xff00ff;
|
||||
m_incr[3] |= data<<8;
|
||||
break;
|
||||
|
||||
case 0x82f:
|
||||
m_incr[3] &= 0xffff00;
|
||||
m_incr[3] |= data;
|
||||
break;
|
||||
}
|
||||
|
||||
m_regs[offset-0x800] = data;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -39,17 +39,21 @@ enum
|
||||
// INTERFACE CONFIGURATION MACROS
|
||||
//**************************************************************************
|
||||
|
||||
#define MDRV_ASC_ADD(_tag, _clock, _type) \
|
||||
#define MDRV_ASC_ADD(_tag, _clock, _type, _irqf) \
|
||||
MDRV_DEVICE_ADD(_tag, ASC, _clock) \
|
||||
MDRV_ASC_TYPE(_type)
|
||||
MDRV_ASC_TYPE(_type) \
|
||||
MDRV_IRQ_FUNC(_irqf)
|
||||
|
||||
#define MDRV_ASC_REPLACE(_tag, _clock, _type) \
|
||||
#define MDRV_ASC_REPLACE(_tag, _clock, _type, _irqf) \
|
||||
MDRV_DEVICE_REPLACE(_tag, ASC, _clock) \
|
||||
MDRV_ASC_TYPE(_type)
|
||||
MDRV_ASC_TYPE(_type) \
|
||||
MDRV_IRQ_FUNC(_irqf)
|
||||
|
||||
#define MDRV_ASC_TYPE(_type) \
|
||||
asc_device_config::static_set_type(device, _type); \
|
||||
|
||||
#define MDRV_IRQ_FUNC(_irqf) \
|
||||
asc_device_config::static_set_irqf(device, _irqf); \
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
@ -72,16 +76,12 @@ public:
|
||||
|
||||
// inline configuration helpers
|
||||
static void static_set_type(device_config *device, int type);
|
||||
static void static_set_irqf(device_config *device, void (*irqf)(running_device *device, int state));
|
||||
|
||||
protected:
|
||||
// device_config overrides
|
||||
virtual const address_space_config *memory_space_config(int spacenum = 0) const;
|
||||
|
||||
// internal state
|
||||
const address_space_config m_space_config;
|
||||
|
||||
// inline data
|
||||
UINT8 m_type;
|
||||
void (*m_irq_func)(running_device *device, int state);
|
||||
};
|
||||
|
||||
|
||||
@ -100,6 +100,26 @@ public:
|
||||
void write(UINT16 offset, UINT8 data);
|
||||
|
||||
protected:
|
||||
enum
|
||||
{
|
||||
R_VERSION = 0x800,
|
||||
R_MODE,
|
||||
R_CONTROL,
|
||||
R_FIFOMODE,
|
||||
R_FIFOSTAT,
|
||||
R_WTCONTROL,
|
||||
R_VOLUME,
|
||||
R_CLOCK,
|
||||
R_REG8,
|
||||
R_REG9,
|
||||
R_PLAYRECA,
|
||||
R_REGB,
|
||||
R_REGC,
|
||||
R_REGD,
|
||||
R_REGE,
|
||||
R_TEST
|
||||
};
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
@ -112,12 +132,19 @@ protected:
|
||||
const asc_device_config &m_config;
|
||||
|
||||
UINT8 m_chip_type;
|
||||
void (*m_irq_cb)(running_device *device, int state);
|
||||
sound_stream *m_stream;
|
||||
|
||||
UINT8 fifo_a[0x400];
|
||||
UINT8 fifo_b[0x400];
|
||||
UINT8 m_fifo_a[0x400];
|
||||
UINT8 m_fifo_b[0x400];
|
||||
|
||||
UINT8 regs[0x100];
|
||||
UINT8 m_regs[0x100];
|
||||
|
||||
UINT32 m_phase[4], m_incr[4];
|
||||
|
||||
int m_fifo_a_rdptr, m_fifo_b_rdptr;
|
||||
int m_fifo_a_wrptr, m_fifo_b_wrptr;
|
||||
int m_fifo_a_wrhalf[2], m_fifo_b_wrhalf[2];
|
||||
};
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user