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Pointer-ified the i86/i286 cores.

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Removed unused v20/v30 implementation.
This commit is contained in:
Aaron Giles 2008-12-09 15:39:20 +00:00
parent 12415fcdcb
commit 89e14c632f
23 changed files with 2496 additions and 4419 deletions
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7
.gitattributes vendored
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@ -162,17 +162,10 @@ src/emu/cpu/i86/instr286.c svneol=native#text/plain
src/emu/cpu/i86/instr286.h svneol=native#text/plain
src/emu/cpu/i86/instr86.c svneol=native#text/plain
src/emu/cpu/i86/instr86.h svneol=native#text/plain
src/emu/cpu/i86/instrv30.c svneol=native#text/plain
src/emu/cpu/i86/instrv30.h svneol=native#text/plain
src/emu/cpu/i86/modrm.h svneol=native#text/plain
src/emu/cpu/i86/table186.h svneol=native#text/plain
src/emu/cpu/i86/table286.h svneol=native#text/plain
src/emu/cpu/i86/table86.h svneol=native#text/plain
src/emu/cpu/i86/tablev30.h svneol=native#text/plain
src/emu/cpu/i86/v20intf.h svneol=native#text/plain
src/emu/cpu/i86/v30.h svneol=native#text/plain
src/emu/cpu/i86/v30intf.h svneol=native#text/plain
src/emu/cpu/i86/v33intf.h svneol=native#text/plain
src/emu/cpu/i8x41/8x41dasm.c svneol=native#text/plain
src/emu/cpu/i8x41/i8x41.c svneol=native#text/plain
src/emu/cpu/i8x41/i8x41.h svneol=native#text/plain

53
src/emu/cpu/i86/ea.h
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@ -1,34 +1,31 @@
static unsigned EA;
static UINT16 EO; /* HJB 12/13/98 effective offset of the address (before segment is added) */
static unsigned EA_000(i8086_state *cpustate) { cpustate->icount-=7; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[SI]); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_001(i8086_state *cpustate) { cpustate->icount-=8; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[DI]); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_002(i8086_state *cpustate) { cpustate->icount-=8; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[SI]); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_003(i8086_state *cpustate) { cpustate->icount-=7; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[DI]); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_004(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[SI]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_005(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[DI]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_006(i8086_state *cpustate) { cpustate->icount-=6; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_007(i8086_state *cpustate) { cpustate->icount-=5; cpustate->eo=cpustate->regs.w[BX]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_000(void) { i8086_ICount-=7; EO=(WORD)(I.regs.w[BX]+I.regs.w[SI]); EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_001(void) { i8086_ICount-=8; EO=(WORD)(I.regs.w[BX]+I.regs.w[DI]); EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_002(void) { i8086_ICount-=8; EO=(WORD)(I.regs.w[BP]+I.regs.w[SI]); EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_003(void) { i8086_ICount-=7; EO=(WORD)(I.regs.w[BP]+I.regs.w[DI]); EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_004(void) { i8086_ICount-=5; EO=I.regs.w[SI]; EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_005(void) { i8086_ICount-=5; EO=I.regs.w[DI]; EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_006(void) { i8086_ICount-=6; EO=FETCHOP; EO+=FETCHOP<<8; EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_007(void) { i8086_ICount-=5; EO=I.regs.w[BX]; EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_100(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_101(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=(WORD)(cpustate->regs.w[BX]+cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_102(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_103(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=(WORD)(cpustate->regs.w[BP]+cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_104(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[SI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_105(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[DI]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_106(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[BP]+(INT8)FETCHOP); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_107(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=(WORD)(cpustate->regs.w[BX]+(INT8)FETCHOP); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
static unsigned EA_100(void) { i8086_ICount-=11; EO=(WORD)(I.regs.w[BX]+I.regs.w[SI]+(INT8)FETCHOP); EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_101(void) { i8086_ICount-=12; EO=(WORD)(I.regs.w[BX]+I.regs.w[DI]+(INT8)FETCHOP); EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_102(void) { i8086_ICount-=12; EO=(WORD)(I.regs.w[BP]+I.regs.w[SI]+(INT8)FETCHOP); EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_103(void) { i8086_ICount-=11; EO=(WORD)(I.regs.w[BP]+I.regs.w[DI]+(INT8)FETCHOP); EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_104(void) { i8086_ICount-=9; EO=(WORD)(I.regs.w[SI]+(INT8)FETCHOP); EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_105(void) { i8086_ICount-=9; EO=(WORD)(I.regs.w[DI]+(INT8)FETCHOP); EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_106(void) { i8086_ICount-=9; EO=(WORD)(I.regs.w[BP]+(INT8)FETCHOP); EA=DefaultBase(SS)+EO; return EA; }
static unsigned EA_107(void) { i8086_ICount-=9; EO=(WORD)(I.regs.w[BX]+(INT8)FETCHOP); EA=DefaultBase(DS)+EO; return EA; }
static unsigned EA_200(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]+cpustate->regs.w[SI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
static unsigned EA_201(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]+cpustate->regs.w[DI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
static unsigned EA_202(i8086_state *cpustate) { cpustate->icount-=12; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[SI]; cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
static unsigned EA_203(i8086_state *cpustate) { cpustate->icount-=11; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]+cpustate->regs.w[DI]; cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
static unsigned EA_204(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[SI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
static unsigned EA_205(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[DI]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
static unsigned EA_206(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BP]; cpustate->ea=DefaultBase(SS)+(WORD)cpustate->eo; return cpustate->ea; }
static unsigned EA_207(i8086_state *cpustate) { cpustate->icount-=9; cpustate->eo=FETCHOP; cpustate->eo+=FETCHOP<<8; cpustate->eo+=cpustate->regs.w[BX]; cpustate->ea=DefaultBase(DS)+(WORD)cpustate->eo; return cpustate->ea; }
static unsigned EA_200(void) { i8086_ICount-=11; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BX]+I.regs.w[SI]; EA=DefaultBase(DS)+(WORD)EO; return EA; }
static unsigned EA_201(void) { i8086_ICount-=12; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BX]+I.regs.w[DI]; EA=DefaultBase(DS)+(WORD)EO; return EA; }
static unsigned EA_202(void) { i8086_ICount-=12; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BP]+I.regs.w[SI]; EA=DefaultBase(SS)+(WORD)EO; return EA; }
static unsigned EA_203(void) { i8086_ICount-=11; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BP]+I.regs.w[DI]; EA=DefaultBase(SS)+(WORD)EO; return EA; }
static unsigned EA_204(void) { i8086_ICount-=9; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[SI]; EA=DefaultBase(DS)+(WORD)EO; return EA; }
static unsigned EA_205(void) { i8086_ICount-=9; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[DI]; EA=DefaultBase(DS)+(WORD)EO; return EA; }
static unsigned EA_206(void) { i8086_ICount-=9; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BP]; EA=DefaultBase(SS)+(WORD)EO; return EA; }
static unsigned EA_207(void) { i8086_ICount-=9; EO=FETCHOP; EO+=FETCHOP<<8; EO+=I.regs.w[BX]; EA=DefaultBase(DS)+(WORD)EO; return EA; }
static unsigned (*const GetEA[192])(void)={
static unsigned (*const GetEA[192])(i8086_state *cpustate)={
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,

418
src/emu/cpu/i86/i286.c
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@ -11,11 +11,9 @@
#define LOG(x) do { if (VERBOSE) mame_printf_debug x; } while (0)
/* All post-i286 CPUs have a 16MB address space */
#define AMASK I.amask
#define AMASK cpustate->amask
#define i8086_ICount i80286_ICount
#define INPUT_LINE_A20 1
#include "i86.h"
@ -35,7 +33,8 @@ typedef union
UINT8 b[16]; /* or as 8 bit registers */
} i80286basicregs;
typedef struct
typedef struct _i80286_state i80286_state;
struct _i80286_state
{
i80286basicregs regs;
UINT32 amask; /* address mask */
@ -71,13 +70,12 @@ typedef struct
INT32 extra_cycles; /* extra cycles for interrupts */
memory_interface mem;
} i80286_Regs;
static int i80286_ICount;
static i80286_Regs I;
static unsigned prefix_base; /* base address of the latest prefix segment */
static char seg_prefix; /* prefix segment indicator */
int icount;
unsigned prefix_base;
char seg_prefix;
unsigned ea;
UINT16 eo; /* HJB 12/13/98 effective offset of the address (before segment is added) */
};
#define INT_IRQ 0x01
#define NMI_IRQ 0x02
@ -93,6 +91,7 @@ static struct i80x86_timing timing;
#define PREFIX86(fname) i80286##fname
#define PREFIX186(fname) i80286##fname
#define PREFIX286(fname) i80286##fname
#define i8086_state i80286_state
#include "ea.h"
#include "modrm.h"
@ -131,13 +130,14 @@ static void i80286_urinit(void)
}
}
static void i80286_set_a20_line(int state)
static void i80286_set_a20_line(i80286_state *cpustate, int state)
{
I.amask = state ? 0x00ffffff : 0x000fffff;
cpustate->amask = state ? 0x00ffffff : 0x000fffff;
}
static CPU_RESET( i80286 )
{
i80286_state *cpustate = device->token;
static int urinit=1;
/* in my docu not all registers are initialized! */
@ -147,20 +147,20 @@ static CPU_RESET( i80286 )
}
I.sregs[CS] = 0xf000;
I.base[CS] = 0xff0000;
cpustate->sregs[CS] = 0xf000;
cpustate->base[CS] = 0xff0000;
/* temporary, until I have the right reset vector working */
I.base[CS] = I.sregs[CS] << 4;
I.pc = 0xffff0;
I.limit[CS]=I.limit[SS]=I.limit[DS]=I.limit[ES]=0xffff;
I.sregs[DS]=I.sregs[SS]=I.sregs[ES]=0;
I.base[DS]=I.base[SS]=I.base[ES]=0;
I.msw=0xfff0;
I.flags=2;
ExpandFlags(I.flags);
I.idtr.base=0;I.idtr.limit=0x3ff;
cpustate->base[CS] = cpustate->sregs[CS] << 4;
cpustate->pc = 0xffff0;
cpustate->limit[CS]=cpustate->limit[SS]=cpustate->limit[DS]=cpustate->limit[ES]=0xffff;
cpustate->sregs[DS]=cpustate->sregs[SS]=cpustate->sregs[ES]=0;
cpustate->base[DS]=cpustate->base[SS]=cpustate->base[ES]=0;
cpustate->msw=0xfff0;
cpustate->flags=2;
ExpandFlags(cpustate->flags);
cpustate->idtr.base=0;cpustate->idtr.limit=0x3ff;
CHANGE_PC(I.pc);
CHANGE_PC(cpustate->pc);
}
@ -168,79 +168,63 @@ static CPU_RESET( i80286 )
/* ASG 971222 -- added these interface functions */
static CPU_GET_CONTEXT( i80286 )
{
if( dst )
*(i80286_Regs*)dst = I;
}
static CPU_SET_CONTEXT( i80286 )
{
if( src )
{
I = *(i80286_Regs*)src;
if (PM) {
} else {
I.base[CS] = SegBase(CS);
I.base[DS] = SegBase(DS);
I.base[ES] = SegBase(ES);
I.base[SS] = SegBase(SS);
}
CHANGE_PC(I.pc);
}
}
static void set_irq_line(int irqline, int state)
static void set_irq_line(i80286_state *cpustate, int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (I.nmi_state == state)
if (cpustate->nmi_state == state)
return;
I.nmi_state = state;
cpustate->nmi_state = state;
/* on a rising edge, signal the NMI */
if (state != CLEAR_LINE)
PREFIX(_interrupt)(I8086_NMI_INT_VECTOR);
PREFIX(_interrupt)(cpustate, I8086_NMI_INT_VECTOR);
}
else
{
I.irq_state = state;
cpustate->irq_state = state;
/* if the IF is set, signal an interrupt */
if (state != CLEAR_LINE && I.IF)
PREFIX(_interrupt)(-1);
if (state != CLEAR_LINE && cpustate->IF)
PREFIX(_interrupt)(cpustate, -1);
}
}
static CPU_EXECUTE( i80286 )
{
i80286_state *cpustate = device->token;
cpustate->base[CS] = SegBase(CS);
cpustate->base[DS] = SegBase(DS);
cpustate->base[ES] = SegBase(ES);
cpustate->base[SS] = SegBase(SS);
/* copy over the cycle counts if they're not correct */
if (timing.id != 80286)
timing = i80286_cycles;
/* adjust for any interrupts that came in */
i80286_ICount = cycles;
i80286_ICount -= I.extra_cycles;
I.extra_cycles = 0;
cpustate->icount = cycles;
cpustate->icount -= cpustate->extra_cycles;
cpustate->extra_cycles = 0;
/* run until we're out */
while(i80286_ICount>0)
while(cpustate->icount>0)
{
LOG(("[%04x:%04x]=%02x\tF:%04x\tAX=%04x\tBX=%04x\tCX=%04x\tDX=%04x %d%d%d%d%d%d%d%d%d\n",I.sregs[CS],I.pc - I.base[CS],ReadByte(I.pc),I.flags,I.regs.w[AX],I.regs.w[BX],I.regs.w[CX],I.regs.w[DX], I.AuxVal?1:0, I.OverVal?1:0, I.SignVal?1:0, I.ZeroVal?1:0, I.CarryVal?1:0, I.ParityVal?1:0,I.TF, I.IF, I.DirVal<0?1:0));
debugger_instruction_hook(device, I.pc);
LOG(("[%04x:%04x]=%02x\tF:%04x\tAX=%04x\tBX=%04x\tCX=%04x\tDX=%04x %d%d%d%d%d%d%d%d%d\n",cpustate->sregs[CS],cpustate->pc - cpustate->base[CS],ReadByte(cpustate->pc),cpustate->flags,cpustate->regs.w[AX],cpustate->regs.w[BX],cpustate->regs.w[CX],cpustate->regs.w[DX], cpustate->AuxVal?1:0, cpustate->OverVal?1:0, cpustate->SignVal?1:0, cpustate->ZeroVal?1:0, cpustate->CarryVal?1:0, cpustate->ParityVal?1:0,cpustate->TF, cpustate->IF, cpustate->DirVal<0?1:0));
debugger_instruction_hook(device, cpustate->pc);
seg_prefix=FALSE;
I.prevpc = I.pc;
cpustate->seg_prefix=FALSE;
cpustate->prevpc = cpustate->pc;
TABLE286 // call instruction
}
/* adjust for any interrupts that came in */
i80286_ICount -= I.extra_cycles;
I.extra_cycles = 0;
cpustate->icount -= cpustate->extra_cycles;
cpustate->extra_cycles = 0;
return cycles - i80286_ICount;
return cycles - cpustate->icount;
}
extern int i386_dasm_one(char *buffer, UINT32 eip, const UINT8 *oprom, int mode);
@ -252,53 +236,55 @@ static CPU_DISASSEMBLE( i80286 )
static CPU_INIT( i80286 )
{
state_save_register_device_item_array(device, 0, I.regs.w);
state_save_register_device_item(device, 0, I.amask);
state_save_register_device_item(device, 0, I.pc);
state_save_register_device_item(device, 0, I.prevpc);
state_save_register_device_item(device, 0, I.msw);
state_save_register_device_item_array(device, 0, I.base);
state_save_register_device_item_array(device, 0, I.sregs);
state_save_register_device_item_array(device, 0, I.limit);
state_save_register_device_item_array(device, 0, I.rights);
state_save_register_device_item(device, 0, I.gdtr.base);
state_save_register_device_item(device, 0, I.gdtr.limit);
state_save_register_device_item(device, 0, I.idtr.base);
state_save_register_device_item(device, 0, I.idtr.limit);
state_save_register_device_item(device, 0, I.ldtr.sel);
state_save_register_device_item(device, 0, I.ldtr.base);
state_save_register_device_item(device, 0, I.ldtr.limit);
state_save_register_device_item(device, 0, I.ldtr.rights);
state_save_register_device_item(device, 0, I.tr.sel);
state_save_register_device_item(device, 0, I.tr.base);
state_save_register_device_item(device, 0, I.tr.limit);
state_save_register_device_item(device, 0, I.tr.rights);
state_save_register_device_item(device, 0, I.AuxVal);
state_save_register_device_item(device, 0, I.OverVal);
state_save_register_device_item(device, 0, I.SignVal);
state_save_register_device_item(device, 0, I.ZeroVal);
state_save_register_device_item(device, 0, I.CarryVal);
state_save_register_device_item(device, 0, I.DirVal);
state_save_register_device_item(device, 0, I.ParityVal);
state_save_register_device_item(device, 0, I.TF);
state_save_register_device_item(device, 0, I.IF);
state_save_register_device_item(device, 0, I.int_vector);
state_save_register_device_item(device, 0, I.nmi_state);
state_save_register_device_item(device, 0, I.irq_state);
state_save_register_device_item(device, 0, I.extra_cycles);
i80286_state *cpustate = device->token;
I.irq_callback = irqcallback;
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
state_save_register_device_item_array(device, 0, cpustate->regs.w);
state_save_register_device_item(device, 0, cpustate->amask);
state_save_register_device_item(device, 0, cpustate->pc);
state_save_register_device_item(device, 0, cpustate->prevpc);
state_save_register_device_item(device, 0, cpustate->msw);
state_save_register_device_item_array(device, 0, cpustate->base);
state_save_register_device_item_array(device, 0, cpustate->sregs);
state_save_register_device_item_array(device, 0, cpustate->limit);
state_save_register_device_item_array(device, 0, cpustate->rights);
state_save_register_device_item(device, 0, cpustate->gdtr.base);
state_save_register_device_item(device, 0, cpustate->gdtr.limit);
state_save_register_device_item(device, 0, cpustate->idtr.base);
state_save_register_device_item(device, 0, cpustate->idtr.limit);
state_save_register_device_item(device, 0, cpustate->ldtr.sel);
state_save_register_device_item(device, 0, cpustate->ldtr.base);
state_save_register_device_item(device, 0, cpustate->ldtr.limit);
state_save_register_device_item(device, 0, cpustate->ldtr.rights);
state_save_register_device_item(device, 0, cpustate->tr.sel);
state_save_register_device_item(device, 0, cpustate->tr.base);
state_save_register_device_item(device, 0, cpustate->tr.limit);
state_save_register_device_item(device, 0, cpustate->tr.rights);
state_save_register_device_item(device, 0, cpustate->AuxVal);
state_save_register_device_item(device, 0, cpustate->OverVal);
state_save_register_device_item(device, 0, cpustate->SignVal);
state_save_register_device_item(device, 0, cpustate->ZeroVal);
state_save_register_device_item(device, 0, cpustate->CarryVal);
state_save_register_device_item(device, 0, cpustate->DirVal);
state_save_register_device_item(device, 0, cpustate->ParityVal);
state_save_register_device_item(device, 0, cpustate->TF);
state_save_register_device_item(device, 0, cpustate->IF);
state_save_register_device_item(device, 0, cpustate->int_vector);
state_save_register_device_item(device, 0, cpustate->nmi_state);
state_save_register_device_item(device, 0, cpustate->irq_state);
state_save_register_device_item(device, 0, cpustate->extra_cycles);
cpustate->irq_callback = irqcallback;
cpustate->device = device;
cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
/* If a reset parameter is given, take it as pointer to an address mask */
if( device->static_config )
I.amask = *(unsigned*)device->static_config;
cpustate->amask = *(unsigned*)device->static_config;
else
I.amask = 0x00ffff;
cpustate->amask = 0x00ffff;
configure_memory_16bit();
configure_memory_16bit(cpustate);
}
@ -311,13 +297,15 @@ static CPU_INIT( i80286 )
static CPU_SET_INFO( i80286 )
{
i80286_state *cpustate = device->token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(0, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(cpustate, 0, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_A20: i80286_set_a20_line(info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_A20: i80286_set_a20_line(cpustate, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + I80286_PC:
@ -327,16 +315,16 @@ static CPU_SET_INFO( i80286 )
}
else
{
if (info->i - I.base[CS] >= 0x10000)
if (info->i - cpustate->base[CS] >= 0x10000)
{
I.base[CS] = info->i & 0xffff0;
I.sregs[CS] = I.base[CS] >> 4;
cpustate->base[CS] = info->i & 0xffff0;
cpustate->sregs[CS] = cpustate->base[CS] >> 4;
}
I.pc = info->i;
cpustate->pc = info->i;
}
break;
case CPUINFO_INT_REGISTER + I80286_IP: I.pc = I.base[CS] + info->i; break;
case CPUINFO_INT_REGISTER + I80286_IP: cpustate->pc = cpustate->base[CS] + info->i; break;
case CPUINFO_INT_SP:
if (PM)
{
@ -344,33 +332,33 @@ static CPU_SET_INFO( i80286 )
}
else
{
if (info->i - I.base[SS] < 0x10000)
if (info->i - cpustate->base[SS] < 0x10000)
{
I.regs.w[SP] = info->i - I.base[SS];
cpustate->regs.w[SP] = info->i - cpustate->base[SS];
}
else
{
I.base[SS] = info->i & 0xffff0;
I.sregs[SS] = I.base[SS] >> 4;
I.regs.w[SP] = info->i & 0x0000f;
cpustate->base[SS] = info->i & 0xffff0;
cpustate->sregs[SS] = cpustate->base[SS] >> 4;
cpustate->regs.w[SP] = info->i & 0x0000f;
}
}
break;
case CPUINFO_INT_REGISTER + I80286_SP: I.regs.w[SP] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_FLAGS: I.flags = info->i; ExpandFlags(info->i); break;
case CPUINFO_INT_REGISTER + I80286_AX: I.regs.w[AX] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_CX: I.regs.w[CX] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_DX: I.regs.w[DX] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_BX: I.regs.w[BX] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_BP: I.regs.w[BP] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_SI: I.regs.w[SI] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_DI: I.regs.w[DI] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_ES: I.sregs[ES] = info->i; I.base[ES] = SegBase(ES); break;
case CPUINFO_INT_REGISTER + I80286_CS: I.sregs[CS] = info->i; I.base[CS] = SegBase(CS); break;
case CPUINFO_INT_REGISTER + I80286_SS: I.sregs[SS] = info->i; I.base[SS] = SegBase(SS); break;
case CPUINFO_INT_REGISTER + I80286_DS: I.sregs[DS] = info->i; I.base[DS] = SegBase(DS); break;
case CPUINFO_INT_REGISTER + I80286_VECTOR: I.int_vector = info->i; break;
case CPUINFO_INT_REGISTER + I80286_SP: cpustate->regs.w[SP] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_FLAGS: cpustate->flags = info->i; ExpandFlags(info->i); break;
case CPUINFO_INT_REGISTER + I80286_AX: cpustate->regs.w[AX] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_CX: cpustate->regs.w[CX] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_DX: cpustate->regs.w[DX] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_BX: cpustate->regs.w[BX] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_BP: cpustate->regs.w[BP] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_SI: cpustate->regs.w[SI] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_DI: cpustate->regs.w[DI] = info->i; break;
case CPUINFO_INT_REGISTER + I80286_ES: cpustate->sregs[ES] = info->i; cpustate->base[ES] = SegBase(ES); break;
case CPUINFO_INT_REGISTER + I80286_CS: cpustate->sregs[CS] = info->i; cpustate->base[CS] = SegBase(CS); break;
case CPUINFO_INT_REGISTER + I80286_SS: cpustate->sregs[SS] = info->i; cpustate->base[SS] = SegBase(SS); break;
case CPUINFO_INT_REGISTER + I80286_DS: cpustate->sregs[DS] = info->i; cpustate->base[DS] = SegBase(DS); break;
case CPUINFO_INT_REGISTER + I80286_VECTOR: cpustate->int_vector = info->i; break;
}
}
@ -382,10 +370,12 @@ static CPU_SET_INFO( i80286 )
CPU_GET_INFO( i80286 )
{
i80286_state *cpustate = (device != NULL) ? device->token : NULL;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(I); break;
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i80286_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
@ -406,107 +396,107 @@ CPU_GET_INFO( i80286 )
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + 0: info->i = I.irq_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = I.nmi_state; break;
case CPUINFO_INT_INPUT_STATE + 0: info->i = cpustate->irq_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break;
case CPUINFO_INT_PREVIOUSPC: info->i = I.prevpc; break;
case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->prevpc; break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + I80286_PC: info->i = I.pc; break;
case CPUINFO_INT_REGISTER + I80286_IP: info->i = I.pc - I.base[CS]; break;
case CPUINFO_INT_SP: info->i = I.base[SS] + I.regs.w[SP]; break;
case CPUINFO_INT_REGISTER + I80286_SP: info->i = I.regs.w[SP]; break;
case CPUINFO_INT_REGISTER + I80286_FLAGS: I.flags = CompressFlags(); info->i = I.flags; break;
case CPUINFO_INT_REGISTER + I80286_AX: info->i = I.regs.w[AX]; break;
case CPUINFO_INT_REGISTER + I80286_CX: info->i = I.regs.w[CX]; break;
case CPUINFO_INT_REGISTER + I80286_DX: info->i = I.regs.w[DX]; break;
case CPUINFO_INT_REGISTER + I80286_BX: info->i = I.regs.w[BX]; break;
case CPUINFO_INT_REGISTER + I80286_BP: info->i = I.regs.w[BP]; break;
case CPUINFO_INT_REGISTER + I80286_SI: info->i = I.regs.w[SI]; break;
case CPUINFO_INT_REGISTER + I80286_DI: info->i = I.regs.w[DI]; break;
case CPUINFO_INT_REGISTER + I80286_ES: info->i = I.sregs[ES]; break;
case CPUINFO_INT_REGISTER + I80286_CS: info->i = I.sregs[CS]; break;
case CPUINFO_INT_REGISTER + I80286_SS: info->i = I.sregs[SS]; break;
case CPUINFO_INT_REGISTER + I80286_DS: info->i = I.sregs[DS]; break;
case CPUINFO_INT_REGISTER + I80286_VECTOR: info->i = I.int_vector; break;
case CPUINFO_INT_REGISTER + I80286_MSW: info->i = I.msw; break;
case CPUINFO_INT_REGISTER + I80286_GDTR_BASE: info->i = I.gdtr.base; break;
case CPUINFO_INT_REGISTER + I80286_GDTR_LIMIT: info->i = I.gdtr.limit; break;
case CPUINFO_INT_REGISTER + I80286_IDTR_BASE: info->i = I.idtr.base; break;
case CPUINFO_INT_REGISTER + I80286_IDTR_LIMIT: info->i = I.idtr.limit; break;
case CPUINFO_INT_REGISTER + I80286_LDTR_BASE: info->i = I.ldtr.base; break;
case CPUINFO_INT_REGISTER + I80286_LDTR_LIMIT: info->i = I.ldtr.limit; break;
case CPUINFO_INT_REGISTER + I80286_TR_BASE: info->i = I.tr.base; break;
case CPUINFO_INT_REGISTER + I80286_TR_LIMIT: info->i = I.tr.limit; break;
case CPUINFO_INT_REGISTER + I80286_PC: info->i = cpustate->pc; break;
case CPUINFO_INT_REGISTER + I80286_IP: info->i = cpustate->pc - cpustate->base[CS]; break;
case CPUINFO_INT_SP: info->i = cpustate->base[SS] + cpustate->regs.w[SP]; break;
case CPUINFO_INT_REGISTER + I80286_SP: info->i = cpustate->regs.w[SP]; break;
case CPUINFO_INT_REGISTER + I80286_FLAGS: cpustate->flags = CompressFlags(); info->i = cpustate->flags; break;
case CPUINFO_INT_REGISTER + I80286_AX: info->i = cpustate->regs.w[AX]; break;
case CPUINFO_INT_REGISTER + I80286_CX: info->i = cpustate->regs.w[CX]; break;
case CPUINFO_INT_REGISTER + I80286_DX: info->i = cpustate->regs.w[DX]; break;
case CPUINFO_INT_REGISTER + I80286_BX: info->i = cpustate->regs.w[BX]; break;
case CPUINFO_INT_REGISTER + I80286_BP: info->i = cpustate->regs.w[BP]; break;
case CPUINFO_INT_REGISTER + I80286_SI: info->i = cpustate->regs.w[SI]; break;
case CPUINFO_INT_REGISTER + I80286_DI: info->i = cpustate->regs.w[DI]; break;
case CPUINFO_INT_REGISTER + I80286_ES: info->i = cpustate->sregs[ES]; break;
case CPUINFO_INT_REGISTER + I80286_CS: info->i = cpustate->sregs[CS]; break;
case CPUINFO_INT_REGISTER + I80286_SS: info->i = cpustate->sregs[SS]; break;
case CPUINFO_INT_REGISTER + I80286_DS: info->i = cpustate->sregs[DS]; break;
case CPUINFO_INT_REGISTER + I80286_VECTOR: info->i = cpustate->int_vector; break;
case CPUINFO_INT_REGISTER + I80286_MSW: info->i = cpustate->msw; break;
case CPUINFO_INT_REGISTER + I80286_GDTR_BASE: info->i = cpustate->gdtr.base; break;
case CPUINFO_INT_REGISTER + I80286_GDTR_LIMIT: info->i = cpustate->gdtr.limit; break;
case CPUINFO_INT_REGISTER + I80286_IDTR_BASE: info->i = cpustate->idtr.base; break;
case CPUINFO_INT_REGISTER + I80286_IDTR_LIMIT: info->i = cpustate->idtr.limit; break;
case CPUINFO_INT_REGISTER + I80286_LDTR_BASE: info->i = cpustate->ldtr.base; break;
case CPUINFO_INT_REGISTER + I80286_LDTR_LIMIT: info->i = cpustate->ldtr.limit; break;
case CPUINFO_INT_REGISTER + I80286_TR_BASE: info->i = cpustate->tr.base; break;
case CPUINFO_INT_REGISTER + I80286_TR_LIMIT: info->i = cpustate->tr.limit; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i80286); break;
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(i80286); break;
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(i80286); break;
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break;
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break;
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i80286); break;
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(i80286); break;
case CPUINFO_PTR_EXIT: info->exit = NULL; break;
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(i80286); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i80286); break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &i80286_ICount; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "80286"); break;
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Intel 80286"); break;
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.4"); break;
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Real mode i286 emulator v1.4 by Fabrice Frances\n(initial work I.based on David Hedley's pcemu)"); break;
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Real mode i286 emulator v1.4 by Fabrice Frances\n(initial work cpustate->based on David Hedley's pcemu)"); break;
case CPUINFO_STR_FLAGS:
I.flags = CompressFlags();
cpustate->flags = CompressFlags();
sprintf(info->s, "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
I.flags & 0x8000 ? '?' : '.',
I.flags & 0x4000 ? '?' : '.',
I.flags & 0x2000 ? '?' : '.',
I.flags & 0x1000 ? '?' : '.',
I.flags & 0x0800 ? 'O' : '.',
I.flags & 0x0400 ? 'D' : '.',
I.flags & 0x0200 ? 'I' : '.',
I.flags & 0x0100 ? 'T' : '.',
I.flags & 0x0080 ? 'S' : '.',
I.flags & 0x0040 ? 'Z' : '.',
I.flags & 0x0020 ? '?' : '.',
I.flags & 0x0010 ? 'A' : '.',
I.flags & 0x0008 ? '?' : '.',
I.flags & 0x0004 ? 'P' : '.',
I.flags & 0x0002 ? 'N' : '.',
I.flags & 0x0001 ? 'C' : '.');
cpustate->flags & 0x8000 ? '?' : '.',
cpustate->flags & 0x4000 ? '?' : '.',
cpustate->flags & 0x2000 ? '?' : '.',
cpustate->flags & 0x1000 ? '?' : '.',
cpustate->flags & 0x0800 ? 'O' : '.',
cpustate->flags & 0x0400 ? 'D' : '.',
cpustate->flags & 0x0200 ? 'I' : '.',
cpustate->flags & 0x0100 ? 'T' : '.',
cpustate->flags & 0x0080 ? 'S' : '.',
cpustate->flags & 0x0040 ? 'Z' : '.',
cpustate->flags & 0x0020 ? '?' : '.',
cpustate->flags & 0x0010 ? 'A' : '.',
cpustate->flags & 0x0008 ? '?' : '.',
cpustate->flags & 0x0004 ? 'P' : '.',
cpustate->flags & 0x0002 ? 'N' : '.',
cpustate->flags & 0x0001 ? 'C' : '.');
break;
case CPUINFO_STR_REGISTER + I80286_PC: sprintf(info->s, "PC:%04X", I.pc); break;
case CPUINFO_STR_REGISTER + I80286_IP: sprintf(info->s, "IP: %04X", I.pc - I.base[CS]); break;
case CPUINFO_STR_REGISTER + I80286_SP: sprintf(info->s, "SP: %04X", I.regs.w[SP]); break;
case CPUINFO_STR_REGISTER + I80286_FLAGS: sprintf(info->s, "F:%04X", I.flags); break;
case CPUINFO_STR_REGISTER + I80286_AX: sprintf(info->s, "AX:%04X", I.regs.w[AX]); break;
case CPUINFO_STR_REGISTER + I80286_CX: sprintf(info->s, "CX:%04X", I.regs.w[CX]); break;
case CPUINFO_STR_REGISTER + I80286_DX: sprintf(info->s, "DX:%04X", I.regs.w[DX]); break;
case CPUINFO_STR_REGISTER + I80286_BX: sprintf(info->s, "BX:%04X", I.regs.w[BX]); break;
case CPUINFO_STR_REGISTER + I80286_BP: sprintf(info->s, "BP:%04X", I.regs.w[BP]); break;
case CPUINFO_STR_REGISTER + I80286_SI: sprintf(info->s, "SI: %04X", I.regs.w[SI]); break;
case CPUINFO_STR_REGISTER + I80286_DI: sprintf(info->s, "DI: %04X", I.regs.w[DI]); break;
case CPUINFO_STR_REGISTER + I80286_CS: sprintf(info->s, "CS: %04X %02X", I.sregs[CS], I.rights[CS]); break;
case CPUINFO_STR_REGISTER + I80286_CS_2: sprintf(info->s, "%06X %04X", I.base[CS], I.limit[CS]); break;
case CPUINFO_STR_REGISTER + I80286_SS: sprintf(info->s, "SS: %04X %02X", I.sregs[SS], I.rights[SS]); break;
case CPUINFO_STR_REGISTER + I80286_SS_2: sprintf(info->s, "%06X %04X", I.base[SS], I.limit[SS]); break;
case CPUINFO_STR_REGISTER + I80286_DS: sprintf(info->s, "DS: %04X %02X", I.sregs[DS], I.rights[DS]); break;
case CPUINFO_STR_REGISTER + I80286_DS_2: sprintf(info->s, "%06X %04X", I.base[DS], I.limit[DS]); break;
case CPUINFO_STR_REGISTER + I80286_ES: sprintf(info->s, "ES: %04X %02X", I.sregs[ES], I.rights[ES]); break;
case CPUINFO_STR_REGISTER + I80286_ES_2: sprintf(info->s, "%06X %04X", I.base[ES], I.limit[ES]); break;
case CPUINFO_STR_REGISTER + I80286_VECTOR: sprintf(info->s, "V:%02X", I.int_vector); break;
case CPUINFO_STR_REGISTER + I80286_MSW: sprintf(info->s, "MSW:%04X", I.msw); break;
case CPUINFO_STR_REGISTER + I80286_TR_BASE: sprintf(info->s, "GDTR: %06X", I.gdtr.base); break;
case CPUINFO_STR_REGISTER + I80286_TR_LIMIT: sprintf(info->s, "%04X", I.gdtr.limit); break;
case CPUINFO_STR_REGISTER + I80286_GDTR_BASE: sprintf(info->s, "IDTR: %06X", I.idtr.base); break;
case CPUINFO_STR_REGISTER + I80286_GDTR_LIMIT: sprintf(info->s, "%04X", I.idtr.limit); break;
case CPUINFO_STR_REGISTER + I80286_LDTR_BASE: sprintf(info->s, "LDTR:%04X %02X", I.ldtr.sel, I.ldtr.rights); break;
case CPUINFO_STR_REGISTER + I80286_LDTR_LIMIT: sprintf(info->s, "%06X %04X", I.ldtr.base, I.ldtr.limit); break;
case CPUINFO_STR_REGISTER + I80286_IDTR_BASE: sprintf(info->s, "IDTR: %06X", I.idtr.base); break;
case CPUINFO_STR_REGISTER + I80286_IDTR_LIMIT: sprintf(info->s, "%04X", I.idtr.limit); break;
case CPUINFO_STR_REGISTER + I80286_PC: sprintf(info->s, "PC:%04X", cpustate->pc); break;
case CPUINFO_STR_REGISTER + I80286_IP: sprintf(info->s, "IP: %04X", cpustate->pc - cpustate->base[CS]); break;
case CPUINFO_STR_REGISTER + I80286_SP: sprintf(info->s, "SP: %04X", cpustate->regs.w[SP]); break;
case CPUINFO_STR_REGISTER + I80286_FLAGS: sprintf(info->s, "F:%04X", cpustate->flags); break;
case CPUINFO_STR_REGISTER + I80286_AX: sprintf(info->s, "AX:%04X", cpustate->regs.w[AX]); break;
case CPUINFO_STR_REGISTER + I80286_CX: sprintf(info->s, "CX:%04X", cpustate->regs.w[CX]); break;
case CPUINFO_STR_REGISTER + I80286_DX: sprintf(info->s, "DX:%04X", cpustate->regs.w[DX]); break;
case CPUINFO_STR_REGISTER + I80286_BX: sprintf(info->s, "BX:%04X", cpustate->regs.w[BX]); break;
case CPUINFO_STR_REGISTER + I80286_BP: sprintf(info->s, "BP:%04X", cpustate->regs.w[BP]); break;
case CPUINFO_STR_REGISTER + I80286_SI: sprintf(info->s, "SI: %04X", cpustate->regs.w[SI]); break;
case CPUINFO_STR_REGISTER + I80286_DI: sprintf(info->s, "DI: %04X", cpustate->regs.w[DI]); break;
case CPUINFO_STR_REGISTER + I80286_CS: sprintf(info->s, "CS: %04X %02X", cpustate->sregs[CS], cpustate->rights[CS]); break;
case CPUINFO_STR_REGISTER + I80286_CS_2: sprintf(info->s, "%06X %04X", cpustate->base[CS], cpustate->limit[CS]); break;
case CPUINFO_STR_REGISTER + I80286_SS: sprintf(info->s, "SS: %04X %02X", cpustate->sregs[SS], cpustate->rights[SS]); break;
case CPUINFO_STR_REGISTER + I80286_SS_2: sprintf(info->s, "%06X %04X", cpustate->base[SS], cpustate->limit[SS]); break;
case CPUINFO_STR_REGISTER + I80286_DS: sprintf(info->s, "DS: %04X %02X", cpustate->sregs[DS], cpustate->rights[DS]); break;
case CPUINFO_STR_REGISTER + I80286_DS_2: sprintf(info->s, "%06X %04X", cpustate->base[DS], cpustate->limit[DS]); break;
case CPUINFO_STR_REGISTER + I80286_ES: sprintf(info->s, "ES: %04X %02X", cpustate->sregs[ES], cpustate->rights[ES]); break;
case CPUINFO_STR_REGISTER + I80286_ES_2: sprintf(info->s, "%06X %04X", cpustate->base[ES], cpustate->limit[ES]); break;
case CPUINFO_STR_REGISTER + I80286_VECTOR: sprintf(info->s, "V:%02X", cpustate->int_vector); break;
case CPUINFO_STR_REGISTER + I80286_MSW: sprintf(info->s, "MSW:%04X", cpustate->msw); break;
case CPUINFO_STR_REGISTER + I80286_TR_BASE: sprintf(info->s, "GDTR: %06X", cpustate->gdtr.base); break;
case CPUINFO_STR_REGISTER + I80286_TR_LIMIT: sprintf(info->s, "%04X", cpustate->gdtr.limit); break;
case CPUINFO_STR_REGISTER + I80286_GDTR_BASE: sprintf(info->s, "IDTR: %06X", cpustate->idtr.base); break;
case CPUINFO_STR_REGISTER + I80286_GDTR_LIMIT: sprintf(info->s, "%04X", cpustate->idtr.limit); break;
case CPUINFO_STR_REGISTER + I80286_LDTR_BASE: sprintf(info->s, "LDTR:%04X %02X", cpustate->ldtr.sel, cpustate->ldtr.rights); break;
case CPUINFO_STR_REGISTER + I80286_LDTR_LIMIT: sprintf(info->s, "%06X %04X", cpustate->ldtr.base, cpustate->ldtr.limit); break;
case CPUINFO_STR_REGISTER + I80286_IDTR_BASE: sprintf(info->s, "IDTR: %06X", cpustate->idtr.base); break;
case CPUINFO_STR_REGISTER + I80286_IDTR_LIMIT: sprintf(info->s, "%04X", cpustate->idtr.limit); break;
}
}

385
src/emu/cpu/i86/i86.c
View File

@ -31,7 +31,8 @@ typedef union
}
i8086basicregs;
typedef struct
typedef struct _i8086_state i8086_state;
struct _i8086_state
{
i8086basicregs regs;
UINT32 pc;
@ -40,9 +41,6 @@ typedef struct
UINT16 sregs[4];
UINT16 flags;
cpu_irq_callback irq_callback;
const device_config *device;
const address_space *program;
const address_space *io;
INT32 AuxVal, OverVal, SignVal, ZeroVal, CarryVal, DirVal; /* 0 or non-0 valued flags */
UINT8 ParityVal;
UINT8 TF, IF; /* 0 or 1 valued flags */
@ -54,8 +52,18 @@ typedef struct
INT32 extra_cycles; /* extra cycles for interrupts */
memory_interface mem;
}
i8086_Regs;
const device_config *device;
const address_space *program;
const address_space *io;
int icount;
unsigned prefix_base; /* base address of the latest prefix segment */
char seg_prefix; /* prefix segment indicator */
unsigned ea;
UINT16 eo; /* HJB 12/13/98 effective offset of the address (before segment is added) */
};
#include "i86time.c"
@ -64,16 +72,11 @@ i8086_Regs;
/* cpu state */
/***************************************************************************/
static int i8086_ICount;
static i8086_Regs I;
static unsigned prefix_base; /* base address of the latest prefix segment */
static char seg_prefix; /* prefix segment indicator */
static UINT8 parity_table[256];
static struct i80x86_timing timing;
static UINT8 parity_table[256];
/* The interrupt number of a pending external interrupt pending NMI is 2. */
/* For INTR interrupts, the level is caught on the bus during an INTA cycle */
@ -94,31 +97,33 @@ static struct i80x86_timing timing;
/***************************************************************************/
static void i8086_state_register(const device_config *device)
{
state_save_register_device_item_array(device, 0, I.regs.w);
state_save_register_device_item(device, 0, I.pc);
state_save_register_device_item(device, 0, I.prevpc);
state_save_register_device_item_array(device, 0, I.base);
state_save_register_device_item_array(device, 0, I.sregs);
state_save_register_device_item(device, 0, I.flags);
state_save_register_device_item(device, 0, I.AuxVal);
state_save_register_device_item(device, 0, I.OverVal);
state_save_register_device_item(device, 0, I.SignVal);
state_save_register_device_item(device, 0, I.ZeroVal);
state_save_register_device_item(device, 0, I.CarryVal);
state_save_register_device_item(device, 0, I.DirVal);
state_save_register_device_item(device, 0, I.ParityVal);
state_save_register_device_item(device, 0, I.TF);
state_save_register_device_item(device, 0, I.IF);
state_save_register_device_item(device, 0, I.MF);
state_save_register_device_item(device, 0, I.int_vector);
state_save_register_device_item(device, 0, I.nmi_state);
state_save_register_device_item(device, 0, I.irq_state);
state_save_register_device_item(device, 0, I.extra_cycles);
state_save_register_device_item(device, 0, I.test_state); /* PJB 03/05 */
i8086_state *cpustate = device->token;
state_save_register_device_item_array(device, 0, cpustate->regs.w);
state_save_register_device_item(device, 0, cpustate->pc);
state_save_register_device_item(device, 0, cpustate->prevpc);
state_save_register_device_item_array(device, 0, cpustate->base);
state_save_register_device_item_array(device, 0, cpustate->sregs);
state_save_register_device_item(device, 0, cpustate->flags);
state_save_register_device_item(device, 0, cpustate->AuxVal);
state_save_register_device_item(device, 0, cpustate->OverVal);
state_save_register_device_item(device, 0, cpustate->SignVal);
state_save_register_device_item(device, 0, cpustate->ZeroVal);
state_save_register_device_item(device, 0, cpustate->CarryVal);
state_save_register_device_item(device, 0, cpustate->DirVal);
state_save_register_device_item(device, 0, cpustate->ParityVal);
state_save_register_device_item(device, 0, cpustate->TF);
state_save_register_device_item(device, 0, cpustate->IF);
state_save_register_device_item(device, 0, cpustate->MF);
state_save_register_device_item(device, 0, cpustate->int_vector);
state_save_register_device_item(device, 0, cpustate->nmi_state);
state_save_register_device_item(device, 0, cpustate->irq_state);
state_save_register_device_item(device, 0, cpustate->extra_cycles);
state_save_register_device_item(device, 0, cpustate->test_state); /* PJB 03/05 */
}
static CPU_INIT( i8086 )
{
i8086_state *cpustate = device->token;
unsigned int i, j, c;
static const BREGS reg_name[8] = {AL, CL, DL, BL, AH, CH, DH, BH};
for (i = 0; i < 256; i++)
@ -142,41 +147,43 @@ static CPU_INIT( i8086 )
Mod_RM.RM.b[i] = (BREGS) reg_name[i & 7];
}
I.irq_callback = irqcallback;
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
cpustate->irq_callback = irqcallback;
cpustate->device = device;
cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
i8086_state_register(device);
configure_memory_16bit();
configure_memory_16bit(cpustate);
}
#if (HAS_I8088||HAS_I80188)
static CPU_INIT( i8088 )
{
i8086_state *cpustate = device->token;
CPU_INIT_CALL(i8086);
configure_memory_8bit();
configure_memory_8bit(cpustate);
}
#endif
static CPU_RESET( i8086 )
{
i8086_state *cpustate = device->token;
cpu_irq_callback save_irqcallback;
memory_interface save_mem;
save_irqcallback = I.irq_callback;
save_mem = I.mem;
memset(&I, 0, sizeof (I));
I.irq_callback = save_irqcallback;
I.mem = save_mem;
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
save_irqcallback = cpustate->irq_callback;
save_mem = cpustate->mem;
memset(cpustate, 0, sizeof(*cpustate));
cpustate->irq_callback = save_irqcallback;
cpustate->mem = save_mem;
cpustate->device = device;
cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
I.sregs[CS] = 0xf000;
I.base[CS] = SegBase(CS);
I.pc = 0xffff0 & AMASK;
ExpandFlags(I.flags);
cpustate->sregs[CS] = 0xf000;
cpustate->base[CS] = SegBase(CS);
cpustate->pc = 0xffff0 & AMASK;
ExpandFlags(cpustate->flags);
}
static CPU_EXIT( i8086 )
@ -186,81 +193,70 @@ static CPU_EXIT( i8086 )
/* ASG 971222 -- added these interface functions */
static CPU_GET_CONTEXT( i8086 )
{
if (dst)
*(i8086_Regs *) dst = I;
}
static CPU_SET_CONTEXT( i8086 )
{
if (src)
{
I = *(i8086_Regs *)src;
I.base[CS] = SegBase(CS);
I.base[DS] = SegBase(DS);
I.base[ES] = SegBase(ES);
I.base[SS] = SegBase(SS);
}
}
static void set_irq_line(int irqline, int state)
static void set_irq_line(i8086_state *cpustate, int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (I.nmi_state == state)
if (cpustate->nmi_state == state)
return;
I.nmi_state = state;
cpustate->nmi_state = state;
/* on a rising edge, signal the NMI */
if (state != CLEAR_LINE)
PREFIX(_interrupt)(I8086_NMI_INT_VECTOR);
PREFIX(_interrupt)(cpustate, I8086_NMI_INT_VECTOR);
}
else
{
I.irq_state = state;
cpustate->irq_state = state;
/* if the IF is set, signal an interrupt */
if (state != CLEAR_LINE && I.IF)
PREFIX(_interrupt)(-1);
if (state != CLEAR_LINE && cpustate->IF)
PREFIX(_interrupt)(cpustate, -1);
}
}
/* PJB 03/05 */
static void set_test_line(int state)
static void set_test_line(i8086_state *cpustate, int state)
{
I.test_state = !state;
cpustate->test_state = !state;
}
static CPU_EXECUTE( i8086 )
{
i8086_state *cpustate = device->token;
cpustate->base[CS] = SegBase(CS);
cpustate->base[DS] = SegBase(DS);
cpustate->base[ES] = SegBase(ES);
cpustate->base[SS] = SegBase(SS);
/* copy over the cycle counts if they're not correct */
if (timing.id != 8086)
timing = i8086_cycles;
/* adjust for any interrupts that came in */
i8086_ICount = cycles;
i8086_ICount -= I.extra_cycles;
I.extra_cycles = 0;
cpustate->icount = cycles;
cpustate->icount -= cpustate->extra_cycles;
cpustate->extra_cycles = 0;
/* run until we're out */
while (i8086_ICount > 0)
while (cpustate->icount > 0)
{
LOG(("[%04x:%04x]=%02x\tF:%04x\tAX=%04x\tBX=%04x\tCX=%04x\tDX=%04x %d%d%d%d%d%d%d%d%d\n",
I.sregs[CS], I.pc - I.base[CS], ReadByte(I.pc), I.flags, I.regs.w[AX], I.regs.w[BX], I.regs.w[CX], I.regs.w[DX], I.AuxVal ? 1 : 0, I.OverVal ? 1 : 0,
I.SignVal ? 1 : 0, I.ZeroVal ? 1 : 0, I.CarryVal ? 1 : 0, I.ParityVal ? 1 : 0, I.TF, I.IF, I.DirVal < 0 ? 1 : 0));
debugger_instruction_hook(device, I.pc);
cpustate->sregs[CS], cpustate->pc - cpustate->base[CS], ReadByte(cpustate->pc), cpustate->flags, cpustate->regs.w[AX], cpustate->regs.w[BX], cpustate->regs.w[CX], cpustate->regs.w[DX], cpustate->AuxVal ? 1 : 0, cpustate->OverVal ? 1 : 0,
cpustate->SignVal ? 1 : 0, cpustate->ZeroVal ? 1 : 0, cpustate->CarryVal ? 1 : 0, cpustate->ParityVal ? 1 : 0, cpustate->TF, cpustate->IF, cpustate->DirVal < 0 ? 1 : 0));
debugger_instruction_hook(device, cpustate->pc);
seg_prefix = FALSE;
I.prevpc = I.pc;
cpustate->seg_prefix = FALSE;
cpustate->prevpc = cpustate->pc;
TABLE86;
}
/* adjust for any interrupts that came in */
i8086_ICount -= I.extra_cycles;
I.extra_cycles = 0;
cpustate->icount -= cpustate->extra_cycles;
cpustate->extra_cycles = 0;
return cycles - i8086_ICount;
return cycles - cpustate->icount;
}
@ -288,32 +284,39 @@ static CPU_DISASSEMBLE( i8086 )
static CPU_EXECUTE( i80186 )
{
i8086_state *cpustate = device->token;
cpustate->base[CS] = SegBase(CS);
cpustate->base[DS] = SegBase(DS);
cpustate->base[ES] = SegBase(ES);
cpustate->base[SS] = SegBase(SS);
/* copy over the cycle counts if they're not correct */
if (timing.id != 80186)
timing = i80186_cycles;
/* adjust for any interrupts that came in */
i8086_ICount = cycles;
i8086_ICount -= I.extra_cycles;
I.extra_cycles = 0;
cpustate->icount = cycles;
cpustate->icount -= cpustate->extra_cycles;
cpustate->extra_cycles = 0;
/* run until we're out */
while (i8086_ICount > 0)
while (cpustate->icount > 0)
{
LOG(("[%04x:%04x]=%02x\tAX=%04x\tBX=%04x\tCX=%04x\tDX=%04x\n", I.sregs[CS], I.pc, ReadByte(I.pc), I.regs.w[AX],
I.regs.w[BX], I.regs.w[CX], I.regs.w[DX]));
debugger_instruction_hook(device, I.pc);
LOG(("[%04x:%04x]=%02x\tAX=%04x\tBX=%04x\tCX=%04x\tDX=%04x\n", cpustate->sregs[CS], cpustate->pc, ReadByte(cpustate->pc), cpustate->regs.w[AX],
cpustate->regs.w[BX], cpustate->regs.w[CX], cpustate->regs.w[DX]));
debugger_instruction_hook(device, cpustate->pc);
seg_prefix = FALSE;
I.prevpc = I.pc;
cpustate->seg_prefix = FALSE;
cpustate->prevpc = cpustate->pc;
TABLE186;
}
/* adjust for any interrupts that came in */
i8086_ICount -= I.extra_cycles;
I.extra_cycles = 0;
cpustate->icount -= cpustate->extra_cycles;
cpustate->extra_cycles = 0;
return cycles - i8086_ICount;
return cycles - cpustate->icount;
}
#endif
@ -326,49 +329,51 @@ static CPU_EXECUTE( i80186 )
static CPU_SET_INFO( i8086 )
{
i8086_state *cpustate = device->token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(0, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_TEST: set_test_line(info->i); break; /* PJB 03/05 */
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(cpustate, 0, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_TEST: set_test_line(cpustate, info->i); break; /* PJB 03/05 */
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + I8086_PC:
if (info->i - I.base[CS] >= 0x10000)
if (info->i - cpustate->base[CS] >= 0x10000)
{
I.base[CS] = info->i & 0xffff0;
I.sregs[CS] = I.base[CS] >> 4;
cpustate->base[CS] = info->i & 0xffff0;
cpustate->sregs[CS] = cpustate->base[CS] >> 4;
}
I.pc = info->i;
cpustate->pc = info->i;
break;
case CPUINFO_INT_REGISTER + I8086_IP: I.pc = I.base[CS] + info->i; break;
case CPUINFO_INT_REGISTER + I8086_IP: cpustate->pc = cpustate->base[CS] + info->i; break;
case CPUINFO_INT_SP:
if (info->i - I.base[SS] < 0x10000)
if (info->i - cpustate->base[SS] < 0x10000)
{
I.regs.w[SP] = info->i - I.base[SS];
cpustate->regs.w[SP] = info->i - cpustate->base[SS];
}
else
{
I.base[SS] = info->i & 0xffff0;
I.sregs[SS] = I.base[SS] >> 4;
I.regs.w[SP] = info->i & 0x0000f;
cpustate->base[SS] = info->i & 0xffff0;
cpustate->sregs[SS] = cpustate->base[SS] >> 4;
cpustate->regs.w[SP] = info->i & 0x0000f;
}
break;
case CPUINFO_INT_REGISTER + I8086_SP: I.regs.w[SP] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_FLAGS: I.flags = info->i; ExpandFlags(info->i); break;
case CPUINFO_INT_REGISTER + I8086_AX: I.regs.w[AX] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_CX: I.regs.w[CX] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_DX: I.regs.w[DX] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_BX: I.regs.w[BX] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_BP: I.regs.w[BP] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_SI: I.regs.w[SI] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_DI: I.regs.w[DI] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_ES: I.sregs[ES] = info->i; I.base[ES] = SegBase(ES); break;
case CPUINFO_INT_REGISTER + I8086_CS: I.sregs[CS] = info->i; I.base[CS] = SegBase(CS); break;
case CPUINFO_INT_REGISTER + I8086_SS: I.sregs[SS] = info->i; I.base[SS] = SegBase(SS); break;
case CPUINFO_INT_REGISTER + I8086_DS: I.sregs[DS] = info->i; I.base[DS] = SegBase(DS); break;
case CPUINFO_INT_REGISTER + I8086_VECTOR: I.int_vector = info->i; break;
case CPUINFO_INT_REGISTER + I8086_SP: cpustate->regs.w[SP] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_FLAGS: cpustate->flags = info->i; ExpandFlags(info->i); break;
case CPUINFO_INT_REGISTER + I8086_AX: cpustate->regs.w[AX] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_CX: cpustate->regs.w[CX] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_DX: cpustate->regs.w[DX] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_BX: cpustate->regs.w[BX] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_BP: cpustate->regs.w[BP] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_SI: cpustate->regs.w[SI] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_DI: cpustate->regs.w[DI] = info->i; break;
case CPUINFO_INT_REGISTER + I8086_ES: cpustate->sregs[ES] = info->i; cpustate->base[ES] = SegBase(ES); break;
case CPUINFO_INT_REGISTER + I8086_CS: cpustate->sregs[CS] = info->i; cpustate->base[CS] = SegBase(CS); break;
case CPUINFO_INT_REGISTER + I8086_SS: cpustate->sregs[SS] = info->i; cpustate->base[SS] = SegBase(SS); break;
case CPUINFO_INT_REGISTER + I8086_DS: cpustate->sregs[DS] = info->i; cpustate->base[DS] = SegBase(DS); break;
case CPUINFO_INT_REGISTER + I8086_VECTOR: cpustate->int_vector = info->i; break;
}
}
@ -380,10 +385,12 @@ static CPU_SET_INFO( i8086 )
CPU_GET_INFO( i8086 )
{
i8086_state *cpustate = (device != NULL) ? device->token : NULL;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(I); break;
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i8086_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
@ -404,88 +411,88 @@ CPU_GET_INFO( i8086 )
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + 0: info->i = I.irq_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = I.nmi_state; break;
case CPUINFO_INT_INPUT_STATE + 0: info->i = cpustate->irq_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_TEST: info->i = I.test_state; break; /* PJB 03/05 */
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_TEST: info->i = cpustate->test_state; break; /* PJB 03/05 */
case CPUINFO_INT_PREVIOUSPC: info->i = I.prevpc; break;
case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->prevpc; break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + I8086_PC: info->i = I.pc; break;
case CPUINFO_INT_REGISTER + I8086_IP: info->i = I.pc - I.base[CS]; break;
case CPUINFO_INT_SP: info->i = I.base[SS] + I.regs.w[SP]; break;
case CPUINFO_INT_REGISTER + I8086_SP: info->i = I.regs.w[SP]; break;
case CPUINFO_INT_REGISTER + I8086_FLAGS: I.flags = CompressFlags(); info->i = I.flags; break;
case CPUINFO_INT_REGISTER + I8086_AX: info->i = I.regs.w[AX]; break;
case CPUINFO_INT_REGISTER + I8086_CX: info->i = I.regs.w[CX]; break;
case CPUINFO_INT_REGISTER + I8086_DX: info->i = I.regs.w[DX]; break;
case CPUINFO_INT_REGISTER + I8086_BX: info->i = I.regs.w[BX]; break;
case CPUINFO_INT_REGISTER + I8086_BP: info->i = I.regs.w[BP]; break;
case CPUINFO_INT_REGISTER + I8086_SI: info->i = I.regs.w[SI]; break;
case CPUINFO_INT_REGISTER + I8086_DI: info->i = I.regs.w[DI]; break;
case CPUINFO_INT_REGISTER + I8086_ES: info->i = I.sregs[ES]; break;
case CPUINFO_INT_REGISTER + I8086_CS: info->i = I.sregs[CS]; break;
case CPUINFO_INT_REGISTER + I8086_SS: info->i = I.sregs[SS]; break;
case CPUINFO_INT_REGISTER + I8086_DS: info->i = I.sregs[DS]; break;
case CPUINFO_INT_REGISTER + I8086_VECTOR: info->i = I.int_vector; break;
case CPUINFO_INT_REGISTER + I8086_PC: info->i = cpustate->pc; break;
case CPUINFO_INT_REGISTER + I8086_IP: info->i = cpustate->pc - cpustate->base[CS]; break;
case CPUINFO_INT_SP: info->i = cpustate->base[SS] + cpustate->regs.w[SP]; break;
case CPUINFO_INT_REGISTER + I8086_SP: info->i = cpustate->regs.w[SP]; break;
case CPUINFO_INT_REGISTER + I8086_FLAGS: cpustate->flags = CompressFlags(); info->i = cpustate->flags; break;
case CPUINFO_INT_REGISTER + I8086_AX: info->i = cpustate->regs.w[AX]; break;
case CPUINFO_INT_REGISTER + I8086_CX: info->i = cpustate->regs.w[CX]; break;
case CPUINFO_INT_REGISTER + I8086_DX: info->i = cpustate->regs.w[DX]; break;
case CPUINFO_INT_REGISTER + I8086_BX: info->i = cpustate->regs.w[BX]; break;
case CPUINFO_INT_REGISTER + I8086_BP: info->i = cpustate->regs.w[BP]; break;
case CPUINFO_INT_REGISTER + I8086_SI: info->i = cpustate->regs.w[SI]; break;
case CPUINFO_INT_REGISTER + I8086_DI: info->i = cpustate->regs.w[DI]; break;
case CPUINFO_INT_REGISTER + I8086_ES: info->i = cpustate->sregs[ES]; break;
case CPUINFO_INT_REGISTER + I8086_CS: info->i = cpustate->sregs[CS]; break;
case CPUINFO_INT_REGISTER + I8086_SS: info->i = cpustate->sregs[SS]; break;
case CPUINFO_INT_REGISTER + I8086_DS: info->i = cpustate->sregs[DS]; break;
case CPUINFO_INT_REGISTER + I8086_VECTOR: info->i = cpustate->int_vector; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i8086); break;
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(i8086); break;
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(i8086); break;
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break;
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break;
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(i8086); break;
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(i8086); break;
case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(i8086); break;
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(i8086); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i8086); break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &i8086_ICount; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "8086"); break;
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Intel 80x86"); break;
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.4"); break;
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Real mode i286 emulator v1.4 by Fabrice Frances\n(initial work I.based on David Hedley's pcemu)"); break;
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Real mode i286 emulator v1.4 by Fabrice Frances\n(initial work cpustate->based on David Hedley's pcemu)"); break;
case CPUINFO_STR_FLAGS:
I.flags = CompressFlags();
cpustate->flags = CompressFlags();
sprintf(info->s, "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c",
I.flags & 0x8000 ? '?' : '.',
I.flags & 0x4000 ? '?' : '.',
I.flags & 0x2000 ? '?' : '.',
I.flags & 0x1000 ? '?' : '.',
I.flags & 0x0800 ? 'O' : '.',
I.flags & 0x0400 ? 'D' : '.',
I.flags & 0x0200 ? 'I' : '.',
I.flags & 0x0100 ? 'T' : '.',
I.flags & 0x0080 ? 'S' : '.',
I.flags & 0x0040 ? 'Z' : '.',
I.flags & 0x0020 ? '?' : '.',
I.flags & 0x0010 ? 'A' : '.',
I.flags & 0x0008 ? '?' : '.',
I.flags & 0x0004 ? 'P' : '.',
I.flags & 0x0002 ? 'N' : '.',
I.flags & 0x0001 ? 'C' : '.');
cpustate->flags & 0x8000 ? '?' : '.',
cpustate->flags & 0x4000 ? '?' : '.',
cpustate->flags & 0x2000 ? '?' : '.',
cpustate->flags & 0x1000 ? '?' : '.',
cpustate->flags & 0x0800 ? 'O' : '.',
cpustate->flags & 0x0400 ? 'D' : '.',
cpustate->flags & 0x0200 ? 'I' : '.',
cpustate->flags & 0x0100 ? 'T' : '.',
cpustate->flags & 0x0080 ? 'S' : '.',
cpustate->flags & 0x0040 ? 'Z' : '.',
cpustate->flags & 0x0020 ? '?' : '.',
cpustate->flags & 0x0010 ? 'A' : '.',
cpustate->flags & 0x0008 ? '?' : '.',
cpustate->flags & 0x0004 ? 'P' : '.',
cpustate->flags & 0x0002 ? 'N' : '.',
cpustate->flags & 0x0001 ? 'C' : '.');
break;
case CPUINFO_STR_REGISTER + I8086_PC: sprintf(info->s, "PC:%04X", I.pc); break;
case CPUINFO_STR_REGISTER + I8086_IP: sprintf(info->s, "IP: %04X", I.pc - I.base[CS]); break;
case CPUINFO_STR_REGISTER + I8086_SP: sprintf(info->s, "SP: %04X", I.regs.w[SP]); break;
case CPUINFO_STR_REGISTER + I8086_FLAGS: sprintf(info->s, "F:%04X", I.flags); break;
case CPUINFO_STR_REGISTER + I8086_AX: sprintf(info->s, "AX:%04X", I.regs.w[AX]); break;
case CPUINFO_STR_REGISTER + I8086_CX: sprintf(info->s, "CX:%04X", I.regs.w[CX]); break;
case CPUINFO_STR_REGISTER + I8086_DX: sprintf(info->s, "DX:%04X", I.regs.w[DX]); break;
case CPUINFO_STR_REGISTER + I8086_BX: sprintf(info->s, "BX:%04X", I.regs.w[BX]); break;
case CPUINFO_STR_REGISTER + I8086_BP: sprintf(info->s, "BP:%04X", I.regs.w[BP]); break;
case CPUINFO_STR_REGISTER + I8086_SI: sprintf(info->s, "SI: %04X", I.regs.w[SI]); break;
case CPUINFO_STR_REGISTER + I8086_DI: sprintf(info->s, "DI: %04X", I.regs.w[DI]); break;
case CPUINFO_STR_REGISTER + I8086_ES: sprintf(info->s, "ES:%04X", I.sregs[ES]); break;
case CPUINFO_STR_REGISTER + I8086_CS: sprintf(info->s, "CS:%04X", I.sregs[CS]); break;
case CPUINFO_STR_REGISTER + I8086_SS: sprintf(info->s, "SS:%04X", I.sregs[SS]); break;
case CPUINFO_STR_REGISTER + I8086_DS: sprintf(info->s, "DS:%04X", I.sregs[DS]); break;
case CPUINFO_STR_REGISTER + I8086_VECTOR: sprintf(info->s, "V:%02X", I.int_vector); break;
case CPUINFO_STR_REGISTER + I8086_PC: sprintf(info->s, "PC:%04X", cpustate->pc); break;
case CPUINFO_STR_REGISTER + I8086_IP: sprintf(info->s, "IP: %04X", cpustate->pc - cpustate->base[CS]); break;
case CPUINFO_STR_REGISTER + I8086_SP: sprintf(info->s, "SP: %04X", cpustate->regs.w[SP]); break;
case CPUINFO_STR_REGISTER + I8086_FLAGS: sprintf(info->s, "F:%04X", cpustate->flags); break;
case CPUINFO_STR_REGISTER + I8086_AX: sprintf(info->s, "AX:%04X", cpustate->regs.w[AX]); break;
case CPUINFO_STR_REGISTER + I8086_CX: sprintf(info->s, "CX:%04X", cpustate->regs.w[CX]); break;
case CPUINFO_STR_REGISTER + I8086_DX: sprintf(info->s, "DX:%04X", cpustate->regs.w[DX]); break;
case CPUINFO_STR_REGISTER + I8086_BX: sprintf(info->s, "BX:%04X", cpustate->regs.w[BX]); break;
case CPUINFO_STR_REGISTER + I8086_BP: sprintf(info->s, "BP:%04X", cpustate->regs.w[BP]); break;
case CPUINFO_STR_REGISTER + I8086_SI: sprintf(info->s, "SI: %04X", cpustate->regs.w[SI]); break;
case CPUINFO_STR_REGISTER + I8086_DI: sprintf(info->s, "DI: %04X", cpustate->regs.w[DI]); break;
case CPUINFO_STR_REGISTER + I8086_ES: sprintf(info->s, "ES:%04X", cpustate->sregs[ES]); break;
case CPUINFO_STR_REGISTER + I8086_CS: sprintf(info->s, "CS:%04X", cpustate->sregs[CS]); break;
case CPUINFO_STR_REGISTER + I8086_SS: sprintf(info->s, "SS:%04X", cpustate->sregs[SS]); break;
case CPUINFO_STR_REGISTER + I8086_DS: sprintf(info->s, "DS:%04X", cpustate->sregs[DS]); break;
case CPUINFO_STR_REGISTER + I8086_VECTOR: sprintf(info->s, "V:%02X", cpustate->int_vector); break;
}
}

110
src/emu/cpu/i86/i86.h
View File

@ -27,24 +27,24 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
/* parameter x = result, y = source 1, z = source 2 */
#define SetTF(x) (I.TF = (x))
#define SetIF(x) (I.IF = (x))
#define SetDF(x) (I.DirVal = (x) ? -1 : 1)
#define SetTF(x) (cpustate->TF = (x))
#define SetIF(x) (cpustate->IF = (x))
#define SetDF(x) (cpustate->DirVal = (x) ? -1 : 1)
#define SetOFW_Add(x,y,z) (I.OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x8000)
#define SetOFB_Add(x,y,z) (I.OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x80)
#define SetOFW_Sub(x,y,z) (I.OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x8000)
#define SetOFB_Sub(x,y,z) (I.OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x80)
#define SetOFW_Add(x,y,z) (cpustate->OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x8000)
#define SetOFB_Add(x,y,z) (cpustate->OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x80)
#define SetOFW_Sub(x,y,z) (cpustate->OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x8000)
#define SetOFB_Sub(x,y,z) (cpustate->OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x80)
#define SetCFB(x) (I.CarryVal = (x) & 0x100)
#define SetCFW(x) (I.CarryVal = (x) & 0x10000)
#define SetAF(x,y,z) (I.AuxVal = ((x) ^ ((y) ^ (z))) & 0x10)
#define SetSF(x) (I.SignVal = (x))
#define SetZF(x) (I.ZeroVal = (x))
#define SetPF(x) (I.ParityVal = (x))
#define SetCFB(x) (cpustate->CarryVal = (x) & 0x100)
#define SetCFW(x) (cpustate->CarryVal = (x) & 0x10000)
#define SetAF(x,y,z) (cpustate->AuxVal = ((x) ^ ((y) ^ (z))) & 0x10)
#define SetSF(x) (cpustate->SignVal = (x))
#define SetZF(x) (cpustate->ZeroVal = (x))
#define SetPF(x) (cpustate->ParityVal = (x))
#define SetSZPF_Byte(x) (I.ParityVal = I.SignVal = I.ZeroVal = (INT8)(x))
#define SetSZPF_Word(x) (I.ParityVal = I.SignVal = I.ZeroVal = (INT16)(x))
#define SetSZPF_Byte(x) (cpustate->ParityVal = cpustate->SignVal = cpustate->ZeroVal = (INT8)(x))
#define SetSZPF_Word(x) (cpustate->ParityVal = cpustate->SignVal = cpustate->ZeroVal = (INT16)(x))
#define ADDB(dst,src) { unsigned res=dst+src; SetCFB(res); SetOFB_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; }
#define ADDW(dst,src) { unsigned res=dst+src; SetCFW(res); SetOFW_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; }
@ -52,40 +52,40 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
#define SUBB(dst,src) { unsigned res=dst-src; SetCFB(res); SetOFB_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(BYTE)res; }
#define SUBW(dst,src) { unsigned res=dst-src; SetCFW(res); SetOFW_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(WORD)res; }
#define ORB(dst,src) dst |= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Byte(dst)
#define ORW(dst,src) dst |= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Word(dst)
#define ORB(dst,src) dst |= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Byte(dst)
#define ORW(dst,src) dst |= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Word(dst)
#define ANDB(dst,src) dst &= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Byte(dst)
#define ANDW(dst,src) dst &= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Word(dst)
#define ANDB(dst,src) dst &= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Byte(dst)
#define ANDW(dst,src) dst &= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Word(dst)
#define XORB(dst,src) dst ^= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Byte(dst)
#define XORW(dst,src) dst ^= src; I.CarryVal = I.OverVal = I.AuxVal = 0; SetSZPF_Word(dst)
#define XORB(dst,src) dst ^= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Byte(dst)
#define XORW(dst,src) dst ^= src; cpustate->CarryVal = cpustate->OverVal = cpustate->AuxVal = 0; SetSZPF_Word(dst)
#define CF (I.CarryVal != 0)
#define SF (I.SignVal < 0)
#define ZF (I.ZeroVal == 0)
#define PF parity_table[I.ParityVal]
#define AF (I.AuxVal != 0)
#define OF (I.OverVal != 0)
#define DF (I.DirVal < 0)
#define CF (cpustate->CarryVal != 0)
#define SF (cpustate->SignVal < 0)
#define ZF (cpustate->ZeroVal == 0)
#define PF parity_table[cpustate->ParityVal]
#define AF (cpustate->AuxVal != 0)
#define OF (cpustate->OverVal != 0)
#define DF (cpustate->DirVal < 0)
/************************************************************************/
#define read_byte(a) (*I.mem.rbyte)(I.program, a)
#define read_word(a) (*I.mem.rword)(I.program, a)
#define write_byte(a,d) (*I.mem.wbyte)(I.program, (a),(d))
#define write_word(a,d) (*I.mem.wword)(I.program, (a),(d))
#define read_byte(a) (*cpustate->mem.rbyte)(cpustate->program, a)
#define read_word(a) (*cpustate->mem.rword)(cpustate->program, a)
#define write_byte(a,d) (*cpustate->mem.wbyte)(cpustate->program, (a),(d))
#define write_word(a,d) (*cpustate->mem.wword)(cpustate->program, (a),(d))
#define read_port_byte(a) (*I.mem.rbyte)(I.io, a)
#define read_port_word(a) (*I.mem.rword)(I.io, a)
#define write_port_byte(a,d) (*I.mem.wbyte)(I.io, (a),(d))
#define write_port_word(a,d) (*I.mem.wword)(I.io, (a),(d))
#define read_port_byte(a) (*cpustate->mem.rbyte)(cpustate->io, a)
#define read_port_word(a) (*cpustate->mem.rword)(cpustate->io, a)
#define write_port_byte(a,d) (*cpustate->mem.wbyte)(cpustate->io, (a),(d))
#define write_port_word(a,d) (*cpustate->mem.wword)(cpustate->io, (a),(d))
/************************************************************************/
#define SegBase(Seg) (I.sregs[Seg] << 4)
#define SegBase(Seg) (cpustate->sregs[Seg] << 4)
#define DefaultBase(Seg) ((seg_prefix && (Seg == DS || Seg == SS)) ? prefix_base : I.base[Seg])
#define DefaultBase(Seg) ((cpustate->seg_prefix && (Seg == DS || Seg == SS)) ? cpustate->prefix_base : cpustate->base[Seg])
#define GetMemB(Seg,Off) (read_byte((DefaultBase(Seg) + (Off)) & AMASK))
#define GetMemW(Seg,Off) (read_word((DefaultBase(Seg) + (Off)) & AMASK))
@ -98,32 +98,32 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
#define WriteByte(ea,val) write_byte((ea) & AMASK, val);
#define WriteWord(ea,val) write_word((ea) & AMASK, val);
#define FETCH_XOR(a) ((a) ^ I.mem.fetch_xor)
#define FETCH (memory_raw_read_byte(I.program, FETCH_XOR(I.pc++)))
#define FETCHOP (memory_decrypted_read_byte(I.program, FETCH_XOR(I.pc++)))
#define PEEKOP(addr) (memory_decrypted_read_byte(I.program, FETCH_XOR(addr)))
#define FETCHWORD(var) { var = memory_raw_read_byte(I.program, FETCH_XOR(I.pc)); var += (memory_raw_read_byte(I.program, FETCH_XOR(I.pc + 1)) << 8); I.pc += 2; }
#define FETCH_XOR(a) ((a) ^ cpustate->mem.fetch_xor)
#define FETCH (memory_raw_read_byte(cpustate->program, FETCH_XOR(cpustate->pc++)))
#define FETCHOP (memory_decrypted_read_byte(cpustate->program, FETCH_XOR(cpustate->pc++)))
#define PEEKOP(addr) (memory_decrypted_read_byte(cpustate->program, FETCH_XOR(addr)))
#define FETCHWORD(var) { var = memory_raw_read_byte(cpustate->program, FETCH_XOR(cpustate->pc)); var += (memory_raw_read_byte(cpustate->program, FETCH_XOR(cpustate->pc + 1)) << 8); cpustate->pc += 2; }
#define CHANGE_PC(addr)
#define PUSH(val) { I.regs.w[SP] -= 2; WriteWord(((I.base[SS] + I.regs.w[SP]) & AMASK), val); }
#define POP(var) { var = ReadWord(((I.base[SS] + I.regs.w[SP]) & AMASK)); I.regs.w[SP] += 2; }
#define PUSH(val) { cpustate->regs.w[SP] -= 2; WriteWord(((cpustate->base[SS] + cpustate->regs.w[SP]) & AMASK), val); }
#define POP(var) { var = ReadWord(((cpustate->base[SS] + cpustate->regs.w[SP]) & AMASK)); cpustate->regs.w[SP] += 2; }
/************************************************************************/
#define CompressFlags() (WORD)(CF | (PF << 2) | (AF << 4) | (ZF << 6) \
| (SF << 7) | (I.TF << 8) | (I.IF << 9) \
| (SF << 7) | (cpustate->TF << 8) | (cpustate->IF << 9) \
| (DF << 10) | (OF << 11))
#define ExpandFlags(f) \
{ \
I.CarryVal = (f) & 1; \
I.ParityVal = !((f) & 4); \
I.AuxVal = (f) & 16; \
I.ZeroVal = !((f) & 64); \
I.SignVal = ((f) & 128) ? -1 : 0; \
I.TF = ((f) & 256) >> 8; \
I.IF = ((f) & 512) >> 9; \
I.DirVal = ((f) & 1024) ? -1 : 1; \
I.OverVal = (f) & 2048; \
cpustate->CarryVal = (f) & 1; \
cpustate->ParityVal = !((f) & 4); \
cpustate->AuxVal = (f) & 16; \
cpustate->ZeroVal = !((f) & 64); \
cpustate->SignVal = ((f) & 128) ? -1 : 0; \
cpustate->TF = ((f) & 256) >> 8; \
cpustate->IF = ((f) & 512) >> 9; \
cpustate->DirVal = ((f) & 1024) ? -1 : 1; \
cpustate->OverVal = (f) & 2048; \
}
#endif /* __I86_H__ */

24
src/emu/cpu/i86/i86mem.c
View File

@ -4,14 +4,14 @@
#ifdef I8086
#if (HAS_I8088||HAS_I80188)
static void configure_memory_8bit(void)
static void configure_memory_8bit(i8086_state *cpustate)
{
I.mem.fetch_xor = 0;
cpustate->mem.fetch_xor = 0;
I.mem.rbyte = memory_read_byte_8le;
I.mem.rword = memory_read_word_8le;
I.mem.wbyte = memory_write_byte_8le;
I.mem.wword = memory_write_word_8le;
cpustate->mem.rbyte = memory_read_byte_8le;
cpustate->mem.rword = memory_read_word_8le;
cpustate->mem.wbyte = memory_write_byte_8le;
cpustate->mem.wword = memory_write_word_8le;
}
#endif
#endif
@ -43,12 +43,12 @@ static void write_word_16le(const address_space *space, offs_t addr, UINT16 data
}
}
static void configure_memory_16bit(void)
static void configure_memory_16bit(i8086_state *cpustate)
{
I.mem.fetch_xor = BYTE_XOR_LE(0);
cpustate->mem.fetch_xor = BYTE_XOR_LE(0);
I.mem.rbyte = memory_read_byte_16le;
I.mem.rword = read_word_16le;
I.mem.wbyte = memory_write_byte_16le;
I.mem.wword = write_word_16le;
cpustate->mem.rbyte = memory_read_byte_16le;
cpustate->mem.rword = read_word_16le;
cpustate->mem.wbyte = memory_write_byte_16le;
cpustate->mem.wword = write_word_16le;
}

104
src/emu/cpu/i86/instr186.c
View File

@ -9,53 +9,53 @@
#undef ICOUNT
#define ICOUNT i8086_ICount
#define ICOUNT cpustate->icount
static void PREFIX186(_pusha)(void) /* Opcode 0x60 */
static void PREFIX186(_pusha)(i8086_state *cpustate) /* Opcode 0x60 */
{
unsigned tmp=I.regs.w[SP];
unsigned tmp=cpustate->regs.w[SP];
ICOUNT -= timing.pusha;
PUSH(I.regs.w[AX]);
PUSH(I.regs.w[CX]);
PUSH(I.regs.w[DX]);
PUSH(I.regs.w[BX]);
PUSH(cpustate->regs.w[AX]);
PUSH(cpustate->regs.w[CX]);
PUSH(cpustate->regs.w[DX]);
PUSH(cpustate->regs.w[BX]);
PUSH(tmp);
PUSH(I.regs.w[BP]);
PUSH(I.regs.w[SI]);
PUSH(I.regs.w[DI]);
PUSH(cpustate->regs.w[BP]);
PUSH(cpustate->regs.w[SI]);
PUSH(cpustate->regs.w[DI]);
}
static void PREFIX186(_popa)(void) /* Opcode 0x61 */
static void PREFIX186(_popa)(i8086_state *cpustate) /* Opcode 0x61 */
{
unsigned tmp;
ICOUNT -= timing.popa;
POP(I.regs.w[DI]);
POP(I.regs.w[SI]);
POP(I.regs.w[BP]);
POP(cpustate->regs.w[DI]);
POP(cpustate->regs.w[SI]);
POP(cpustate->regs.w[BP]);
POP(tmp);
POP(I.regs.w[BX]);
POP(I.regs.w[DX]);
POP(I.regs.w[CX]);
POP(I.regs.w[AX]);
POP(cpustate->regs.w[BX]);
POP(cpustate->regs.w[DX]);
POP(cpustate->regs.w[CX]);
POP(cpustate->regs.w[AX]);
}
static void PREFIX186(_bound)(void) /* Opcode 0x62 */
static void PREFIX186(_bound)(i8086_state *cpustate) /* Opcode 0x62 */
{
unsigned ModRM = FETCHOP;
int low = (INT16)GetRMWord(ModRM);
int high= (INT16)GetnextRMWord;
int tmp= (INT16)RegWord(ModRM);
if (tmp<low || tmp>high) {
I.pc-=2;
PREFIX86(_interrupt)(5);
cpustate->pc-=2;
PREFIX86(_interrupt)(cpustate, 5);
}
ICOUNT -= timing.bound;
}
static void PREFIX186(_push_d16)(void) /* Opcode 0x68 */
static void PREFIX186(_push_d16)(i8086_state *cpustate) /* Opcode 0x68 */
{
unsigned tmp = FETCH;
@ -64,7 +64,7 @@ static void PREFIX186(_push_d16)(void) /* Opcode 0x68 */
PUSH(tmp);
}
static void PREFIX186(_imul_d16)(void) /* Opcode 0x69 */
static void PREFIX186(_imul_d16)(i8086_state *cpustate) /* Opcode 0x69 */
{
DEF_r16w(dst,src);
unsigned src2=FETCH;
@ -73,12 +73,12 @@ static void PREFIX186(_imul_d16)(void) /* Opcode 0x69 */
ICOUNT -= (ModRM >= 0xc0) ? timing.imul_rri16 : timing.imul_rmi16;
dst = (INT32)((INT16)src)*(INT32)((INT16)src2);
I.CarryVal = I.OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1);
cpustate->CarryVal = cpustate->OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1);
RegWord(ModRM)=(WORD)dst;
}
static void PREFIX186(_push_d8)(void) /* Opcode 0x6a */
static void PREFIX186(_push_d8)(i8086_state *cpustate) /* Opcode 0x6a */
{
unsigned tmp = (WORD)((INT16)((INT8)FETCH));
@ -86,7 +86,7 @@ static void PREFIX186(_push_d8)(void) /* Opcode 0x6a */
PUSH(tmp);
}
static void PREFIX186(_imul_d8)(void) /* Opcode 0x6b */
static void PREFIX186(_imul_d8)(i8086_state *cpustate) /* Opcode 0x6b */
{
DEF_r16w(dst,src);
unsigned src2= (WORD)((INT16)((INT8)FETCH));
@ -94,72 +94,72 @@ static void PREFIX186(_imul_d8)(void) /* Opcode 0x6b */
ICOUNT -= (ModRM >= 0xc0) ? timing.imul_rri8 : timing.imul_rmi8;
dst = (INT32)((INT16)src)*(INT32)((INT16)src2);
I.CarryVal = I.OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1);
cpustate->CarryVal = cpustate->OverVal = (((INT32)dst) >> 15 != 0) && (((INT32)dst) >> 15 != -1);
RegWord(ModRM)=(WORD)dst;
}
static void PREFIX186(_insb)(void) /* Opcode 0x6c */
static void PREFIX186(_insb)(i8086_state *cpustate) /* Opcode 0x6c */
{
ICOUNT -= timing.ins8;
PutMemB(ES,I.regs.w[DI],read_port_byte(I.regs.w[DX]));
I.regs.w[DI] += I.DirVal;
PutMemB(ES,cpustate->regs.w[DI],read_port_byte(cpustate->regs.w[DX]));
cpustate->regs.w[DI] += cpustate->DirVal;
}
static void PREFIX186(_insw)(void) /* Opcode 0x6d */
static void PREFIX186(_insw)(i8086_state *cpustate) /* Opcode 0x6d */
{
ICOUNT -= timing.ins16;
PutMemW(ES,I.regs.w[DI],read_port_word(I.regs.w[DX]));
I.regs.w[DI] += 2 * I.DirVal;
PutMemW(ES,cpustate->regs.w[DI],read_port_word(cpustate->regs.w[DX]));
cpustate->regs.w[DI] += 2 * cpustate->DirVal;
}
static void PREFIX186(_outsb)(void) /* Opcode 0x6e */
static void PREFIX186(_outsb)(i8086_state *cpustate) /* Opcode 0x6e */
{
ICOUNT -= timing.outs8;
write_port_byte(I.regs.w[DX],GetMemB(DS,I.regs.w[SI]));
I.regs.w[SI] += I.DirVal; /* GOL 11/27/01 */
write_port_byte(cpustate->regs.w[DX],GetMemB(DS,cpustate->regs.w[SI]));
cpustate->regs.w[SI] += cpustate->DirVal; /* GOL 11/27/01 */
}
static void PREFIX186(_outsw)(void) /* Opcode 0x6f */
static void PREFIX186(_outsw)(i8086_state *cpustate) /* Opcode 0x6f */
{
ICOUNT -= timing.outs16;
write_port_word(I.regs.w[DX],GetMemW(DS,I.regs.w[SI]));
I.regs.w[SI] += 2 * I.DirVal; /* GOL 11/27/01 */
write_port_word(cpustate->regs.w[DX],GetMemW(DS,cpustate->regs.w[SI]));
cpustate->regs.w[SI] += 2 * cpustate->DirVal; /* GOL 11/27/01 */
}
static void PREFIX186(_rotshft_bd8)(void) /* Opcode 0xc0 */
static void PREFIX186(_rotshft_bd8)(i8086_state *cpustate) /* Opcode 0xc0 */
{
unsigned ModRM = FETCH;
unsigned count = FETCH;
PREFIX86(_rotate_shift_Byte)(ModRM,count);
PREFIX86(_rotate_shift_Byte)(cpustate,ModRM,count);
}
static void PREFIX186(_rotshft_wd8)(void) /* Opcode 0xc1 */
static void PREFIX186(_rotshft_wd8)(i8086_state *cpustate) /* Opcode 0xc1 */
{
unsigned ModRM = FETCH;
unsigned count = FETCH;
PREFIX86(_rotate_shift_Word)(ModRM,count);
PREFIX86(_rotate_shift_Word)(cpustate,ModRM,count);
}
static void PREFIX186(_enter)(void) /* Opcode 0xc8 */
static void PREFIX186(_enter)(i8086_state *cpustate) /* Opcode 0xc8 */
{
unsigned nb = FETCH; unsigned i,level;
nb += FETCH << 8;
level = FETCH;
ICOUNT -= (level == 0) ? timing.enter0 : (level == 1) ? timing.enter1 : timing.enter_base + level * timing.enter_count;
PUSH(I.regs.w[BP]);
I.regs.w[BP]=I.regs.w[SP];
I.regs.w[SP] -= nb;
PUSH(cpustate->regs.w[BP]);
cpustate->regs.w[BP]=cpustate->regs.w[SP];
cpustate->regs.w[SP] -= nb;
for (i=1;i<level;i++)
PUSH(GetMemW(SS,I.regs.w[BP]-i*2));
if (level) PUSH(I.regs.w[BP]);
PUSH(GetMemW(SS,cpustate->regs.w[BP]-i*2));
if (level) PUSH(cpustate->regs.w[BP]);
}
static void PREFIX186(_leave)(void) /* Opcode 0xc9 */
static void PREFIX186(_leave)(i8086_state *cpustate) /* Opcode 0xc9 */
{
ICOUNT -= timing.leave;
I.regs.w[SP]=I.regs.w[BP];
POP(I.regs.w[BP]);
cpustate->regs.w[SP]=cpustate->regs.w[BP];
POP(cpustate->regs.w[BP]);
}

34
src/emu/cpu/i86/instr186.h
View File

@ -6,22 +6,22 @@
// file will be included in all cpu variants
// timing value should move to separate array
static void PREFIX186(_pusha)(void);
static void PREFIX186(_popa)(void);
static void PREFIX186(_bound)(void);
static void PREFIX186(_push_d16)(void);
static void PREFIX186(_imul_d16)(void);
static void PREFIX186(_push_d8)(void);
static void PREFIX186(_imul_d8)(void);
static void PREFIX186(_rotshft_bd8)(void);
static void PREFIX186(_rotshft_wd8)(void);
static void PREFIX186(_enter)(void);
static void PREFIX186(_leave)(void);
static void PREFIX186(_insb)(void);
static void PREFIX186(_insw)(void);
static void PREFIX186(_outsb)(void);
static void PREFIX186(_outsw)(void);
static void PREFIX186(_pusha)(i8086_state *cpustate);
static void PREFIX186(_popa)(i8086_state *cpustate);
static void PREFIX186(_bound)(i8086_state *cpustate);
static void PREFIX186(_push_d16)(i8086_state *cpustate);
static void PREFIX186(_imul_d16)(i8086_state *cpustate);
static void PREFIX186(_push_d8)(i8086_state *cpustate);
static void PREFIX186(_imul_d8)(i8086_state *cpustate);
static void PREFIX186(_rotshft_bd8)(i8086_state *cpustate);
static void PREFIX186(_rotshft_wd8)(i8086_state *cpustate);
static void PREFIX186(_enter)(i8086_state *cpustate);
static void PREFIX186(_leave)(i8086_state *cpustate);
static void PREFIX186(_insb)(i8086_state *cpustate);
static void PREFIX186(_insw)(i8086_state *cpustate);
static void PREFIX186(_outsb)(i8086_state *cpustate);
static void PREFIX186(_outsw)(i8086_state *cpustate);
/* changed instructions */
static void PREFIX186(_repne)(void);
static void PREFIX186(_repe)(void);
static void PREFIX186(_repne)(i8086_state *cpustate);
static void PREFIX186(_repe)(i8086_state *cpustate);

260
src/emu/cpu/i86/instr286.c
View File

@ -20,30 +20,30 @@
#define WRITEABLE(a) ((a&0xa)==2)
#define READABLE(a) ( ((a&0xa)==0xa)|| ((a&8)==0) )
static void i80286_trap2(int number)
static void i80286_trap2(i80286_state *cpustate,int number)
{
i80286_interrupt(number);
i80286_interrupt(cpustate,number);
}
static int i80286_selector_okay(UINT16 selector)
static int i80286_selector_okay(i80286_state *cpustate,UINT16 selector)
{
if (selector&4) {
return (selector&~7)<I.ldtr.limit;
return (selector&~7)<cpustate->ldtr.limit;
} else {
return (selector&~7)<I.gdtr.limit;
return (selector&~7)<cpustate->gdtr.limit;
}
}
static offs_t i80286_selector_to_address(UINT16 selector)
static offs_t i80286_selector_to_address(i80286_state *cpustate,UINT16 selector)
{
if (selector&4) {
return I.ldtr.base+(selector&~7);
return cpustate->ldtr.base+(selector&~7);
} else {
return I.gdtr.base+(selector&~7);
return cpustate->gdtr.base+(selector&~7);
}
}
static void i80286_data_descriptor(int reg, UINT16 selector)
static void i80286_data_descriptor(i80286_state *cpustate,int reg, UINT16 selector)
{
if (PM) {
UINT16 help;
@ -53,29 +53,29 @@ static void i80286_data_descriptor(int reg, UINT16 selector)
1,0: requested privileg level
must be higher or same as current privileg level in code selector */
if (selector&4) { /* local descriptor table */
if (selector>I.ldtr.limit) i80286_trap2(GENERAL_PROTECTION_FAULT);
I.sregs[reg]=selector;
I.limit[reg]=ReadWord(I.ldtr.base+(selector&~7));
I.base[reg]=ReadWord(I.ldtr.base+(selector&~7)+2)
|(ReadWord(I.ldtr.base+(selector&~7)+4)<<16);
I.rights[reg]=I.base[reg]>>24;
I.base[reg]&=0xffffff;
if (selector>cpustate->ldtr.limit) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
cpustate->sregs[reg]=selector;
cpustate->limit[reg]=ReadWord(cpustate->ldtr.base+(selector&~7));
cpustate->base[reg]=ReadWord(cpustate->ldtr.base+(selector&~7)+2)
|(ReadWord(cpustate->ldtr.base+(selector&~7)+4)<<16);
cpustate->rights[reg]=cpustate->base[reg]>>24;
cpustate->base[reg]&=0xffffff;
} else { /* global descriptor table */
if (!(selector&~7)||(selector>I.gdtr.limit)) i80286_trap2(GENERAL_PROTECTION_FAULT);
I.sregs[reg]=selector;
I.limit[reg]=ReadWord(I.gdtr.base+(selector&~7));
I.base[reg]=ReadWord(I.gdtr.base+(selector&~7)+2);
help=ReadWord(I.gdtr.base+(selector&~7)+4);
I.rights[reg]=help>>8;
I.base[reg]|=(help&0xff)<<16;
if (!(selector&~7)||(selector>cpustate->gdtr.limit)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
cpustate->sregs[reg]=selector;
cpustate->limit[reg]=ReadWord(cpustate->gdtr.base+(selector&~7));
cpustate->base[reg]=ReadWord(cpustate->gdtr.base+(selector&~7)+2);
help=ReadWord(cpustate->gdtr.base+(selector&~7)+4);
cpustate->rights[reg]=help>>8;
cpustate->base[reg]|=(help&0xff)<<16;
}
} else {
I.sregs[reg]=selector;
I.base[reg]=selector<<4;
cpustate->sregs[reg]=selector;
cpustate->base[reg]=selector<<4;
}
}
static void i80286_code_descriptor(UINT16 selector, UINT16 offset)
static void i80286_code_descriptor(i80286_state *cpustate,UINT16 selector, UINT16 offset)
{
UINT16 word1, word2, word3;
if (PM) {
@ -85,82 +85,82 @@ static void i80286_code_descriptor(UINT16 selector, UINT16 offset)
1,0: requested privileg level
must be higher or same as current privileg level in code selector */
if (selector&4) { /* local descriptor table */
if (selector>I.ldtr.limit) i80286_trap2(GENERAL_PROTECTION_FAULT);
word1=ReadWord(I.ldtr.base+(selector&~7));
word2=ReadWord(I.ldtr.base+(selector&~7)+2);
word3=ReadWord(I.ldtr.base+(selector&~7)+4);
if (selector>cpustate->ldtr.limit) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
word1=ReadWord(cpustate->ldtr.base+(selector&~7));
word2=ReadWord(cpustate->ldtr.base+(selector&~7)+2);
word3=ReadWord(cpustate->ldtr.base+(selector&~7)+4);
} else { /* global descriptor table */
if (!(selector&~7)||(selector>I.gdtr.limit)) i80286_trap2(GENERAL_PROTECTION_FAULT);
word1=ReadWord(I.gdtr.base+(selector&~7));
word2=ReadWord(I.gdtr.base+(selector&~7)+2);
word3=ReadWord(I.gdtr.base+(selector&~7)+4);
if (!(selector&~7)||(selector>cpustate->gdtr.limit)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
word1=ReadWord(cpustate->gdtr.base+(selector&~7));
word2=ReadWord(cpustate->gdtr.base+(selector&~7)+2);
word3=ReadWord(cpustate->gdtr.base+(selector&~7)+4);
}
if (word3&0x1000) {
I.sregs[CS]=selector;
I.limit[CS]=word1;
I.base[CS]=word2|((word3&0xff)<<16);
I.rights[CS]=word3>>8;
I.pc=I.base[CS]+offset;
cpustate->sregs[CS]=selector;
cpustate->limit[CS]=word1;
cpustate->base[CS]=word2|((word3&0xff)<<16);
cpustate->rights[CS]=word3>>8;
cpustate->pc=cpustate->base[CS]+offset;
} else { // systemdescriptor
switch (word3&0xf00) {
case 0x400: // call gate
// word3&0x1f words to be copied from stack to stack
i80286_data_descriptor(CS, word2);
I.pc=I.base[CS]+word1;
i80286_data_descriptor(cpustate, CS, word2);
cpustate->pc=cpustate->base[CS]+word1;
break;
case 0x500: // task gate
i80286_data_descriptor(CS, word2);
I.pc=I.base[CS]+word1;
i80286_data_descriptor(cpustate, CS, word2);
cpustate->pc=cpustate->base[CS]+word1;
break;
case 0x600: // interrupt gate
I.TF = I.IF = 0;
i80286_data_descriptor(CS, word2);
I.pc=I.base[CS]+word1;
cpustate->TF = cpustate->IF = 0;
i80286_data_descriptor(cpustate, CS, word2);
cpustate->pc=cpustate->base[CS]+word1;
break;
case 0x700: // trap gate
i80286_data_descriptor(CS, word2);
I.pc=I.base[CS]+word1;
i80286_data_descriptor(cpustate, CS, word2);
cpustate->pc=cpustate->base[CS]+word1;
break;
}
}
} else {
I.sregs[CS]=selector;
I.base[CS]=selector<<4;
I.pc=I.base[CS]+offset;
cpustate->sregs[CS]=selector;
cpustate->base[CS]=selector<<4;
cpustate->pc=cpustate->base[CS]+offset;
}
}
static void i80286_interrupt_descriptor(UINT16 number)
static void i80286_interrupt_descriptor(i80286_state *cpustate,UINT16 number)
{
UINT16 word1,word2,word3;
if ((number<<3)>=I.idtr.limit) {
if ((number<<3)>=cpustate->idtr.limit) {
;// go into shutdown mode
return;
}
PREFIX(_pushf());
PUSH(I.sregs[CS]);
PUSH(I.pc - I.base[CS]);
word1=ReadWord(I.idtr.base+(number<<3));
word2=ReadWord(I.idtr.base+(number<<3)+2);
word3=ReadWord(I.idtr.base+(number<<3)+4);
PREFIX(_pushf(cpustate));
PUSH(cpustate->sregs[CS]);
PUSH(cpustate->pc - cpustate->base[CS]);
word1=ReadWord(cpustate->idtr.base+(number<<3));
word2=ReadWord(cpustate->idtr.base+(number<<3)+2);
word3=ReadWord(cpustate->idtr.base+(number<<3)+4);
switch (word3&0xf00) {
case 0x500: // task gate
i80286_data_descriptor(CS, word2);
I.pc=I.base[CS]+word1;
i80286_data_descriptor(cpustate, CS, word2);
cpustate->pc=cpustate->base[CS]+word1;
break;
case 0x600: // interrupt gate
I.TF = I.IF = 0;
i80286_data_descriptor(CS, word2);
I.pc=I.base[CS]+word1;
cpustate->TF = cpustate->IF = 0;
i80286_data_descriptor(cpustate, CS, word2);
cpustate->pc=cpustate->base[CS]+word1;
break;
case 0x700: // trap gate
i80286_data_descriptor(CS, word2);
I.pc=I.base[CS]+word1;
i80286_data_descriptor(cpustate, CS, word2);
cpustate->pc=cpustate->base[CS]+word1;
break;
}
}
static void PREFIX286(_0fpre)(void)
static void PREFIX286(_0fpre)(i8086_state *cpustate)
{
unsigned next = FETCHOP;
UINT16 ModRM;
@ -172,59 +172,59 @@ static void PREFIX286(_0fpre)(void)
ModRM=FETCHOP;
switch (ModRM&0x38) {
case 0: /* sldt */
if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
PutRMWord(ModRM, I.ldtr.sel);
if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
PutRMWord(ModRM, cpustate->ldtr.sel);
break;
case 8: /* str */
if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
PutRMWord(ModRM, I.tr.sel);
if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
PutRMWord(ModRM, cpustate->tr.sel);
break;
case 0x10: /* lldt */
if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
if (PM&&(CPL!=0)) i80286_trap2(GENERAL_PROTECTION_FAULT);
I.ldtr.sel=GetRMWord(ModRM);
if ((I.ldtr.sel&~7)>=I.gdtr.limit) i80286_trap2(GENERAL_PROTECTION_FAULT);
I.ldtr.limit=ReadWord(I.gdtr.base+(I.ldtr.sel&~7));
I.ldtr.base=ReadWord(I.gdtr.base+(I.ldtr.sel&~7)+2)
|(ReadWord(I.gdtr.base+(I.ldtr.sel&~7)+4)<<16);
I.ldtr.rights=I.ldtr.base>>24;
I.ldtr.base&=0xffffff;
if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
cpustate->ldtr.sel=GetRMWord(ModRM);
if ((cpustate->ldtr.sel&~7)>=cpustate->gdtr.limit) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
cpustate->ldtr.limit=ReadWord(cpustate->gdtr.base+(cpustate->ldtr.sel&~7));
cpustate->ldtr.base=ReadWord(cpustate->gdtr.base+(cpustate->ldtr.sel&~7)+2)
|(ReadWord(cpustate->gdtr.base+(cpustate->ldtr.sel&~7)+4)<<16);
cpustate->ldtr.rights=cpustate->ldtr.base>>24;
cpustate->ldtr.base&=0xffffff;
break;
case 0x18: /* ltr */
if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
if (CPL!=0) i80286_trap2(GENERAL_PROTECTION_FAULT);
I.tr.sel=GetRMWord(ModRM);
if ((I.tr.sel&~7)>=I.gdtr.limit) i80286_trap2(GENERAL_PROTECTION_FAULT);
I.tr.limit=ReadWord(I.gdtr.base+(I.tr.sel&~7));
I.tr.base=ReadWord(I.gdtr.base+(I.tr.sel&~7)+2)
|(ReadWord(I.gdtr.base+(I.tr.sel&~7)+4)<<16);
I.tr.rights=I.tr.base>>24;
I.tr.base&=0xffffff;
if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
if (CPL!=0) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
cpustate->tr.sel=GetRMWord(ModRM);
if ((cpustate->tr.sel&~7)>=cpustate->gdtr.limit) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
cpustate->tr.limit=ReadWord(cpustate->gdtr.base+(cpustate->tr.sel&~7));
cpustate->tr.base=ReadWord(cpustate->gdtr.base+(cpustate->tr.sel&~7)+2)
|(ReadWord(cpustate->gdtr.base+(cpustate->tr.sel&~7)+4)<<16);
cpustate->tr.rights=cpustate->tr.base>>24;
cpustate->tr.base&=0xffffff;
break;
case 0x20: /* verr */
if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
tmp=GetRMWord(ModRM);
if (tmp&4) {
I.ZeroVal=( ((tmp&~7)<I.ldtr.limit)
&& READABLE( ReadByte(I.ldtr.base+(tmp&~7)+5)) );
cpustate->ZeroVal=( ((tmp&~7)<cpustate->ldtr.limit)
&& READABLE( ReadByte(cpustate->ldtr.base+(tmp&~7)+5)) );
} else {
I.ZeroVal=( ((tmp&~7)<I.gdtr.limit)
&& READABLE( ReadByte(I.gdtr.base+(tmp&~7)+5)) );
cpustate->ZeroVal=( ((tmp&~7)<cpustate->gdtr.limit)
&& READABLE( ReadByte(cpustate->gdtr.base+(tmp&~7)+5)) );
}
break;
case 0x28: /* verw */
if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
tmp=GetRMWord(ModRM);
if (tmp&4) {
I.ZeroVal=( ((tmp&~7)<I.ldtr.limit)
&& WRITEABLE( ReadByte(I.ldtr.base+(tmp&~7)+5)) );
cpustate->ZeroVal=( ((tmp&~7)<cpustate->ldtr.limit)
&& WRITEABLE( ReadByte(cpustate->ldtr.base+(tmp&~7)+5)) );
} else {
I.ZeroVal=( ((tmp&~7)<I.gdtr.limit)
&& WRITEABLE( ReadByte(I.gdtr.base+(tmp&~7)+5)) );
cpustate->ZeroVal=( ((tmp&~7)<cpustate->gdtr.limit)
&& WRITEABLE( ReadByte(cpustate->gdtr.base+(tmp&~7)+5)) );
}
break;
default:
i80286_trap2(ILLEGAL_INSTRUCTION);
i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
break;
}
break;
@ -234,75 +234,75 @@ static void PREFIX286(_0fpre)(void)
ModRM = FETCHOP;
switch (ModRM&0x38) {
case 0: /* sgdt */
PutRMWord(ModRM,I.gdtr.limit);
PutRMWordOffset(2,I.gdtr.base&0xffff);
PutRMByteOffset(4,I.gdtr.base>>16);
PutRMWord(ModRM,cpustate->gdtr.limit);
PutRMWordOffset(2,cpustate->gdtr.base&0xffff);
PutRMByteOffset(4,cpustate->gdtr.base>>16);
break;
case 8: /* sidt */
PutRMWord(ModRM,I.idtr.limit);
PutRMWordOffset(2,I.idtr.base&0xffff);
PutRMByteOffset(4,I.idtr.base>>16);
PutRMWord(ModRM,cpustate->idtr.limit);
PutRMWordOffset(2,cpustate->idtr.base&0xffff);
PutRMByteOffset(4,cpustate->idtr.base>>16);
break;
case 0x10: /* lgdt */
if (PM&&(CPL!=0)) i80286_trap2(GENERAL_PROTECTION_FAULT);
I.gdtr.limit=GetRMWord(ModRM);
I.gdtr.base=GetRMWordOffset(2)|(GetRMByteOffset(4)<<16);
if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
cpustate->gdtr.limit=GetRMWord(ModRM);
cpustate->gdtr.base=GetRMWordOffset(2)|(GetRMByteOffset(4)<<16);
break;
case 0x18: /* lidt */
if (PM&&(CPL!=0)) i80286_trap2(GENERAL_PROTECTION_FAULT);
I.idtr.limit=GetRMWord(ModRM);
I.idtr.base=GetRMWordOffset(2)|(GetRMByteOffset(4)<<16);
if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
cpustate->idtr.limit=GetRMWord(ModRM);
cpustate->idtr.base=GetRMWordOffset(2)|(GetRMByteOffset(4)<<16);
break;
case 0x20: /* smsw */
PutRMWord(ModRM, I.msw);
PutRMWord(ModRM, cpustate->msw);
break;
case 0x30: /* lmsw */
if (PM&&(CPL!=0)) i80286_trap2(GENERAL_PROTECTION_FAULT);
I.msw=(I.msw&1)|GetRMWord(ModRM);
if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
cpustate->msw=(cpustate->msw&1)|GetRMWord(ModRM);
break;
default:
i80286_trap2(ILLEGAL_INSTRUCTION);
i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
break;
}
break;
case 2: /* LAR */
ModRM = FETCHOP;
tmp=GetRMWord(ModRM);
I.ZeroVal=i80286_selector_okay(tmp);
if (I.ZeroVal) {
cpustate->ZeroVal=i80286_selector_okay(cpustate,tmp);
if (cpustate->ZeroVal) {
RegWord(ModRM)=tmp;
}
break;
case 3: /* LSL */
if (!PM) i80286_trap2(ILLEGAL_INSTRUCTION);
if (!PM) i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
ModRM = FETCHOP;
tmp=GetRMWord(ModRM);
I.ZeroVal=i80286_selector_okay(tmp);
if (I.ZeroVal) {
addr=i80286_selector_to_address(tmp);
cpustate->ZeroVal=i80286_selector_okay(cpustate,tmp);
if (cpustate->ZeroVal) {
addr=i80286_selector_to_address(cpustate,tmp);
RegWord(ModRM)=ReadWord(addr);
}
break;
case 6: /* clts */
if (PM&&(CPL!=0)) i80286_trap2(GENERAL_PROTECTION_FAULT);
I.msw=~8;
if (PM&&(CPL!=0)) i80286_trap2(cpustate,GENERAL_PROTECTION_FAULT);
cpustate->msw=~8;
break;
default:
i80286_trap2(ILLEGAL_INSTRUCTION);
i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
break;
}
}
static void PREFIX286(_arpl)(void) /* 0x63 */
static void PREFIX286(_arpl)(i8086_state *cpustate) /* 0x63 */
{
if (PM) {
UINT16 ModRM=FETCHOP, tmp=GetRMWord(ModRM);
I.ZeroVal=i80286_selector_okay(RegWord(ModRM))
&&i80286_selector_okay(RegWord(ModRM))
cpustate->ZeroVal=i80286_selector_okay(cpustate,RegWord(ModRM))
&&i80286_selector_okay(cpustate,RegWord(ModRM))
&&((tmp&3)<(RegWord(ModRM)&3));
if (I.ZeroVal) PutbackRMWord(ModRM, (tmp&~3)|(RegWord(ModRM)&3));
if (cpustate->ZeroVal) PutbackRMWord(ModRM, (tmp&~3)|(RegWord(ModRM)&3));
} else {
i80286_trap2(ILLEGAL_INSTRUCTION);
i80286_trap2(cpustate,ILLEGAL_INSTRUCTION);
}
}

18
src/emu/cpu/i86/instr286.h
View File

@ -1,13 +1,13 @@
#define ILLEGAL_INSTRUCTION 6
#define GENERAL_PROTECTION_FAULT 0xd
#define PM (I.msw&1)
#define CPL (I.sregs[CS]&3)
#define IOPL ((I.flags&0x3000)>>12)
#define PM (cpustate->msw&1)
#define CPL (cpustate->sregs[CS]&3)
#define IOPL ((cpustate->flags&0x3000)>>12)
static void i80286_trap2(int number);
static void i80286_interrupt_descriptor(UINT16 number);
static void i80286_code_descriptor(UINT16 selector, UINT16 offset);
static void i80286_data_descriptor(int reg, UINT16 selector);
static void PREFIX286(_0fpre)(void);
static void PREFIX286(_arpl)(void);
static void i80286_trap2(i80286_state *cpustate,int number);
static void i80286_interrupt_descriptor(i80286_state *cpustate,UINT16 number);
static void i80286_code_descriptor(i80286_state *cpustate,UINT16 selector, UINT16 offset);
static void i80286_data_descriptor(i80286_state *cpustate,int reg, UINT16 selector);
static void PREFIX286(_0fpre)(i80286_state *cpustate);
static void PREFIX286(_arpl)(i80286_state *cpustate);

1538
src/emu/cpu/i86/instr86.c
View File

File diff suppressed because it is too large Load Diff

454
src/emu/cpu/i86/instr86.h
View File

@ -13,232 +13,232 @@
// function renaming will be added when neccessary
// timing value should move to separate array
static void PREFIX86(_add_br8)(void);
static void PREFIX86(_add_wr16)(void);
static void PREFIX86(_add_r8b)(void);
static void PREFIX86(_add_r16w)(void);
static void PREFIX86(_add_ald8)(void);
static void PREFIX86(_add_axd16)(void);
static void PREFIX86(_push_es)(void);
static void PREFIX86(_pop_es)(void);
static void PREFIX86(_or_br8)(void);
static void PREFIX86(_or_r8b)(void);
static void PREFIX86(_or_wr16)(void);
static void PREFIX86(_or_r16w)(void);
static void PREFIX86(_or_ald8)(void);
static void PREFIX86(_or_axd16)(void);
static void PREFIX86(_push_cs)(void);
static void PREFIX86(_adc_br8)(void);
static void PREFIX86(_adc_wr16)(void);
static void PREFIX86(_adc_r8b)(void);
static void PREFIX86(_adc_r16w)(void);
static void PREFIX86(_adc_ald8)(void);
static void PREFIX86(_adc_axd16)(void);
static void PREFIX86(_push_ss)(void);
static void PREFIX86(_pop_ss)(void);
static void PREFIX86(_sbb_br8)(void);
static void PREFIX86(_sbb_wr16)(void);
static void PREFIX86(_sbb_r8b)(void);
static void PREFIX86(_sbb_r16w)(void);
static void PREFIX86(_sbb_ald8)(void);
static void PREFIX86(_sbb_axd16)(void);
static void PREFIX86(_push_ds)(void);
static void PREFIX86(_pop_ds)(void);
static void PREFIX86(_and_br8)(void);
static void PREFIX86(_and_r8b)(void);
static void PREFIX86(_and_wr16)(void);
static void PREFIX86(_and_r16w)(void);
static void PREFIX86(_and_ald8)(void);
static void PREFIX86(_and_axd16)(void);
static void PREFIX86(_es)(void);
static void PREFIX86(_daa)(void);
static void PREFIX86(_sub_br8)(void);
static void PREFIX86(_sub_wr16)(void);
static void PREFIX86(_sub_r8b)(void);
static void PREFIX86(_sub_r16w)(void);
static void PREFIX86(_sub_ald8)(void);
static void PREFIX86(_sub_axd16)(void);
static void PREFIX86(_cs)(void);
static void PREFIX86(_das)(void);
static void PREFIX86(_xor_br8)(void);
static void PREFIX86(_xor_r8b)(void);
static void PREFIX86(_xor_wr16)(void);
static void PREFIX86(_xor_r16w)(void);
static void PREFIX86(_xor_ald8)(void);
static void PREFIX86(_xor_axd16)(void);
static void PREFIX86(_ss)(void);
static void PREFIX86(_aaa)(void);
static void PREFIX86(_cmp_br8)(void);
static void PREFIX86(_cmp_wr16)(void);
static void PREFIX86(_cmp_r8b)(void);
static void PREFIX86(_cmp_r16w)(void);
static void PREFIX86(_cmp_ald8)(void);
static void PREFIX86(_cmp_axd16)(void);
static void PREFIX86(_ds)(void);
static void PREFIX86(_aas)(void);
static void PREFIX86(_inc_ax)(void);
static void PREFIX86(_inc_cx)(void);
static void PREFIX86(_inc_dx)(void);
static void PREFIX86(_inc_bx)(void);
static void PREFIX86(_inc_sp)(void);
static void PREFIX86(_inc_bp)(void);
static void PREFIX86(_inc_si)(void);
static void PREFIX86(_inc_di)(void);
static void PREFIX86(_dec_ax)(void);
static void PREFIX86(_dec_cx)(void);
static void PREFIX86(_dec_dx)(void);
static void PREFIX86(_dec_bx)(void);
static void PREFIX86(_dec_sp)(void);
static void PREFIX86(_dec_bp)(void);
static void PREFIX86(_dec_si)(void);
static void PREFIX86(_dec_di)(void);
static void PREFIX86(_push_ax)(void);
static void PREFIX86(_push_cx)(void);
static void PREFIX86(_push_dx)(void);
static void PREFIX86(_push_bx)(void);
static void PREFIX86(_push_sp)(void);
static void PREFIX86(_push_bp)(void);
static void PREFIX86(_push_si)(void);
static void PREFIX86(_push_di)(void);
static void PREFIX86(_pop_ax)(void);
static void PREFIX86(_pop_cx)(void);
static void PREFIX86(_pop_dx)(void);
static void PREFIX86(_pop_bx)(void);
static void PREFIX86(_pop_sp)(void);
static void PREFIX86(_pop_bp)(void);
static void PREFIX86(_pop_si)(void);
static void PREFIX86(_pop_di)(void);
static void PREFIX86(_jo)(void);
static void PREFIX86(_jno)(void);
static void PREFIX86(_jb)(void);
static void PREFIX86(_jnb)(void);
static void PREFIX86(_jz)(void);
static void PREFIX86(_jnz)(void);
static void PREFIX86(_jbe)(void);
static void PREFIX86(_jnbe)(void);
static void PREFIX86(_js)(void);
static void PREFIX86(_jns)(void);
static void PREFIX86(_jp)(void);
static void PREFIX86(_jnp)(void);
static void PREFIX86(_jl)(void);
static void PREFIX86(_jnl)(void);
static void PREFIX86(_jle)(void);
static void PREFIX86(_jnle)(void);
static void PREFIX86(_80pre)(void);
static void PREFIX86(_82pre)(void);
static void PREFIX86(_81pre)(void);
static void PREFIX86(_83pre)(void);
static void PREFIX86(_test_br8)(void);
static void PREFIX86(_test_wr16)(void);
static void PREFIX86(_xchg_br8)(void);
static void PREFIX86(_xchg_wr16)(void);
static void PREFIX86(_mov_br8)(void);
static void PREFIX86(_mov_r8b)(void);
static void PREFIX86(_mov_wr16)(void);
static void PREFIX86(_mov_r16w)(void);
static void PREFIX86(_mov_wsreg)(void);
static void PREFIX86(_lea)(void);
static void PREFIX86(_mov_sregw)(void);
static void PREFIX86(_invalid)(void);
static void PREFIX86(_popw)(void);
static void PREFIX86(_nop)(void);
static void PREFIX86(_xchg_axcx)(void);
static void PREFIX86(_xchg_axdx)(void);
static void PREFIX86(_xchg_axbx)(void);
static void PREFIX86(_xchg_axsp)(void);
static void PREFIX86(_xchg_axbp)(void);
static void PREFIX86(_xchg_axsi)(void);
static void PREFIX86(_xchg_axdi)(void);
static void PREFIX86(_cbw)(void);
static void PREFIX86(_cwd)(void);
static void PREFIX86(_call_far)(void);
static void PREFIX86(_pushf)(void);
static void PREFIX86(_popf)(void);
static void PREFIX86(_sahf)(void);
static void PREFIX86(_lahf)(void);
static void PREFIX86(_mov_aldisp)(void);
static void PREFIX86(_mov_axdisp)(void);
static void PREFIX86(_mov_dispal)(void);
static void PREFIX86(_mov_dispax)(void);
static void PREFIX86(_movsb)(void);
static void PREFIX86(_movsw)(void);
static void PREFIX86(_cmpsb)(void);
static void PREFIX86(_cmpsw)(void);
static void PREFIX86(_test_ald8)(void);
static void PREFIX86(_test_axd16)(void);
static void PREFIX86(_stosb)(void);
static void PREFIX86(_stosw)(void);
static void PREFIX86(_lodsb)(void);
static void PREFIX86(_lodsw)(void);
static void PREFIX86(_scasb)(void);
static void PREFIX86(_scasw)(void);
static void PREFIX86(_mov_ald8)(void);
static void PREFIX86(_mov_cld8)(void);
static void PREFIX86(_mov_dld8)(void);
static void PREFIX86(_mov_bld8)(void);
static void PREFIX86(_mov_ahd8)(void);
static void PREFIX86(_mov_chd8)(void);
static void PREFIX86(_mov_dhd8)(void);
static void PREFIX86(_mov_bhd8)(void);
static void PREFIX86(_mov_axd16)(void);
static void PREFIX86(_mov_cxd16)(void);
static void PREFIX86(_mov_dxd16)(void);
static void PREFIX86(_mov_bxd16)(void);
static void PREFIX86(_mov_spd16)(void);
static void PREFIX86(_mov_bpd16)(void);
static void PREFIX86(_mov_sid16)(void);
static void PREFIX86(_mov_did16)(void);
static void PREFIX86(_ret_d16)(void);
static void PREFIX86(_ret)(void);
static void PREFIX86(_les_dw)(void);
static void PREFIX86(_lds_dw)(void);
static void PREFIX86(_mov_bd8)(void);
static void PREFIX86(_mov_wd16)(void);
static void PREFIX86(_retf_d16)(void);
static void PREFIX86(_retf)(void);
static void PREFIX86(_int3)(void);
static void PREFIX86(_int)(void);
static void PREFIX86(_into)(void);
static void PREFIX86(_iret)(void);
static void PREFIX86(_rotshft_b)(void);
static void PREFIX86(_rotshft_w)(void);
static void PREFIX86(_rotshft_bcl)(void);
static void PREFIX86(_rotshft_wcl)(void);
static void PREFIX86(_aam)(void);
static void PREFIX86(_aad)(void);
static void PREFIX86(_xlat)(void);
static void PREFIX86(_escape)(void);
static void PREFIX86(_loopne)(void);
static void PREFIX86(_loope)(void);
static void PREFIX86(_loop)(void);
static void PREFIX86(_jcxz)(void);
static void PREFIX86(_inal)(void);
static void PREFIX86(_inax)(void);
static void PREFIX86(_outal)(void);
static void PREFIX86(_outax)(void);
static void PREFIX86(_call_d16)(void);
static void PREFIX86(_jmp_d16)(void);
static void PREFIX86(_jmp_far)(void);
static void PREFIX86(_jmp_d8)(void);
static void PREFIX86(_inaldx)(void);
static void PREFIX86(_inaxdx)(void);
static void PREFIX86(_outdxal)(void);
static void PREFIX86(_outdxax)(void);
static void PREFIX86(_lock)(void);
static void PREFIX86(_repne)(void);
static void PREFIX86(_repe)(void);
static void PREFIX86(_hlt)(void);
static void PREFIX86(_cmc)(void);
static void PREFIX86(_f6pre)(void);
static void PREFIX86(_f7pre)(void);
static void PREFIX86(_clc)(void);
static void PREFIX86(_stc)(void);
static void PREFIX86(_cli)(void);
static void PREFIX86(_sti)(void);
static void PREFIX86(_cld)(void);
static void PREFIX86(_std)(void);
static void PREFIX86(_fepre)(void);
static void PREFIX86(_ffpre)(void);
static void PREFIX86(_wait)(void);
static void PREFIX86(_add_br8)(i8086_state *cpustate);
static void PREFIX86(_add_wr16)(i8086_state *cpustate);
static void PREFIX86(_add_r8b)(i8086_state *cpustate);
static void PREFIX86(_add_r16w)(i8086_state *cpustate);
static void PREFIX86(_add_ald8)(i8086_state *cpustate);
static void PREFIX86(_add_axd16)(i8086_state *cpustate);
static void PREFIX86(_push_es)(i8086_state *cpustate);
static void PREFIX86(_pop_es)(i8086_state *cpustate);
static void PREFIX86(_or_br8)(i8086_state *cpustate);
static void PREFIX86(_or_r8b)(i8086_state *cpustate);
static void PREFIX86(_or_wr16)(i8086_state *cpustate);
static void PREFIX86(_or_r16w)(i8086_state *cpustate);
static void PREFIX86(_or_ald8)(i8086_state *cpustate);
static void PREFIX86(_or_axd16)(i8086_state *cpustate);
static void PREFIX86(_push_cs)(i8086_state *cpustate);
static void PREFIX86(_adc_br8)(i8086_state *cpustate);
static void PREFIX86(_adc_wr16)(i8086_state *cpustate);
static void PREFIX86(_adc_r8b)(i8086_state *cpustate);
static void PREFIX86(_adc_r16w)(i8086_state *cpustate);
static void PREFIX86(_adc_ald8)(i8086_state *cpustate);
static void PREFIX86(_adc_axd16)(i8086_state *cpustate);
static void PREFIX86(_push_ss)(i8086_state *cpustate);
static void PREFIX86(_pop_ss)(i8086_state *cpustate);
static void PREFIX86(_sbb_br8)(i8086_state *cpustate);
static void PREFIX86(_sbb_wr16)(i8086_state *cpustate);
static void PREFIX86(_sbb_r8b)(i8086_state *cpustate);
static void PREFIX86(_sbb_r16w)(i8086_state *cpustate);
static void PREFIX86(_sbb_ald8)(i8086_state *cpustate);
static void PREFIX86(_sbb_axd16)(i8086_state *cpustate);
static void PREFIX86(_push_ds)(i8086_state *cpustate);
static void PREFIX86(_pop_ds)(i8086_state *cpustate);
static void PREFIX86(_and_br8)(i8086_state *cpustate);
static void PREFIX86(_and_r8b)(i8086_state *cpustate);
static void PREFIX86(_and_wr16)(i8086_state *cpustate);
static void PREFIX86(_and_r16w)(i8086_state *cpustate);
static void PREFIX86(_and_ald8)(i8086_state *cpustate);
static void PREFIX86(_and_axd16)(i8086_state *cpustate);
static void PREFIX86(_es)(i8086_state *cpustate);
static void PREFIX86(_daa)(i8086_state *cpustate);
static void PREFIX86(_sub_br8)(i8086_state *cpustate);
static void PREFIX86(_sub_wr16)(i8086_state *cpustate);
static void PREFIX86(_sub_r8b)(i8086_state *cpustate);
static void PREFIX86(_sub_r16w)(i8086_state *cpustate);
static void PREFIX86(_sub_ald8)(i8086_state *cpustate);
static void PREFIX86(_sub_axd16)(i8086_state *cpustate);
static void PREFIX86(_cs)(i8086_state *cpustate);
static void PREFIX86(_das)(i8086_state *cpustate);
static void PREFIX86(_xor_br8)(i8086_state *cpustate);
static void PREFIX86(_xor_r8b)(i8086_state *cpustate);
static void PREFIX86(_xor_wr16)(i8086_state *cpustate);
static void PREFIX86(_xor_r16w)(i8086_state *cpustate);
static void PREFIX86(_xor_ald8)(i8086_state *cpustate);
static void PREFIX86(_xor_axd16)(i8086_state *cpustate);
static void PREFIX86(_ss)(i8086_state *cpustate);
static void PREFIX86(_aaa)(i8086_state *cpustate);
static void PREFIX86(_cmp_br8)(i8086_state *cpustate);
static void PREFIX86(_cmp_wr16)(i8086_state *cpustate);
static void PREFIX86(_cmp_r8b)(i8086_state *cpustate);
static void PREFIX86(_cmp_r16w)(i8086_state *cpustate);
static void PREFIX86(_cmp_ald8)(i8086_state *cpustate);
static void PREFIX86(_cmp_axd16)(i8086_state *cpustate);
static void PREFIX86(_ds)(i8086_state *cpustate);
static void PREFIX86(_aas)(i8086_state *cpustate);
static void PREFIX86(_inc_ax)(i8086_state *cpustate);
static void PREFIX86(_inc_cx)(i8086_state *cpustate);
static void PREFIX86(_inc_dx)(i8086_state *cpustate);
static void PREFIX86(_inc_bx)(i8086_state *cpustate);
static void PREFIX86(_inc_sp)(i8086_state *cpustate);
static void PREFIX86(_inc_bp)(i8086_state *cpustate);
static void PREFIX86(_inc_si)(i8086_state *cpustate);
static void PREFIX86(_inc_di)(i8086_state *cpustate);
static void PREFIX86(_dec_ax)(i8086_state *cpustate);
static void PREFIX86(_dec_cx)(i8086_state *cpustate);
static void PREFIX86(_dec_dx)(i8086_state *cpustate);
static void PREFIX86(_dec_bx)(i8086_state *cpustate);
static void PREFIX86(_dec_sp)(i8086_state *cpustate);
static void PREFIX86(_dec_bp)(i8086_state *cpustate);
static void PREFIX86(_dec_si)(i8086_state *cpustate);
static void PREFIX86(_dec_di)(i8086_state *cpustate);
static void PREFIX86(_push_ax)(i8086_state *cpustate);
static void PREFIX86(_push_cx)(i8086_state *cpustate);
static void PREFIX86(_push_dx)(i8086_state *cpustate);
static void PREFIX86(_push_bx)(i8086_state *cpustate);
static void PREFIX86(_push_sp)(i8086_state *cpustate);
static void PREFIX86(_push_bp)(i8086_state *cpustate);
static void PREFIX86(_push_si)(i8086_state *cpustate);
static void PREFIX86(_push_di)(i8086_state *cpustate);
static void PREFIX86(_pop_ax)(i8086_state *cpustate);
static void PREFIX86(_pop_cx)(i8086_state *cpustate);
static void PREFIX86(_pop_dx)(i8086_state *cpustate);
static void PREFIX86(_pop_bx)(i8086_state *cpustate);
static void PREFIX86(_pop_sp)(i8086_state *cpustate);
static void PREFIX86(_pop_bp)(i8086_state *cpustate);
static void PREFIX86(_pop_si)(i8086_state *cpustate);
static void PREFIX86(_pop_di)(i8086_state *cpustate);
static void PREFIX86(_jo)(i8086_state *cpustate);
static void PREFIX86(_jno)(i8086_state *cpustate);
static void PREFIX86(_jb)(i8086_state *cpustate);
static void PREFIX86(_jnb)(i8086_state *cpustate);
static void PREFIX86(_jz)(i8086_state *cpustate);
static void PREFIX86(_jnz)(i8086_state *cpustate);
static void PREFIX86(_jbe)(i8086_state *cpustate);
static void PREFIX86(_jnbe)(i8086_state *cpustate);
static void PREFIX86(_js)(i8086_state *cpustate);
static void PREFIX86(_jns)(i8086_state *cpustate);
static void PREFIX86(_jp)(i8086_state *cpustate);
static void PREFIX86(_jnp)(i8086_state *cpustate);
static void PREFIX86(_jl)(i8086_state *cpustate);
static void PREFIX86(_jnl)(i8086_state *cpustate);
static void PREFIX86(_jle)(i8086_state *cpustate);
static void PREFIX86(_jnle)(i8086_state *cpustate);
static void PREFIX86(_80pre)(i8086_state *cpustate);
static void PREFIX86(_82pre)(i8086_state *cpustate);
static void PREFIX86(_81pre)(i8086_state *cpustate);
static void PREFIX86(_83pre)(i8086_state *cpustate);
static void PREFIX86(_test_br8)(i8086_state *cpustate);
static void PREFIX86(_test_wr16)(i8086_state *cpustate);
static void PREFIX86(_xchg_br8)(i8086_state *cpustate);
static void PREFIX86(_xchg_wr16)(i8086_state *cpustate);
static void PREFIX86(_mov_br8)(i8086_state *cpustate);
static void PREFIX86(_mov_r8b)(i8086_state *cpustate);
static void PREFIX86(_mov_wr16)(i8086_state *cpustate);
static void PREFIX86(_mov_r16w)(i8086_state *cpustate);
static void PREFIX86(_mov_wsreg)(i8086_state *cpustate);
static void PREFIX86(_lea)(i8086_state *cpustate);
static void PREFIX86(_mov_sregw)(i8086_state *cpustate);
static void PREFIX86(_invalid)(i8086_state *cpustate);
static void PREFIX86(_popw)(i8086_state *cpustate);
static void PREFIX86(_nop)(i8086_state *cpustate);
static void PREFIX86(_xchg_axcx)(i8086_state *cpustate);
static void PREFIX86(_xchg_axdx)(i8086_state *cpustate);
static void PREFIX86(_xchg_axbx)(i8086_state *cpustate);
static void PREFIX86(_xchg_axsp)(i8086_state *cpustate);
static void PREFIX86(_xchg_axbp)(i8086_state *cpustate);
static void PREFIX86(_xchg_axsi)(i8086_state *cpustate);
static void PREFIX86(_xchg_axdi)(i8086_state *cpustate);
static void PREFIX86(_cbw)(i8086_state *cpustate);
static void PREFIX86(_cwd)(i8086_state *cpustate);
static void PREFIX86(_call_far)(i8086_state *cpustate);
static void PREFIX86(_pushf)(i8086_state *cpustate);
static void PREFIX86(_popf)(i8086_state *cpustate);
static void PREFIX86(_sahf)(i8086_state *cpustate);
static void PREFIX86(_lahf)(i8086_state *cpustate);
static void PREFIX86(_mov_aldisp)(i8086_state *cpustate);
static void PREFIX86(_mov_axdisp)(i8086_state *cpustate);
static void PREFIX86(_mov_dispal)(i8086_state *cpustate);
static void PREFIX86(_mov_dispax)(i8086_state *cpustate);
static void PREFIX86(_movsb)(i8086_state *cpustate);
static void PREFIX86(_movsw)(i8086_state *cpustate);
static void PREFIX86(_cmpsb)(i8086_state *cpustate);
static void PREFIX86(_cmpsw)(i8086_state *cpustate);
static void PREFIX86(_test_ald8)(i8086_state *cpustate);
static void PREFIX86(_test_axd16)(i8086_state *cpustate);
static void PREFIX86(_stosb)(i8086_state *cpustate);
static void PREFIX86(_stosw)(i8086_state *cpustate);
static void PREFIX86(_lodsb)(i8086_state *cpustate);
static void PREFIX86(_lodsw)(i8086_state *cpustate);
static void PREFIX86(_scasb)(i8086_state *cpustate);
static void PREFIX86(_scasw)(i8086_state *cpustate);
static void PREFIX86(_mov_ald8)(i8086_state *cpustate);
static void PREFIX86(_mov_cld8)(i8086_state *cpustate);
static void PREFIX86(_mov_dld8)(i8086_state *cpustate);
static void PREFIX86(_mov_bld8)(i8086_state *cpustate);
static void PREFIX86(_mov_ahd8)(i8086_state *cpustate);
static void PREFIX86(_mov_chd8)(i8086_state *cpustate);
static void PREFIX86(_mov_dhd8)(i8086_state *cpustate);
static void PREFIX86(_mov_bhd8)(i8086_state *cpustate);
static void PREFIX86(_mov_axd16)(i8086_state *cpustate);
static void PREFIX86(_mov_cxd16)(i8086_state *cpustate);
static void PREFIX86(_mov_dxd16)(i8086_state *cpustate);
static void PREFIX86(_mov_bxd16)(i8086_state *cpustate);
static void PREFIX86(_mov_spd16)(i8086_state *cpustate);
static void PREFIX86(_mov_bpd16)(i8086_state *cpustate);
static void PREFIX86(_mov_sid16)(i8086_state *cpustate);
static void PREFIX86(_mov_did16)(i8086_state *cpustate);
static void PREFIX86(_ret_d16)(i8086_state *cpustate);
static void PREFIX86(_ret)(i8086_state *cpustate);
static void PREFIX86(_les_dw)(i8086_state *cpustate);
static void PREFIX86(_lds_dw)(i8086_state *cpustate);
static void PREFIX86(_mov_bd8)(i8086_state *cpustate);
static void PREFIX86(_mov_wd16)(i8086_state *cpustate);
static void PREFIX86(_retf_d16)(i8086_state *cpustate);
static void PREFIX86(_retf)(i8086_state *cpustate);
static void PREFIX86(_int3)(i8086_state *cpustate);
static void PREFIX86(_int)(i8086_state *cpustate);
static void PREFIX86(_into)(i8086_state *cpustate);
static void PREFIX86(_iret)(i8086_state *cpustate);
static void PREFIX86(_rotshft_b)(i8086_state *cpustate);
static void PREFIX86(_rotshft_w)(i8086_state *cpustate);
static void PREFIX86(_rotshft_bcl)(i8086_state *cpustate);
static void PREFIX86(_rotshft_wcl)(i8086_state *cpustate);
static void PREFIX86(_aam)(i8086_state *cpustate);
static void PREFIX86(_aad)(i8086_state *cpustate);
static void PREFIX86(_xlat)(i8086_state *cpustate);
static void PREFIX86(_escape)(i8086_state *cpustate);
static void PREFIX86(_loopne)(i8086_state *cpustate);
static void PREFIX86(_loope)(i8086_state *cpustate);
static void PREFIX86(_loop)(i8086_state *cpustate);
static void PREFIX86(_jcxz)(i8086_state *cpustate);
static void PREFIX86(_inal)(i8086_state *cpustate);
static void PREFIX86(_inax)(i8086_state *cpustate);
static void PREFIX86(_outal)(i8086_state *cpustate);
static void PREFIX86(_outax)(i8086_state *cpustate);
static void PREFIX86(_call_d16)(i8086_state *cpustate);
static void PREFIX86(_jmp_d16)(i8086_state *cpustate);
static void PREFIX86(_jmp_far)(i8086_state *cpustate);
static void PREFIX86(_jmp_d8)(i8086_state *cpustate);
static void PREFIX86(_inaldx)(i8086_state *cpustate);
static void PREFIX86(_inaxdx)(i8086_state *cpustate);
static void PREFIX86(_outdxal)(i8086_state *cpustate);
static void PREFIX86(_outdxax)(i8086_state *cpustate);
static void PREFIX86(_lock)(i8086_state *cpustate);
static void PREFIX86(_repne)(i8086_state *cpustate);
static void PREFIX86(_repe)(i8086_state *cpustate);
static void PREFIX86(_hlt)(i8086_state *cpustate);
static void PREFIX86(_cmc)(i8086_state *cpustate);
static void PREFIX86(_f6pre)(i8086_state *cpustate);
static void PREFIX86(_f7pre)(i8086_state *cpustate);
static void PREFIX86(_clc)(i8086_state *cpustate);
static void PREFIX86(_stc)(i8086_state *cpustate);
static void PREFIX86(_cli)(i8086_state *cpustate);
static void PREFIX86(_sti)(i8086_state *cpustate);
static void PREFIX86(_cld)(i8086_state *cpustate);
static void PREFIX86(_std)(i8086_state *cpustate);
static void PREFIX86(_fepre)(i8086_state *cpustate);
static void PREFIX86(_ffpre)(i8086_state *cpustate);
static void PREFIX86(_wait)(i8086_state *cpustate);
#endif /* __INSTR86_H__ */

1311
src/emu/cpu/i86/instrv30.c
View File

File diff suppressed because it is too large Load Diff

7
src/emu/cpu/i86/instrv30.h
View File

@ -1,7 +0,0 @@
static void PREFIXV30(_0fpre)(void);
static void PREFIXV30(_repnc)(void);
static void PREFIXV30(_repc)(void);
static void PREFIXV30(_setalc)(void);
#if 0
static void PREFIXV30(_brks)(void);
#endif

52
src/emu/cpu/i86/modrm.h
View File

@ -12,81 +12,81 @@ static struct
} RM;
} Mod_RM;
#define RegWord(ModRM) I.regs.w[Mod_RM.reg.w[ModRM]]
#define RegByte(ModRM) I.regs.b[Mod_RM.reg.b[ModRM]]
#define RegWord(ModRM) cpustate->regs.w[Mod_RM.reg.w[ModRM]]
#define RegByte(ModRM) cpustate->regs.b[Mod_RM.reg.b[ModRM]]
#define GetRMWord(ModRM) \
((ModRM) >= 0xc0 ? I.regs.w[Mod_RM.RM.w[ModRM]] : ( (*GetEA[ModRM])(), ReadWord( EA ) ))
((ModRM) >= 0xc0 ? cpustate->regs.w[Mod_RM.RM.w[ModRM]] : ( (*GetEA[ModRM])(cpustate), ReadWord( cpustate->ea ) ))
#define PutbackRMWord(ModRM,val) \
{ \
if (ModRM >= 0xc0) I.regs.w[Mod_RM.RM.w[ModRM]]=val; \
else WriteWord(EA,val); \
if (ModRM >= 0xc0) cpustate->regs.w[Mod_RM.RM.w[ModRM]]=val; \
else WriteWord(cpustate->ea,val); \
}
#define GetnextRMWord ReadWord(EA+2)
#define GetnextRMWord ReadWord(cpustate->ea+2)
#define GetRMWordOffset(offs) \
ReadWord(EA-EO+(UINT16)(EO+offs))
ReadWord(cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs))
#define GetRMByteOffset(offs) \
ReadByte(EA-EO+(UINT16)(EO+offs))
ReadByte(cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs))
#define PutRMWord(ModRM,val) \
{ \
if (ModRM >= 0xc0) \
I.regs.w[Mod_RM.RM.w[ModRM]]=val; \
cpustate->regs.w[Mod_RM.RM.w[ModRM]]=val; \
else { \
(*GetEA[ModRM])(); \
WriteWord( EA ,val); \
(*GetEA[ModRM])(cpustate); \
WriteWord( cpustate->ea ,val); \
} \
}
#define PutRMWordOffset(offs, val) \
WriteWord( EA-EO+(UINT16)(EO+offs), val)
WriteWord( cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs), val)
#define PutRMByteOffset(offs, val) \
WriteByte( EA-EO+(UINT16)(EO+offs), val)
WriteByte( cpustate->ea-cpustate->eo+(UINT16)(cpustate->eo+offs), val)
#define PutImmRMWord(ModRM) \
{ \
WORD val; \
if (ModRM >= 0xc0) \
FETCHWORD(I.regs.w[Mod_RM.RM.w[ModRM]]) \
FETCHWORD(cpustate->regs.w[Mod_RM.RM.w[ModRM]]) \
else { \
(*GetEA[ModRM])(); \
(*GetEA[ModRM])(cpustate); \
FETCHWORD(val) \
WriteWord( EA , val); \
WriteWord( cpustate->ea , val); \
} \
}
#define GetRMByte(ModRM) \
((ModRM) >= 0xc0 ? I.regs.b[Mod_RM.RM.b[ModRM]] : ReadByte( (*GetEA[ModRM])() ))
((ModRM) >= 0xc0 ? cpustate->regs.b[Mod_RM.RM.b[ModRM]] : ReadByte( (*GetEA[ModRM])(cpustate) ))
#define PutRMByte(ModRM,val) \
{ \
if (ModRM >= 0xc0) \
I.regs.b[Mod_RM.RM.b[ModRM]]=val; \
cpustate->regs.b[Mod_RM.RM.b[ModRM]]=val; \
else \
WriteByte( (*GetEA[ModRM])() ,val); \
WriteByte( (*GetEA[ModRM])(cpustate) ,val); \
}
#define PutImmRMByte(ModRM) \
{ \
if (ModRM >= 0xc0) \
I.regs.b[Mod_RM.RM.b[ModRM]]=FETCH; \
cpustate->regs.b[Mod_RM.RM.b[ModRM]]=FETCH; \
else { \
(*GetEA[ModRM])(); \
WriteByte( EA , FETCH ); \
(*GetEA[ModRM])(cpustate); \
WriteByte( cpustate->ea , FETCH ); \
} \
}
#define PutbackRMByte(ModRM,val) \
{ \
if (ModRM >= 0xc0) \
I.regs.b[Mod_RM.RM.b[ModRM]]=val; \
cpustate->regs.b[Mod_RM.RM.b[ModRM]]=val; \
else \
WriteByte(EA,val); \
WriteByte(cpustate->ea,val); \
}
#define DEF_br8(dst,src) \
@ -111,9 +111,9 @@ static struct
#define DEF_ald8(dst,src) \
unsigned src = FETCHOP; \
unsigned dst = I.regs.b[AL]
unsigned dst = cpustate->regs.b[AL]
#define DEF_axd16(dst,src) \
unsigned src = FETCHOP; \
unsigned dst = I.regs.w[AX]; \
unsigned dst = cpustate->regs.w[AX]; \
src += (FETCH << 8)

516
src/emu/cpu/i86/table186.h
View File

@ -1,4 +1,4 @@
static void (*const PREFIX186(_instruction)[256])(void) =
static void (*const PREFIX186(_instruction)[256])(i8086_state *cpustate) =
{
PREFIX86(_add_br8), /* 0x00 */
PREFIX86(_add_wr16), /* 0x01 */
@ -263,263 +263,263 @@ static void (*const PREFIX186(_instruction)[256])(void) =
#define TABLE186 \
switch(FETCHOP)\
{\
case 0x00: PREFIX86(_add_br8)(); break;\
case 0x01: PREFIX86(_add_wr16)(); break;\
case 0x02: PREFIX86(_add_r8b)(); break;\
case 0x03: PREFIX86(_add_r16w)(); break;\
case 0x04: PREFIX86(_add_ald8)(); break;\
case 0x05: PREFIX86(_add_axd16)(); break;\
case 0x06: PREFIX86(_push_es)(); break;\
case 0x07: PREFIX86(_pop_es)(); break;\
case 0x08: PREFIX86(_or_br8)(); break;\
case 0x09: PREFIX86(_or_wr16)(); break;\
case 0x0a: PREFIX86(_or_r8b)(); break;\
case 0x0b: PREFIX86(_or_r16w)(); break;\
case 0x0c: PREFIX86(_or_ald8)(); break;\
case 0x0d: PREFIX86(_or_axd16)(); break;\
case 0x0e: PREFIX86(_push_cs)(); break;\
case 0x0f: PREFIX86(_invalid)(); break;\
case 0x10: PREFIX86(_adc_br8)(); break;\
case 0x11: PREFIX86(_adc_wr16)(); break;\
case 0x12: PREFIX86(_adc_r8b)(); break;\
case 0x13: PREFIX86(_adc_r16w)(); break;\
case 0x14: PREFIX86(_adc_ald8)(); break;\
case 0x15: PREFIX86(_adc_axd16)(); break;\
case 0x16: PREFIX86(_push_ss)(); break;\
case 0x17: PREFIX86(_pop_ss)(); break;\
case 0x18: PREFIX86(_sbb_br8)(); break;\
case 0x19: PREFIX86(_sbb_wr16)(); break;\
case 0x1a: PREFIX86(_sbb_r8b)(); break;\
case 0x1b: PREFIX86(_sbb_r16w)(); break;\
case 0x1c: PREFIX86(_sbb_ald8)(); break;\
case 0x1d: PREFIX86(_sbb_axd16)(); break;\
case 0x1e: PREFIX86(_push_ds)(); break;\
case 0x1f: PREFIX86(_pop_ds)(); break;\
case 0x20: PREFIX86(_and_br8)(); break;\
case 0x21: PREFIX86(_and_wr16)(); break;\
case 0x22: PREFIX86(_and_r8b)(); break;\
case 0x23: PREFIX86(_and_r16w)(); break;\
case 0x24: PREFIX86(_and_ald8)(); break;\
case 0x25: PREFIX86(_and_axd16)(); break;\
case 0x26: PREFIX86(_es)(); break;\
case 0x27: PREFIX86(_daa)(); break;\
case 0x28: PREFIX86(_sub_br8)(); break;\
case 0x29: PREFIX86(_sub_wr16)(); break;\
case 0x2a: PREFIX86(_sub_r8b)(); break;\
case 0x2b: PREFIX86(_sub_r16w)(); break;\
case 0x2c: PREFIX86(_sub_ald8)(); break;\
case 0x2d: PREFIX86(_sub_axd16)(); break;\
case 0x2e: PREFIX86(_cs)(); break;\
case 0x2f: PREFIX86(_das)(); break;\
case 0x30: PREFIX86(_xor_br8)(); break;\
case 0x31: PREFIX86(_xor_wr16)(); break;\
case 0x32: PREFIX86(_xor_r8b)(); break;\
case 0x33: PREFIX86(_xor_r16w)(); break;\
case 0x34: PREFIX86(_xor_ald8)(); break;\
case 0x35: PREFIX86(_xor_axd16)(); break;\
case 0x36: PREFIX86(_ss)(); break;\
case 0x37: PREFIX86(_aaa)(); break;\
case 0x38: PREFIX86(_cmp_br8)(); break;\
case 0x39: PREFIX86(_cmp_wr16)(); break;\
case 0x3a: PREFIX86(_cmp_r8b)(); break;\
case 0x3b: PREFIX86(_cmp_r16w)(); break;\
case 0x3c: PREFIX86(_cmp_ald8)(); break;\
case 0x3d: PREFIX86(_cmp_axd16)(); break;\
case 0x3e: PREFIX86(_ds)(); break;\
case 0x3f: PREFIX86(_aas)(); break;\
case 0x40: PREFIX86(_inc_ax)(); break;\
case 0x41: PREFIX86(_inc_cx)(); break;\
case 0x42: PREFIX86(_inc_dx)(); break;\
case 0x43: PREFIX86(_inc_bx)(); break;\
case 0x44: PREFIX86(_inc_sp)(); break;\
case 0x45: PREFIX86(_inc_bp)(); break;\
case 0x46: PREFIX86(_inc_si)(); break;\
case 0x47: PREFIX86(_inc_di)(); break;\
case 0x48: PREFIX86(_dec_ax)(); break;\
case 0x49: PREFIX86(_dec_cx)(); break;\
case 0x4a: PREFIX86(_dec_dx)(); break;\
case 0x4b: PREFIX86(_dec_bx)(); break;\
case 0x4c: PREFIX86(_dec_sp)(); break;\
case 0x4d: PREFIX86(_dec_bp)(); break;\
case 0x4e: PREFIX86(_dec_si)(); break;\
case 0x4f: PREFIX86(_dec_di)(); break;\
case 0x50: PREFIX86(_push_ax)(); break;\
case 0x51: PREFIX86(_push_cx)(); break;\
case 0x52: PREFIX86(_push_dx)(); break;\
case 0x53: PREFIX86(_push_bx)(); break;\
case 0x54: PREFIX86(_push_sp)(); break;\
case 0x55: PREFIX86(_push_bp)(); break;\
case 0x56: PREFIX86(_push_si)(); break;\
case 0x57: PREFIX86(_push_di)(); break;\
case 0x58: PREFIX86(_pop_ax)(); break;\
case 0x59: PREFIX86(_pop_cx)(); break;\
case 0x5a: PREFIX86(_pop_dx)(); break;\
case 0x5b: PREFIX86(_pop_bx)(); break;\
case 0x5c: PREFIX86(_pop_sp)(); break;\
case 0x5d: PREFIX86(_pop_bp)(); break;\
case 0x5e: PREFIX86(_pop_si)(); break;\
case 0x5f: PREFIX86(_pop_di)(); break;\
case 0x60: PREFIX186(_pusha)(); break;\
case 0x61: PREFIX186(_popa)(); break;\
case 0x62: PREFIX186(_bound)(); break;\
case 0x63: PREFIX86(_invalid)(); break;\
case 0x64: PREFIX86(_invalid)(); break;\
case 0x65: PREFIX86(_invalid)(); break;\
case 0x66: PREFIX86(_invalid)(); break;\
case 0x67: PREFIX86(_invalid)(); break;\
case 0x68: PREFIX186(_push_d16)(); break;\
case 0x69: PREFIX186(_imul_d16)(); break;\
case 0x6a: PREFIX186(_push_d8)(); break;\
case 0x6b: PREFIX186(_imul_d8)(); break;\
case 0x6c: PREFIX186(_insb)(); break;\
case 0x6d: PREFIX186(_insw)(); break;\
case 0x6e: PREFIX186(_outsb)(); break;\
case 0x6f: PREFIX186(_outsw)(); break;\
case 0x70: PREFIX86(_jo)(); break;\
case 0x71: PREFIX86(_jno)(); break;\
case 0x72: PREFIX86(_jb)(); break;\
case 0x73: PREFIX86(_jnb)(); break;\
case 0x74: PREFIX86(_jz)(); break;\
case 0x75: PREFIX86(_jnz)(); break;\
case 0x76: PREFIX86(_jbe)(); break;\
case 0x77: PREFIX86(_jnbe)(); break;\
case 0x78: PREFIX86(_js)(); break;\
case 0x79: PREFIX86(_jns)(); break;\
case 0x7a: PREFIX86(_jp)(); break;\
case 0x7b: PREFIX86(_jnp)(); break;\
case 0x7c: PREFIX86(_jl)(); break;\
case 0x7d: PREFIX86(_jnl)(); break;\
case 0x7e: PREFIX86(_jle)(); break;\
case 0x7f: PREFIX86(_jnle)(); break;\
case 0x80: PREFIX86(_80pre)(); break;\
case 0x81: PREFIX86(_81pre)(); break;\
case 0x82: PREFIX86(_82pre)(); break;\
case 0x83: PREFIX86(_83pre)(); break;\
case 0x84: PREFIX86(_test_br8)(); break;\
case 0x85: PREFIX86(_test_wr16)(); break;\
case 0x86: PREFIX86(_xchg_br8)(); break;\
case 0x87: PREFIX86(_xchg_wr16)(); break;\
case 0x88: PREFIX86(_mov_br8)(); break;\
case 0x89: PREFIX86(_mov_wr16)(); break;\
case 0x8a: PREFIX86(_mov_r8b)(); break;\
case 0x8b: PREFIX86(_mov_r16w)(); break;\
case 0x8c: PREFIX86(_mov_wsreg)(); break;\
case 0x8d: PREFIX86(_lea)(); break;\
case 0x8e: PREFIX86(_mov_sregw)(); break;\
case 0x8f: PREFIX86(_popw)(); break;\
case 0x90: PREFIX86(_nop)(); break;\
case 0x91: PREFIX86(_xchg_axcx)(); break;\
case 0x92: PREFIX86(_xchg_axdx)(); break;\
case 0x93: PREFIX86(_xchg_axbx)(); break;\
case 0x94: PREFIX86(_xchg_axsp)(); break;\
case 0x95: PREFIX86(_xchg_axbp)(); break;\
case 0x96: PREFIX86(_xchg_axsi)(); break;\
case 0x97: PREFIX86(_xchg_axdi)(); break;\
case 0x98: PREFIX86(_cbw)(); break;\
case 0x99: PREFIX86(_cwd)(); break;\
case 0x9a: PREFIX86(_call_far)(); break;\
case 0x9b: PREFIX86(_wait)(); break;\
case 0x9c: PREFIX86(_pushf)(); break;\
case 0x9d: PREFIX86(_popf)(); break;\
case 0x9e: PREFIX86(_sahf)(); break;\
case 0x9f: PREFIX86(_lahf)(); break;\
case 0xa0: PREFIX86(_mov_aldisp)(); break;\
case 0xa1: PREFIX86(_mov_axdisp)(); break;\
case 0xa2: PREFIX86(_mov_dispal)(); break;\
case 0xa3: PREFIX86(_mov_dispax)(); break;\
case 0xa4: PREFIX86(_movsb)(); break;\
case 0xa5: PREFIX86(_movsw)(); break;\
case 0xa6: PREFIX86(_cmpsb)(); break;\
case 0xa7: PREFIX86(_cmpsw)(); break;\
case 0xa8: PREFIX86(_test_ald8)(); break;\
case 0xa9: PREFIX86(_test_axd16)(); break;\
case 0xaa: PREFIX86(_stosb)(); break;\
case 0xab: PREFIX86(_stosw)(); break;\
case 0xac: PREFIX86(_lodsb)(); break;\
case 0xad: PREFIX86(_lodsw)(); break;\
case 0xae: PREFIX86(_scasb)(); break;\
case 0xaf: PREFIX86(_scasw)(); break;\
case 0xb0: PREFIX86(_mov_ald8)(); break;\
case 0xb1: PREFIX86(_mov_cld8)(); break;\
case 0xb2: PREFIX86(_mov_dld8)(); break;\
case 0xb3: PREFIX86(_mov_bld8)(); break;\
case 0xb4: PREFIX86(_mov_ahd8)(); break;\
case 0xb5: PREFIX86(_mov_chd8)(); break;\
case 0xb6: PREFIX86(_mov_dhd8)(); break;\
case 0xb7: PREFIX86(_mov_bhd8)(); break;\
case 0xb8: PREFIX86(_mov_axd16)(); break;\
case 0xb9: PREFIX86(_mov_cxd16)(); break;\
case 0xba: PREFIX86(_mov_dxd16)(); break;\
case 0xbb: PREFIX86(_mov_bxd16)(); break;\
case 0xbc: PREFIX86(_mov_spd16)(); break;\
case 0xbd: PREFIX86(_mov_bpd16)(); break;\
case 0xbe: PREFIX86(_mov_sid16)(); break;\
case 0xbf: PREFIX86(_mov_did16)(); break;\
case 0xc0: PREFIX186(_rotshft_bd8)(); break;\
case 0xc1: PREFIX186(_rotshft_wd8)(); break;\
case 0xc2: PREFIX86(_ret_d16)(); break;\
case 0xc3: PREFIX86(_ret)(); break;\
case 0xc4: PREFIX86(_les_dw)(); break;\
case 0xc5: PREFIX86(_lds_dw)(); break;\
case 0xc6: PREFIX86(_mov_bd8)(); break;\
case 0xc7: PREFIX86(_mov_wd16)(); break;\
case 0xc8: PREFIX186(_enter)(); break;\
case 0xc9: PREFIX186(_leave)(); break;\
case 0xca: PREFIX86(_retf_d16)(); break;\
case 0xcb: PREFIX86(_retf)(); break;\
case 0xcc: PREFIX86(_int3)(); break;\
case 0xcd: PREFIX86(_int)(); break;\
case 0xce: PREFIX86(_into)(); break;\
case 0xcf: PREFIX86(_iret)(); break;\
case 0xd0: PREFIX86(_rotshft_b)(); break;\
case 0xd1: PREFIX86(_rotshft_w)(); break;\
case 0xd2: PREFIX86(_rotshft_bcl)(); break;\
case 0xd3: PREFIX86(_rotshft_wcl)(); break;\
case 0xd4: PREFIX86(_aam)(); break;\
case 0xd5: PREFIX86(_aad)(); break;\
case 0xd6: PREFIX86(_invalid)(); break;\
case 0xd7: PREFIX86(_xlat)(); break;\
case 0xd8: PREFIX86(_escape)(); break;\
case 0xd9: PREFIX86(_escape)(); break;\
case 0xda: PREFIX86(_escape)(); break;\
case 0xdb: PREFIX86(_escape)(); break;\
case 0xdc: PREFIX86(_escape)(); break;\
case 0xdd: PREFIX86(_escape)(); break;\
case 0xde: PREFIX86(_escape)(); break;\
case 0xdf: PREFIX86(_escape)(); break;\
case 0xe0: PREFIX86(_loopne)(); break;\
case 0xe1: PREFIX86(_loope)(); break;\
case 0xe2: PREFIX86(_loop)(); break;\
case 0xe3: PREFIX86(_jcxz)(); break;\
case 0xe4: PREFIX86(_inal)(); break;\
case 0xe5: PREFIX86(_inax)(); break;\
case 0xe6: PREFIX86(_outal)(); break;\
case 0xe7: PREFIX86(_outax)(); break;\
case 0xe8: PREFIX86(_call_d16)(); break;\
case 0xe9: PREFIX86(_jmp_d16)(); break;\
case 0xea: PREFIX86(_jmp_far)(); break;\
case 0xeb: PREFIX86(_jmp_d8)(); break;\
case 0xec: PREFIX86(_inaldx)(); break;\
case 0xed: PREFIX86(_inaxdx)(); break;\
case 0xee: PREFIX86(_outdxal)(); break;\
case 0xef: PREFIX86(_outdxax)(); break;\
case 0xf0: PREFIX86(_lock)(); break;\
case 0xf1: PREFIX86(_invalid)(); break;\
case 0xf2: PREFIX186(_repne)(); break;\
case 0xf3: PREFIX186(_repe)(); break;\
case 0xf4: PREFIX86(_hlt)(); break;\
case 0xf5: PREFIX86(_cmc)(); break;\
case 0xf6: PREFIX86(_f6pre)(); break;\
case 0xf7: PREFIX86(_f7pre)(); break;\
case 0xf8: PREFIX86(_clc)(); break;\
case 0xf9: PREFIX86(_stc)(); break;\
case 0xfa: PREFIX86(_cli)(); break;\
case 0xfb: PREFIX86(_sti)(); break;\
case 0xfc: PREFIX86(_cld)(); break;\
case 0xfd: PREFIX86(_std)(); break;\
case 0xfe: PREFIX86(_fepre)(); break;\
case 0xff: PREFIX86(_ffpre)(); break;\
case 0x00: PREFIX86(_add_br8)(cpustate); break;\
case 0x01: PREFIX86(_add_wr16)(cpustate); break;\
case 0x02: PREFIX86(_add_r8b)(cpustate); break;\
case 0x03: PREFIX86(_add_r16w)(cpustate); break;\
case 0x04: PREFIX86(_add_ald8)(cpustate); break;\
case 0x05: PREFIX86(_add_axd16)(cpustate); break;\
case 0x06: PREFIX86(_push_es)(cpustate); break;\
case 0x07: PREFIX86(_pop_es)(cpustate); break;\
case 0x08: PREFIX86(_or_br8)(cpustate); break;\
case 0x09: PREFIX86(_or_wr16)(cpustate); break;\
case 0x0a: PREFIX86(_or_r8b)(cpustate); break;\
case 0x0b: PREFIX86(_or_r16w)(cpustate); break;\
case 0x0c: PREFIX86(_or_ald8)(cpustate); break;\
case 0x0d: PREFIX86(_or_axd16)(cpustate); break;\
case 0x0e: PREFIX86(_push_cs)(cpustate); break;\
case 0x0f: PREFIX86(_invalid)(cpustate); break;\
case 0x10: PREFIX86(_adc_br8)(cpustate); break;\
case 0x11: PREFIX86(_adc_wr16)(cpustate); break;\
case 0x12: PREFIX86(_adc_r8b)(cpustate); break;\
case 0x13: PREFIX86(_adc_r16w)(cpustate); break;\
case 0x14: PREFIX86(_adc_ald8)(cpustate); break;\
case 0x15: PREFIX86(_adc_axd16)(cpustate); break;\
case 0x16: PREFIX86(_push_ss)(cpustate); break;\
case 0x17: PREFIX86(_pop_ss)(cpustate); break;\
case 0x18: PREFIX86(_sbb_br8)(cpustate); break;\
case 0x19: PREFIX86(_sbb_wr16)(cpustate); break;\
case 0x1a: PREFIX86(_sbb_r8b)(cpustate); break;\
case 0x1b: PREFIX86(_sbb_r16w)(cpustate); break;\
case 0x1c: PREFIX86(_sbb_ald8)(cpustate); break;\
case 0x1d: PREFIX86(_sbb_axd16)(cpustate); break;\
case 0x1e: PREFIX86(_push_ds)(cpustate); break;\
case 0x1f: PREFIX86(_pop_ds)(cpustate); break;\
case 0x20: PREFIX86(_and_br8)(cpustate); break;\
case 0x21: PREFIX86(_and_wr16)(cpustate); break;\
case 0x22: PREFIX86(_and_r8b)(cpustate); break;\
case 0x23: PREFIX86(_and_r16w)(cpustate); break;\
case 0x24: PREFIX86(_and_ald8)(cpustate); break;\
case 0x25: PREFIX86(_and_axd16)(cpustate); break;\
case 0x26: PREFIX86(_es)(cpustate); break;\
case 0x27: PREFIX86(_daa)(cpustate); break;\
case 0x28: PREFIX86(_sub_br8)(cpustate); break;\
case 0x29: PREFIX86(_sub_wr16)(cpustate); break;\
case 0x2a: PREFIX86(_sub_r8b)(cpustate); break;\
case 0x2b: PREFIX86(_sub_r16w)(cpustate); break;\
case 0x2c: PREFIX86(_sub_ald8)(cpustate); break;\
case 0x2d: PREFIX86(_sub_axd16)(cpustate); break;\
case 0x2e: PREFIX86(_cs)(cpustate); break;\
case 0x2f: PREFIX86(_das)(cpustate); break;\
case 0x30: PREFIX86(_xor_br8)(cpustate); break;\
case 0x31: PREFIX86(_xor_wr16)(cpustate); break;\
case 0x32: PREFIX86(_xor_r8b)(cpustate); break;\
case 0x33: PREFIX86(_xor_r16w)(cpustate); break;\
case 0x34: PREFIX86(_xor_ald8)(cpustate); break;\
case 0x35: PREFIX86(_xor_axd16)(cpustate); break;\
case 0x36: PREFIX86(_ss)(cpustate); break;\
case 0x37: PREFIX86(_aaa)(cpustate); break;\
case 0x38: PREFIX86(_cmp_br8)(cpustate); break;\
case 0x39: PREFIX86(_cmp_wr16)(cpustate); break;\
case 0x3a: PREFIX86(_cmp_r8b)(cpustate); break;\
case 0x3b: PREFIX86(_cmp_r16w)(cpustate); break;\
case 0x3c: PREFIX86(_cmp_ald8)(cpustate); break;\
case 0x3d: PREFIX86(_cmp_axd16)(cpustate); break;\
case 0x3e: PREFIX86(_ds)(cpustate); break;\
case 0x3f: PREFIX86(_aas)(cpustate); break;\
case 0x40: PREFIX86(_inc_ax)(cpustate); break;\
case 0x41: PREFIX86(_inc_cx)(cpustate); break;\
case 0x42: PREFIX86(_inc_dx)(cpustate); break;\
case 0x43: PREFIX86(_inc_bx)(cpustate); break;\
case 0x44: PREFIX86(_inc_sp)(cpustate); break;\
case 0x45: PREFIX86(_inc_bp)(cpustate); break;\
case 0x46: PREFIX86(_inc_si)(cpustate); break;\
case 0x47: PREFIX86(_inc_di)(cpustate); break;\
case 0x48: PREFIX86(_dec_ax)(cpustate); break;\
case 0x49: PREFIX86(_dec_cx)(cpustate); break;\
case 0x4a: PREFIX86(_dec_dx)(cpustate); break;\
case 0x4b: PREFIX86(_dec_bx)(cpustate); break;\
case 0x4c: PREFIX86(_dec_sp)(cpustate); break;\
case 0x4d: PREFIX86(_dec_bp)(cpustate); break;\
case 0x4e: PREFIX86(_dec_si)(cpustate); break;\
case 0x4f: PREFIX86(_dec_di)(cpustate); break;\
case 0x50: PREFIX86(_push_ax)(cpustate); break;\
case 0x51: PREFIX86(_push_cx)(cpustate); break;\
case 0x52: PREFIX86(_push_dx)(cpustate); break;\
case 0x53: PREFIX86(_push_bx)(cpustate); break;\
case 0x54: PREFIX86(_push_sp)(cpustate); break;\
case 0x55: PREFIX86(_push_bp)(cpustate); break;\
case 0x56: PREFIX86(_push_si)(cpustate); break;\
case 0x57: PREFIX86(_push_di)(cpustate); break;\
case 0x58: PREFIX86(_pop_ax)(cpustate); break;\
case 0x59: PREFIX86(_pop_cx)(cpustate); break;\
case 0x5a: PREFIX86(_pop_dx)(cpustate); break;\
case 0x5b: PREFIX86(_pop_bx)(cpustate); break;\
case 0x5c: PREFIX86(_pop_sp)(cpustate); break;\
case 0x5d: PREFIX86(_pop_bp)(cpustate); break;\
case 0x5e: PREFIX86(_pop_si)(cpustate); break;\
case 0x5f: PREFIX86(_pop_di)(cpustate); break;\
case 0x60: PREFIX186(_pusha)(cpustate); break;\
case 0x61: PREFIX186(_popa)(cpustate); break;\
case 0x62: PREFIX186(_bound)(cpustate); break;\
case 0x63: PREFIX86(_invalid)(cpustate); break;\
case 0x64: PREFIX86(_invalid)(cpustate); break;\
case 0x65: PREFIX86(_invalid)(cpustate); break;\
case 0x66: PREFIX86(_invalid)(cpustate); break;\
case 0x67: PREFIX86(_invalid)(cpustate); break;\
case 0x68: PREFIX186(_push_d16)(cpustate); break;\
case 0x69: PREFIX186(_imul_d16)(cpustate); break;\
case 0x6a: PREFIX186(_push_d8)(cpustate); break;\
case 0x6b: PREFIX186(_imul_d8)(cpustate); break;\
case 0x6c: PREFIX186(_insb)(cpustate); break;\
case 0x6d: PREFIX186(_insw)(cpustate); break;\
case 0x6e: PREFIX186(_outsb)(cpustate); break;\
case 0x6f: PREFIX186(_outsw)(cpustate); break;\
case 0x70: PREFIX86(_jo)(cpustate); break;\
case 0x71: PREFIX86(_jno)(cpustate); break;\
case 0x72: PREFIX86(_jb)(cpustate); break;\
case 0x73: PREFIX86(_jnb)(cpustate); break;\
case 0x74: PREFIX86(_jz)(cpustate); break;\
case 0x75: PREFIX86(_jnz)(cpustate); break;\
case 0x76: PREFIX86(_jbe)(cpustate); break;\
case 0x77: PREFIX86(_jnbe)(cpustate); break;\
case 0x78: PREFIX86(_js)(cpustate); break;\
case 0x79: PREFIX86(_jns)(cpustate); break;\
case 0x7a: PREFIX86(_jp)(cpustate); break;\
case 0x7b: PREFIX86(_jnp)(cpustate); break;\
case 0x7c: PREFIX86(_jl)(cpustate); break;\
case 0x7d: PREFIX86(_jnl)(cpustate); break;\
case 0x7e: PREFIX86(_jle)(cpustate); break;\
case 0x7f: PREFIX86(_jnle)(cpustate); break;\
case 0x80: PREFIX86(_80pre)(cpustate); break;\
case 0x81: PREFIX86(_81pre)(cpustate); break;\
case 0x82: PREFIX86(_82pre)(cpustate); break;\
case 0x83: PREFIX86(_83pre)(cpustate); break;\
case 0x84: PREFIX86(_test_br8)(cpustate); break;\
case 0x85: PREFIX86(_test_wr16)(cpustate); break;\
case 0x86: PREFIX86(_xchg_br8)(cpustate); break;\
case 0x87: PREFIX86(_xchg_wr16)(cpustate); break;\
case 0x88: PREFIX86(_mov_br8)(cpustate); break;\
case 0x89: PREFIX86(_mov_wr16)(cpustate); break;\
case 0x8a: PREFIX86(_mov_r8b)(cpustate); break;\
case 0x8b: PREFIX86(_mov_r16w)(cpustate); break;\
case 0x8c: PREFIX86(_mov_wsreg)(cpustate); break;\
case 0x8d: PREFIX86(_lea)(cpustate); break;\
case 0x8e: PREFIX86(_mov_sregw)(cpustate); break;\
case 0x8f: PREFIX86(_popw)(cpustate); break;\
case 0x90: PREFIX86(_nop)(cpustate); break;\
case 0x91: PREFIX86(_xchg_axcx)(cpustate); break;\
case 0x92: PREFIX86(_xchg_axdx)(cpustate); break;\
case 0x93: PREFIX86(_xchg_axbx)(cpustate); break;\
case 0x94: PREFIX86(_xchg_axsp)(cpustate); break;\
case 0x95: PREFIX86(_xchg_axbp)(cpustate); break;\
case 0x96: PREFIX86(_xchg_axsi)(cpustate); break;\
case 0x97: PREFIX86(_xchg_axdi)(cpustate); break;\
case 0x98: PREFIX86(_cbw)(cpustate); break;\
case 0x99: PREFIX86(_cwd)(cpustate); break;\
case 0x9a: PREFIX86(_call_far)(cpustate); break;\
case 0x9b: PREFIX86(_wait)(cpustate); break;\
case 0x9c: PREFIX86(_pushf)(cpustate); break;\
case 0x9d: PREFIX86(_popf)(cpustate); break;\
case 0x9e: PREFIX86(_sahf)(cpustate); break;\
case 0x9f: PREFIX86(_lahf)(cpustate); break;\
case 0xa0: PREFIX86(_mov_aldisp)(cpustate); break;\
case 0xa1: PREFIX86(_mov_axdisp)(cpustate); break;\
case 0xa2: PREFIX86(_mov_dispal)(cpustate); break;\
case 0xa3: PREFIX86(_mov_dispax)(cpustate); break;\
case 0xa4: PREFIX86(_movsb)(cpustate); break;\
case 0xa5: PREFIX86(_movsw)(cpustate); break;\
case 0xa6: PREFIX86(_cmpsb)(cpustate); break;\
case 0xa7: PREFIX86(_cmpsw)(cpustate); break;\
case 0xa8: PREFIX86(_test_ald8)(cpustate); break;\
case 0xa9: PREFIX86(_test_axd16)(cpustate); break;\
case 0xaa: PREFIX86(_stosb)(cpustate); break;\
case 0xab: PREFIX86(_stosw)(cpustate); break;\
case 0xac: PREFIX86(_lodsb)(cpustate); break;\
case 0xad: PREFIX86(_lodsw)(cpustate); break;\
case 0xae: PREFIX86(_scasb)(cpustate); break;\
case 0xaf: PREFIX86(_scasw)(cpustate); break;\
case 0xb0: PREFIX86(_mov_ald8)(cpustate); break;\
case 0xb1: PREFIX86(_mov_cld8)(cpustate); break;\
case 0xb2: PREFIX86(_mov_dld8)(cpustate); break;\
case 0xb3: PREFIX86(_mov_bld8)(cpustate); break;\
case 0xb4: PREFIX86(_mov_ahd8)(cpustate); break;\
case 0xb5: PREFIX86(_mov_chd8)(cpustate); break;\
case 0xb6: PREFIX86(_mov_dhd8)(cpustate); break;\
case 0xb7: PREFIX86(_mov_bhd8)(cpustate); break;\
case 0xb8: PREFIX86(_mov_axd16)(cpustate); break;\
case 0xb9: PREFIX86(_mov_cxd16)(cpustate); break;\
case 0xba: PREFIX86(_mov_dxd16)(cpustate); break;\
case 0xbb: PREFIX86(_mov_bxd16)(cpustate); break;\
case 0xbc: PREFIX86(_mov_spd16)(cpustate); break;\
case 0xbd: PREFIX86(_mov_bpd16)(cpustate); break;\
case 0xbe: PREFIX86(_mov_sid16)(cpustate); break;\
case 0xbf: PREFIX86(_mov_did16)(cpustate); break;\
case 0xc0: PREFIX186(_rotshft_bd8)(cpustate); break;\
case 0xc1: PREFIX186(_rotshft_wd8)(cpustate); break;\
case 0xc2: PREFIX86(_ret_d16)(cpustate); break;\
case 0xc3: PREFIX86(_ret)(cpustate); break;\
case 0xc4: PREFIX86(_les_dw)(cpustate); break;\
case 0xc5: PREFIX86(_lds_dw)(cpustate); break;\
case 0xc6: PREFIX86(_mov_bd8)(cpustate); break;\
case 0xc7: PREFIX86(_mov_wd16)(cpustate); break;\
case 0xc8: PREFIX186(_enter)(cpustate); break;\
case 0xc9: PREFIX186(_leave)(cpustate); break;\
case 0xca: PREFIX86(_retf_d16)(cpustate); break;\
case 0xcb: PREFIX86(_retf)(cpustate); break;\
case 0xcc: PREFIX86(_int3)(cpustate); break;\
case 0xcd: PREFIX86(_int)(cpustate); break;\
case 0xce: PREFIX86(_into)(cpustate); break;\
case 0xcf: PREFIX86(_iret)(cpustate); break;\
case 0xd0: PREFIX86(_rotshft_b)(cpustate); break;\
case 0xd1: PREFIX86(_rotshft_w)(cpustate); break;\
case 0xd2: PREFIX86(_rotshft_bcl)(cpustate); break;\
case 0xd3: PREFIX86(_rotshft_wcl)(cpustate); break;\
case 0xd4: PREFIX86(_aam)(cpustate); break;\
case 0xd5: PREFIX86(_aad)(cpustate); break;\
case 0xd6: PREFIX86(_invalid)(cpustate); break;\
case 0xd7: PREFIX86(_xlat)(cpustate); break;\
case 0xd8: PREFIX86(_escape)(cpustate); break;\
case 0xd9: PREFIX86(_escape)(cpustate); break;\
case 0xda: PREFIX86(_escape)(cpustate); break;\
case 0xdb: PREFIX86(_escape)(cpustate); break;\
case 0xdc: PREFIX86(_escape)(cpustate); break;\
case 0xdd: PREFIX86(_escape)(cpustate); break;\
case 0xde: PREFIX86(_escape)(cpustate); break;\
case 0xdf: PREFIX86(_escape)(cpustate); break;\
case 0xe0: PREFIX86(_loopne)(cpustate); break;\
case 0xe1: PREFIX86(_loope)(cpustate); break;\
case 0xe2: PREFIX86(_loop)(cpustate); break;\
case 0xe3: PREFIX86(_jcxz)(cpustate); break;\
case 0xe4: PREFIX86(_inal)(cpustate); break;\
case 0xe5: PREFIX86(_inax)(cpustate); break;\
case 0xe6: PREFIX86(_outal)(cpustate); break;\
case 0xe7: PREFIX86(_outax)(cpustate); break;\
case 0xe8: PREFIX86(_call_d16)(cpustate); break;\
case 0xe9: PREFIX86(_jmp_d16)(cpustate); break;\
case 0xea: PREFIX86(_jmp_far)(cpustate); break;\
case 0xeb: PREFIX86(_jmp_d8)(cpustate); break;\
case 0xec: PREFIX86(_inaldx)(cpustate); break;\
case 0xed: PREFIX86(_inaxdx)(cpustate); break;\
case 0xee: PREFIX86(_outdxal)(cpustate); break;\
case 0xef: PREFIX86(_outdxax)(cpustate); break;\
case 0xf0: PREFIX86(_lock)(cpustate); break;\
case 0xf1: PREFIX86(_invalid)(cpustate); break;\
case 0xf2: PREFIX186(_repne)(cpustate); break;\
case 0xf3: PREFIX186(_repe)(cpustate); break;\
case 0xf4: PREFIX86(_hlt)(cpustate); break;\
case 0xf5: PREFIX86(_cmc)(cpustate); break;\
case 0xf6: PREFIX86(_f6pre)(cpustate); break;\
case 0xf7: PREFIX86(_f7pre)(cpustate); break;\
case 0xf8: PREFIX86(_clc)(cpustate); break;\
case 0xf9: PREFIX86(_stc)(cpustate); break;\
case 0xfa: PREFIX86(_cli)(cpustate); break;\
case 0xfb: PREFIX86(_sti)(cpustate); break;\
case 0xfc: PREFIX86(_cld)(cpustate); break;\
case 0xfd: PREFIX86(_std)(cpustate); break;\
case 0xfe: PREFIX86(_fepre)(cpustate); break;\
case 0xff: PREFIX86(_ffpre)(cpustate); break;\
};
#else
#define TABLE186 PREFIX186(_instruction)[FETCHOP]();
#define TABLE186 PREFIX186(_instruction)[FETCHOP](cpustate);
#endif

516
src/emu/cpu/i86/table286.h
View File

@ -3,7 +3,7 @@
* at the time the same like table186.h
*/
static void (*const PREFIX286(_instruction)[256])(void) =
static void (*const PREFIX286(_instruction)[256])(i8086_state *cpustate) =
{
PREFIX86(_add_br8), /* 0x00 */
PREFIX86(_add_wr16), /* 0x01 */
@ -268,263 +268,263 @@ static void (*const PREFIX286(_instruction)[256])(void) =
#define TABLE286 \
switch(FETCHOP)\
{\
case 0x00: PREFIX86(_add_br8)(); break;\
case 0x01: PREFIX86(_add_wr16)(); break;\
case 0x02: PREFIX86(_add_r8b)(); break;\
case 0x03: PREFIX86(_add_r16w)(); break;\
case 0x04: PREFIX86(_add_ald8)(); break;\
case 0x05: PREFIX86(_add_axd16)(); break;\
case 0x06: PREFIX86(_push_es)(); break;\
case 0x07: PREFIX86(_pop_es)(); break;\
case 0x08: PREFIX86(_or_br8)(); break;\
case 0x09: PREFIX86(_or_wr16)(); break;\
case 0x0a: PREFIX86(_or_r8b)(); break;\
case 0x0b: PREFIX86(_or_r16w)(); break;\
case 0x0c: PREFIX86(_or_ald8)(); break;\
case 0x0d: PREFIX86(_or_axd16)(); break;\
case 0x0e: PREFIX86(_push_cs)(); break;\
case 0x0f: PREFIX286(_0fpre)(); break;\
case 0x10: PREFIX86(_adc_br8)(); break;\
case 0x11: PREFIX86(_adc_wr16)(); break;\
case 0x12: PREFIX86(_adc_r8b)(); break;\
case 0x13: PREFIX86(_adc_r16w)(); break;\
case 0x14: PREFIX86(_adc_ald8)(); break;\
case 0x15: PREFIX86(_adc_axd16)(); break;\
case 0x16: PREFIX86(_push_ss)(); break;\
case 0x17: PREFIX86(_pop_ss)(); break;\
case 0x18: PREFIX86(_sbb_br8)(); break;\
case 0x19: PREFIX86(_sbb_wr16)(); break;\
case 0x1a: PREFIX86(_sbb_r8b)(); break;\
case 0x1b: PREFIX86(_sbb_r16w)(); break;\
case 0x1c: PREFIX86(_sbb_ald8)(); break;\
case 0x1d: PREFIX86(_sbb_axd16)(); break;\
case 0x1e: PREFIX86(_push_ds)(); break;\
case 0x1f: PREFIX86(_pop_ds)(); break;\
case 0x20: PREFIX86(_and_br8)(); break;\
case 0x21: PREFIX86(_and_wr16)(); break;\
case 0x22: PREFIX86(_and_r8b)(); break;\
case 0x23: PREFIX86(_and_r16w)(); break;\
case 0x24: PREFIX86(_and_ald8)(); break;\
case 0x25: PREFIX86(_and_axd16)(); break;\
case 0x26: PREFIX86(_es)(); break;\
case 0x27: PREFIX86(_daa)(); break;\
case 0x28: PREFIX86(_sub_br8)(); break;\
case 0x29: PREFIX86(_sub_wr16)(); break;\
case 0x2a: PREFIX86(_sub_r8b)(); break;\
case 0x2b: PREFIX86(_sub_r16w)(); break;\
case 0x2c: PREFIX86(_sub_ald8)(); break;\
case 0x2d: PREFIX86(_sub_axd16)(); break;\
case 0x2e: PREFIX86(_cs)(); break;\
case 0x2f: PREFIX86(_das)(); break;\
case 0x30: PREFIX86(_xor_br8)(); break;\
case 0x31: PREFIX86(_xor_wr16)(); break;\
case 0x32: PREFIX86(_xor_r8b)(); break;\
case 0x33: PREFIX86(_xor_r16w)(); break;\
case 0x34: PREFIX86(_xor_ald8)(); break;\
case 0x35: PREFIX86(_xor_axd16)(); break;\
case 0x36: PREFIX86(_ss)(); break;\
case 0x37: PREFIX86(_aaa)(); break;\
case 0x38: PREFIX86(_cmp_br8)(); break;\
case 0x39: PREFIX86(_cmp_wr16)(); break;\
case 0x3a: PREFIX86(_cmp_r8b)(); break;\
case 0x3b: PREFIX86(_cmp_r16w)(); break;\
case 0x3c: PREFIX86(_cmp_ald8)(); break;\
case 0x3d: PREFIX86(_cmp_axd16)(); break;\
case 0x3e: PREFIX86(_ds)(); break;\
case 0x3f: PREFIX86(_aas)(); break;\
case 0x40: PREFIX86(_inc_ax)(); break;\
case 0x41: PREFIX86(_inc_cx)(); break;\
case 0x42: PREFIX86(_inc_dx)(); break;\
case 0x43: PREFIX86(_inc_bx)(); break;\
case 0x44: PREFIX86(_inc_sp)(); break;\
case 0x45: PREFIX86(_inc_bp)(); break;\
case 0x46: PREFIX86(_inc_si)(); break;\
case 0x47: PREFIX86(_inc_di)(); break;\
case 0x48: PREFIX86(_dec_ax)(); break;\
case 0x49: PREFIX86(_dec_cx)(); break;\
case 0x4a: PREFIX86(_dec_dx)(); break;\
case 0x4b: PREFIX86(_dec_bx)(); break;\
case 0x4c: PREFIX86(_dec_sp)(); break;\
case 0x4d: PREFIX86(_dec_bp)(); break;\
case 0x4e: PREFIX86(_dec_si)(); break;\
case 0x4f: PREFIX86(_dec_di)(); break;\
case 0x50: PREFIX86(_push_ax)(); break;\
case 0x51: PREFIX86(_push_cx)(); break;\
case 0x52: PREFIX86(_push_dx)(); break;\
case 0x53: PREFIX86(_push_bx)(); break;\
case 0x54: PREFIX86(_push_sp)(); break;\
case 0x55: PREFIX86(_push_bp)(); break;\
case 0x56: PREFIX86(_push_si)(); break;\
case 0x57: PREFIX86(_push_di)(); break;\
case 0x58: PREFIX86(_pop_ax)(); break;\
case 0x59: PREFIX86(_pop_cx)(); break;\
case 0x5a: PREFIX86(_pop_dx)(); break;\
case 0x5b: PREFIX86(_pop_bx)(); break;\
case 0x5c: PREFIX86(_pop_sp)(); break;\
case 0x5d: PREFIX86(_pop_bp)(); break;\
case 0x5e: PREFIX86(_pop_si)(); break;\
case 0x5f: PREFIX86(_pop_di)(); break;\
case 0x60: PREFIX186(_pusha)(); break;\
case 0x61: PREFIX186(_popa)(); break;\
case 0x62: PREFIX186(_bound)(); break;\
case 0x63: PREFIX286(_arpl)(); break;\
case 0x64: PREFIX286(_invalid)(); break;\
case 0x65: PREFIX286(_invalid)(); break;\
case 0x66: PREFIX286(_invalid)(); break;\
case 0x67: PREFIX286(_invalid)(); break;\
case 0x68: PREFIX186(_push_d16)(); break;\
case 0x69: PREFIX186(_imul_d16)(); break;\
case 0x6a: PREFIX186(_push_d8)(); break;\
case 0x6b: PREFIX186(_imul_d8)(); break;\
case 0x6c: PREFIX186(_insb)(); break;\
case 0x6d: PREFIX186(_insw)(); break;\
case 0x6e: PREFIX186(_outsb)(); break;\
case 0x6f: PREFIX186(_outsw)(); break;\
case 0x70: PREFIX86(_jo)(); break;\
case 0x71: PREFIX86(_jno)(); break;\
case 0x72: PREFIX86(_jb)(); break;\
case 0x73: PREFIX86(_jnb)(); break;\
case 0x74: PREFIX86(_jz)(); break;\
case 0x75: PREFIX86(_jnz)(); break;\
case 0x76: PREFIX86(_jbe)(); break;\
case 0x77: PREFIX86(_jnbe)(); break;\
case 0x78: PREFIX86(_js)(); break;\
case 0x79: PREFIX86(_jns)(); break;\
case 0x7a: PREFIX86(_jp)(); break;\
case 0x7b: PREFIX86(_jnp)(); break;\
case 0x7c: PREFIX86(_jl)(); break;\
case 0x7d: PREFIX86(_jnl)(); break;\
case 0x7e: PREFIX86(_jle)(); break;\
case 0x7f: PREFIX86(_jnle)(); break;\
case 0x80: PREFIX86(_80pre)(); break;\
case 0x81: PREFIX86(_81pre)(); break;\
case 0x82: PREFIX86(_82pre)(); break;\
case 0x83: PREFIX86(_83pre)(); break;\
case 0x84: PREFIX86(_test_br8)(); break;\
case 0x85: PREFIX86(_test_wr16)(); break;\
case 0x86: PREFIX86(_xchg_br8)(); break;\
case 0x87: PREFIX86(_xchg_wr16)(); break;\
case 0x88: PREFIX86(_mov_br8)(); break;\
case 0x89: PREFIX86(_mov_wr16)(); break;\
case 0x8a: PREFIX86(_mov_r8b)(); break;\
case 0x8b: PREFIX86(_mov_r16w)(); break;\
case 0x8c: PREFIX86(_mov_wsreg)(); break;\
case 0x8d: PREFIX86(_lea)(); break;\
case 0x8e: PREFIX86(_mov_sregw)(); break;\
case 0x8f: PREFIX86(_popw)(); break;\
case 0x90: PREFIX86(_nop)(); break;\
case 0x91: PREFIX86(_xchg_axcx)(); break;\
case 0x92: PREFIX86(_xchg_axdx)(); break;\
case 0x93: PREFIX86(_xchg_axbx)(); break;\
case 0x94: PREFIX86(_xchg_axsp)(); break;\
case 0x95: PREFIX86(_xchg_axbp)(); break;\
case 0x96: PREFIX86(_xchg_axsi)(); break;\
case 0x97: PREFIX86(_xchg_axdi)(); break;\
case 0x98: PREFIX86(_cbw)(); break;\
case 0x99: PREFIX86(_cwd)(); break;\
case 0x9a: PREFIX86(_call_far)(); break;\
case 0x9b: PREFIX86(_wait)(); break;\
case 0x9c: PREFIX86(_pushf)(); break;\
case 0x9d: PREFIX86(_popf)(); break;\
case 0x9e: PREFIX86(_sahf)(); break;\
case 0x9f: PREFIX86(_lahf)(); break;\
case 0xa0: PREFIX86(_mov_aldisp)(); break;\
case 0xa1: PREFIX86(_mov_axdisp)(); break;\
case 0xa2: PREFIX86(_mov_dispal)(); break;\
case 0xa3: PREFIX86(_mov_dispax)(); break;\
case 0xa4: PREFIX86(_movsb)(); break;\
case 0xa5: PREFIX86(_movsw)(); break;\
case 0xa6: PREFIX86(_cmpsb)(); break;\
case 0xa7: PREFIX86(_cmpsw)(); break;\
case 0xa8: PREFIX86(_test_ald8)(); break;\
case 0xa9: PREFIX86(_test_axd16)(); break;\
case 0xaa: PREFIX86(_stosb)(); break;\
case 0xab: PREFIX86(_stosw)(); break;\
case 0xac: PREFIX86(_lodsb)(); break;\
case 0xad: PREFIX86(_lodsw)(); break;\
case 0xae: PREFIX86(_scasb)(); break;\
case 0xaf: PREFIX86(_scasw)(); break;\
case 0xb0: PREFIX86(_mov_ald8)(); break;\
case 0xb1: PREFIX86(_mov_cld8)(); break;\
case 0xb2: PREFIX86(_mov_dld8)(); break;\
case 0xb3: PREFIX86(_mov_bld8)(); break;\
case 0xb4: PREFIX86(_mov_ahd8)(); break;\
case 0xb5: PREFIX86(_mov_chd8)(); break;\
case 0xb6: PREFIX86(_mov_dhd8)(); break;\
case 0xb7: PREFIX86(_mov_bhd8)(); break;\
case 0xb8: PREFIX86(_mov_axd16)(); break;\
case 0xb9: PREFIX86(_mov_cxd16)(); break;\
case 0xba: PREFIX86(_mov_dxd16)(); break;\
case 0xbb: PREFIX86(_mov_bxd16)(); break;\
case 0xbc: PREFIX86(_mov_spd16)(); break;\
case 0xbd: PREFIX86(_mov_bpd16)(); break;\
case 0xbe: PREFIX86(_mov_sid16)(); break;\
case 0xbf: PREFIX86(_mov_did16)(); break;\
case 0xc0: PREFIX186(_rotshft_bd8)(); break;\
case 0xc1: PREFIX186(_rotshft_wd8)(); break;\
case 0xc2: PREFIX86(_ret_d16)(); break;\
case 0xc3: PREFIX86(_ret)(); break;\
case 0xc4: PREFIX86(_les_dw)(); break;\
case 0xc5: PREFIX86(_lds_dw)(); break;\
case 0xc6: PREFIX86(_mov_bd8)(); break;\
case 0xc7: PREFIX86(_mov_wd16)(); break;\
case 0xc8: PREFIX186(_enter)(); break;\
case 0xc9: PREFIX186(_leave)(); break;\
case 0xca: PREFIX86(_retf_d16)(); break;\
case 0xcb: PREFIX86(_retf)(); break;\
case 0xcc: PREFIX86(_int3)(); break;\
case 0xcd: PREFIX86(_int)(); break;\
case 0xce: PREFIX86(_into)(); break;\
case 0xcf: PREFIX86(_iret)(); break;\
case 0xd0: PREFIX86(_rotshft_b)(); break;\
case 0xd1: PREFIX86(_rotshft_w)(); break;\
case 0xd2: PREFIX86(_rotshft_bcl)(); break;\
case 0xd3: PREFIX86(_rotshft_wcl)(); break;\
case 0xd4: PREFIX86(_aam)(); break;\
case 0xd5: PREFIX86(_aad)(); break;\
case 0xd6: PREFIX286(_invalid)(); break;\
case 0xd7: PREFIX86(_xlat)(); break;\
case 0xd8: PREFIX86(_escape)(); break;\
case 0xd9: PREFIX86(_escape)(); break;\
case 0xda: PREFIX86(_escape)(); break;\
case 0xdb: PREFIX86(_escape)(); break;\
case 0xdc: PREFIX86(_escape)(); break;\
case 0xdd: PREFIX86(_escape)(); break;\
case 0xde: PREFIX86(_escape)(); break;\
case 0xdf: PREFIX86(_escape)(); break;\
case 0xe0: PREFIX86(_loopne)(); break;\
case 0xe1: PREFIX86(_loope)(); break;\
case 0xe2: PREFIX86(_loop)(); break;\
case 0xe3: PREFIX86(_jcxz)(); break;\
case 0xe4: PREFIX86(_inal)(); break;\
case 0xe5: PREFIX86(_inax)(); break;\
case 0xe6: PREFIX86(_outal)(); break;\
case 0xe7: PREFIX86(_outax)(); break;\
case 0xe8: PREFIX86(_call_d16)(); break;\
case 0xe9: PREFIX86(_jmp_d16)(); break;\
case 0xea: PREFIX86(_jmp_far)(); break;\
case 0xeb: PREFIX86(_jmp_d8)(); break;\
case 0xec: PREFIX86(_inaldx)(); break;\
case 0xed: PREFIX86(_inaxdx)(); break;\
case 0xee: PREFIX86(_outdxal)(); break;\
case 0xef: PREFIX86(_outdxax)(); break;\
case 0xf0: PREFIX86(_lock)(); break;\
case 0xf1: PREFIX286(_invalid)(); break;\
case 0xf2: PREFIX186(_repne)(); break;\
case 0xf3: PREFIX186(_repe)(); break;\
case 0xf4: PREFIX86(_hlt)(); break;\
case 0xf5: PREFIX86(_cmc)(); break;\
case 0xf6: PREFIX86(_f6pre)(); break;\
case 0xf7: PREFIX86(_f7pre)(); break;\
case 0xf8: PREFIX86(_clc)(); break;\
case 0xf9: PREFIX86(_stc)(); break;\
case 0xfa: PREFIX86(_cli)(); break;\
case 0xfb: PREFIX86(_sti)(); break;\
case 0xfc: PREFIX86(_cld)(); break;\
case 0xfd: PREFIX86(_std)(); break;\
case 0xfe: PREFIX86(_fepre)(); break;\
case 0xff: PREFIX86(_ffpre)(); break;\
case 0x00: PREFIX86(_add_br8)(cpustate); break;\
case 0x01: PREFIX86(_add_wr16)(cpustate); break;\
case 0x02: PREFIX86(_add_r8b)(cpustate); break;\
case 0x03: PREFIX86(_add_r16w)(cpustate); break;\
case 0x04: PREFIX86(_add_ald8)(cpustate); break;\
case 0x05: PREFIX86(_add_axd16)(cpustate); break;\
case 0x06: PREFIX86(_push_es)(cpustate); break;\
case 0x07: PREFIX86(_pop_es)(cpustate); break;\
case 0x08: PREFIX86(_or_br8)(cpustate); break;\
case 0x09: PREFIX86(_or_wr16)(cpustate); break;\
case 0x0a: PREFIX86(_or_r8b)(cpustate); break;\
case 0x0b: PREFIX86(_or_r16w)(cpustate); break;\
case 0x0c: PREFIX86(_or_ald8)(cpustate); break;\
case 0x0d: PREFIX86(_or_axd16)(cpustate); break;\
case 0x0e: PREFIX86(_push_cs)(cpustate); break;\
case 0x0f: PREFIX286(_0fpre)(cpustate); break;\
case 0x10: PREFIX86(_adc_br8)(cpustate); break;\
case 0x11: PREFIX86(_adc_wr16)(cpustate); break;\
case 0x12: PREFIX86(_adc_r8b)(cpustate); break;\
case 0x13: PREFIX86(_adc_r16w)(cpustate); break;\
case 0x14: PREFIX86(_adc_ald8)(cpustate); break;\
case 0x15: PREFIX86(_adc_axd16)(cpustate); break;\
case 0x16: PREFIX86(_push_ss)(cpustate); break;\
case 0x17: PREFIX86(_pop_ss)(cpustate); break;\
case 0x18: PREFIX86(_sbb_br8)(cpustate); break;\
case 0x19: PREFIX86(_sbb_wr16)(cpustate); break;\
case 0x1a: PREFIX86(_sbb_r8b)(cpustate); break;\
case 0x1b: PREFIX86(_sbb_r16w)(cpustate); break;\
case 0x1c: PREFIX86(_sbb_ald8)(cpustate); break;\
case 0x1d: PREFIX86(_sbb_axd16)(cpustate); break;\
case 0x1e: PREFIX86(_push_ds)(cpustate); break;\
case 0x1f: PREFIX86(_pop_ds)(cpustate); break;\
case 0x20: PREFIX86(_and_br8)(cpustate); break;\
case 0x21: PREFIX86(_and_wr16)(cpustate); break;\
case 0x22: PREFIX86(_and_r8b)(cpustate); break;\
case 0x23: PREFIX86(_and_r16w)(cpustate); break;\
case 0x24: PREFIX86(_and_ald8)(cpustate); break;\
case 0x25: PREFIX86(_and_axd16)(cpustate); break;\
case 0x26: PREFIX86(_es)(cpustate); break;\
case 0x27: PREFIX86(_daa)(cpustate); break;\
case 0x28: PREFIX86(_sub_br8)(cpustate); break;\
case 0x29: PREFIX86(_sub_wr16)(cpustate); break;\
case 0x2a: PREFIX86(_sub_r8b)(cpustate); break;\
case 0x2b: PREFIX86(_sub_r16w)(cpustate); break;\
case 0x2c: PREFIX86(_sub_ald8)(cpustate); break;\
case 0x2d: PREFIX86(_sub_axd16)(cpustate); break;\
case 0x2e: PREFIX86(_cs)(cpustate); break;\
case 0x2f: PREFIX86(_das)(cpustate); break;\
case 0x30: PREFIX86(_xor_br8)(cpustate); break;\
case 0x31: PREFIX86(_xor_wr16)(cpustate); break;\
case 0x32: PREFIX86(_xor_r8b)(cpustate); break;\
case 0x33: PREFIX86(_xor_r16w)(cpustate); break;\
case 0x34: PREFIX86(_xor_ald8)(cpustate); break;\
case 0x35: PREFIX86(_xor_axd16)(cpustate); break;\
case 0x36: PREFIX86(_ss)(cpustate); break;\
case 0x37: PREFIX86(_aaa)(cpustate); break;\
case 0x38: PREFIX86(_cmp_br8)(cpustate); break;\
case 0x39: PREFIX86(_cmp_wr16)(cpustate); break;\
case 0x3a: PREFIX86(_cmp_r8b)(cpustate); break;\
case 0x3b: PREFIX86(_cmp_r16w)(cpustate); break;\
case 0x3c: PREFIX86(_cmp_ald8)(cpustate); break;\
case 0x3d: PREFIX86(_cmp_axd16)(cpustate); break;\
case 0x3e: PREFIX86(_ds)(cpustate); break;\
case 0x3f: PREFIX86(_aas)(cpustate); break;\
case 0x40: PREFIX86(_inc_ax)(cpustate); break;\
case 0x41: PREFIX86(_inc_cx)(cpustate); break;\
case 0x42: PREFIX86(_inc_dx)(cpustate); break;\
case 0x43: PREFIX86(_inc_bx)(cpustate); break;\
case 0x44: PREFIX86(_inc_sp)(cpustate); break;\
case 0x45: PREFIX86(_inc_bp)(cpustate); break;\
case 0x46: PREFIX86(_inc_si)(cpustate); break;\
case 0x47: PREFIX86(_inc_di)(cpustate); break;\
case 0x48: PREFIX86(_dec_ax)(cpustate); break;\
case 0x49: PREFIX86(_dec_cx)(cpustate); break;\
case 0x4a: PREFIX86(_dec_dx)(cpustate); break;\
case 0x4b: PREFIX86(_dec_bx)(cpustate); break;\
case 0x4c: PREFIX86(_dec_sp)(cpustate); break;\
case 0x4d: PREFIX86(_dec_bp)(cpustate); break;\
case 0x4e: PREFIX86(_dec_si)(cpustate); break;\
case 0x4f: PREFIX86(_dec_di)(cpustate); break;\
case 0x50: PREFIX86(_push_ax)(cpustate); break;\
case 0x51: PREFIX86(_push_cx)(cpustate); break;\
case 0x52: PREFIX86(_push_dx)(cpustate); break;\
case 0x53: PREFIX86(_push_bx)(cpustate); break;\
case 0x54: PREFIX86(_push_sp)(cpustate); break;\
case 0x55: PREFIX86(_push_bp)(cpustate); break;\
case 0x56: PREFIX86(_push_si)(cpustate); break;\
case 0x57: PREFIX86(_push_di)(cpustate); break;\
case 0x58: PREFIX86(_pop_ax)(cpustate); break;\
case 0x59: PREFIX86(_pop_cx)(cpustate); break;\
case 0x5a: PREFIX86(_pop_dx)(cpustate); break;\
case 0x5b: PREFIX86(_pop_bx)(cpustate); break;\
case 0x5c: PREFIX86(_pop_sp)(cpustate); break;\
case 0x5d: PREFIX86(_pop_bp)(cpustate); break;\
case 0x5e: PREFIX86(_pop_si)(cpustate); break;\
case 0x5f: PREFIX86(_pop_di)(cpustate); break;\
case 0x60: PREFIX186(_pusha)(cpustate); break;\
case 0x61: PREFIX186(_popa)(cpustate); break;\
case 0x62: PREFIX186(_bound)(cpustate); break;\
case 0x63: PREFIX286(_arpl)(cpustate); break;\
case 0x64: PREFIX286(_invalid)(cpustate); break;\
case 0x65: PREFIX286(_invalid)(cpustate); break;\
case 0x66: PREFIX286(_invalid)(cpustate); break;\
case 0x67: PREFIX286(_invalid)(cpustate); break;\
case 0x68: PREFIX186(_push_d16)(cpustate); break;\
case 0x69: PREFIX186(_imul_d16)(cpustate); break;\
case 0x6a: PREFIX186(_push_d8)(cpustate); break;\
case 0x6b: PREFIX186(_imul_d8)(cpustate); break;\
case 0x6c: PREFIX186(_insb)(cpustate); break;\
case 0x6d: PREFIX186(_insw)(cpustate); break;\
case 0x6e: PREFIX186(_outsb)(cpustate); break;\
case 0x6f: PREFIX186(_outsw)(cpustate); break;\
case 0x70: PREFIX86(_jo)(cpustate); break;\
case 0x71: PREFIX86(_jno)(cpustate); break;\
case 0x72: PREFIX86(_jb)(cpustate); break;\
case 0x73: PREFIX86(_jnb)(cpustate); break;\
case 0x74: PREFIX86(_jz)(cpustate); break;\
case 0x75: PREFIX86(_jnz)(cpustate); break;\
case 0x76: PREFIX86(_jbe)(cpustate); break;\
case 0x77: PREFIX86(_jnbe)(cpustate); break;\
case 0x78: PREFIX86(_js)(cpustate); break;\
case 0x79: PREFIX86(_jns)(cpustate); break;\
case 0x7a: PREFIX86(_jp)(cpustate); break;\
case 0x7b: PREFIX86(_jnp)(cpustate); break;\
case 0x7c: PREFIX86(_jl)(cpustate); break;\
case 0x7d: PREFIX86(_jnl)(cpustate); break;\
case 0x7e: PREFIX86(_jle)(cpustate); break;\
case 0x7f: PREFIX86(_jnle)(cpustate); break;\
case 0x80: PREFIX86(_80pre)(cpustate); break;\
case 0x81: PREFIX86(_81pre)(cpustate); break;\
case 0x82: PREFIX86(_82pre)(cpustate); break;\
case 0x83: PREFIX86(_83pre)(cpustate); break;\
case 0x84: PREFIX86(_test_br8)(cpustate); break;\
case 0x85: PREFIX86(_test_wr16)(cpustate); break;\
case 0x86: PREFIX86(_xchg_br8)(cpustate); break;\
case 0x87: PREFIX86(_xchg_wr16)(cpustate); break;\
case 0x88: PREFIX86(_mov_br8)(cpustate); break;\
case 0x89: PREFIX86(_mov_wr16)(cpustate); break;\
case 0x8a: PREFIX86(_mov_r8b)(cpustate); break;\
case 0x8b: PREFIX86(_mov_r16w)(cpustate); break;\
case 0x8c: PREFIX86(_mov_wsreg)(cpustate); break;\
case 0x8d: PREFIX86(_lea)(cpustate); break;\
case 0x8e: PREFIX86(_mov_sregw)(cpustate); break;\
case 0x8f: PREFIX86(_popw)(cpustate); break;\
case 0x90: PREFIX86(_nop)(cpustate); break;\
case 0x91: PREFIX86(_xchg_axcx)(cpustate); break;\
case 0x92: PREFIX86(_xchg_axdx)(cpustate); break;\
case 0x93: PREFIX86(_xchg_axbx)(cpustate); break;\
case 0x94: PREFIX86(_xchg_axsp)(cpustate); break;\
case 0x95: PREFIX86(_xchg_axbp)(cpustate); break;\
case 0x96: PREFIX86(_xchg_axsi)(cpustate); break;\
case 0x97: PREFIX86(_xchg_axdi)(cpustate); break;\
case 0x98: PREFIX86(_cbw)(cpustate); break;\
case 0x99: PREFIX86(_cwd)(cpustate); break;\
case 0x9a: PREFIX86(_call_far)(cpustate); break;\
case 0x9b: PREFIX86(_wait)(cpustate); break;\
case 0x9c: PREFIX86(_pushf)(cpustate); break;\
case 0x9d: PREFIX86(_popf)(cpustate); break;\
case 0x9e: PREFIX86(_sahf)(cpustate); break;\
case 0x9f: PREFIX86(_lahf)(cpustate); break;\
case 0xa0: PREFIX86(_mov_aldisp)(cpustate); break;\
case 0xa1: PREFIX86(_mov_axdisp)(cpustate); break;\
case 0xa2: PREFIX86(_mov_dispal)(cpustate); break;\
case 0xa3: PREFIX86(_mov_dispax)(cpustate); break;\
case 0xa4: PREFIX86(_movsb)(cpustate); break;\
case 0xa5: PREFIX86(_movsw)(cpustate); break;\
case 0xa6: PREFIX86(_cmpsb)(cpustate); break;\
case 0xa7: PREFIX86(_cmpsw)(cpustate); break;\
case 0xa8: PREFIX86(_test_ald8)(cpustate); break;\
case 0xa9: PREFIX86(_test_axd16)(cpustate); break;\
case 0xaa: PREFIX86(_stosb)(cpustate); break;\
case 0xab: PREFIX86(_stosw)(cpustate); break;\
case 0xac: PREFIX86(_lodsb)(cpustate); break;\
case 0xad: PREFIX86(_lodsw)(cpustate); break;\
case 0xae: PREFIX86(_scasb)(cpustate); break;\
case 0xaf: PREFIX86(_scasw)(cpustate); break;\
case 0xb0: PREFIX86(_mov_ald8)(cpustate); break;\
case 0xb1: PREFIX86(_mov_cld8)(cpustate); break;\
case 0xb2: PREFIX86(_mov_dld8)(cpustate); break;\
case 0xb3: PREFIX86(_mov_bld8)(cpustate); break;\
case 0xb4: PREFIX86(_mov_ahd8)(cpustate); break;\
case 0xb5: PREFIX86(_mov_chd8)(cpustate); break;\
case 0xb6: PREFIX86(_mov_dhd8)(cpustate); break;\
case 0xb7: PREFIX86(_mov_bhd8)(cpustate); break;\
case 0xb8: PREFIX86(_mov_axd16)(cpustate); break;\
case 0xb9: PREFIX86(_mov_cxd16)(cpustate); break;\
case 0xba: PREFIX86(_mov_dxd16)(cpustate); break;\
case 0xbb: PREFIX86(_mov_bxd16)(cpustate); break;\
case 0xbc: PREFIX86(_mov_spd16)(cpustate); break;\
case 0xbd: PREFIX86(_mov_bpd16)(cpustate); break;\
case 0xbe: PREFIX86(_mov_sid16)(cpustate); break;\
case 0xbf: PREFIX86(_mov_did16)(cpustate); break;\
case 0xc0: PREFIX186(_rotshft_bd8)(cpustate); break;\
case 0xc1: PREFIX186(_rotshft_wd8)(cpustate); break;\
case 0xc2: PREFIX86(_ret_d16)(cpustate); break;\
case 0xc3: PREFIX86(_ret)(cpustate); break;\
case 0xc4: PREFIX86(_les_dw)(cpustate); break;\
case 0xc5: PREFIX86(_lds_dw)(cpustate); break;\
case 0xc6: PREFIX86(_mov_bd8)(cpustate); break;\
case 0xc7: PREFIX86(_mov_wd16)(cpustate); break;\
case 0xc8: PREFIX186(_enter)(cpustate); break;\
case 0xc9: PREFIX186(_leave)(cpustate); break;\
case 0xca: PREFIX86(_retf_d16)(cpustate); break;\
case 0xcb: PREFIX86(_retf)(cpustate); break;\
case 0xcc: PREFIX86(_int3)(cpustate); break;\
case 0xcd: PREFIX86(_int)(cpustate); break;\
case 0xce: PREFIX86(_into)(cpustate); break;\
case 0xcf: PREFIX86(_iret)(cpustate); break;\
case 0xd0: PREFIX86(_rotshft_b)(cpustate); break;\
case 0xd1: PREFIX86(_rotshft_w)(cpustate); break;\
case 0xd2: PREFIX86(_rotshft_bcl)(cpustate); break;\
case 0xd3: PREFIX86(_rotshft_wcl)(cpustate); break;\
case 0xd4: PREFIX86(_aam)(cpustate); break;\
case 0xd5: PREFIX86(_aad)(cpustate); break;\
case 0xd6: PREFIX286(_invalid)(cpustate); break;\
case 0xd7: PREFIX86(_xlat)(cpustate); break;\
case 0xd8: PREFIX86(_escape)(cpustate); break;\
case 0xd9: PREFIX86(_escape)(cpustate); break;\
case 0xda: PREFIX86(_escape)(cpustate); break;\
case 0xdb: PREFIX86(_escape)(cpustate); break;\
case 0xdc: PREFIX86(_escape)(cpustate); break;\
case 0xdd: PREFIX86(_escape)(cpustate); break;\
case 0xde: PREFIX86(_escape)(cpustate); break;\
case 0xdf: PREFIX86(_escape)(cpustate); break;\
case 0xe0: PREFIX86(_loopne)(cpustate); break;\
case 0xe1: PREFIX86(_loope)(cpustate); break;\
case 0xe2: PREFIX86(_loop)(cpustate); break;\
case 0xe3: PREFIX86(_jcxz)(cpustate); break;\
case 0xe4: PREFIX86(_inal)(cpustate); break;\
case 0xe5: PREFIX86(_inax)(cpustate); break;\
case 0xe6: PREFIX86(_outal)(cpustate); break;\
case 0xe7: PREFIX86(_outax)(cpustate); break;\
case 0xe8: PREFIX86(_call_d16)(cpustate); break;\
case 0xe9: PREFIX86(_jmp_d16)(cpustate); break;\
case 0xea: PREFIX86(_jmp_far)(cpustate); break;\
case 0xeb: PREFIX86(_jmp_d8)(cpustate); break;\
case 0xec: PREFIX86(_inaldx)(cpustate); break;\
case 0xed: PREFIX86(_inaxdx)(cpustate); break;\
case 0xee: PREFIX86(_outdxal)(cpustate); break;\
case 0xef: PREFIX86(_outdxax)(cpustate); break;\
case 0xf0: PREFIX86(_lock)(cpustate); break;\
case 0xf1: PREFIX286(_invalid)(cpustate); break;\
case 0xf2: PREFIX186(_repne)(cpustate); break;\
case 0xf3: PREFIX186(_repe)(cpustate); break;\
case 0xf4: PREFIX86(_hlt)(cpustate); break;\
case 0xf5: PREFIX86(_cmc)(cpustate); break;\
case 0xf6: PREFIX86(_f6pre)(cpustate); break;\
case 0xf7: PREFIX86(_f7pre)(cpustate); break;\
case 0xf8: PREFIX86(_clc)(cpustate); break;\
case 0xf9: PREFIX86(_stc)(cpustate); break;\
case 0xfa: PREFIX86(_cli)(cpustate); break;\
case 0xfb: PREFIX86(_sti)(cpustate); break;\
case 0xfc: PREFIX86(_cld)(cpustate); break;\
case 0xfd: PREFIX86(_std)(cpustate); break;\
case 0xfe: PREFIX86(_fepre)(cpustate); break;\
case 0xff: PREFIX86(_ffpre)(cpustate); break;\
};
#else
#define TABLE286 PREFIX286(_instruction)[FETCHOP]();
#define TABLE286 PREFIX286(_instruction)[FETCHOP](cpustate);
#endif

516
src/emu/cpu/i86/table86.h
View File

@ -1,4 +1,4 @@
static void (*const PREFIX86(_instruction)[256])(void) =
static void (*const PREFIX86(_instruction)[256])(i8086_state *cpustate) =
{
PREFIX86(_add_br8), /* 0x00 */
PREFIX86(_add_wr16), /* 0x01 */
@ -263,263 +263,263 @@ static void (*const PREFIX86(_instruction)[256])(void) =
#define TABLE86 \
switch(FETCHOP)\
{\
case 0x00: PREFIX86(_add_br8)(); break;\
case 0x01: PREFIX86(_add_wr16)(); break;\
case 0x02: PREFIX86(_add_r8b)(); break;\
case 0x03: PREFIX86(_add_r16w)(); break;\
case 0x04: PREFIX86(_add_ald8)(); break;\
case 0x05: PREFIX86(_add_axd16)(); break;\
case 0x06: PREFIX86(_push_es)(); break;\
case 0x07: PREFIX86(_pop_es)(); break;\
case 0x08: PREFIX86(_or_br8)(); break;\
case 0x09: PREFIX86(_or_wr16)(); break;\
case 0x0a: PREFIX86(_or_r8b)(); break;\
case 0x0b: PREFIX86(_or_r16w)(); break;\
case 0x0c: PREFIX86(_or_ald8)(); break;\
case 0x0d: PREFIX86(_or_axd16)(); break;\
case 0x0e: PREFIX86(_push_cs)(); break;\
case 0x0f: PREFIX86(_invalid)(); break;\
case 0x10: PREFIX86(_adc_br8)(); break;\
case 0x11: PREFIX86(_adc_wr16)(); break;\
case 0x12: PREFIX86(_adc_r8b)(); break;\
case 0x13: PREFIX86(_adc_r16w)(); break;\
case 0x14: PREFIX86(_adc_ald8)(); break;\
case 0x15: PREFIX86(_adc_axd16)(); break;\
case 0x16: PREFIX86(_push_ss)(); break;\
case 0x17: PREFIX86(_pop_ss)(); break;\
case 0x18: PREFIX86(_sbb_br8)(); break;\
case 0x19: PREFIX86(_sbb_wr16)(); break;\
case 0x1a: PREFIX86(_sbb_r8b)(); break;\
case 0x1b: PREFIX86(_sbb_r16w)(); break;\
case 0x1c: PREFIX86(_sbb_ald8)(); break;\
case 0x1d: PREFIX86(_sbb_axd16)(); break;\
case 0x1e: PREFIX86(_push_ds)(); break;\
case 0x1f: PREFIX86(_pop_ds)(); break;\
case 0x20: PREFIX86(_and_br8)(); break;\
case 0x21: PREFIX86(_and_wr16)(); break;\
case 0x22: PREFIX86(_and_r8b)(); break;\
case 0x23: PREFIX86(_and_r16w)(); break;\
case 0x24: PREFIX86(_and_ald8)(); break;\
case 0x25: PREFIX86(_and_axd16)(); break;\
case 0x26: PREFIX86(_es)(); break;\
case 0x27: PREFIX86(_daa)(); break;\
case 0x28: PREFIX86(_sub_br8)(); break;\
case 0x29: PREFIX86(_sub_wr16)(); break;\
case 0x2a: PREFIX86(_sub_r8b)(); break;\
case 0x2b: PREFIX86(_sub_r16w)(); break;\
case 0x2c: PREFIX86(_sub_ald8)(); break;\
case 0x2d: PREFIX86(_sub_axd16)(); break;\
case 0x2e: PREFIX86(_cs)(); break;\
case 0x2f: PREFIX86(_das)(); break;\
case 0x30: PREFIX86(_xor_br8)(); break;\
case 0x31: PREFIX86(_xor_wr16)(); break;\
case 0x32: PREFIX86(_xor_r8b)(); break;\
case 0x33: PREFIX86(_xor_r16w)(); break;\
case 0x34: PREFIX86(_xor_ald8)(); break;\
case 0x35: PREFIX86(_xor_axd16)(); break;\
case 0x36: PREFIX86(_ss)(); break;\
case 0x37: PREFIX86(_aaa)(); break;\
case 0x38: PREFIX86(_cmp_br8)(); break;\
case 0x39: PREFIX86(_cmp_wr16)(); break;\
case 0x3a: PREFIX86(_cmp_r8b)(); break;\
case 0x3b: PREFIX86(_cmp_r16w)(); break;\
case 0x3c: PREFIX86(_cmp_ald8)(); break;\
case 0x3d: PREFIX86(_cmp_axd16)(); break;\
case 0x3e: PREFIX86(_ds)(); break;\
case 0x3f: PREFIX86(_aas)(); break;\
case 0x40: PREFIX86(_inc_ax)(); break;\
case 0x41: PREFIX86(_inc_cx)(); break;\
case 0x42: PREFIX86(_inc_dx)(); break;\
case 0x43: PREFIX86(_inc_bx)(); break;\
case 0x44: PREFIX86(_inc_sp)(); break;\
case 0x45: PREFIX86(_inc_bp)(); break;\
case 0x46: PREFIX86(_inc_si)(); break;\
case 0x47: PREFIX86(_inc_di)(); break;\
case 0x48: PREFIX86(_dec_ax)(); break;\
case 0x49: PREFIX86(_dec_cx)(); break;\
case 0x4a: PREFIX86(_dec_dx)(); break;\
case 0x4b: PREFIX86(_dec_bx)(); break;\
case 0x4c: PREFIX86(_dec_sp)(); break;\
case 0x4d: PREFIX86(_dec_bp)(); break;\
case 0x4e: PREFIX86(_dec_si)(); break;\
case 0x4f: PREFIX86(_dec_di)(); break;\
case 0x50: PREFIX86(_push_ax)(); break;\
case 0x51: PREFIX86(_push_cx)(); break;\
case 0x52: PREFIX86(_push_dx)(); break;\
case 0x53: PREFIX86(_push_bx)(); break;\
case 0x54: PREFIX86(_push_sp)(); break;\
case 0x55: PREFIX86(_push_bp)(); break;\
case 0x56: PREFIX86(_push_si)(); break;\
case 0x57: PREFIX86(_push_di)(); break;\
case 0x58: PREFIX86(_pop_ax)(); break;\
case 0x59: PREFIX86(_pop_cx)(); break;\
case 0x5a: PREFIX86(_pop_dx)(); break;\
case 0x5b: PREFIX86(_pop_bx)(); break;\
case 0x5c: PREFIX86(_pop_sp)(); break;\
case 0x5d: PREFIX86(_pop_bp)(); break;\
case 0x5e: PREFIX86(_pop_si)(); break;\
case 0x5f: PREFIX86(_pop_di)(); break;\
case 0x60: PREFIX86(_invalid)(); break;\
case 0x61: PREFIX86(_invalid)(); break;\
case 0x62: PREFIX86(_invalid)(); break;\
case 0x63: PREFIX86(_invalid)(); break;\
case 0x64: PREFIX86(_invalid)(); break;\
case 0x65: PREFIX86(_invalid)(); break;\
case 0x66: PREFIX86(_invalid)(); break;\
case 0x67: PREFIX86(_invalid)(); break;\
case 0x68: PREFIX86(_invalid)(); break;\
case 0x69: PREFIX86(_invalid)(); break;\
case 0x6a: PREFIX86(_invalid)(); break;\
case 0x6b: PREFIX86(_invalid)(); break;\
case 0x6c: PREFIX86(_invalid)(); break;\
case 0x6d: PREFIX86(_invalid)(); break;\
case 0x6e: PREFIX86(_invalid)(); break;\
case 0x6f: PREFIX86(_invalid)(); break;\
case 0x70: PREFIX86(_jo)(); break;\
case 0x71: PREFIX86(_jno)(); break;\
case 0x72: PREFIX86(_jb)(); break;\
case 0x73: PREFIX86(_jnb)(); break;\
case 0x74: PREFIX86(_jz)(); break;\
case 0x75: PREFIX86(_jnz)(); break;\
case 0x76: PREFIX86(_jbe)(); break;\
case 0x77: PREFIX86(_jnbe)(); break;\
case 0x78: PREFIX86(_js)(); break;\
case 0x79: PREFIX86(_jns)(); break;\
case 0x7a: PREFIX86(_jp)(); break;\
case 0x7b: PREFIX86(_jnp)(); break;\
case 0x7c: PREFIX86(_jl)(); break;\
case 0x7d: PREFIX86(_jnl)(); break;\
case 0x7e: PREFIX86(_jle)(); break;\
case 0x7f: PREFIX86(_jnle)(); break;\
case 0x80: PREFIX86(_80pre)(); break;\
case 0x81: PREFIX86(_81pre)(); break;\
case 0x82: PREFIX86(_82pre)(); break;\
case 0x83: PREFIX86(_83pre)(); break;\
case 0x84: PREFIX86(_test_br8)(); break;\
case 0x85: PREFIX86(_test_wr16)(); break;\
case 0x86: PREFIX86(_xchg_br8)(); break;\
case 0x87: PREFIX86(_xchg_wr16)(); break;\
case 0x88: PREFIX86(_mov_br8)(); break;\
case 0x89: PREFIX86(_mov_wr16)(); break;\
case 0x8a: PREFIX86(_mov_r8b)(); break;\
case 0x8b: PREFIX86(_mov_r16w)(); break;\
case 0x8c: PREFIX86(_mov_wsreg)(); break;\
case 0x8d: PREFIX86(_lea)(); break;\
case 0x8e: PREFIX86(_mov_sregw)(); break;\
case 0x8f: PREFIX86(_popw)(); break;\
case 0x90: PREFIX86(_nop)(); break;\
case 0x91: PREFIX86(_xchg_axcx)(); break;\
case 0x92: PREFIX86(_xchg_axdx)(); break;\
case 0x93: PREFIX86(_xchg_axbx)(); break;\
case 0x94: PREFIX86(_xchg_axsp)(); break;\
case 0x95: PREFIX86(_xchg_axbp)(); break;\
case 0x96: PREFIX86(_xchg_axsi)(); break;\
case 0x97: PREFIX86(_xchg_axdi)(); break;\
case 0x98: PREFIX86(_cbw)(); break;\
case 0x99: PREFIX86(_cwd)(); break;\
case 0x9a: PREFIX86(_call_far)(); break;\
case 0x9b: PREFIX86(_wait)(); break;\
case 0x9c: PREFIX86(_pushf)(); break;\
case 0x9d: PREFIX86(_popf)(); break;\
case 0x9e: PREFIX86(_sahf)(); break;\
case 0x9f: PREFIX86(_lahf)(); break;\
case 0xa0: PREFIX86(_mov_aldisp)(); break;\
case 0xa1: PREFIX86(_mov_axdisp)(); break;\
case 0xa2: PREFIX86(_mov_dispal)(); break;\
case 0xa3: PREFIX86(_mov_dispax)(); break;\
case 0xa4: PREFIX86(_movsb)(); break;\
case 0xa5: PREFIX86(_movsw)(); break;\
case 0xa6: PREFIX86(_cmpsb)(); break;\
case 0xa7: PREFIX86(_cmpsw)(); break;\
case 0xa8: PREFIX86(_test_ald8)(); break;\
case 0xa9: PREFIX86(_test_axd16)(); break;\
case 0xaa: PREFIX86(_stosb)(); break;\
case 0xab: PREFIX86(_stosw)(); break;\
case 0xac: PREFIX86(_lodsb)(); break;\
case 0xad: PREFIX86(_lodsw)(); break;\
case 0xae: PREFIX86(_scasb)(); break;\
case 0xaf: PREFIX86(_scasw)(); break;\
case 0xb0: PREFIX86(_mov_ald8)(); break;\
case 0xb1: PREFIX86(_mov_cld8)(); break;\
case 0xb2: PREFIX86(_mov_dld8)(); break;\
case 0xb3: PREFIX86(_mov_bld8)(); break;\
case 0xb4: PREFIX86(_mov_ahd8)(); break;\
case 0xb5: PREFIX86(_mov_chd8)(); break;\
case 0xb6: PREFIX86(_mov_dhd8)(); break;\
case 0xb7: PREFIX86(_mov_bhd8)(); break;\
case 0xb8: PREFIX86(_mov_axd16)(); break;\
case 0xb9: PREFIX86(_mov_cxd16)(); break;\
case 0xba: PREFIX86(_mov_dxd16)(); break;\
case 0xbb: PREFIX86(_mov_bxd16)(); break;\
case 0xbc: PREFIX86(_mov_spd16)(); break;\
case 0xbd: PREFIX86(_mov_bpd16)(); break;\
case 0xbe: PREFIX86(_mov_sid16)(); break;\
case 0xbf: PREFIX86(_mov_did16)(); break;\
case 0xc0: PREFIX86(_invalid)(); break;\
case 0xc1: PREFIX86(_invalid)(); break;\
case 0xc2: PREFIX86(_ret_d16)(); break;\
case 0xc3: PREFIX86(_ret)(); break;\
case 0xc4: PREFIX86(_les_dw)(); break;\
case 0xc5: PREFIX86(_lds_dw)(); break;\
case 0xc6: PREFIX86(_mov_bd8)(); break;\
case 0xc7: PREFIX86(_mov_wd16)(); break;\
case 0xc8: PREFIX86(_invalid)(); break;\
case 0xc9: PREFIX86(_invalid)(); break;\
case 0xca: PREFIX86(_retf_d16)(); break;\
case 0xcb: PREFIX86(_retf)(); break;\
case 0xcc: PREFIX86(_int3)(); break;\
case 0xcd: PREFIX86(_int)(); break;\
case 0xce: PREFIX86(_into)(); break;\
case 0xcf: PREFIX86(_iret)(); break;\
case 0xd0: PREFIX86(_rotshft_b)(); break;\
case 0xd1: PREFIX86(_rotshft_w)(); break;\
case 0xd2: PREFIX86(_rotshft_bcl)(); break;\
case 0xd3: PREFIX86(_rotshft_wcl)(); break;\
case 0xd4: PREFIX86(_aam)(); break;\
case 0xd5: PREFIX86(_aad)(); break;\
case 0xd6: PREFIX86(_invalid)(); break;\
case 0xd7: PREFIX86(_xlat)(); break;\
case 0xd8: PREFIX86(_escape)(); break;\
case 0xd9: PREFIX86(_escape)(); break;\
case 0xda: PREFIX86(_escape)(); break;\
case 0xdb: PREFIX86(_escape)(); break;\
case 0xdc: PREFIX86(_escape)(); break;\
case 0xdd: PREFIX86(_escape)(); break;\
case 0xde: PREFIX86(_escape)(); break;\
case 0xdf: PREFIX86(_escape)(); break;\
case 0xe0: PREFIX86(_loopne)(); break;\
case 0xe1: PREFIX86(_loope)(); break;\
case 0xe2: PREFIX86(_loop)(); break;\
case 0xe3: PREFIX86(_jcxz)(); break;\
case 0xe4: PREFIX86(_inal)(); break;\
case 0xe5: PREFIX86(_inax)(); break;\
case 0xe6: PREFIX86(_outal)(); break;\
case 0xe7: PREFIX86(_outax)(); break;\
case 0xe8: PREFIX86(_call_d16)(); break;\
case 0xe9: PREFIX86(_jmp_d16)(); break;\
case 0xea: PREFIX86(_jmp_far)(); break;\
case 0xeb: PREFIX86(_jmp_d8)(); break;\
case 0xec: PREFIX86(_inaldx)(); break;\
case 0xed: PREFIX86(_inaxdx)(); break;\
case 0xee: PREFIX86(_outdxal)(); break;\
case 0xef: PREFIX86(_outdxax)(); break;\
case 0xf0: PREFIX86(_lock)(); break;\
case 0xf1: PREFIX86(_invalid)(); break;\
case 0xf2: PREFIX86(_repne)(); break;\
case 0xf3: PREFIX86(_repe)(); break;\
case 0xf4: PREFIX86(_hlt)(); break;\
case 0xf5: PREFIX86(_cmc)(); break;\
case 0xf6: PREFIX86(_f6pre)(); break;\
case 0xf7: PREFIX86(_f7pre)(); break;\
case 0xf8: PREFIX86(_clc)(); break;\
case 0xf9: PREFIX86(_stc)(); break;\
case 0xfa: PREFIX86(_cli)(); break;\
case 0xfb: PREFIX86(_sti)(); break;\
case 0xfc: PREFIX86(_cld)(); break;\
case 0xfd: PREFIX86(_std)(); break;\
case 0xfe: PREFIX86(_fepre)(); break;\
case 0xff: PREFIX86(_ffpre)(); break;\
case 0x00: PREFIX86(_add_br8)(cpustate); break;\
case 0x01: PREFIX86(_add_wr16)(cpustate); break;\
case 0x02: PREFIX86(_add_r8b)(cpustate); break;\
case 0x03: PREFIX86(_add_r16w)(cpustate); break;\
case 0x04: PREFIX86(_add_ald8)(cpustate); break;\
case 0x05: PREFIX86(_add_axd16)(cpustate); break;\
case 0x06: PREFIX86(_push_es)(cpustate); break;\
case 0x07: PREFIX86(_pop_es)(cpustate); break;\
case 0x08: PREFIX86(_or_br8)(cpustate); break;\
case 0x09: PREFIX86(_or_wr16)(cpustate); break;\
case 0x0a: PREFIX86(_or_r8b)(cpustate); break;\
case 0x0b: PREFIX86(_or_r16w)(cpustate); break;\
case 0x0c: PREFIX86(_or_ald8)(cpustate); break;\
case 0x0d: PREFIX86(_or_axd16)(cpustate); break;\
case 0x0e: PREFIX86(_push_cs)(cpustate); break;\
case 0x0f: PREFIX86(_invalid)(cpustate); break;\
case 0x10: PREFIX86(_adc_br8)(cpustate); break;\
case 0x11: PREFIX86(_adc_wr16)(cpustate); break;\
case 0x12: PREFIX86(_adc_r8b)(cpustate); break;\
case 0x13: PREFIX86(_adc_r16w)(cpustate); break;\
case 0x14: PREFIX86(_adc_ald8)(cpustate); break;\
case 0x15: PREFIX86(_adc_axd16)(cpustate); break;\
case 0x16: PREFIX86(_push_ss)(cpustate); break;\
case 0x17: PREFIX86(_pop_ss)(cpustate); break;\
case 0x18: PREFIX86(_sbb_br8)(cpustate); break;\
case 0x19: PREFIX86(_sbb_wr16)(cpustate); break;\
case 0x1a: PREFIX86(_sbb_r8b)(cpustate); break;\
case 0x1b: PREFIX86(_sbb_r16w)(cpustate); break;\
case 0x1c: PREFIX86(_sbb_ald8)(cpustate); break;\
case 0x1d: PREFIX86(_sbb_axd16)(cpustate); break;\
case 0x1e: PREFIX86(_push_ds)(cpustate); break;\
case 0x1f: PREFIX86(_pop_ds)(cpustate); break;\
case 0x20: PREFIX86(_and_br8)(cpustate); break;\
case 0x21: PREFIX86(_and_wr16)(cpustate); break;\
case 0x22: PREFIX86(_and_r8b)(cpustate); break;\
case 0x23: PREFIX86(_and_r16w)(cpustate); break;\
case 0x24: PREFIX86(_and_ald8)(cpustate); break;\
case 0x25: PREFIX86(_and_axd16)(cpustate); break;\
case 0x26: PREFIX86(_es)(cpustate); break;\
case 0x27: PREFIX86(_daa)(cpustate); break;\
case 0x28: PREFIX86(_sub_br8)(cpustate); break;\
case 0x29: PREFIX86(_sub_wr16)(cpustate); break;\
case 0x2a: PREFIX86(_sub_r8b)(cpustate); break;\
case 0x2b: PREFIX86(_sub_r16w)(cpustate); break;\
case 0x2c: PREFIX86(_sub_ald8)(cpustate); break;\
case 0x2d: PREFIX86(_sub_axd16)(cpustate); break;\
case 0x2e: PREFIX86(_cs)(cpustate); break;\
case 0x2f: PREFIX86(_das)(cpustate); break;\
case 0x30: PREFIX86(_xor_br8)(cpustate); break;\
case 0x31: PREFIX86(_xor_wr16)(cpustate); break;\
case 0x32: PREFIX86(_xor_r8b)(cpustate); break;\
case 0x33: PREFIX86(_xor_r16w)(cpustate); break;\
case 0x34: PREFIX86(_xor_ald8)(cpustate); break;\
case 0x35: PREFIX86(_xor_axd16)(cpustate); break;\
case 0x36: PREFIX86(_ss)(cpustate); break;\
case 0x37: PREFIX86(_aaa)(cpustate); break;\
case 0x38: PREFIX86(_cmp_br8)(cpustate); break;\
case 0x39: PREFIX86(_cmp_wr16)(cpustate); break;\
case 0x3a: PREFIX86(_cmp_r8b)(cpustate); break;\
case 0x3b: PREFIX86(_cmp_r16w)(cpustate); break;\
case 0x3c: PREFIX86(_cmp_ald8)(cpustate); break;\
case 0x3d: PREFIX86(_cmp_axd16)(cpustate); break;\
case 0x3e: PREFIX86(_ds)(cpustate); break;\
case 0x3f: PREFIX86(_aas)(cpustate); break;\
case 0x40: PREFIX86(_inc_ax)(cpustate); break;\
case 0x41: PREFIX86(_inc_cx)(cpustate); break;\
case 0x42: PREFIX86(_inc_dx)(cpustate); break;\
case 0x43: PREFIX86(_inc_bx)(cpustate); break;\
case 0x44: PREFIX86(_inc_sp)(cpustate); break;\
case 0x45: PREFIX86(_inc_bp)(cpustate); break;\
case 0x46: PREFIX86(_inc_si)(cpustate); break;\
case 0x47: PREFIX86(_inc_di)(cpustate); break;\
case 0x48: PREFIX86(_dec_ax)(cpustate); break;\
case 0x49: PREFIX86(_dec_cx)(cpustate); break;\
case 0x4a: PREFIX86(_dec_dx)(cpustate); break;\
case 0x4b: PREFIX86(_dec_bx)(cpustate); break;\
case 0x4c: PREFIX86(_dec_sp)(cpustate); break;\
case 0x4d: PREFIX86(_dec_bp)(cpustate); break;\
case 0x4e: PREFIX86(_dec_si)(cpustate); break;\
case 0x4f: PREFIX86(_dec_di)(cpustate); break;\
case 0x50: PREFIX86(_push_ax)(cpustate); break;\
case 0x51: PREFIX86(_push_cx)(cpustate); break;\
case 0x52: PREFIX86(_push_dx)(cpustate); break;\
case 0x53: PREFIX86(_push_bx)(cpustate); break;\
case 0x54: PREFIX86(_push_sp)(cpustate); break;\
case 0x55: PREFIX86(_push_bp)(cpustate); break;\
case 0x56: PREFIX86(_push_si)(cpustate); break;\
case 0x57: PREFIX86(_push_di)(cpustate); break;\
case 0x58: PREFIX86(_pop_ax)(cpustate); break;\
case 0x59: PREFIX86(_pop_cx)(cpustate); break;\
case 0x5a: PREFIX86(_pop_dx)(cpustate); break;\
case 0x5b: PREFIX86(_pop_bx)(cpustate); break;\
case 0x5c: PREFIX86(_pop_sp)(cpustate); break;\
case 0x5d: PREFIX86(_pop_bp)(cpustate); break;\
case 0x5e: PREFIX86(_pop_si)(cpustate); break;\
case 0x5f: PREFIX86(_pop_di)(cpustate); break;\
case 0x60: PREFIX86(_invalid)(cpustate); break;\
case 0x61: PREFIX86(_invalid)(cpustate); break;\
case 0x62: PREFIX86(_invalid)(cpustate); break;\
case 0x63: PREFIX86(_invalid)(cpustate); break;\
case 0x64: PREFIX86(_invalid)(cpustate); break;\
case 0x65: PREFIX86(_invalid)(cpustate); break;\
case 0x66: PREFIX86(_invalid)(cpustate); break;\
case 0x67: PREFIX86(_invalid)(cpustate); break;\
case 0x68: PREFIX86(_invalid)(cpustate); break;\
case 0x69: PREFIX86(_invalid)(cpustate); break;\
case 0x6a: PREFIX86(_invalid)(cpustate); break;\
case 0x6b: PREFIX86(_invalid)(cpustate); break;\
case 0x6c: PREFIX86(_invalid)(cpustate); break;\
case 0x6d: PREFIX86(_invalid)(cpustate); break;\
case 0x6e: PREFIX86(_invalid)(cpustate); break;\
case 0x6f: PREFIX86(_invalid)(cpustate); break;\
case 0x70: PREFIX86(_jo)(cpustate); break;\
case 0x71: PREFIX86(_jno)(cpustate); break;\
case 0x72: PREFIX86(_jb)(cpustate); break;\
case 0x73: PREFIX86(_jnb)(cpustate); break;\
case 0x74: PREFIX86(_jz)(cpustate); break;\
case 0x75: PREFIX86(_jnz)(cpustate); break;\
case 0x76: PREFIX86(_jbe)(cpustate); break;\
case 0x77: PREFIX86(_jnbe)(cpustate); break;\
case 0x78: PREFIX86(_js)(cpustate); break;\
case 0x79: PREFIX86(_jns)(cpustate); break;\
case 0x7a: PREFIX86(_jp)(cpustate); break;\
case 0x7b: PREFIX86(_jnp)(cpustate); break;\
case 0x7c: PREFIX86(_jl)(cpustate); break;\
case 0x7d: PREFIX86(_jnl)(cpustate); break;\
case 0x7e: PREFIX86(_jle)(cpustate); break;\
case 0x7f: PREFIX86(_jnle)(cpustate); break;\
case 0x80: PREFIX86(_80pre)(cpustate); break;\
case 0x81: PREFIX86(_81pre)(cpustate); break;\
case 0x82: PREFIX86(_82pre)(cpustate); break;\
case 0x83: PREFIX86(_83pre)(cpustate); break;\
case 0x84: PREFIX86(_test_br8)(cpustate); break;\
case 0x85: PREFIX86(_test_wr16)(cpustate); break;\
case 0x86: PREFIX86(_xchg_br8)(cpustate); break;\
case 0x87: PREFIX86(_xchg_wr16)(cpustate); break;\
case 0x88: PREFIX86(_mov_br8)(cpustate); break;\
case 0x89: PREFIX86(_mov_wr16)(cpustate); break;\
case 0x8a: PREFIX86(_mov_r8b)(cpustate); break;\
case 0x8b: PREFIX86(_mov_r16w)(cpustate); break;\
case 0x8c: PREFIX86(_mov_wsreg)(cpustate); break;\
case 0x8d: PREFIX86(_lea)(cpustate); break;\
case 0x8e: PREFIX86(_mov_sregw)(cpustate); break;\
case 0x8f: PREFIX86(_popw)(cpustate); break;\
case 0x90: PREFIX86(_nop)(cpustate); break;\
case 0x91: PREFIX86(_xchg_axcx)(cpustate); break;\
case 0x92: PREFIX86(_xchg_axdx)(cpustate); break;\
case 0x93: PREFIX86(_xchg_axbx)(cpustate); break;\
case 0x94: PREFIX86(_xchg_axsp)(cpustate); break;\
case 0x95: PREFIX86(_xchg_axbp)(cpustate); break;\
case 0x96: PREFIX86(_xchg_axsi)(cpustate); break;\
case 0x97: PREFIX86(_xchg_axdi)(cpustate); break;\
case 0x98: PREFIX86(_cbw)(cpustate); break;\
case 0x99: PREFIX86(_cwd)(cpustate); break;\
case 0x9a: PREFIX86(_call_far)(cpustate); break;\
case 0x9b: PREFIX86(_wait)(cpustate); break;\
case 0x9c: PREFIX86(_pushf)(cpustate); break;\
case 0x9d: PREFIX86(_popf)(cpustate); break;\
case 0x9e: PREFIX86(_sahf)(cpustate); break;\
case 0x9f: PREFIX86(_lahf)(cpustate); break;\
case 0xa0: PREFIX86(_mov_aldisp)(cpustate); break;\
case 0xa1: PREFIX86(_mov_axdisp)(cpustate); break;\
case 0xa2: PREFIX86(_mov_dispal)(cpustate); break;\
case 0xa3: PREFIX86(_mov_dispax)(cpustate); break;\
case 0xa4: PREFIX86(_movsb)(cpustate); break;\
case 0xa5: PREFIX86(_movsw)(cpustate); break;\
case 0xa6: PREFIX86(_cmpsb)(cpustate); break;\
case 0xa7: PREFIX86(_cmpsw)(cpustate); break;\
case 0xa8: PREFIX86(_test_ald8)(cpustate); break;\
case 0xa9: PREFIX86(_test_axd16)(cpustate); break;\
case 0xaa: PREFIX86(_stosb)(cpustate); break;\
case 0xab: PREFIX86(_stosw)(cpustate); break;\
case 0xac: PREFIX86(_lodsb)(cpustate); break;\
case 0xad: PREFIX86(_lodsw)(cpustate); break;\
case 0xae: PREFIX86(_scasb)(cpustate); break;\
case 0xaf: PREFIX86(_scasw)(cpustate); break;\
case 0xb0: PREFIX86(_mov_ald8)(cpustate); break;\
case 0xb1: PREFIX86(_mov_cld8)(cpustate); break;\
case 0xb2: PREFIX86(_mov_dld8)(cpustate); break;\
case 0xb3: PREFIX86(_mov_bld8)(cpustate); break;\
case 0xb4: PREFIX86(_mov_ahd8)(cpustate); break;\
case 0xb5: PREFIX86(_mov_chd8)(cpustate); break;\
case 0xb6: PREFIX86(_mov_dhd8)(cpustate); break;\
case 0xb7: PREFIX86(_mov_bhd8)(cpustate); break;\
case 0xb8: PREFIX86(_mov_axd16)(cpustate); break;\
case 0xb9: PREFIX86(_mov_cxd16)(cpustate); break;\
case 0xba: PREFIX86(_mov_dxd16)(cpustate); break;\
case 0xbb: PREFIX86(_mov_bxd16)(cpustate); break;\
case 0xbc: PREFIX86(_mov_spd16)(cpustate); break;\
case 0xbd: PREFIX86(_mov_bpd16)(cpustate); break;\
case 0xbe: PREFIX86(_mov_sid16)(cpustate); break;\
case 0xbf: PREFIX86(_mov_did16)(cpustate); break;\
case 0xc0: PREFIX86(_invalid)(cpustate); break;\
case 0xc1: PREFIX86(_invalid)(cpustate); break;\
case 0xc2: PREFIX86(_ret_d16)(cpustate); break;\
case 0xc3: PREFIX86(_ret)(cpustate); break;\
case 0xc4: PREFIX86(_les_dw)(cpustate); break;\
case 0xc5: PREFIX86(_lds_dw)(cpustate); break;\
case 0xc6: PREFIX86(_mov_bd8)(cpustate); break;\
case 0xc7: PREFIX86(_mov_wd16)(cpustate); break;\
case 0xc8: PREFIX86(_invalid)(cpustate); break;\
case 0xc9: PREFIX86(_invalid)(cpustate); break;\
case 0xca: PREFIX86(_retf_d16)(cpustate); break;\
case 0xcb: PREFIX86(_retf)(cpustate); break;\
case 0xcc: PREFIX86(_int3)(cpustate); break;\
case 0xcd: PREFIX86(_int)(cpustate); break;\
case 0xce: PREFIX86(_into)(cpustate); break;\
case 0xcf: PREFIX86(_iret)(cpustate); break;\
case 0xd0: PREFIX86(_rotshft_b)(cpustate); break;\
case 0xd1: PREFIX86(_rotshft_w)(cpustate); break;\
case 0xd2: PREFIX86(_rotshft_bcl)(cpustate); break;\
case 0xd3: PREFIX86(_rotshft_wcl)(cpustate); break;\
case 0xd4: PREFIX86(_aam)(cpustate); break;\
case 0xd5: PREFIX86(_aad)(cpustate); break;\
case 0xd6: PREFIX86(_invalid)(cpustate); break;\
case 0xd7: PREFIX86(_xlat)(cpustate); break;\
case 0xd8: PREFIX86(_escape)(cpustate); break;\
case 0xd9: PREFIX86(_escape)(cpustate); break;\
case 0xda: PREFIX86(_escape)(cpustate); break;\
case 0xdb: PREFIX86(_escape)(cpustate); break;\
case 0xdc: PREFIX86(_escape)(cpustate); break;\
case 0xdd: PREFIX86(_escape)(cpustate); break;\
case 0xde: PREFIX86(_escape)(cpustate); break;\
case 0xdf: PREFIX86(_escape)(cpustate); break;\
case 0xe0: PREFIX86(_loopne)(cpustate); break;\
case 0xe1: PREFIX86(_loope)(cpustate); break;\
case 0xe2: PREFIX86(_loop)(cpustate); break;\
case 0xe3: PREFIX86(_jcxz)(cpustate); break;\
case 0xe4: PREFIX86(_inal)(cpustate); break;\
case 0xe5: PREFIX86(_inax)(cpustate); break;\
case 0xe6: PREFIX86(_outal)(cpustate); break;\
case 0xe7: PREFIX86(_outax)(cpustate); break;\
case 0xe8: PREFIX86(_call_d16)(cpustate); break;\
case 0xe9: PREFIX86(_jmp_d16)(cpustate); break;\
case 0xea: PREFIX86(_jmp_far)(cpustate); break;\
case 0xeb: PREFIX86(_jmp_d8)(cpustate); break;\
case 0xec: PREFIX86(_inaldx)(cpustate); break;\
case 0xed: PREFIX86(_inaxdx)(cpustate); break;\
case 0xee: PREFIX86(_outdxal)(cpustate); break;\
case 0xef: PREFIX86(_outdxax)(cpustate); break;\
case 0xf0: PREFIX86(_lock)(cpustate); break;\
case 0xf1: PREFIX86(_invalid)(cpustate); break;\
case 0xf2: PREFIX86(_repne)(cpustate); break;\
case 0xf3: PREFIX86(_repe)(cpustate); break;\
case 0xf4: PREFIX86(_hlt)(cpustate); break;\
case 0xf5: PREFIX86(_cmc)(cpustate); break;\
case 0xf6: PREFIX86(_f6pre)(cpustate); break;\
case 0xf7: PREFIX86(_f7pre)(cpustate); break;\
case 0xf8: PREFIX86(_clc)(cpustate); break;\
case 0xf9: PREFIX86(_stc)(cpustate); break;\
case 0xfa: PREFIX86(_cli)(cpustate); break;\
case 0xfb: PREFIX86(_sti)(cpustate); break;\
case 0xfc: PREFIX86(_cld)(cpustate); break;\
case 0xfd: PREFIX86(_std)(cpustate); break;\
case 0xfe: PREFIX86(_fepre)(cpustate); break;\
case 0xff: PREFIX86(_ffpre)(cpustate); break;\
};
#else
#define TABLE86 PREFIX86(_instruction)[FETCHOP]();
#define TABLE86 PREFIX86(_instruction)[FETCHOP](cpustate);
#endif

528
src/emu/cpu/i86/tablev30.h
View File

@ -1,528 +0,0 @@
// special nec instructions missing
// at the time the same like table186.h
static void (*const PREFIXV30(_instruction)[256])(void) =
{
PREFIX86(_add_br8), /* 0x00 */
PREFIX86(_add_wr16), /* 0x01 */
PREFIX86(_add_r8b), /* 0x02 */
PREFIX86(_add_r16w), /* 0x03 */
PREFIX86(_add_ald8), /* 0x04 */
PREFIX86(_add_axd16), /* 0x05 */
PREFIX86(_push_es), /* 0x06 */
PREFIX86(_pop_es), /* 0x07 */
PREFIX86(_or_br8), /* 0x08 */
PREFIX86(_or_wr16), /* 0x09 */
PREFIX86(_or_r8b), /* 0x0a */
PREFIX86(_or_r16w), /* 0x0b */
PREFIX86(_or_ald8), /* 0x0c */
PREFIX86(_or_axd16), /* 0x0d */
PREFIX86(_push_cs), /* 0x0e */
PREFIXV30(_0fpre),
PREFIX86(_adc_br8), /* 0x10 */
PREFIX86(_adc_wr16), /* 0x11 */
PREFIX86(_adc_r8b), /* 0x12 */
PREFIX86(_adc_r16w), /* 0x13 */
PREFIX86(_adc_ald8), /* 0x14 */
PREFIX86(_adc_axd16), /* 0x15 */
PREFIX86(_push_ss), /* 0x16 */
PREFIX86(_pop_ss), /* 0x17 */
PREFIX86(_sbb_br8), /* 0x18 */
PREFIX86(_sbb_wr16), /* 0x19 */
PREFIX86(_sbb_r8b), /* 0x1a */
PREFIX86(_sbb_r16w), /* 0x1b */
PREFIX86(_sbb_ald8), /* 0x1c */
PREFIX86(_sbb_axd16), /* 0x1d */
PREFIX86(_push_ds), /* 0x1e */
PREFIX86(_pop_ds), /* 0x1f */
PREFIX86(_and_br8), /* 0x20 */
PREFIX86(_and_wr16), /* 0x21 */
PREFIX86(_and_r8b), /* 0x22 */
PREFIX86(_and_r16w), /* 0x23 */
PREFIX86(_and_ald8), /* 0x24 */
PREFIX86(_and_axd16), /* 0x25 */
PREFIX86(_es), /* 0x26 */
PREFIX86(_daa), /* 0x27 */
PREFIX86(_sub_br8), /* 0x28 */
PREFIX86(_sub_wr16), /* 0x29 */
PREFIX86(_sub_r8b), /* 0x2a */
PREFIX86(_sub_r16w), /* 0x2b */
PREFIX86(_sub_ald8), /* 0x2c */
PREFIX86(_sub_axd16), /* 0x2d */
PREFIX86(_cs), /* 0x2e */
PREFIX86(_das), /* 0x2f */
PREFIX86(_xor_br8), /* 0x30 */
PREFIX86(_xor_wr16), /* 0x31 */
PREFIX86(_xor_r8b), /* 0x32 */
PREFIX86(_xor_r16w), /* 0x33 */
PREFIX86(_xor_ald8), /* 0x34 */
PREFIX86(_xor_axd16), /* 0x35 */
PREFIX86(_ss), /* 0x36 */
PREFIX86(_aaa), /* 0x37 */
PREFIX86(_cmp_br8), /* 0x38 */
PREFIX86(_cmp_wr16), /* 0x39 */
PREFIX86(_cmp_r8b), /* 0x3a */
PREFIX86(_cmp_r16w), /* 0x3b */
PREFIX86(_cmp_ald8), /* 0x3c */
PREFIX86(_cmp_axd16), /* 0x3d */
PREFIX86(_ds), /* 0x3e */
PREFIX86(_aas), /* 0x3f */
PREFIX86(_inc_ax), /* 0x40 */
PREFIX86(_inc_cx), /* 0x41 */
PREFIX86(_inc_dx), /* 0x42 */
PREFIX86(_inc_bx), /* 0x43 */
PREFIX86(_inc_sp), /* 0x44 */
PREFIX86(_inc_bp), /* 0x45 */
PREFIX86(_inc_si), /* 0x46 */
PREFIX86(_inc_di), /* 0x47 */
PREFIX86(_dec_ax), /* 0x48 */
PREFIX86(_dec_cx), /* 0x49 */
PREFIX86(_dec_dx), /* 0x4a */
PREFIX86(_dec_bx), /* 0x4b */
PREFIX86(_dec_sp), /* 0x4c */
PREFIX86(_dec_bp), /* 0x4d */
PREFIX86(_dec_si), /* 0x4e */
PREFIX86(_dec_di), /* 0x4f */
PREFIX86(_push_ax), /* 0x50 */
PREFIX86(_push_cx), /* 0x51 */
PREFIX86(_push_dx), /* 0x52 */
PREFIX86(_push_bx), /* 0x53 */
PREFIX86(_push_sp), /* 0x54 */
PREFIX86(_push_bp), /* 0x55 */
PREFIX86(_push_si), /* 0x56 */
PREFIX86(_push_di), /* 0x57 */
PREFIX86(_pop_ax), /* 0x58 */
PREFIX86(_pop_cx), /* 0x59 */
PREFIX86(_pop_dx), /* 0x5a */
PREFIX86(_pop_bx), /* 0x5b */
PREFIX86(_pop_sp), /* 0x5c */
PREFIX86(_pop_bp), /* 0x5d */
PREFIX86(_pop_si), /* 0x5e */
PREFIX86(_pop_di), /* 0x5f */
PREFIX186(_pusha), /* 0x60 */
PREFIX186(_popa), /* 0x61 */
PREFIX186(_bound), /* 0x62 */
PREFIX86(_invalid),
PREFIXV30(_repnc),
PREFIXV30(_repc),
PREFIX86(_invalid),
PREFIX86(_invalid),
PREFIX186(_push_d16), /* 0x68 */
PREFIX186(_imul_d16), /* 0x69 */
PREFIX186(_push_d8), /* 0x6a */
PREFIX186(_imul_d8), /* 0x6b */
PREFIX186(_insb), /* 0x6c */
PREFIX186(_insw), /* 0x6d */
PREFIX186(_outsb), /* 0x6e */
PREFIX186(_outsw), /* 0x6f */
PREFIX86(_jo), /* 0x70 */
PREFIX86(_jno), /* 0x71 */
PREFIX86(_jb), /* 0x72 */
PREFIX86(_jnb), /* 0x73 */
PREFIX86(_jz), /* 0x74 */
PREFIX86(_jnz), /* 0x75 */
PREFIX86(_jbe), /* 0x76 */
PREFIX86(_jnbe), /* 0x77 */
PREFIX86(_js), /* 0x78 */
PREFIX86(_jns), /* 0x79 */
PREFIX86(_jp), /* 0x7a */
PREFIX86(_jnp), /* 0x7b */
PREFIX86(_jl), /* 0x7c */
PREFIX86(_jnl), /* 0x7d */
PREFIX86(_jle), /* 0x7e */
PREFIX86(_jnle), /* 0x7f */
PREFIX86(_80pre), /* 0x80 */
PREFIX86(_81pre), /* 0x81 */
PREFIX86(_82pre), /* 0x82 */
PREFIX86(_83pre), /* 0x83 */
PREFIX86(_test_br8), /* 0x84 */
PREFIX86(_test_wr16), /* 0x85 */
PREFIX86(_xchg_br8), /* 0x86 */
PREFIX86(_xchg_wr16), /* 0x87 */
PREFIX86(_mov_br8), /* 0x88 */
PREFIX86(_mov_wr16), /* 0x89 */
PREFIX86(_mov_r8b), /* 0x8a */
PREFIX86(_mov_r16w), /* 0x8b */
PREFIX86(_mov_wsreg), /* 0x8c */
PREFIX86(_lea), /* 0x8d */
PREFIX86(_mov_sregw), /* 0x8e */
PREFIX86(_popw), /* 0x8f */
PREFIX86(_nop), /* 0x90 */
PREFIX86(_xchg_axcx), /* 0x91 */
PREFIX86(_xchg_axdx), /* 0x92 */
PREFIX86(_xchg_axbx), /* 0x93 */
PREFIX86(_xchg_axsp), /* 0x94 */
PREFIX86(_xchg_axbp), /* 0x95 */
PREFIX86(_xchg_axsi), /* 0x97 */
PREFIX86(_xchg_axdi), /* 0x97 */
PREFIX86(_cbw), /* 0x98 */
PREFIX86(_cwd), /* 0x99 */
PREFIX86(_call_far), /* 0x9a */
PREFIX86(_wait), /* 0x9b */
PREFIXV30(_pushf), /* 0x9c */
PREFIX86(_popf), /* 0x9d */
PREFIX86(_sahf), /* 0x9e */
PREFIX86(_lahf), /* 0x9f */
PREFIX86(_mov_aldisp), /* 0xa0 */
PREFIX86(_mov_axdisp), /* 0xa1 */
PREFIX86(_mov_dispal), /* 0xa2 */
PREFIX86(_mov_dispax), /* 0xa3 */
PREFIX86(_movsb), /* 0xa4 */
PREFIX86(_movsw), /* 0xa5 */
PREFIX86(_cmpsb), /* 0xa6 */
PREFIX86(_cmpsw), /* 0xa7 */
PREFIX86(_test_ald8), /* 0xa8 */
PREFIX86(_test_axd16), /* 0xa9 */
PREFIX86(_stosb), /* 0xaa */
PREFIX86(_stosw), /* 0xab */
PREFIX86(_lodsb), /* 0xac */
PREFIX86(_lodsw), /* 0xad */
PREFIX86(_scasb), /* 0xae */
PREFIX86(_scasw), /* 0xaf */
PREFIX86(_mov_ald8), /* 0xb0 */
PREFIX86(_mov_cld8), /* 0xb1 */
PREFIX86(_mov_dld8), /* 0xb2 */
PREFIX86(_mov_bld8), /* 0xb3 */
PREFIX86(_mov_ahd8), /* 0xb4 */
PREFIX86(_mov_chd8), /* 0xb5 */
PREFIX86(_mov_dhd8), /* 0xb6 */
PREFIX86(_mov_bhd8), /* 0xb7 */
PREFIX86(_mov_axd16), /* 0xb8 */
PREFIX86(_mov_cxd16), /* 0xb9 */
PREFIX86(_mov_dxd16), /* 0xba */
PREFIX86(_mov_bxd16), /* 0xbb */
PREFIX86(_mov_spd16), /* 0xbc */
PREFIX86(_mov_bpd16), /* 0xbd */
PREFIX86(_mov_sid16), /* 0xbe */
PREFIX86(_mov_did16), /* 0xbf */
PREFIX186(_rotshft_bd8), /* 0xc0 */
PREFIX186(_rotshft_wd8), /* 0xc1 */
PREFIX86(_ret_d16), /* 0xc2 */
PREFIX86(_ret), /* 0xc3 */
PREFIX86(_les_dw), /* 0xc4 */
PREFIX86(_lds_dw), /* 0xc5 */
PREFIX86(_mov_bd8), /* 0xc6 */
PREFIX86(_mov_wd16), /* 0xc7 */
PREFIX186(_enter), /* 0xc8 */
PREFIX186(_leave), /* 0xc9 */
PREFIX86(_retf_d16), /* 0xca */
PREFIX86(_retf), /* 0xcb */
PREFIX86(_int3), /* 0xcc */
PREFIX86(_int), /* 0xcd */
PREFIX86(_into), /* 0xce */
PREFIX86(_iret), /* 0xcf */
PREFIX86(_rotshft_b), /* 0xd0 */
PREFIX86(_rotshft_w), /* 0xd1 */
PREFIX86(_rotshft_bcl), /* 0xd2 */
PREFIX86(_rotshft_wcl), /* 0xd3 */
PREFIX86(_aam), /* 0xd4 */
PREFIX86(_aad), /* 0xd5 */
PREFIXV30(_setalc),
PREFIX86(_xlat), /* 0xd7 */
PREFIX86(_escape), /* 0xd8 */
PREFIX86(_escape), /* 0xd9 */
PREFIX86(_escape), /* 0xda */
PREFIX86(_escape), /* 0xdb */
PREFIX86(_escape), /* 0xdc */
PREFIX86(_escape), /* 0xdd */
PREFIX86(_escape), /* 0xde */
PREFIX86(_escape), /* 0xdf */
PREFIX86(_loopne), /* 0xe0 */
PREFIX86(_loope), /* 0xe1 */
PREFIX86(_loop), /* 0xe2 */
PREFIX86(_jcxz), /* 0xe3 */
PREFIX86(_inal), /* 0xe4 */
PREFIX86(_inax), /* 0xe5 */
PREFIX86(_outal), /* 0xe6 */
PREFIX86(_outax), /* 0xe7 */
PREFIX86(_call_d16), /* 0xe8 */
PREFIX86(_jmp_d16), /* 0xe9 */
PREFIX86(_jmp_far), /* 0xea */
PREFIX86(_jmp_d8), /* 0xeb */
PREFIX86(_inaldx), /* 0xec */
PREFIX86(_inaxdx), /* 0xed */
PREFIX86(_outdxal), /* 0xee */
PREFIX86(_outdxax), /* 0xef */
PREFIX86(_lock), /* 0xf0 */
PREFIX86(_invalid), /* 0xf1 */
PREFIX186(_repne), /* 0xf2 */
PREFIX186(_repe), /* 0xf3 */
PREFIX86(_hlt), /* 0xf4 */
PREFIX86(_cmc), /* 0xf5 */
PREFIX86(_f6pre), /* 0xf6 */
PREFIX86(_f7pre), /* 0xf7 */
PREFIX86(_clc), /* 0xf8 */
PREFIX86(_stc), /* 0xf9 */
PREFIX86(_cli), /* 0xfa */
PREFIX86(_sti), /* 0xfb */
PREFIX86(_cld), /* 0xfc */
PREFIX86(_std), /* 0xfd */
PREFIX86(_fepre), /* 0xfe */
PREFIX86(_ffpre) /* 0xff */
};
#if defined(BIGCASE) && !defined(RS6000)
/* Some compilers cannot handle large case statements */
#define TABLEV30 \
switch(FETCHOP)\
{\
case 0x00: PREFIX86(_add_br8)(); break;\
case 0x01: PREFIX86(_add_wr16)(); break;\
case 0x02: PREFIX86(_add_r8b)(); break;\
case 0x03: PREFIX86(_add_r16w)(); break;\
case 0x04: PREFIX86(_add_ald8)(); break;\
case 0x05: PREFIX86(_add_axd16)(); break;\
case 0x06: PREFIX86(_push_es)(); break;\
case 0x07: PREFIX86(_pop_es)(); break;\
case 0x08: PREFIX86(_or_br8)(); break;\
case 0x09: PREFIX86(_or_wr16)(); break;\
case 0x0a: PREFIX86(_or_r8b)(); break;\
case 0x0b: PREFIX86(_or_r16w)(); break;\
case 0x0c: PREFIX86(_or_ald8)(); break;\
case 0x0d: PREFIX86(_or_axd16)(); break;\
case 0x0e: PREFIX86(_push_cs)(); break;\
case 0x0f: PREFIXV30(_0fpre)(); break;\
case 0x10: PREFIX86(_adc_br8)(); break;\
case 0x11: PREFIX86(_adc_wr16)(); break;\
case 0x12: PREFIX86(_adc_r8b)(); break;\
case 0x13: PREFIX86(_adc_r16w)(); break;\
case 0x14: PREFIX86(_adc_ald8)(); break;\
case 0x15: PREFIX86(_adc_axd16)(); break;\
case 0x16: PREFIX86(_push_ss)(); break;\
case 0x17: PREFIX86(_pop_ss)(); break;\
case 0x18: PREFIX86(_sbb_br8)(); break;\
case 0x19: PREFIX86(_sbb_wr16)(); break;\
case 0x1a: PREFIX86(_sbb_r8b)(); break;\
case 0x1b: PREFIX86(_sbb_r16w)(); break;\
case 0x1c: PREFIX86(_sbb_ald8)(); break;\
case 0x1d: PREFIX86(_sbb_axd16)(); break;\
case 0x1e: PREFIX86(_push_ds)(); break;\
case 0x1f: PREFIX86(_pop_ds)(); break;\
case 0x20: PREFIX86(_and_br8)(); break;\
case 0x21: PREFIX86(_and_wr16)(); break;\
case 0x22: PREFIX86(_and_r8b)(); break;\
case 0x23: PREFIX86(_and_r16w)(); break;\
case 0x24: PREFIX86(_and_ald8)(); break;\
case 0x25: PREFIX86(_and_axd16)(); break;\
case 0x26: PREFIX86(_es)(); break;\
case 0x27: PREFIX86(_daa)(); break;\
case 0x28: PREFIX86(_sub_br8)(); break;\
case 0x29: PREFIX86(_sub_wr16)(); break;\
case 0x2a: PREFIX86(_sub_r8b)(); break;\
case 0x2b: PREFIX86(_sub_r16w)(); break;\
case 0x2c: PREFIX86(_sub_ald8)(); break;\
case 0x2d: PREFIX86(_sub_axd16)(); break;\
case 0x2e: PREFIX86(_cs)(); break;\
case 0x2f: PREFIX86(_das)(); break;\
case 0x30: PREFIX86(_xor_br8)(); break;\
case 0x31: PREFIX86(_xor_wr16)(); break;\
case 0x32: PREFIX86(_xor_r8b)(); break;\
case 0x33: PREFIX86(_xor_r16w)(); break;\
case 0x34: PREFIX86(_xor_ald8)(); break;\
case 0x35: PREFIX86(_xor_axd16)(); break;\
case 0x36: PREFIX86(_ss)(); break;\
case 0x37: PREFIX86(_aaa)(); break;\
case 0x38: PREFIX86(_cmp_br8)(); break;\
case 0x39: PREFIX86(_cmp_wr16)(); break;\
case 0x3a: PREFIX86(_cmp_r8b)(); break;\
case 0x3b: PREFIX86(_cmp_r16w)(); break;\
case 0x3c: PREFIX86(_cmp_ald8)(); break;\
case 0x3d: PREFIX86(_cmp_axd16)(); break;\
case 0x3e: PREFIX86(_ds)(); break;\
case 0x3f: PREFIX86(_aas)(); break;\
case 0x40: PREFIX86(_inc_ax)(); break;\
case 0x41: PREFIX86(_inc_cx)(); break;\
case 0x42: PREFIX86(_inc_dx)(); break;\
case 0x43: PREFIX86(_inc_bx)(); break;\
case 0x44: PREFIX86(_inc_sp)(); break;\
case 0x45: PREFIX86(_inc_bp)(); break;\
case 0x46: PREFIX86(_inc_si)(); break;\
case 0x47: PREFIX86(_inc_di)(); break;\
case 0x48: PREFIX86(_dec_ax)(); break;\
case 0x49: PREFIX86(_dec_cx)(); break;\
case 0x4a: PREFIX86(_dec_dx)(); break;\
case 0x4b: PREFIX86(_dec_bx)(); break;\
case 0x4c: PREFIX86(_dec_sp)(); break;\
case 0x4d: PREFIX86(_dec_bp)(); break;\
case 0x4e: PREFIX86(_dec_si)(); break;\
case 0x4f: PREFIX86(_dec_di)(); break;\
case 0x50: PREFIX86(_push_ax)(); break;\
case 0x51: PREFIX86(_push_cx)(); break;\
case 0x52: PREFIX86(_push_dx)(); break;\
case 0x53: PREFIX86(_push_bx)(); break;\
case 0x54: PREFIX86(_push_sp)(); break;\
case 0x55: PREFIX86(_push_bp)(); break;\
case 0x56: PREFIX86(_push_si)(); break;\
case 0x57: PREFIX86(_push_di)(); break;\
case 0x58: PREFIX86(_pop_ax)(); break;\
case 0x59: PREFIX86(_pop_cx)(); break;\
case 0x5a: PREFIX86(_pop_dx)(); break;\
case 0x5b: PREFIX86(_pop_bx)(); break;\
case 0x5c: PREFIX86(_pop_sp)(); break;\
case 0x5d: PREFIX86(_pop_bp)(); break;\
case 0x5e: PREFIX86(_pop_si)(); break;\
case 0x5f: PREFIX86(_pop_di)(); break;\
case 0x60: PREFIX186(_pusha)(); break;\
case 0x61: PREFIX186(_popa)(); break;\
case 0x62: PREFIX186(_bound)(); break;\
case 0x63: PREFIX86(_invalid)(); break;\
case 0x64: PREFIXV30(_repnc)(); break;\
case 0x65: PREFIXV30(_repc)(); break;\
case 0x66: PREFIX86(_invalid)(); break;\
case 0x67: PREFIX86(_invalid)(); break;\
case 0x68: PREFIX186(_push_d16)(); break;\
case 0x69: PREFIX186(_imul_d16)(); break;\
case 0x6a: PREFIX186(_push_d8)(); break;\
case 0x6b: PREFIX186(_imul_d8)(); break;\
case 0x6c: PREFIX186(_insb)(); break;\
case 0x6d: PREFIX186(_insw)(); break;\
case 0x6e: PREFIX186(_outsb)(); break;\
case 0x6f: PREFIX186(_outsw)(); break;\
case 0x70: PREFIX86(_jo)(); break;\
case 0x71: PREFIX86(_jno)(); break;\
case 0x72: PREFIX86(_jb)(); break;\
case 0x73: PREFIX86(_jnb)(); break;\
case 0x74: PREFIX86(_jz)(); break;\
case 0x75: PREFIX86(_jnz)(); break;\
case 0x76: PREFIX86(_jbe)(); break;\
case 0x77: PREFIX86(_jnbe)(); break;\
case 0x78: PREFIX86(_js)(); break;\
case 0x79: PREFIX86(_jns)(); break;\
case 0x7a: PREFIX86(_jp)(); break;\
case 0x7b: PREFIX86(_jnp)(); break;\
case 0x7c: PREFIX86(_jl)(); break;\
case 0x7d: PREFIX86(_jnl)(); break;\
case 0x7e: PREFIX86(_jle)(); break;\
case 0x7f: PREFIX86(_jnle)(); break;\
case 0x80: PREFIX86(_80pre)(); break;\
case 0x81: PREFIX86(_81pre)(); break;\
case 0x82: PREFIX86(_82pre)(); break;\
case 0x83: PREFIX86(_83pre)(); break;\
case 0x84: PREFIX86(_test_br8)(); break;\
case 0x85: PREFIX86(_test_wr16)(); break;\
case 0x86: PREFIX86(_xchg_br8)(); break;\
case 0x87: PREFIX86(_xchg_wr16)(); break;\
case 0x88: PREFIX86(_mov_br8)(); break;\
case 0x89: PREFIX86(_mov_wr16)(); break;\
case 0x8a: PREFIX86(_mov_r8b)(); break;\
case 0x8b: PREFIX86(_mov_r16w)(); break;\
case 0x8c: PREFIX86(_mov_wsreg)(); break;\
case 0x8d: PREFIX86(_lea)(); break;\
case 0x8e: PREFIX86(_mov_sregw)(); break;\
case 0x8f: PREFIX86(_popw)(); break;\
case 0x90: PREFIX86(_nop)(); break;\
case 0x91: PREFIX86(_xchg_axcx)(); break;\
case 0x92: PREFIX86(_xchg_axdx)(); break;\
case 0x93: PREFIX86(_xchg_axbx)(); break;\
case 0x94: PREFIX86(_xchg_axsp)(); break;\
case 0x95: PREFIX86(_xchg_axbp)(); break;\
case 0x96: PREFIX86(_xchg_axsi)(); break;\
case 0x97: PREFIX86(_xchg_axdi)(); break;\
case 0x98: PREFIX86(_cbw)(); break;\
case 0x99: PREFIX86(_cwd)(); break;\
case 0x9a: PREFIX86(_call_far)(); break;\
case 0x9b: PREFIX86(_wait)(); break;\
case 0x9c: PREFIXV30(_pushf)(); break;\
case 0x9d: PREFIX86(_popf)(); break;\
case 0x9e: PREFIX86(_sahf)(); break;\
case 0x9f: PREFIX86(_lahf)(); break;\
case 0xa0: PREFIX86(_mov_aldisp)(); break;\
case 0xa1: PREFIX86(_mov_axdisp)(); break;\
case 0xa2: PREFIX86(_mov_dispal)(); break;\
case 0xa3: PREFIX86(_mov_dispax)(); break;\
case 0xa4: PREFIX86(_movsb)(); break;\
case 0xa5: PREFIX86(_movsw)(); break;\
case 0xa6: PREFIX86(_cmpsb)(); break;\
case 0xa7: PREFIX86(_cmpsw)(); break;\
case 0xa8: PREFIX86(_test_ald8)(); break;\
case 0xa9: PREFIX86(_test_axd16)(); break;\
case 0xaa: PREFIX86(_stosb)(); break;\
case 0xab: PREFIX86(_stosw)(); break;\
case 0xac: PREFIX86(_lodsb)(); break;\
case 0xad: PREFIX86(_lodsw)(); break;\
case 0xae: PREFIX86(_scasb)(); break;\
case 0xaf: PREFIX86(_scasw)(); break;\
case 0xb0: PREFIX86(_mov_ald8)(); break;\
case 0xb1: PREFIX86(_mov_cld8)(); break;\
case 0xb2: PREFIX86(_mov_dld8)(); break;\
case 0xb3: PREFIX86(_mov_bld8)(); break;\
case 0xb4: PREFIX86(_mov_ahd8)(); break;\
case 0xb5: PREFIX86(_mov_chd8)(); break;\
case 0xb6: PREFIX86(_mov_dhd8)(); break;\
case 0xb7: PREFIX86(_mov_bhd8)(); break;\
case 0xb8: PREFIX86(_mov_axd16)(); break;\
case 0xb9: PREFIX86(_mov_cxd16)(); break;\
case 0xba: PREFIX86(_mov_dxd16)(); break;\
case 0xbb: PREFIX86(_mov_bxd16)(); break;\
case 0xbc: PREFIX86(_mov_spd16)(); break;\
case 0xbd: PREFIX86(_mov_bpd16)(); break;\
case 0xbe: PREFIX86(_mov_sid16)(); break;\
case 0xbf: PREFIX86(_mov_did16)(); break;\
case 0xc0: PREFIX186(_rotshft_bd8)(); break;\
case 0xc1: PREFIX186(_rotshft_wd8)(); break;\
case 0xc2: PREFIX86(_ret_d16)(); break;\
case 0xc3: PREFIX86(_ret)(); break;\
case 0xc4: PREFIX86(_les_dw)(); break;\
case 0xc5: PREFIX86(_lds_dw)(); break;\
case 0xc6: PREFIX86(_mov_bd8)(); break;\
case 0xc7: PREFIX86(_mov_wd16)(); break;\
case 0xc8: PREFIX186(_enter)(); break;\
case 0xc9: PREFIX186(_leave)(); break;\
case 0xca: PREFIX86(_retf_d16)(); break;\
case 0xcb: PREFIX86(_retf)(); break;\
case 0xcc: PREFIX86(_int3)(); break;\
case 0xcd: PREFIX86(_int)(); break;\
case 0xce: PREFIX86(_into)(); break;\
case 0xcf: PREFIX86(_iret)(); break;\
case 0xd0: PREFIX86(_rotshft_b)(); break;\
case 0xd1: PREFIX86(_rotshft_w)(); break;\
case 0xd2: PREFIX86(_rotshft_bcl)(); break;\
case 0xd3: PREFIX86(_rotshft_wcl)(); break;\
case 0xd4: PREFIX86(_aam)(); break;\
case 0xd5: PREFIX86(_aad)(); break;\
case 0xd6: PREFIXV30(_setalc)(); break;\
case 0xd7: PREFIX86(_xlat)(); break;\
case 0xd8: PREFIX86(_escape)(); break;\
case 0xd9: PREFIX86(_escape)(); break;\
case 0xda: PREFIX86(_escape)(); break;\
case 0xdb: PREFIX86(_escape)(); break;\
case 0xdc: PREFIX86(_escape)(); break;\
case 0xdd: PREFIX86(_escape)(); break;\
case 0xde: PREFIX86(_escape)(); break;\
case 0xdf: PREFIX86(_escape)(); break;\
case 0xe0: PREFIX86(_loopne)(); break;\
case 0xe1: PREFIX86(_loope)(); break;\
case 0xe2: PREFIX86(_loop)(); break;\
case 0xe3: PREFIX86(_jcxz)(); break;\
case 0xe4: PREFIX86(_inal)(); break;\
case 0xe5: PREFIX86(_inax)(); break;\
case 0xe6: PREFIX86(_outal)(); break;\
case 0xe7: PREFIX86(_outax)(); break;\
case 0xe8: PREFIX86(_call_d16)(); break;\
case 0xe9: PREFIX86(_jmp_d16)(); break;\
case 0xea: PREFIX86(_jmp_far)(); break;\
case 0xeb: PREFIX86(_jmp_d8)(); break;\
case 0xec: PREFIX86(_inaldx)(); break;\
case 0xed: PREFIX86(_inaxdx)(); break;\
case 0xee: PREFIX86(_outdxal)(); break;\
case 0xef: PREFIX86(_outdxax)(); break;\
case 0xf0: PREFIX86(_lock)(); break;\
case 0xf1: PREFIX86(_invalid)(); break;\
case 0xf2: PREFIX186(_repne)(); break;\
case 0xf3: PREFIX186(_repe)(); break;\
case 0xf4: PREFIX86(_hlt)(); break;\
case 0xf5: PREFIX86(_cmc)(); break;\
case 0xf6: PREFIX86(_f6pre)(); break;\
case 0xf7: PREFIX86(_f7pre)(); break;\
case 0xf8: PREFIX86(_clc)(); break;\
case 0xf9: PREFIX86(_stc)(); break;\
case 0xfa: PREFIX86(_cli)(); break;\
case 0xfb: PREFIX86(_sti)(); break;\
case 0xfc: PREFIX86(_cld)(); break;\
case 0xfd: PREFIX86(_std)(); break;\
case 0xfe: PREFIX86(_fepre)(); break;\
case 0xff: PREFIX86(_ffpre)(); break;\
};
#else
#define TABLEV30 PREFIXV30(_instruction)[FETCHOP]();
#endif

13
src/emu/cpu/i86/v20intf.h
View File

@ -1,13 +0,0 @@
/* ASG 971222 -- rewrote this interface */
#pragma once
#ifndef __V20INTF_H__
#define __V20INTF_H__
#include "i86intrf.h"
#include "v30intrf.h"
/* Public functions */
CPU_GET_INFO( v20 );
#endif /* __V20INTF_H__ */

30
src/emu/cpu/i86/v30.h
View File

@ -1,30 +0,0 @@
#pragma once
#ifndef __V30_H__
#define __V30_H__
#define SetMD(x) (I.MF = (x)) /* OB [19.07.99] Mode Flag V30 */
#define MD (I.MF!=0)
#undef CompressFlags
#define CompressFlags() (WORD)(CF | (PF << 2) | (AF << 4) | (ZF << 6) \
| (SF << 7) | (I.TF << 8) | (I.IF << 9) \
| (I.DF << 10) | (OF << 11)| (MD << 15))
#undef ExpandFlags
#define ExpandFlags(f) \
{ \
I.CarryVal = (f) & 1; \
I.ParityVal = !((f) & 4); \
I.AuxVal = (f) & 16; \
I.ZeroVal = !((f) & 64); \
I.SignVal = (f) & 128 ? -1 : 0; \
I.TF = ((f) & 256) == 256; \
I.IF = ((f) & 512) == 512; \
I.DF = ((f) & 1024) == 1024; \
I.OverVal = (f) & 2048; \
I.MF = ((f) & 0x8000) == 0x8000; \
}
#endif /* __V30_H__ */

11
src/emu/cpu/i86/v30intf.h
View File

@ -1,11 +0,0 @@
#pragma once
#ifndef __V30INTF_H__
#define __V30INTF_H__
#include "i86intf.h"
/* Public functions */
CPU_GET_INFO( v30 );
#endif /* __V30INTF_H__ */

10
src/emu/cpu/i86/v33intf.h
View File

@ -1,10 +0,0 @@
#ifndef __V33INTF_H__
#define __V33INTF_H__
#include "i86intrf.h"
#include "v30intrf.h"
/* Public functions */
CPU_GET_INFO( v33 );
#endif /* __V33INTF_H__ */