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Merge pull request #4155 from hp9k/hp98620_fixes

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hp98620: add channel control/status register
This commit is contained in:
ajrhacker 2018-10-18 10:31:01 -04:00 committed by GitHub
commit 89e260781c
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2 changed files with 40 additions and 11 deletions
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27
src/devices/bus/hp_dio/hp98620.cpp
View File

@ -188,9 +188,18 @@ READ16_MEMBER(dio16_98620_device::dma_r)
break;
case REG0_1TQ4_STATUS:
ret = 0;
if (m_regs[0].armed)
ret |= REG_1TQ4_STATUS_ARMED;
if (m_regs[0].irq)
ret |= REG_1TQ4_STATUS_INT;
break;
case REG1_1TQ4_STATUS:
ret = 0;
if (m_regs[1].armed)
ret |= REG_1TQ4_STATUS_ARMED;
if (m_regs[1].irq)
ret |= REG_1TQ4_STATUS_INT;
break;
default:
LOG("%s: unknown register read: %02X\n", __FUNCTION__, offset << 1);
@ -204,7 +213,7 @@ void dio16_98620_device::update_ctrl(const int channel, const uint16_t data, con
{
assert(channel < 2);
m_regs[channel].control = data;
m_regs[channel].control = data & ~REG_1TQ4_CONTROL_START;
m_regs[channel].ie = data & REG_CONTROL_IE;
m_regs[channel].irq_level = 3 + ((data >> REG_CONTROL_INT_SHIFT) & REG_CONTROL_INT_MASK);
m_regs[channel].lword = (data & REG_1TQ4_CONTROL_LWORD) && is_1tq4;
@ -288,6 +297,16 @@ WRITE16_MEMBER(dio16_98620_device::dma_w)
update_ctrl(1, data, false);
break;
case REG_GENERAL_CONTROL:
if (data & REG_GENERAL_CONTROL_RESET0) {
m_regs[0].armed = 0;
}
if (data & REG_GENERAL_CONTROL_RESET1) {
m_regs[1].armed = 0;
}
break;
case REG0_1TQ4_CONTROL:
update_ctrl(0, data, true);
break;
@ -342,8 +361,10 @@ void dio16_98620_device::dma_transfer(int channel)
if (m_regs[channel].tc-- == 0) {
LOG("DMA%d done\n", channel);
m_regs[channel].armed = false;
m_regs[channel].irq = true;
update_irq();
if (m_regs[channel].ie) {
m_regs[channel].irq = true;
update_irq();
}
return;
}

24
src/devices/bus/hp_dio/hp98620.h
View File

@ -65,23 +65,31 @@ private:
/* general control registers */
static constexpr int REG_1TQ4_ID_LOW = 0x10;
static constexpr int REG_1TQ4_ID_HIGH = 0x12;
static constexpr int REG_GENERAL_CONTROL = 0x14;
static constexpr int REG_GENERAL_CONTROL_RESET0 = 1 << 4;
static constexpr int REG_GENERAL_CONTROL_RESET1 = 1 << 5;
/* channel specific registers */
static constexpr int REG0_1TQ4_ADDRESS_LOW = 0x100;
static constexpr int REG0_1TQ4_ADDRESS_HIGH = 0x102;
static constexpr int REG0_1TQ4_TRANSFER_COUNT_LOW = 0x104;
static constexpr int REG0_1TQ4_TRANSFER_COUNT_HIGH = 0x106;
static constexpr int REG0_1TQ4_ADDRESS_HIGH = 0x100;
static constexpr int REG0_1TQ4_ADDRESS_LOW = 0x102;
static constexpr int REG0_1TQ4_TRANSFER_COUNT_HIGH = 0x104;
static constexpr int REG0_1TQ4_TRANSFER_COUNT_LOW = 0x106;
static constexpr int REG0_1TQ4_CONTROL = 0x108;
static constexpr int REG0_1TQ4_STATUS = 0x10a;
static constexpr uint16_t REG_1TQ4_CONTROL_LWORD = 1 << 8;
static constexpr uint16_t REG_1TQ4_CONTROL_START = 1 << 15;
static constexpr uint16_t REG_1TQ4_STATUS_ARMED = 1 << 0;
static constexpr uint16_t REG_1TQ4_STATUS_INT = 1 << 1;
/* registers */
static constexpr int REG1_1TQ4_ADDRESS_LOW = 0x200;
static constexpr int REG1_1TQ4_ADDRESS_HIGH = 0x202;
static constexpr int REG1_1TQ4_TRANSFER_COUNT_LOW = 0x204;
static constexpr int REG1_1TQ4_TRANSFER_COUNT_HIGH = 0x206;
static constexpr int REG1_1TQ4_ADDRESS_HIGH = 0x200;
static constexpr int REG1_1TQ4_ADDRESS_LOW = 0x202;
static constexpr int REG1_1TQ4_TRANSFER_COUNT_HIGH = 0x204;
static constexpr int REG1_1TQ4_TRANSFER_COUNT_LOW = 0x206;
static constexpr int REG1_1TQ4_CONTROL = 0x208;
static constexpr int REG1_1TQ4_STATUS = 0x20a;