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https://github.com/holub/mame
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Latest megadriv.c from MESS
This commit is contained in:
Angelo Salese
parent
3830a0299d
commit
8a0f33bf15
@ -74,7 +74,7 @@ On SegaC2 the VDP never turns on the IRQ6 enable register
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vdp line state change, which can be configured in the init
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rather than hardcoding them.
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32x Marsch tests documentation:
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32x Marsch tests documentation (keep start pressed at start-up for individual tests):
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MD side check:
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#1 Communication Check
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@ -117,12 +117,12 @@ MD side check:
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#37 SH-2 Slave ROM Read Check
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#38 SH-2 Serial Communication (ERROR - returns a Timeout Error)
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MD & 32x check:
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#39 MD&SH-2 Master Communication (ERROR)
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#40 MD&SH-2 Slave Communication (STALLS)
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#39 MD&SH-2 Master Communication
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#40 MD&SH-2 Slave Communication
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#41 MD&SH-2 Master FM Bit R/W
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#42 MD&SH-2 Slave FM Bit R/W
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#43 MD&SH-2 Master DREQ CTL (ERROR)
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#44 MD&SH-2 Slave DREQ CTL (ERROR)
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#43 MD&SH-2 Master DREQ CTL
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#44 MD&SH-2 Slave DREQ CTL
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#45 MD&SH-2 Master DREQ SRC address
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#46 MD&SH-2 Slave DREQ SRC address
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#47 MD&SH-2 Master DREQ DST address
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@ -131,12 +131,12 @@ MD & 32x check:
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#50 MD&SH-2 Slave DREQ SIZE address
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#51 SH-2 Master V IRQ
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#52 SH-2 Slave V IRQ
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#53 SH2 Master H IRQ (MD 0) (ERROR)
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#54 SH2 Slave H IRQ (MD 0) (ERROR)
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#55 SH2 Master H IRQ (MD 1) (ERROR)
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#56 SH2 Slave H IRQ (MD 1) (ERROR)
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#57 SH2 Master H IRQ (MD 2) (ERROR)
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#58 SH2 Slave H IRQ (MD 2) (ERROR)
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#53 SH2 Master H IRQ (MD 0)
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#54 SH2 Slave H IRQ (MD 0)
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#55 SH2 Master H IRQ (MD 1)
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#56 SH2 Slave H IRQ (MD 1)
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#57 SH2 Master H IRQ (MD 2)
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#58 SH2 Slave H IRQ (MD 2)
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MD VDP check:
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#59 Bitmap Mode Register
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#60 Shift Register
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@ -304,6 +304,7 @@ static int sh2_hint_in_vbl;
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static int sh2_master_vint_pending;
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static int sh2_slave_vint_pending;
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static int _32x_fb_swap;
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static int _32x_hcount_reg,_32x_hcount_compare_val;
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void _32x_check_irqs(running_machine* machine);
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@ -2985,6 +2986,7 @@ TODO:
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*/
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#define PWM_FIFO_SIZE pwm_tm_reg // guess, Marsch calls this register as FIFO width
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#define PWM_CLOCK megadrive_region_pal ? ((MASTER_CLOCK_PAL*3) / 7) : ((MASTER_CLOCK_NTSC*3) / 7)
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static UINT16 pwm_ctrl,pwm_cycle,pwm_tm_reg;
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static UINT16 cur_lch[0x10],cur_rch[0x10];
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@ -3009,7 +3011,7 @@ static void calculate_pwm_timer(void)
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lch_fifo_state = rch_fifo_state = 0x4000;
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lch_index_r = rch_index_r = 0;
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lch_index_w = rch_index_w = 0;
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timer_adjust_oneshot(_32x_pwm_timer, ATTOTIME_IN_HZ(((MASTER_CLOCK_NTSC*3 / 7) / (pwm_cycle - 1))), 0);
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timer_adjust_oneshot(_32x_pwm_timer, ATTOTIME_IN_HZ((PWM_CLOCK) / (pwm_cycle - 1)), 0);
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}
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}
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@ -3054,7 +3056,7 @@ static TIMER_CALLBACK( _32x_pwm_callback )
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if(sh2_slave_pwmint_enable) { cpu_set_input_line(_32x_slave_cpu, SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
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}
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timer_adjust_oneshot(_32x_pwm_timer, ATTOTIME_IN_HZ(((MASTER_CLOCK_NTSC*3 / 7) / (pwm_cycle - 1))), 0);
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timer_adjust_oneshot(_32x_pwm_timer, ATTOTIME_IN_HZ((PWM_CLOCK) / (pwm_cycle - 1)), 0);
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}
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static READ16_HANDLER( _32x_pwm_r )
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@ -3392,7 +3394,7 @@ static WRITE16_HANDLER( _32x_sh2_master_4000_w )
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sh2_master_cmdint_enable = data & 0x2;
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sh2_master_pwmint_enable = data & 0x1;
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if (sh2_master_hint_enable) printf("sh2_master_hint_enable enable!\n");
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//if (sh2_master_hint_enable) printf("sh2_master_hint_enable enable!\n");
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//if (sh2_master_pwmint_enable) printf("sh2_master_pwn_enable enable!\n");
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_32x_check_irqs(space->machine);
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@ -3430,7 +3432,7 @@ static WRITE16_HANDLER( _32x_sh2_slave_4000_w )
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sh2_slave_cmdint_enable = data & 0x2;
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sh2_slave_pwmint_enable = data & 0x1;
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if (sh2_slave_hint_enable) printf("sh2_slave_hint_enable enable!\n");
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//if (sh2_slave_hint_enable) printf("sh2_slave_hint_enable enable!\n");
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//if (sh2_slave_pwmint_enable) printf("sh2_slave_pwm_enable enable!\n");
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_32x_check_irqs(space->machine);
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@ -3461,16 +3463,14 @@ static WRITE16_HANDLER( _32x_sh2_common_4002_w )
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// H Count Register (H Interrupt)
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// 0 = every line
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/**********************************************************************************************/
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static UINT16 hcount;
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static READ16_HANDLER( _32x_sh2_common_4004_r )
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{
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return hcount;
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return _32x_hcount_reg;
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}
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static WRITE16_HANDLER( _32x_sh2_common_4004_w )
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{
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hcount = data & 0xff;
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_32x_hcount_reg = data & 0xff;
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}
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@ -4338,6 +4338,8 @@ static WRITE16_HANDLER( segacd_sub_led_ready_w )
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{
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segacd_redled = (data >> 8)&1;
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segacd_greenled = (data >> 9)&1;
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popmessage("%02x %02x",segacd_greenled,segacd_redled);
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}
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}
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@ -4408,27 +4410,52 @@ static WRITE16_HANDLER( segacd_sub_dataram_part2_w )
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}
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else if (segacd_ram_mode==1)
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{
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printf("Unspported: segacd_sub_dataram_part2_w in mode 1\n");
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printf("Unsupported: segacd_sub_dataram_part2_w in mode 1\n");
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}
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}
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static ADDRESS_MAP_START( segacd_map, ADDRESS_SPACE_PROGRAM, 16 )
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AM_RANGE(0x0000000, 0x007ffff) AM_RAM AM_BASE(&segacd_4meg_prgram)
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AM_RANGE(0x000000, 0x07ffff) AM_RAM AM_BASE(&segacd_4meg_prgram)
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AM_RANGE(0x0080000, 0x00bffff) AM_READWRITE(segacd_sub_dataram_part1_r, segacd_sub_dataram_part1_w) AM_BASE(&segacd_dataram)
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AM_RANGE(0x00c0000, 0x00dffff) AM_READWRITE(segacd_sub_dataram_part2_r, segacd_sub_dataram_part2_w) AM_BASE(&segacd_dataram2)
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AM_RANGE(0x080000, 0x0bffff) AM_READWRITE(segacd_sub_dataram_part1_r, segacd_sub_dataram_part1_w) AM_BASE(&segacd_dataram)
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AM_RANGE(0x0c0000, 0x0dffff) AM_READWRITE(segacd_sub_dataram_part2_r, segacd_sub_dataram_part2_w) AM_BASE(&segacd_dataram2)
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// AM_RANGE(0xfe0000, 0xfe3fff) // backup RAM, odd bytes only!
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AM_RANGE(0x0ff8000 ,0x0ff8001) AM_READWRITE(segacd_sub_led_ready_r, segacd_sub_led_ready_w)
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AM_RANGE(0x0ff8002 ,0x0ff8003) AM_READWRITE(segacd_sub_memory_mode_r, segacd_sub_memory_mode_w)
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// AM_RANGE(0xff0000, 0xff7fff) // PCM, RF5C164
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AM_RANGE(0xff8000 ,0xff8001) AM_READWRITE(segacd_sub_led_ready_r, segacd_sub_led_ready_w)
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AM_RANGE(0xff8002 ,0xff8003) AM_READWRITE(segacd_sub_memory_mode_r, segacd_sub_memory_mode_w)
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AM_RANGE(0x0ff8004 ,0x0ff8005) AM_READWRITE(segacd_cdc_mode_address_r, segacd_cdc_mode_address_w)
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AM_RANGE(0x0ff8006 ,0x0ff8007) AM_READWRITE(segacd_cdc_data_r, segacd_cdc_data_w)
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AM_RANGE(0xff8004 ,0xff8005) AM_READWRITE(segacd_cdc_mode_address_r, segacd_cdc_mode_address_w)
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AM_RANGE(0xff8006 ,0xff8007) AM_READWRITE(segacd_cdc_data_r, segacd_cdc_data_w)
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// AM_RANGE(0xff8008, 0xff8009) // CDC Host Data
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// AM_RANGE(0xff800a, 0xff800b) // CDC DMA Address
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// AM_RANGE(0xff800c, 0xff800d) // Stopwatch timer
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AM_RANGE(0xff800e ,0xff800f) AM_READWRITE(segacd_comms_flags_r, segacd_comms_flags_subcpu_w)
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AM_RANGE(0xff8010 ,0xff801f) AM_READWRITE(segacd_comms_sub_part1_r, segacd_comms_sub_part1_w)
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AM_RANGE(0xff8020 ,0xff802f) AM_READWRITE(segacd_comms_sub_part2_r, segacd_comms_sub_part2_w)
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// AM_RANGE(0xff8030, 0xff8031) // Timer W/INT3
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// AM_RANGE(0xff8032, 0xff8033) // IRQ Mask
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// AM_RANGE(0xff8034, 0xff8035) // CD Fader
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// AM_RANGE(0xff8036, 0xff8037) // CDD Control
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// AM_RANGE(0xff8038, 0xff804b) // CDD Communication ports 0-9
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// AM_RANGE(0xff804c, 0xff804d) // Font Color
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// AM_RANGE(0xff804e, 0xff804f) // Font bit
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// AM_RANGE(0xff8050, 0xff8057) // Font data (read only)
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// AM_RANGE(0xff8058, 0xff8059) // Stamp size
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// AM_RANGE(0xff805a, 0xff805b) // Stamp map base address
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// AM_RANGE(0xff805c, 0xff805d) // Image buffer V cell size
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// AM_RANGE(0xff805e, 0xff805f) // Image buffer start address
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// AM_RANGE(0xff8060, 0xff8061) // Image buffer offset
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// AM_RANGE(0xff8062, 0xff8063) // Image buffer H dot size
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// AM_RANGE(0xff8064, 0xff8065) // Image buffer V dot size
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// AM_RANGE(0xff8066, 0xff8067) // Trace vector base address
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// AM_RANGE(0xff8068, 0xff8069) // Subcode address
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// AM_RANGE(0xff8100, 0xff817f) // Subcode buffer area
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// AM_RANGE(0xff8180, 0xff81ff) // Image of subcode buffer area
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AM_RANGE(0x0ff800e ,0x0ff800f) AM_READWRITE(segacd_comms_flags_r, segacd_comms_flags_subcpu_w)
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AM_RANGE(0x0ff8010 ,0x0ff801f) AM_READWRITE(segacd_comms_sub_part1_r, segacd_comms_sub_part1_w)
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AM_RANGE(0x0ff8020 ,0x0ff802f) AM_READWRITE(segacd_comms_sub_part2_r, segacd_comms_sub_part2_w)
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ADDRESS_MAP_END
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@ -6780,8 +6807,6 @@ static TIMER_DEVICE_CALLBACK( scanline_timer_callback )
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// if (genesis_scanline_counter==0) irq4counter = MEGADRIVE_REG0A_HINT_VALUE;
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// irq4counter = MEGADRIVE_REG0A_HINT_VALUE;
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if (genesis_scanline_counter<=224)
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{
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irq4counter--;
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@ -6808,7 +6833,21 @@ static TIMER_DEVICE_CALLBACK( scanline_timer_callback )
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//if (genesis_scanline_counter==0) irq4_on_timer->adjust(ATTOTIME_IN_USEC(2));
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if(_32x_is_connected)
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{
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_32x_hcount_compare_val++;
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if(_32x_hcount_compare_val >= _32x_hcount_reg)
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{
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_32x_hcount_compare_val = -1;
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if(genesis_scanline_counter < 224 || sh2_hint_in_vbl)
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{
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if(sh2_master_hint_enable) { cpu_set_input_line(_32x_master_cpu,SH2_HINT_IRQ_LEVEL,ASSERT_LINE); }
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if(sh2_slave_hint_enable) { cpu_set_input_line(_32x_slave_cpu,SH2_HINT_IRQ_LEVEL,ASSERT_LINE); }
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}
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}
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}
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if (timer.machine->device("genesis_snd_z80") != NULL)
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@ -6955,13 +6994,17 @@ MACHINE_RESET( megadriv )
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}
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current_fifo_block = fifo_block_a;
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current_fifo_readblock = fifo_block_b;
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current_fifo_write_pos = 0;
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current_fifo_read_pos = 0;
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fifo_block_a_full = 0;
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fifo_block_b_full = 0;
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if(_32x_is_connected)
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{
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current_fifo_block = fifo_block_a;
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current_fifo_readblock = fifo_block_b;
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current_fifo_write_pos = 0;
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current_fifo_read_pos = 0;
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fifo_block_a_full = 0;
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fifo_block_b_full = 0;
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_32x_hcount_compare_val = -1;
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}
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}
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void megadriv_stop_scanline_timer(void)
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@ -7087,6 +7130,8 @@ int megadrive_z80irq_hpos = 320;
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scanline_timer->adjust(attotime_zero);
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if(_32x_is_connected)
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_32x_hcount_compare_val = -1;
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}
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@ -9590,7 +9590,7 @@ Other Sun games
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DRIVER( miniboy7a ) /* (c) 1983, Bonanza Enterprises */
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DRIVER( 39in1 ) /* MAME based bootleg */
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DRIVER( 48in1 ) /* MAME based bootleg */
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DRIVER( 48in1a ) /* MAME based bootleg */
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DRIVER( 48in1a ) /* MAME based bootleg */
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DRIVER( kingpin ) /* (c) 1983 American Communications Laboratories Inc. */
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DRIVER( kingpinm ) /* (c) 1983 American Communications Laboratories Inc. */
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DRIVER( thayers ) /* (c) 1983 RDI Video Systems */
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