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https://github.com/holub/mame
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ncr5390: various improvements (nw)
DMA/DRQ handling is simplified and hopefully more correct. Tested working with mips, interpro and sun4. * added 16 bit dma for ncr53c94 * added reset atn command * refactored dma/drq code * avoid a hang in disconnected selection
This commit is contained in:
Patrick Mackinlay
parent
51c99c26c7
commit
8a754b17a1
@ -1,6 +1,12 @@
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// license:BSD-3-Clause
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// copyright-holders:Olivier Galibert
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/*
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* TODO
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* - 16 bit dma order, alignment and last byte handling
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* - clean up variable naming and protection
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*/
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#include "emu.h"
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#include "ncr5390.h"
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@ -143,6 +149,7 @@ ncr53c90a_device::ncr53c90a_device(const machine_config &mconfig, const char *ta
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ncr53c94_device::ncr53c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: ncr53c90a_device(mconfig, NCR53C94, tag, owner, clock)
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, config3(0)
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, m_busmd(BUSMD_0)
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{
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}
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@ -267,7 +274,7 @@ void ncr5390_device::step(bool timeout)
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if(win != scsi_id) {
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scsi_bus->data_w(scsi_refid, 0);
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scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
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fatalerror("need to wait for bus free\n");
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fatalerror("ncr5390_device::step need to wait for bus free\n");
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}
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state = (state & STATE_MASK) | (ARB_ASSERT_SEL << SUB_SHIFT);
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scsi_bus->ctrl_w(scsi_refid, S_SEL, S_SEL);
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@ -407,10 +414,9 @@ void ncr5390_device::step(bool timeout)
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case DISC_SEL_ARBITRATION_INIT:
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// wait until a command is in the fifo
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if (!fifo_pos && dma_command && !(status & S_TC0)) {
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if (!fifo_pos) {
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// dma starts after bus arbitration/selection is complete
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dma_set(DMA_OUT);
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step(false);
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check_drq();
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break;
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}
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@ -680,7 +686,7 @@ void ncr5390_device::function_bus_complete()
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state = IDLE;
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istatus |= I_FUNCTION|I_BUS;
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dma_set(DMA_NONE);
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drq_clear();
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check_drq();
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check_irq();
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}
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@ -690,7 +696,7 @@ void ncr5390_device::function_complete()
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state = IDLE;
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istatus |= I_FUNCTION;
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dma_set(DMA_NONE);
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drq_clear();
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check_drq();
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check_irq();
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}
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@ -700,7 +706,7 @@ void ncr5390_device::bus_complete()
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state = IDLE;
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istatus |= I_BUS;
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dma_set(DMA_NONE);
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drq_clear();
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check_drq();
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check_irq();
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}
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@ -746,16 +752,14 @@ uint8_t ncr5390_device::fifo_pop()
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uint8_t r = fifo[0];
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fifo_pos--;
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memmove(fifo, fifo+1, fifo_pos);
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if((!fifo_pos) && dma_dir == DMA_OUT && !(status & S_TC0))
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drq_set();
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check_drq();
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return r;
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}
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void ncr5390_device::fifo_push(uint8_t val)
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{
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fifo[fifo_pos++] = val;
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if(!drq && dma_dir == DMA_IN && !(status & S_TC0))
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drq_set();
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check_drq();
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}
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READ8_MEMBER(ncr5390_device::fifo_r)
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@ -878,6 +882,7 @@ void ncr5390_device::start_command()
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"Select with ATN and stop sequence\n");
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seq = 0;
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state = DISC_SEL_ARBITRATION_INIT;
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dma_set(dma_command ? DMA_OUT : DMA_NONE);
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arbitrate();
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break;
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@ -896,6 +901,7 @@ void ncr5390_device::start_command()
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state = INIT_XFR;
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xfr_phase = scsi_bus->ctrl_r() & S_PHASE_MASK;
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dma_set(dma_command ? ((xfr_phase & S_INP) ? DMA_IN : DMA_OUT) : DMA_NONE);
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check_drq();
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step(false);
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break;
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@ -936,8 +942,14 @@ void ncr5390_device::start_command()
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command_pop_and_chain();
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break;
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case CI_RESET_ATN:
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LOGMASKED(LOG_COMMAND, "Reset ATN\n");
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scsi_bus->ctrl_w(scsi_refid, 0, S_ATN);
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command_pop_and_chain();
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break;
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default:
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fatalerror("start unimplemented command %02x\n", c);
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fatalerror("ncr5390_device::start_command unimplemented command %02x\n", c);
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}
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}
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@ -1065,16 +1077,17 @@ WRITE8_MEMBER(ncr5390_device::clock_w)
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void ncr5390_device::dma_set(int dir)
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{
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dma_dir = dir;
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if(dma_dir == DMA_OUT && fifo_pos != 16 && ((tcounter > fifo_pos) || !tcounter))
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drq_set();
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// account for data already in the fifo
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if (dir == DMA_OUT && fifo_pos)
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decrement_tcounter(fifo_pos);
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}
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void ncr5390_device::dma_w(uint8_t val)
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{
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fifo_push(val);
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decrement_tcounter();
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if(fifo_pos == 16 || (status & S_TC0))
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drq_clear();
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check_drq();
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step(false);
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}
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@ -1082,34 +1095,41 @@ uint8_t ncr5390_device::dma_r()
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{
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uint8_t r = fifo_pop();
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decrement_tcounter();
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if(!fifo_pos || (status & S_TC0))
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drq_clear();
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check_drq();
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step(false);
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return r;
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}
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void ncr5390_device::drq_set()
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void ncr5390_device::check_drq()
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{
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if(!drq) {
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drq = true;
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bool drq_state = drq;
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switch (dma_dir) {
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case DMA_NONE:
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drq_state = false;
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break;
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case DMA_IN: // device to memory
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drq_state = !(status & S_TC0) && fifo_pos;
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break;
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case DMA_OUT: // memory to device
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drq_state = !(status & S_TC0) && fifo_pos < 16;
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break;
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}
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if (drq_state != drq) {
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drq = drq_state;
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m_drq_handler(drq);
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}
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}
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void ncr5390_device::drq_clear()
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{
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if(drq) {
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drq = false;
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m_drq_handler(drq);
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}
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}
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void ncr5390_device::decrement_tcounter()
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void ncr5390_device::decrement_tcounter(int count)
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{
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if (!dma_command)
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return;
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tcounter--;
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tcounter -= count;
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if (tcounter == 0)
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status |= S_TC0;
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}
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@ -1186,3 +1206,69 @@ void ncr53c94_device::reset_soft()
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ncr53c90a_device::reset_soft();
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}
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u16 ncr53c94_device::dma16_r()
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{
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// check fifo underflow
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if (fifo_pos < 2)
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fatalerror("ncr53c94_device::dma16_r fifo_pos %d\n", fifo_pos);
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// pop two bytes from fifo
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u16 const data = (fifo[0] << 8) | fifo[1];
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fifo_pos -= 2;
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memmove(fifo, fifo + 2, fifo_pos);
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// update drq
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decrement_tcounter(2);
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check_drq();
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step(false);
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return data;
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}
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void ncr53c94_device::dma16_w(u16 data)
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{
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// check fifo overflow
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if (fifo_pos > 14)
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fatalerror("ncr53c94_device::dma16_w fifo_pos %d\n", fifo_pos);
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// push two bytes into fifo
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fifo[fifo_pos++] = data >> 8;
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fifo[fifo_pos++] = data;
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// update drq
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decrement_tcounter(2);
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check_drq();
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step(false);
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}
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void ncr53c94_device::check_drq()
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{
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if (m_busmd != BUSMD_0)
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{
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bool drq_state = drq;
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switch (dma_dir) {
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case DMA_NONE:
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drq_state = false;
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break;
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case DMA_IN: // device to memory
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drq_state = !(status & S_TC0) && fifo_pos > 1;
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break;
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case DMA_OUT: // memory to device
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drq_state = !(status & S_TC0) && fifo_pos < 15;
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break;
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}
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if (drq_state != drq) {
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drq = drq_state;
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m_drq_handler(drq);
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}
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}
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else
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ncr5390_device::check_drq();
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}
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@ -207,8 +207,7 @@ protected:
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bool test_mode;
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void dma_set(int dir);
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void drq_set();
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void drq_clear();
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virtual void check_drq();
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void start_command();
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void step(bool timeout);
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@ -222,10 +221,7 @@ protected:
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void command_pop_and_chain();
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void check_irq();
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protected:
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virtual void reset_soft();
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private:
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void reset_disconnect();
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uint8_t fifo_pop();
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@ -236,7 +232,7 @@ private:
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void delay(int cycles);
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void delay_cycles(int cycles);
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void decrement_tcounter();
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void decrement_tcounter(int count = 1);
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devcb_write_line m_irq_handler;
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devcb_write_line m_drq_handler;
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@ -270,6 +266,18 @@ protected:
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S_INTERRUPT = 0x80,
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};
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enum conf2_mask : u8
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{
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PGDP = 0x01, // pass through/generate data parity
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PGRP = 0x02, // pass through/generate register parity
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ACDPE = 0x04, // abort on command/data parity error
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S2FE = 0x08, // scsi-2 features enable
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TSDR = 0x10, // tri-state dma request
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SBO = 0x20, // select byte order
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LSP = 0x40, // latch scsi phase
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DAE = 0x80, // data alignment enable
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};
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private:
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u8 config2;
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};
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@ -279,6 +287,15 @@ class ncr53c94_device : public ncr53c90a_device
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public:
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ncr53c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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enum busmd_t : u8
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{
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BUSMD_0 = 0, // single bus: 8-bit host, 8 bit dma
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BUSMD_1 = 1, // single bus: 8 bit host, 16 bit dma
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BUSMD_2 = 2, // two buses: 8 bit multiplexed host, 16 bit dma
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BUSMD_3 = 3, // two buses: 8 bit host, 16 bit dma
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};
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void set_busmd(busmd_t const busmd) { m_busmd = busmd; }
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virtual void map(address_map &map) override;
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DECLARE_READ8_MEMBER(conf3_r) { return config3; };
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@ -288,13 +305,25 @@ public:
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virtual DECLARE_READ8_MEMBER(read) override;
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virtual DECLARE_WRITE8_MEMBER(write) override;
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u16 dma16_r();
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void dma16_w(u16 data);
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protected:
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enum conf3_mask : u8
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{
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BS8 = 0x01, // burst size 8
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MDM = 0x02, // modify dma mode
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LBTM = 0x04, // last byte transfer mode
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};
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virtual void device_start() override;
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virtual void reset_soft() override;
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virtual void check_drq() override;
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private:
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u8 config3;
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u8 fifo_align;
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busmd_t m_busmd;
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};
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DECLARE_DEVICE_TYPE(NCR5390, ncr5390_device)
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