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Modernize nes_apu device. (nw)

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Needs merging with N2A03 cpu core.
This commit is contained in:
Ivan Vangelista 2013-11-05 20:38:57 +00:00
parent a96d323817
commit 8abb340ad3
19 changed files with 522 additions and 444 deletions
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514
src/emu/sound/nes_apu.c
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@ -47,36 +47,8 @@
#include "emu.h"
#include "nes_apu.h"
#include "cpu/m6502/n2a03.h"
#include "devlegcy.h"
#include "nes_defs.h"
/* GLOBAL CONSTANTS */
#define SYNCS_MAX1 0x20
#define SYNCS_MAX2 0x80
/* GLOBAL VARIABLES */
struct nesapu_state
{
apu_t APU; /* Actual APUs */
float apu_incsize; /* Adjustment increment */
uint32 samps_per_sync; /* Number of samples per vsync */
uint32 buffer_size; /* Actual buffer size in bytes */
uint32 real_rate; /* Actual playback rate */
uint8 noise_lut[NOISE_LONG]; /* Noise sample lookup table */
uint32 vbl_times[0x20]; /* VBL durations in samples */
uint32 sync_times1[SYNCS_MAX1]; /* Samples per sync table */
uint32 sync_times2[SYNCS_MAX2]; /* Samples per sync table */
sound_stream *stream;
};
INLINE nesapu_state *get_safe_token(device_t *device)
{
assert(device != NULL);
assert(device->type() == NES);
return (nesapu_state *)downcast<nesapu_device *>(device)->token();
}
/* INTERNAL FUNCTIONS */
@ -90,22 +62,22 @@ static void create_vbltimes(uint32 * table,const uint8 *vbl,unsigned int rate)
}
/* INITIALIZE SAMPLE TIMES IN TERMS OF VSYNCS */
static void create_syncs(nesapu_state *info, unsigned long sps)
void nesapu_device::create_syncs(unsigned long sps)
{
int i;
unsigned long val = sps;
for (i = 0; i < SYNCS_MAX1; i++)
{
info->sync_times1[i] = val;
m_sync_times1[i] = val;
val += sps;
}
val = 0;
for (i = 0; i < SYNCS_MAX2; i++)
{
info->sync_times2[i] = val;
info->sync_times2[i] >>= 2;
m_sync_times2[i] = val;
m_sync_times2[i] >>= 2;
val += sps;
}
}
@ -127,10 +99,147 @@ static void create_noise(uint8 *buf, const int bits, int size)
}
}
const device_type NES_APU = &device_creator<nesapu_device>;
nesapu_device::nesapu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, NES_APU, "N2A03 APU", tag, owner, clock, "nesapu", __FILE__),
device_sound_interface(mconfig, *this),
m_apu_incsize(0.0d),
m_samps_per_sync(0),
m_buffer_size(0),
m_real_rate(0),
m_stream(NULL)
{
for (int i = 0; i < NOISE_LONG; i++)
{
m_noise_lut[i] = 0;
}
for (int i = 0; i < 0X20; i++)
{
m_vbl_times[i] = 0;
}
for (int i = 0; i < SYNCS_MAX1; i++)
{
m_sync_times1[i] = 0;
}
for (int i = 0; i < SYNCS_MAX2; i++)
{
m_sync_times2[i] = 0;
}
}
//-------------------------------------------------
// device_config_complete - perform any
// operations now that the configuration is
// complete
//-------------------------------------------------
void nesapu_device::device_config_complete()
{
// inherit a copy of the static data
const nesapu_interface *intf = reinterpret_cast<const nesapu_interface *>(static_config());
if (intf != NULL)
*static_cast<nesapu_interface *>(this) = *intf;
// or initialize to defaults if none provided
else
{
m_cpu_tag = "";
}
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void nesapu_device::device_start()
{
int rate = clock() / 4;
int i;
/* Initialize global variables */
m_samps_per_sync = rate / ATTOSECONDS_TO_HZ(machine().primary_screen->frame_period().attoseconds);
m_buffer_size = m_samps_per_sync;
m_real_rate = m_samps_per_sync * ATTOSECONDS_TO_HZ(machine().primary_screen->frame_period().attoseconds);
m_apu_incsize = (float) (clock() / (float) m_real_rate);
/* Use initializer calls */
create_noise(m_noise_lut, 13, NOISE_LONG);
create_vbltimes(m_vbl_times,vbl_length,m_samps_per_sync);
create_syncs(m_samps_per_sync);
/* Adjust buffer size if 16 bits */
m_buffer_size+=m_samps_per_sync;
/* Initialize individual chips */
(m_APU.dpcm).memory = &machine().device(m_cpu_tag)->memory().space(AS_PROGRAM);
m_stream = machine().sound().stream_alloc(*this, 0, 1, rate, this);
/* register for save */
for (i = 0; i < 2; i++)
{
save_item(NAME(m_APU.squ[i].regs), i);
save_item(NAME(m_APU.squ[i].vbl_length), i);
save_item(NAME(m_APU.squ[i].freq), i);
save_item(NAME(m_APU.squ[i].phaseacc), i);
save_item(NAME(m_APU.squ[i].output_vol), i);
save_item(NAME(m_APU.squ[i].env_phase), i);
save_item(NAME(m_APU.squ[i].sweep_phase), i);
save_item(NAME(m_APU.squ[i].adder), i);
save_item(NAME(m_APU.squ[i].env_vol), i);
save_item(NAME(m_APU.squ[i].enabled), i);
}
save_item(NAME(m_APU.tri.regs));
save_item(NAME(m_APU.tri.linear_length));
save_item(NAME(m_APU.tri.vbl_length));
save_item(NAME(m_APU.tri.write_latency));
save_item(NAME(m_APU.tri.phaseacc));
save_item(NAME(m_APU.tri.output_vol));
save_item(NAME(m_APU.tri.adder));
save_item(NAME(m_APU.tri.counter_started));
save_item(NAME(m_APU.tri.enabled));
save_item(NAME(m_APU.noi.regs));
save_item(NAME(m_APU.noi.cur_pos));
save_item(NAME(m_APU.noi.vbl_length));
save_item(NAME(m_APU.noi.phaseacc));
save_item(NAME(m_APU.noi.output_vol));
save_item(NAME(m_APU.noi.env_phase));
save_item(NAME(m_APU.noi.env_vol));
save_item(NAME(m_APU.noi.enabled));
save_item(NAME(m_APU.dpcm.regs));
save_item(NAME(m_APU.dpcm.address));
save_item(NAME(m_APU.dpcm.length));
save_item(NAME(m_APU.dpcm.bits_left));
save_item(NAME(m_APU.dpcm.phaseacc));
save_item(NAME(m_APU.dpcm.output_vol));
save_item(NAME(m_APU.dpcm.cur_byte));
save_item(NAME(m_APU.dpcm.enabled));
save_item(NAME(m_APU.dpcm.irq_occurred));
save_item(NAME(m_APU.dpcm.vol));
save_item(NAME(m_APU.regs));
#ifdef USE_QUEUE
save_item(NAME(m_APU.queue));
save_item(NAME(m_APU.head));
save_item(NAME(m_APU.tail));
#else
save_item(NAME(m_APU.buf_pos));
save_item(NAME(m_APU.step_mode));
#endif
}
/* TODO: sound channels should *ALL* have DC volume decay */
/* OUTPUT SQUARE WAVE SAMPLE (VALUES FROM -16 to +15) */
static int8 apu_square(nesapu_state *info, square_t *chan)
int8 nesapu_device::apu_square(square_t *chan)
{
int env_delay;
int sweep_delay;
@ -146,7 +255,7 @@ static int8 apu_square(nesapu_state *info, square_t *chan)
return 0;
/* enveloping */
env_delay = info->sync_times1[chan->regs[0] & 0x0F];
env_delay = m_sync_times1[chan->regs[0] & 0x0F];
/* decay is at a rate of (env_regs + 1) / 240 secs */
chan->env_phase -= 4;
@ -169,7 +278,7 @@ static int8 apu_square(nesapu_state *info, square_t *chan)
/* freqsweeps */
if ((chan->regs[1] & 0x80) && (chan->regs[1] & 7))
{
sweep_delay = info->sync_times1[(chan->regs[1] >> 4) & 7];
sweep_delay = m_sync_times1[(chan->regs[1] >> 4) & 7];
chan->sweep_phase -= 2;
while (chan->sweep_phase < 0)
{
@ -185,7 +294,7 @@ static int8 apu_square(nesapu_state *info, square_t *chan)
|| (chan->freq >> 16) < 4)
return 0;
chan->phaseacc -= (float) info->apu_incsize; /* # of cycles per sample */
chan->phaseacc -= (float) m_apu_incsize; /* # of cycles per sample */
while (chan->phaseacc < 0)
{
@ -205,7 +314,7 @@ static int8 apu_square(nesapu_state *info, square_t *chan)
}
/* OUTPUT TRIANGLE WAVE SAMPLE (VALUES FROM -16 to +15) */
static int8 apu_triangle(nesapu_state *info, triangle_t *chan)
int8 nesapu_device::apu_triangle(triangle_t *chan)
{
int freq;
int8 output;
@ -244,7 +353,7 @@ static int8 apu_triangle(nesapu_state *info, triangle_t *chan)
if (freq < 4) /* inaudible */
return 0;
chan->phaseacc -= (float) info->apu_incsize; /* # of cycles per sample */
chan->phaseacc -= (float) m_apu_incsize; /* # of cycles per sample */
while (chan->phaseacc < 0)
{
chan->phaseacc += freq;
@ -263,7 +372,7 @@ static int8 apu_triangle(nesapu_state *info, triangle_t *chan)
}
/* OUTPUT NOISE WAVE SAMPLE (VALUES FROM -16 to +15) */
static int8 apu_noise(nesapu_state *info, noise_t *chan)
int8 nesapu_device::apu_noise(noise_t *chan)
{
int freq, env_delay;
uint8 outvol;
@ -278,7 +387,7 @@ static int8 apu_noise(nesapu_state *info, noise_t *chan)
return 0;
/* enveloping */
env_delay = info->sync_times1[chan->regs[0] & 0x0F];
env_delay = m_sync_times1[chan->regs[0] & 0x0F];
/* decay is at a rate of (env_regs + 1) / 240 secs */
chan->env_phase -= 4;
@ -302,7 +411,7 @@ static int8 apu_noise(nesapu_state *info, noise_t *chan)
return 0;
freq = noise_freq[chan->regs[2] & 0x0F];
chan->phaseacc -= (float) info->apu_incsize; /* # of cycles per sample */
chan->phaseacc -= (float) m_apu_incsize; /* # of cycles per sample */
while (chan->phaseacc < 0)
{
chan->phaseacc += freq;
@ -319,11 +428,11 @@ static int8 apu_noise(nesapu_state *info, noise_t *chan)
else
outvol = 0x0F - chan->env_vol;
output = info->noise_lut[chan->cur_pos];
output = m_noise_lut[chan->cur_pos];
if (output > outvol)
output = outvol;
if (info->noise_lut[chan->cur_pos] & 0x80) /* make it negative */
if (m_noise_lut[chan->cur_pos] & 0x80) /* make it negative */
output = -output;
return (int8) output;
@ -342,7 +451,7 @@ INLINE void apu_dpcmreset(dpcm_t *chan)
/* OUTPUT DPCM WAVE SAMPLE (VALUES FROM -64 to +63) */
/* TODO: centerline naughtiness */
static int8 apu_dpcm(nesapu_state *info, dpcm_t *chan)
int8 nesapu_device::apu_dpcm(dpcm_t *chan)
{
int freq, bit_pos;
@ -355,7 +464,7 @@ static int8 apu_dpcm(nesapu_state *info, dpcm_t *chan)
if (chan->enabled)
{
freq = dpcm_clocks[chan->regs[0] & 0x0F];
chan->phaseacc -= (float) info->apu_incsize; /* # of cycles per sample */
chan->phaseacc -= (float) m_apu_incsize; /* # of cycles per sample */
while (chan->phaseacc < 0)
{
@ -372,7 +481,7 @@ static int8 apu_dpcm(nesapu_state *info, dpcm_t *chan)
if (chan->regs[0] & 0x80) /* IRQ Generator */
{
chan->irq_occurred = TRUE;
downcast<n2a03_device &>(info->APU.dpcm.memory->device()).set_input_line(N2A03_APU_IRQ_LINE, ASSERT_LINE);
downcast<n2a03_device &>(m_APU.dpcm.memory->device()).set_input_line(N2A03_APU_IRQ_LINE, ASSERT_LINE);
}
break;
}
@ -383,7 +492,7 @@ static int8 apu_dpcm(nesapu_state *info, dpcm_t *chan)
bit_pos = 7 - (chan->bits_left & 7);
if (7 == bit_pos)
{
chan->cur_byte = info->APU.dpcm.memory->read_byte(chan->address);
chan->cur_byte = m_APU.dpcm.memory->read_byte(chan->address);
chan->address++;
chan->length--;
}
@ -406,7 +515,7 @@ static int8 apu_dpcm(nesapu_state *info, dpcm_t *chan)
}
/* WRITE REGISTER VALUE */
INLINE void apu_regwrite(nesapu_state *info,int address, uint8 value)
inline void nesapu_device::apu_regwrite(int address, uint8 value)
{
int chan = (address & 4) ? 1 : 0;
@ -415,57 +524,57 @@ INLINE void apu_regwrite(nesapu_state *info,int address, uint8 value)
/* squares */
case APU_WRA0:
case APU_WRB0:
info->APU.squ[chan].regs[0] = value;
m_APU.squ[chan].regs[0] = value;
break;
case APU_WRA1:
case APU_WRB1:
info->APU.squ[chan].regs[1] = value;
m_APU.squ[chan].regs[1] = value;
break;
case APU_WRA2:
case APU_WRB2:
info->APU.squ[chan].regs[2] = value;
if (info->APU.squ[chan].enabled)
info->APU.squ[chan].freq = ((((info->APU.squ[chan].regs[3] & 7) << 8) + value) + 1) << 16;
m_APU.squ[chan].regs[2] = value;
if (m_APU.squ[chan].enabled)
m_APU.squ[chan].freq = ((((m_APU.squ[chan].regs[3] & 7) << 8) + value) + 1) << 16;
break;
case APU_WRA3:
case APU_WRB3:
info->APU.squ[chan].regs[3] = value;
m_APU.squ[chan].regs[3] = value;
if (info->APU.squ[chan].enabled)
if (m_APU.squ[chan].enabled)
{
info->APU.squ[chan].vbl_length = info->vbl_times[value >> 3];
info->APU.squ[chan].env_vol = 0;
info->APU.squ[chan].freq = ((((value & 7) << 8) + info->APU.squ[chan].regs[2]) + 1) << 16;
m_APU.squ[chan].vbl_length = m_vbl_times[value >> 3];
m_APU.squ[chan].env_vol = 0;
m_APU.squ[chan].freq = ((((value & 7) << 8) + m_APU.squ[chan].regs[2]) + 1) << 16;
}
break;
/* triangle */
case APU_WRC0:
info->APU.tri.regs[0] = value;
m_APU.tri.regs[0] = value;
if (info->APU.tri.enabled)
if (m_APU.tri.enabled)
{ /* ??? */
if (FALSE == info->APU.tri.counter_started)
info->APU.tri.linear_length = info->sync_times2[value & 0x7F];
if (FALSE == m_APU.tri.counter_started)
m_APU.tri.linear_length = m_sync_times2[value & 0x7F];
}
break;
case 0x4009:
/* unused */
info->APU.tri.regs[1] = value;
m_APU.tri.regs[1] = value;
break;
case APU_WRC2:
info->APU.tri.regs[2] = value;
m_APU.tri.regs[2] = value;
break;
case APU_WRC3:
info->APU.tri.regs[3] = value;
m_APU.tri.regs[3] = value;
/* this is somewhat of a hack. there is some latency on the Real
** Thing between when trireg0 is written to and when the linear
@ -483,121 +592,121 @@ INLINE void apu_regwrite(nesapu_state *info,int address, uint8 value)
*/
/* used to be 3, but now we run the clock faster, so base it on samples/sync */
info->APU.tri.write_latency = (info->samps_per_sync + 239) / 240;
m_APU.tri.write_latency = (m_samps_per_sync + 239) / 240;
if (info->APU.tri.enabled)
if (m_APU.tri.enabled)
{
info->APU.tri.counter_started = FALSE;
info->APU.tri.vbl_length = info->vbl_times[value >> 3];
info->APU.tri.linear_length = info->sync_times2[info->APU.tri.regs[0] & 0x7F];
m_APU.tri.counter_started = FALSE;
m_APU.tri.vbl_length = m_vbl_times[value >> 3];
m_APU.tri.linear_length = m_sync_times2[m_APU.tri.regs[0] & 0x7F];
}
break;
/* noise */
case APU_WRD0:
info->APU.noi.regs[0] = value;
m_APU.noi.regs[0] = value;
break;
case 0x400D:
/* unused */
info->APU.noi.regs[1] = value;
m_APU.noi.regs[1] = value;
break;
case APU_WRD2:
info->APU.noi.regs[2] = value;
m_APU.noi.regs[2] = value;
break;
case APU_WRD3:
info->APU.noi.regs[3] = value;
m_APU.noi.regs[3] = value;
if (info->APU.noi.enabled)
if (m_APU.noi.enabled)
{
info->APU.noi.vbl_length = info->vbl_times[value >> 3];
info->APU.noi.env_vol = 0; /* reset envelope */
m_APU.noi.vbl_length = m_vbl_times[value >> 3];
m_APU.noi.env_vol = 0; /* reset envelope */
}
break;
/* DMC */
case APU_WRE0:
info->APU.dpcm.regs[0] = value;
m_APU.dpcm.regs[0] = value;
if (0 == (value & 0x80)) {
downcast<n2a03_device &>(info->APU.dpcm.memory->device()).set_input_line(N2A03_APU_IRQ_LINE, CLEAR_LINE);
info->APU.dpcm.irq_occurred = FALSE;
downcast<n2a03_device &>(m_APU.dpcm.memory->device()).set_input_line(N2A03_APU_IRQ_LINE, CLEAR_LINE);
m_APU.dpcm.irq_occurred = FALSE;
}
break;
case APU_WRE1: /* 7-bit DAC */
//info->APU.dpcm.regs[1] = value - 0x40;
info->APU.dpcm.regs[1] = value & 0x7F;
info->APU.dpcm.vol = (info->APU.dpcm.regs[1]-64);
//m_APU.dpcm.regs[1] = value - 0x40;
m_APU.dpcm.regs[1] = value & 0x7F;
m_APU.dpcm.vol = (m_APU.dpcm.regs[1]-64);
break;
case APU_WRE2:
info->APU.dpcm.regs[2] = value;
//apu_dpcmreset(info->APU.dpcm);
m_APU.dpcm.regs[2] = value;
//apu_dpcmreset(m_APU.dpcm);
break;
case APU_WRE3:
info->APU.dpcm.regs[3] = value;
m_APU.dpcm.regs[3] = value;
break;
case APU_IRQCTRL:
if(value & 0x80)
info->APU.step_mode = 5;
m_APU.step_mode = 5;
else
info->APU.step_mode = 4;
m_APU.step_mode = 4;
break;
case APU_SMASK:
if (value & 0x01)
info->APU.squ[0].enabled = TRUE;
m_APU.squ[0].enabled = TRUE;
else
{
info->APU.squ[0].enabled = FALSE;
info->APU.squ[0].vbl_length = 0;
m_APU.squ[0].enabled = FALSE;
m_APU.squ[0].vbl_length = 0;
}
if (value & 0x02)
info->APU.squ[1].enabled = TRUE;
m_APU.squ[1].enabled = TRUE;
else
{
info->APU.squ[1].enabled = FALSE;
info->APU.squ[1].vbl_length = 0;
m_APU.squ[1].enabled = FALSE;
m_APU.squ[1].vbl_length = 0;
}
if (value & 0x04)
info->APU.tri.enabled = TRUE;
m_APU.tri.enabled = TRUE;
else
{
info->APU.tri.enabled = FALSE;
info->APU.tri.vbl_length = 0;
info->APU.tri.linear_length = 0;
info->APU.tri.counter_started = FALSE;
info->APU.tri.write_latency = 0;
m_APU.tri.enabled = FALSE;
m_APU.tri.vbl_length = 0;
m_APU.tri.linear_length = 0;
m_APU.tri.counter_started = FALSE;
m_APU.tri.write_latency = 0;
}
if (value & 0x08)
info->APU.noi.enabled = TRUE;
m_APU.noi.enabled = TRUE;
else
{
info->APU.noi.enabled = FALSE;
info->APU.noi.vbl_length = 0;
m_APU.noi.enabled = FALSE;
m_APU.noi.vbl_length = 0;
}
if (value & 0x10)
{
/* only reset dpcm values if DMA is finished */
if (FALSE == info->APU.dpcm.enabled)
if (FALSE == m_APU.dpcm.enabled)
{
info->APU.dpcm.enabled = TRUE;
apu_dpcmreset(&info->APU.dpcm);
m_APU.dpcm.enabled = TRUE;
apu_dpcmreset(&m_APU.dpcm);
}
}
else
info->APU.dpcm.enabled = FALSE;
m_APU.dpcm.enabled = FALSE;
info->APU.dpcm.irq_occurred = FALSE;
m_APU.dpcm.irq_occurred = FALSE;
break;
default:
@ -608,192 +717,52 @@ logerror("invalid apu write: $%02X at $%04X\n", value, address);
}
}
/* UPDATE SOUND BUFFER USING CURRENT DATA */
INLINE void apu_update(nesapu_state *info, stream_sample_t *buffer16, int samples)
{
int accum;
while (samples--)
{
accum = apu_square(info, &info->APU.squ[0]);
accum += apu_square(info, &info->APU.squ[1]);
accum += apu_triangle(info, &info->APU.tri);
accum += apu_noise(info, &info->APU.noi);
accum += apu_dpcm(info, &info->APU.dpcm);
/* 8-bit clamps */
if (accum > 127)
accum = 127;
else if (accum < -128)
accum = -128;
*(buffer16++)=accum<<8;
}
}
/* READ VALUES FROM REGISTERS */
INLINE uint8 apu_read(nesapu_state *info,int address)
inline uint8 nesapu_device::apu_read(int address)
{
if (address == 0x15) /*FIXED* Address $4015 has different behaviour*/
{
int readval = 0;
if (info->APU.squ[0].vbl_length > 0)
if (m_APU.squ[0].vbl_length > 0)
readval |= 0x01;
if (info->APU.squ[1].vbl_length > 0)
if (m_APU.squ[1].vbl_length > 0)
readval |= 0x02;
if (info->APU.tri.vbl_length > 0)
if (m_APU.tri.vbl_length > 0)
readval |= 0x04;
if (info->APU.noi.vbl_length > 0)
if (m_APU.noi.vbl_length > 0)
readval |= 0x08;
if (info->APU.dpcm.enabled == TRUE)
if (m_APU.dpcm.enabled == TRUE)
readval |= 0x10;
if (info->APU.dpcm.irq_occurred == TRUE)
if (m_APU.dpcm.irq_occurred == TRUE)
readval |= 0x80;
return readval;
}
else
return info->APU.regs[address];
return m_APU.regs[address];
}
/* WRITE VALUE TO TEMP REGISTRY AND QUEUE EVENT */
INLINE void apu_write(nesapu_state *info,int address, uint8 value)
inline void nesapu_device::apu_write(int address, uint8 value)
{
info->APU.regs[address]=value;
info->stream->update();
apu_regwrite(info,address,value);
m_APU.regs[address]=value;
m_stream->update();
apu_regwrite(address,value);
}
/* EXTERNAL INTERFACE FUNCTIONS */
/* REGISTER READ/WRITE FUNCTIONS */
READ8_DEVICE_HANDLER( nes_psg_r ) {return apu_read(get_safe_token(device),offset);}
WRITE8_DEVICE_HANDLER( nes_psg_w ) {apu_write(get_safe_token(device),offset,data);}
READ8_MEMBER( nesapu_device::read ) {return apu_read(offset);}
WRITE8_MEMBER( nesapu_device::write ) {apu_write(offset,data);}
/* UPDATE APU SYSTEM */
static STREAM_UPDATE( nes_psg_update_sound )
{
nesapu_state *info = (nesapu_state *)param;
apu_update(info, outputs[0], samples);
}
/* INITIALIZE APU SYSTEM */
static DEVICE_START( nesapu )
{
const nes_interface *intf = (const nes_interface *)device->static_config();
nesapu_state *info = get_safe_token(device);
int rate = device->clock() / 4;
int i;
/* Initialize global variables */
info->samps_per_sync = rate / ATTOSECONDS_TO_HZ(device->machine().primary_screen->frame_period().attoseconds);
info->buffer_size = info->samps_per_sync;
info->real_rate = info->samps_per_sync * ATTOSECONDS_TO_HZ(device->machine().primary_screen->frame_period().attoseconds);
info->apu_incsize = (float) (device->clock() / (float) info->real_rate);
/* Use initializer calls */
create_noise(info->noise_lut, 13, NOISE_LONG);
create_vbltimes(info->vbl_times,vbl_length,info->samps_per_sync);
create_syncs(info, info->samps_per_sync);
/* Adjust buffer size if 16 bits */
info->buffer_size+=info->samps_per_sync;
/* Initialize individual chips */
(info->APU.dpcm).memory = &device->machine().device(intf->cpu_tag)->memory().space(AS_PROGRAM);
info->stream = device->machine().sound().stream_alloc(*device, 0, 1, rate, info, nes_psg_update_sound);
/* register for save */
for (i = 0; i < 2; i++)
{
device->save_item(NAME(info->APU.squ[i].regs), i);
device->save_item(NAME(info->APU.squ[i].vbl_length), i);
device->save_item(NAME(info->APU.squ[i].freq), i);
device->save_item(NAME(info->APU.squ[i].phaseacc), i);
device->save_item(NAME(info->APU.squ[i].output_vol), i);
device->save_item(NAME(info->APU.squ[i].env_phase), i);
device->save_item(NAME(info->APU.squ[i].sweep_phase), i);
device->save_item(NAME(info->APU.squ[i].adder), i);
device->save_item(NAME(info->APU.squ[i].env_vol), i);
device->save_item(NAME(info->APU.squ[i].enabled), i);
}
device->save_item(NAME(info->APU.tri.regs));
device->save_item(NAME(info->APU.tri.linear_length));
device->save_item(NAME(info->APU.tri.vbl_length));
device->save_item(NAME(info->APU.tri.write_latency));
device->save_item(NAME(info->APU.tri.phaseacc));
device->save_item(NAME(info->APU.tri.output_vol));
device->save_item(NAME(info->APU.tri.adder));
device->save_item(NAME(info->APU.tri.counter_started));
device->save_item(NAME(info->APU.tri.enabled));
device->save_item(NAME(info->APU.noi.regs));
device->save_item(NAME(info->APU.noi.cur_pos));
device->save_item(NAME(info->APU.noi.vbl_length));
device->save_item(NAME(info->APU.noi.phaseacc));
device->save_item(NAME(info->APU.noi.output_vol));
device->save_item(NAME(info->APU.noi.env_phase));
device->save_item(NAME(info->APU.noi.env_vol));
device->save_item(NAME(info->APU.noi.enabled));
device->save_item(NAME(info->APU.dpcm.regs));
device->save_item(NAME(info->APU.dpcm.address));
device->save_item(NAME(info->APU.dpcm.length));
device->save_item(NAME(info->APU.dpcm.bits_left));
device->save_item(NAME(info->APU.dpcm.phaseacc));
device->save_item(NAME(info->APU.dpcm.output_vol));
device->save_item(NAME(info->APU.dpcm.cur_byte));
device->save_item(NAME(info->APU.dpcm.enabled));
device->save_item(NAME(info->APU.dpcm.irq_occurred));
device->save_item(NAME(info->APU.dpcm.vol));
device->save_item(NAME(info->APU.regs));
#ifdef USE_QUEUE
device->save_item(NAME(info->APU.queue));
device->save_item(NAME(info->APU.head));
device->save_item(NAME(info->APU.tail));
#else
device->save_item(NAME(info->APU.buf_pos));
device->save_item(NAME(info->APU.step_mode));
#endif
}
const device_type NES = &device_creator<nesapu_device>;
nesapu_device::nesapu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, NES, "N2A03 APU", tag, owner, clock, "nesapu", __FILE__),
device_sound_interface(mconfig, *this)
{
m_token = global_alloc_clear(nesapu_state);
}
//-------------------------------------------------
// device_config_complete - perform any
// operations now that the configuration is
// complete
//-------------------------------------------------
void nesapu_device::device_config_complete()
{
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void nesapu_device::device_start()
{
DEVICE_START_NAME( nesapu )(this);
}
//-------------------------------------------------
// sound_stream_update - handle a stream update
@ -801,6 +770,23 @@ void nesapu_device::device_start()
void nesapu_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
{
// should never get here
fatalerror("sound_stream_update called; not applicable to legacy sound devices\n");
int accum;
memset( outputs[0], 0, samples*sizeof(*outputs[0]) );
while (samples--)
{
accum = apu_square(&m_APU.squ[0]);
accum += apu_square(&m_APU.squ[1]);
accum += apu_triangle(&m_APU.tri);
accum += apu_noise(&m_APU.noi);
accum += apu_dpcm(&m_APU.dpcm);
/* 8-bit clamps */
if (accum > 127)
accum = 127;
else if (accum < -128)
accum = -128;
*(outputs[0]++)=accum<<8;
}
}

47
src/emu/sound/nes_apu.h
View File

@ -27,7 +27,6 @@
#define __NES_APU_H__
/* AN EXPLANATION
*
* The NES APU is actually integrated into the Nintendo processor.
@ -35,24 +34,29 @@
* Also make sure to correspond the memory regions to those used in the
* processor, as each is shared.
*/
#include "nes_defs.h"
/* GLOBAL CONSTANTS */
#define SYNCS_MAX1 0x20
#define SYNCS_MAX2 0x80
struct nes_interface
struct nesapu_interface
{
const char *cpu_tag; /* CPU tag */
const char *m_cpu_tag; /* CPU tag */
};
DECLARE_READ8_DEVICE_HANDLER( nes_psg_r );
DECLARE_WRITE8_DEVICE_HANDLER( nes_psg_w );
class nesapu_device : public device_t,
public device_sound_interface
public device_sound_interface,
public nesapu_interface
{
public:
nesapu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
~nesapu_device() { global_free(m_token); }
~nesapu_device() {}
// access to legacy token
void *token() const { assert(m_token != NULL); return m_token; }
DECLARE_READ8_MEMBER( read );
DECLARE_WRITE8_MEMBER( write );
protected:
// device-level overrides
virtual void device_config_complete();
@ -60,12 +64,31 @@ protected:
// sound stream update overrides
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
private:
// internal state
void *m_token;
apu_t m_APU; /* Actual APUs */
float m_apu_incsize; /* Adjustment increment */
uint32 m_samps_per_sync; /* Number of samples per vsync */
uint32 m_buffer_size; /* Actual buffer size in bytes */
uint32 m_real_rate; /* Actual playback rate */
uint8 m_noise_lut[NOISE_LONG]; /* Noise sample lookup table */
uint32 m_vbl_times[0x20]; /* VBL durations in samples */
uint32 m_sync_times1[SYNCS_MAX1]; /* Samples per sync table */
uint32 m_sync_times2[SYNCS_MAX2]; /* Samples per sync table */
sound_stream *m_stream;
void create_syncs(unsigned long sps);
int8 apu_square(square_t *chan);
int8 apu_triangle(triangle_t *chan);
int8 apu_noise(noise_t *chan);
int8 apu_dpcm(dpcm_t *chan);
inline void apu_regwrite(int address, uint8 value);
inline uint8 apu_read(int address);
inline void apu_write(int address, uint8 value);
};
extern const device_type NES;
extern const device_type NES_APU;
#endif /* __NES_APU_H__ */

82
src/emu/sound/nes_defs.h
View File

@ -26,6 +26,8 @@
#ifndef __NES_DEFS_H__
#define __NES_DEFS_H__
#include "nes_defs.h"
/* BOOLEAN CONSTANTS */
#ifndef TRUE
#define TRUE 1
@ -50,8 +52,12 @@ typedef UINT8 boolean;
struct queue_t
{
queue_t():
pos(0),
reg(""),val("") {}
int pos;
unsigned char reg,val;
unsigned char reg, val;
};
#endif
@ -86,6 +92,23 @@ struct queue_t
/* Square Wave */
struct square_t
{
square_t()
{
for (int i = 0; i < 4; i++)
{
regs[i] = 0;
}
vbl_length =0;
freq = 0;
phaseacc = 0.0d;
output_vol = 0.0d;
env_phase = 0.0d;
sweep_phase = 0.0d;
adder = 0;
env_vol = 0;
enabled = false;
}
uint8 regs[4];
int vbl_length;
int freq;
@ -101,6 +124,22 @@ struct square_t
/* Triangle Wave */
struct triangle_t
{
triangle_t()
{
for (int i = 0; i < 4; i++)
{
regs[i] = 0;
}
linear_length =0;
vbl_length =0;
write_latency = 0;
phaseacc = 0.0d;
output_vol = 0.0d;
adder = 0;
counter_started = false;
enabled = false;
}
uint8 regs[4]; /* regs[1] unused */
int linear_length;
int vbl_length;
@ -115,6 +154,21 @@ struct triangle_t
/* Noise Wave */
struct noise_t
{
noise_t()
{
for (int i = 0; i < 4; i++)
{
regs[i] = 0;
}
cur_pos =0;
vbl_length =0;
phaseacc = 0.0d;
output_vol = 0.0d;
env_phase = 0.0d;
env_vol = 0;
enabled = false;
}
uint8 regs[4]; /* regs[1] unused */
int cur_pos;
int vbl_length;
@ -128,6 +182,24 @@ struct noise_t
/* DPCM Wave */
struct dpcm_t
{
dpcm_t()
{
for (int i = 0; i < 4; i++)
{
regs[i] = 0;
}
address = 0;
length = 0;
bits_left = 0;
phaseacc = 0.0d;
output_vol = 0.0d;
cur_byte = 0;
enabled = false;
irq_occurred = false;
memory = NULL;
vol = '\u0000';
}
uint8 regs[4];
uint32 address;
uint32 length;
@ -144,6 +216,14 @@ struct dpcm_t
/* APU type */
struct apu_t
{
apu_t()
{
memset(regs, 0, sizeof(regs));
buffer = NULL;
buf_pos = 0;
step_mode = 0;
}
/* Sound channels */
square_t squ[2];
triangle_t tri;

4
src/emu/sound/sound.mak
View File

@ -403,10 +403,10 @@ endif
#-------------------------------------------------
# Nintendo custom sound chips
#@src/emu/sound/nes_apu.h,SOUNDS += NES
#@src/emu/sound/nes_apu.h,SOUNDS += NES_APU
#-------------------------------------------------
ifneq ($(filter NES,$(SOUNDS)),)
ifneq ($(filter NES_APU,$(SOUNDS)),)
SOUNDOBJS += $(SOUNDOBJ)/nes_apu.o
endif

16
src/mame/audio/dkong.c
View File

@ -1313,16 +1313,16 @@ static ADDRESS_MAP_START( dkong3_sound1_map, AS_PROGRAM, 8, dkong_state )
AM_RANGE(0x0000, 0x01ff) AM_RAM
AM_RANGE(0x4016, 0x4016) AM_LATCH8_READ("latch1") /* overwrite default */
AM_RANGE(0x4017, 0x4017) AM_LATCH8_READ("latch2")
AM_RANGE(0x4000, 0x4017) AM_DEVREAD_LEGACY("nes1", nes_psg_r)
AM_RANGE(0x4000, 0x4017) AM_DEVWRITE_LEGACY("nes1", nes_psg_w)
AM_RANGE(0x4000, 0x4017) AM_DEVREAD("nesapu1", nesapu_device, read)
AM_RANGE(0x4000, 0x4017) AM_DEVWRITE("nesapu1", nesapu_device, write)
AM_RANGE(0xe000, 0xffff) AM_ROM
ADDRESS_MAP_END
static ADDRESS_MAP_START( dkong3_sound2_map, AS_PROGRAM, 8, dkong_state )
AM_RANGE(0x0000, 0x01ff) AM_RAM
AM_RANGE(0x4016, 0x4016) AM_LATCH8_READ("latch3") /* overwrite default */
AM_RANGE(0x4000, 0x4017) AM_DEVREAD_LEGACY("nes2", nes_psg_r)
AM_RANGE(0x4000, 0x4017) AM_DEVWRITE_LEGACY("nes2", nes_psg_w)
AM_RANGE(0x4000, 0x4017) AM_DEVREAD("nesapu2", nesapu_device, read)
AM_RANGE(0x4000, 0x4017) AM_DEVWRITE("nesapu2", nesapu_device, write)
AM_RANGE(0xe000, 0xffff) AM_ROM
ADDRESS_MAP_END
@ -1332,8 +1332,8 @@ ADDRESS_MAP_END
*
*************************************/
static const nes_interface nes_interface_1 = { "n2a03a" };
static const nes_interface nes_interface_2 = { "n2a03b" };
static const nesapu_interface nes_interface_1 = { "n2a03a" };
static const nesapu_interface nes_interface_2 = { "n2a03b" };
const tms5110_interface tms_interface = {
NULL,
@ -1466,11 +1466,11 @@ MACHINE_CONFIG_FRAGMENT( dkong3_audio )
MCFG_LATCH8_ADD( "latch3")
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("nes1", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu1", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(nes_interface_1)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
MCFG_SOUND_ADD("nes2", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu2", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(nes_interface_2)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)

37
src/mame/drivers/cham24.c
View File

@ -66,8 +66,14 @@ class cham24_state : public driver_device
public:
cham24_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu") { }
m_maincpu(*this, "maincpu"),
m_nesapu(*this, "nesapu"),
m_ppu(*this, "ppu") { }
required_device<cpu_device> m_maincpu;
required_device<nesapu_device> m_nesapu;
required_device<ppu2c0x_device> m_ppu;
UINT8* m_nt_ram;
UINT8* m_nt_page[4];
UINT32 m_in_0;
@ -92,7 +98,6 @@ public:
UINT32 screen_update_cham24(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
void cham24_set_mirroring( int mirroring );
void ppu_irq(int *ppu_regs);
required_device<cpu_device> m_maincpu;
};
@ -145,26 +150,22 @@ READ8_MEMBER(cham24_state::nt_r)
WRITE8_MEMBER(cham24_state::sprite_dma_w)
{
int source = (data & 7);
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
ppu->spriteram_dma(space, source);
m_ppu->spriteram_dma(space, source);
}
READ8_MEMBER(cham24_state::psg_4015_r)
{
device_t *device = machine().device("nes");
return nes_psg_r(device,space,0x15);
return m_nesapu->read(space,0x15);
}
WRITE8_MEMBER(cham24_state::psg_4015_w)
{
device_t *device = machine().device("nes");
nes_psg_w(device,space,0x15, data);
m_nesapu->write(space,0x15, data);
}
WRITE8_MEMBER(cham24_state::psg_4017_w)
{
device_t *device = machine().device("nes");
nes_psg_w(device,space,0x17, data);
m_nesapu->write(space,0x17, data);
}
@ -241,7 +242,7 @@ WRITE8_MEMBER(cham24_state::cham24_mapper_w)
static ADDRESS_MAP_START( cham24_map, AS_PROGRAM, 8, cham24_state )
AM_RANGE(0x0000, 0x07ff) AM_RAM /* NES RAM */
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes", nes_psg_r, nes_psg_w) /* PSG primary registers */
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nesapu", nesapu_device, read, write) /* PSG primary registers */
AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_w)
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg_4015_r, psg_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(cham24_IN0_r, cham24_IN0_w) /* IN0 - input port 1 */
@ -271,7 +272,7 @@ static INPUT_PORTS_START( cham24 )
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
INPUT_PORTS_END
static const nes_interface cham24_interface_1 =
static const nesapu_interface cham24_interface_1 =
{
"maincpu"
};
@ -282,8 +283,7 @@ void cham24_state::machine_reset()
void cham24_state::palette_init()
{
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
ppu->init_palette(machine(), 0);
m_ppu->init_palette(machine(), 0);
}
void cham24_state::ppu_irq(int *ppu_regs)
@ -307,8 +307,7 @@ void cham24_state::video_start()
UINT32 cham24_state::screen_update_cham24(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
/* render the ppu */
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
ppu->render(bitmap, 0, 0, 0, 0);
m_ppu->render(bitmap, 0, 0, 0, 0);
return 0;
}
@ -323,7 +322,7 @@ void cham24_state::machine_start()
memcpy(&dst[0xc000], &src[0x0f8000], 0x4000);
/* uses 8K swapping, all ROM!*/
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x0000, 0x1fff, "bank1");
m_ppu->space(AS_PROGRAM).install_read_bank(0x0000, 0x1fff, "bank1");
membank("bank1")->set_base(memregion("gfx1")->base());
/* need nametable ram, though. I doubt this uses more than 2k, but it starts up configured for 4 */
@ -334,7 +333,7 @@ void cham24_state::machine_start()
m_nt_page[3] = m_nt_ram + 0xc00;
/* and read/write handlers */
machine().device("ppu")->memory().space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff,read8_delegate(FUNC(cham24_state::nt_r), this), write8_delegate(FUNC(cham24_state::nt_w), this));
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff,read8_delegate(FUNC(cham24_state::nt_r), this), write8_delegate(FUNC(cham24_state::nt_w), this));
}
DRIVER_INIT_MEMBER(cham24_state,cham24)
@ -368,7 +367,7 @@ static MACHINE_CONFIG_START( cham24, cham24_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("nes", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(cham24_interface_1)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)

38
src/mame/drivers/famibox.c
View File

@ -71,8 +71,15 @@ class famibox_state : public driver_device
public:
famibox_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu") { }
m_maincpu(*this, "maincpu"),
m_nesapu(*this, "nesapu"),
m_ppu(*this, "ppu") { }
required_device<cpu_device> m_maincpu;
required_device<nesapu_device> m_nesapu;
required_device<ppu2c0x_device> m_ppu;
UINT8* m_nt_ram;
UINT8* m_nt_page[4];
@ -117,7 +124,6 @@ public:
void famicombox_bankswitch(UINT8 bank);
void famicombox_reset();
void ppu_irq(int *ppu_regs);
required_device<cpu_device> m_maincpu;
};
/******************************************************
@ -181,27 +187,23 @@ READ8_MEMBER(famibox_state::famibox_nt_r)
WRITE8_MEMBER(famibox_state::sprite_dma_w)
{
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
int source = (data & 7);
ppu->spriteram_dma(space, source);
m_ppu->spriteram_dma(space, source);
}
READ8_MEMBER(famibox_state::psg_4015_r)
{
device_t *device = machine().device("nes");
return nes_psg_r(device, space, 0x15);
return m_nesapu->read(space, 0x15);
}
WRITE8_MEMBER(famibox_state::psg_4015_w)
{
device_t *device = machine().device("nes");
nes_psg_w(device, space, 0x15, data);
m_nesapu->write(space, 0x15, data);
}
WRITE8_MEMBER(famibox_state::psg_4017_w)
{
device_t *device = machine().device("nes");
nes_psg_w(device, space, 0x17, data);
m_nesapu->write(space, 0x17, data);
}
/******************************************************
@ -393,7 +395,7 @@ WRITE8_MEMBER(famibox_state::famibox_system_w)
static ADDRESS_MAP_START( famibox_map, AS_PROGRAM, 8, famibox_state )
AM_RANGE(0x0000, 0x1fff) AM_RAM
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes", nes_psg_r, nes_psg_w) /* PSG primary registers */
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nesapu", nesapu_device, read, write) /* PSG primary registers */
AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_w)
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg_4015_r, psg_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(famibox_IN0_r, famibox_IN0_w) /* IN0 - input port 1 */
@ -509,15 +511,14 @@ INPUT_PORTS_END
*******************************************************/
static const nes_interface famibox_interface_1 =
static const nesapu_interface famibox_interface_1 =
{
"maincpu"
};
void famibox_state::palette_init()
{
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
ppu->init_palette(machine(), 0);
m_ppu->init_palette(machine(), 0);
}
void famibox_state::ppu_irq(int *ppu_regs)
@ -541,8 +542,7 @@ void famibox_state::video_start()
UINT32 famibox_state::screen_update_famibox(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
/* render the ppu */
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
ppu->render(bitmap, 0, 0, 0, 0);
m_ppu->render(bitmap, 0, 0, 0, 0);
return 0;
}
@ -563,8 +563,8 @@ void famibox_state::machine_start()
m_nt_page[2] = m_nt_ram + 0x800;
m_nt_page[3] = m_nt_ram + 0xc00;
machine().device("ppu")->memory().space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(famibox_state::famibox_nt_r), this), write8_delegate(FUNC(famibox_state::famibox_nt_w), this));
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x0000, 0x1fff, "ppubank1");
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(famibox_state::famibox_nt_r), this), write8_delegate(FUNC(famibox_state::famibox_nt_w), this));
m_ppu->space(AS_PROGRAM).install_read_bank(0x0000, 0x1fff, "ppubank1");
famicombox_bankswitch(0);
@ -601,7 +601,7 @@ static MACHINE_CONFIG_START( famibox, famibox_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("nes", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(famibox_interface_1)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)

104
src/mame/drivers/multigam.c
View File

@ -116,8 +116,14 @@ class multigam_state : public driver_device
public:
multigam_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu") { }
m_maincpu(*this, "maincpu"),
m_nesapu(*this, "nesapu"),
m_ppu(*this, "ppu") { }
required_device<cpu_device> m_maincpu;
required_device<nesapu_device> m_nesapu;
required_device<ppu2c0x_device> m_ppu;
UINT8* m_nt_ram;
UINT8* m_vram;
UINT8* m_nt_page[4];
@ -195,7 +201,6 @@ public:
void multigm3_decrypt(UINT8* mem, int memsize, const UINT8* decode_nibble);
void multigam3_mmc3_scanline_cb(int scanline, int vblank, int blanked);
void ppu_irq(int *ppu_regs);
required_device<cpu_device> m_maincpu;
};
@ -286,26 +291,22 @@ void multigam_state::set_videoram_bank( int start, int count, int bank, int bank
WRITE8_MEMBER(multigam_state::sprite_dma_w)
{
int source = (data & 7);
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
ppu->spriteram_dma(space, source);
m_ppu->spriteram_dma(space, source);
}
READ8_MEMBER(multigam_state::psg_4015_r)
{
device_t *device = machine().device("nes");
return nes_psg_r(device, space, 0x15);
return m_nesapu->read(space, 0x15);
}
WRITE8_MEMBER(multigam_state::psg_4015_w)
{
device_t *device = machine().device("nes");
nes_psg_w(device, space, 0x15, data);
m_nesapu->write(space, 0x15, data);
}
WRITE8_MEMBER(multigam_state::psg_4017_w)
{
device_t *device = machine().device("nes");
nes_psg_w(device, space, 0x17, data);
m_nesapu->write(space, 0x17, data);
}
/******************************************************
@ -408,7 +409,7 @@ static ADDRESS_MAP_START( multigam_map, AS_PROGRAM, 8, multigam_state )
AM_RANGE(0x0000, 0x07ff) AM_RAM /* NES RAM */
AM_RANGE(0x0800, 0x0fff) AM_RAM /* additional RAM */
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes", nes_psg_r, nes_psg_w) /* PSG primary registers */
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nesapu", nesapu_device, read, write) /* PSG primary registers */
AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_w)
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg_4015_r, psg_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(multigam_IN0_r, multigam_IN0_w) /* IN0 - input port 1 */
@ -428,7 +429,7 @@ static ADDRESS_MAP_START( multigmt_map, AS_PROGRAM, 8, multigam_state )
AM_RANGE(0x3000, 0x3000) AM_WRITE(multigam_switch_prg_rom)
AM_RANGE(0x3fff, 0x3fff) AM_WRITE(multigam_switch_gfx_rom)
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes", nes_psg_r, nes_psg_w) /* PSG primary registers */
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nesapu", nesapu_device, read, write) /* PSG primary registers */
AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_w)
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg_4015_r, psg_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(multigam_IN0_r, multigam_IN0_w) /* IN0 - input port 1 */
@ -461,8 +462,6 @@ void multigam_state::multigam3_mmc3_scanline_cb( int scanline, int vblank, int b
WRITE8_MEMBER(multigam_state::multigam3_mmc3_rom_switch_w)
{
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
/* basically, a MMC3 mapper from the nes */
int bankmask = m_multigam3_mmc3_prg_size == 0x40000 ? 0x1f : 0x0f;
@ -599,11 +598,11 @@ WRITE8_MEMBER(multigam_state::multigam3_mmc3_rom_switch_w)
case 0x6000: /* disable irqs */
machine().device("maincpu")->execute().set_input_line(M6502_IRQ_LINE, CLEAR_LINE);
ppu->set_scanline_callback(ppu2c0x_scanline_delegate());
m_ppu->set_scanline_callback(ppu2c0x_scanline_delegate());
break;
case 0x6001: /* enable irqs */
ppu->set_scanline_callback(ppu2c0x_scanline_delegate(FUNC(multigam_state::multigam3_mmc3_scanline_cb),this));
m_ppu->set_scanline_callback(ppu2c0x_scanline_delegate(FUNC(multigam_state::multigam3_mmc3_scanline_cb),this));
break;
}
}
@ -693,7 +692,7 @@ static ADDRESS_MAP_START( multigm3_map, AS_PROGRAM, 8, multigam_state )
AM_RANGE(0x0000, 0x07ff) AM_RAM /* NES RAM */
AM_RANGE(0x0800, 0x0fff) AM_RAM /* additional RAM */
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes", nes_psg_r, nes_psg_w) /* PSG primary registers */
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nesapu", nesapu_device, read, write) /* PSG primary registers */
AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_w)
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg_4015_r, psg_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(multigam_IN0_r, multigam_IN0_w) /* IN0 - input port 1 */
@ -724,14 +723,13 @@ WRITE8_MEMBER(multigam_state::multigam3_mapper02_rom_switch_w)
void multigam_state::multigam_init_mapper02(UINT8* prg_base, int prg_size)
{
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
UINT8* mem = memregion("maincpu")->base();
memcpy(mem + 0x8000, prg_base + prg_size - 0x8000, 0x8000);
m_maincpu->space(AS_PROGRAM).install_write_handler(0x8000, 0xffff, write8_delegate(FUNC(multigam_state::multigam3_mapper02_rom_switch_w),this));
m_mapper02_prg_base = prg_base;
m_mapper02_prg_size = prg_size;
ppu->set_scanline_callback(ppu2c0x_scanline_delegate());
m_ppu->set_scanline_callback(ppu2c0x_scanline_delegate());
}
/******************************************************
@ -877,8 +875,7 @@ WRITE8_MEMBER(multigam_state::mmc1_rom_switch_w)
void multigam_state::multigam_init_mmc1(UINT8 *prg_base, int prg_size, int chr_bank_base)
{
UINT8* dst = memregion("maincpu")->base();
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
memcpy(&dst[0x8000], prg_base + (prg_size - 0x8000), 0x8000);
m_maincpu->space(AS_PROGRAM).install_write_handler(0x8000, 0xffff, write8_delegate(FUNC(multigam_state::mmc1_rom_switch_w),this));
@ -889,7 +886,7 @@ void multigam_state::multigam_init_mmc1(UINT8 *prg_base, int prg_size, int chr_b
m_mmc1_prg_size = prg_size;
m_mmc1_chr_bank_base = chr_bank_base;
ppu->set_scanline_callback(ppu2c0x_scanline_delegate());
m_ppu->set_scanline_callback(ppu2c0x_scanline_delegate());
};
@ -917,7 +914,6 @@ void multigam_state::multigam_init_mmc1(UINT8 *prg_base, int prg_size, int chr_b
void multigam_state::supergm3_set_bank()
{
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
UINT8* mem = memregion("maincpu")->base();
// video bank
@ -925,8 +921,8 @@ void multigam_state::supergm3_set_bank()
m_supergm3_chr_bank == 0x40 )
{
// VRAM
ppu->space(AS_PROGRAM).install_read_bank(0x0000, 0x1fff, "bank1");
ppu->space(AS_PROGRAM).install_write_bank(0x0000, 0x1fff, "bank1");
m_ppu->space(AS_PROGRAM).install_read_bank(0x0000, 0x1fff, "bank1");
m_ppu->space(AS_PROGRAM).install_write_bank(0x0000, 0x1fff, "bank1");
membank("bank1")->set_base(m_vram);
if (m_supergm3_chr_bank == 0x40)
@ -934,15 +930,15 @@ void multigam_state::supergm3_set_bank()
}
else
{
ppu->space(AS_PROGRAM).install_read_bank(0x0000, 0x03ff, "bank2");
ppu->space(AS_PROGRAM).install_read_bank(0x0400, 0x07ff, "bank3");
ppu->space(AS_PROGRAM).install_read_bank(0x0800, 0x0bff, "bank4");
ppu->space(AS_PROGRAM).install_read_bank(0x0c00, 0x0fff, "bank5");
ppu->space(AS_PROGRAM).install_read_bank(0x1000, 0x13ff, "bank6");
ppu->space(AS_PROGRAM).install_read_bank(0x1400, 0x17ff, "bank7");
ppu->space(AS_PROGRAM).install_read_bank(0x1800, 0x1bff, "bank8");
ppu->space(AS_PROGRAM).install_read_bank(0x1c00, 0x1fff, "bank9");
ppu->space(AS_PROGRAM).unmap_write(0x0000, 0x1fff);
m_ppu->space(AS_PROGRAM).install_read_bank(0x0000, 0x03ff, "bank2");
m_ppu->space(AS_PROGRAM).install_read_bank(0x0400, 0x07ff, "bank3");
m_ppu->space(AS_PROGRAM).install_read_bank(0x0800, 0x0bff, "bank4");
m_ppu->space(AS_PROGRAM).install_read_bank(0x0c00, 0x0fff, "bank5");
m_ppu->space(AS_PROGRAM).install_read_bank(0x1000, 0x13ff, "bank6");
m_ppu->space(AS_PROGRAM).install_read_bank(0x1400, 0x17ff, "bank7");
m_ppu->space(AS_PROGRAM).install_read_bank(0x1800, 0x1bff, "bank8");
m_ppu->space(AS_PROGRAM).install_read_bank(0x1c00, 0x1fff, "bank9");
m_ppu->space(AS_PROGRAM).unmap_write(0x0000, 0x1fff);
set_videorom_bank(0, 8, 0, 8);
}
@ -953,7 +949,7 @@ void multigam_state::supergm3_set_bank()
// title screen
memcpy(mem + 0x8000, mem + 0x18000, 0x8000);
membank("bank10")->set_base(mem + 0x6000);
ppu->set_scanline_callback(ppu2c0x_scanline_delegate());
m_ppu->set_scanline_callback(ppu2c0x_scanline_delegate());
}
else if ((m_supergm3_prg_bank & 0x40) == 0)
{
@ -998,7 +994,7 @@ static ADDRESS_MAP_START( supergm3_map, AS_PROGRAM, 8, multigam_state )
AM_RANGE(0x0000, 0x07ff) AM_RAM /* NES RAM */
AM_RANGE(0x0800, 0x0fff) AM_RAM /* additional RAM */
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes", nes_psg_r, nes_psg_w) /* PSG primary registers */
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nesapu", nesapu_device, read, write) /* PSG primary registers */
AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_w)
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg_4015_r, psg_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(multigam_IN0_r, multigam_IN0_w) /* IN0 - input port 1 */
@ -1144,15 +1140,14 @@ INPUT_PORTS_END
*******************************************************/
static const nes_interface multigam_interface_1 =
static const nesapu_interface multigam_interface_1 =
{
"maincpu"
};
void multigam_state::palette_init()
{
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
ppu->init_palette(machine(), 0);
m_ppu->init_palette(machine(), 0);
}
void multigam_state::ppu_irq(int *ppu_regs)
@ -1176,8 +1171,7 @@ void multigam_state::video_start()
UINT32 multigam_state::screen_update_multigam(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
/* render the ppu */
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
ppu->render(bitmap, 0, 0, 0, 0);
m_ppu->render(bitmap, 0, 0, 0, 0);
return 0;
}
@ -1210,8 +1204,8 @@ void multigam_state::machine_start()
m_nt_page[2] = m_nt_ram + 0x800;
m_nt_page[3] = m_nt_ram + 0xc00;
machine().device("ppu")->memory().space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(multigam_state::multigam_nt_r),this), write8_delegate(FUNC(multigam_state::multigam_nt_w),this));
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x0000, 0x1fff, "bank1");
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(multigam_state::multigam_nt_r),this), write8_delegate(FUNC(multigam_state::multigam_nt_w),this));
m_ppu->space(AS_PROGRAM).install_read_bank(0x0000, 0x1fff, "bank1");
membank("bank1")->set_base(memregion("gfx1")->base());
}
@ -1223,16 +1217,16 @@ MACHINE_START_MEMBER(multigam_state,multigm3)
m_nt_page[2] = m_nt_ram + 0x800;
m_nt_page[3] = m_nt_ram + 0xc00;
machine().device("ppu")->memory().space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(multigam_state::multigam_nt_r),this), write8_delegate(FUNC(multigam_state::multigam_nt_w),this));
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(multigam_state::multigam_nt_r),this), write8_delegate(FUNC(multigam_state::multigam_nt_w),this));
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x0000, 0x03ff, "bank2");
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x0400, 0x07ff, "bank3");
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x0800, 0x0bff, "bank4");
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x0c00, 0x0fff, "bank5");
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x1000, 0x13ff, "bank6");
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x1400, 0x17ff, "bank7");
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x1800, 0x1bff, "bank8");
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_bank(0x1c00, 0x1fff, "bank9");
m_ppu->space(AS_PROGRAM).install_read_bank(0x0000, 0x03ff, "bank2");
m_ppu->space(AS_PROGRAM).install_read_bank(0x0400, 0x07ff, "bank3");
m_ppu->space(AS_PROGRAM).install_read_bank(0x0800, 0x0bff, "bank4");
m_ppu->space(AS_PROGRAM).install_read_bank(0x0c00, 0x0fff, "bank5");
m_ppu->space(AS_PROGRAM).install_read_bank(0x1000, 0x13ff, "bank6");
m_ppu->space(AS_PROGRAM).install_read_bank(0x1400, 0x17ff, "bank7");
m_ppu->space(AS_PROGRAM).install_read_bank(0x1800, 0x1bff, "bank8");
m_ppu->space(AS_PROGRAM).install_read_bank(0x1c00, 0x1fff, "bank9");
set_videorom_bank(0, 8, 0, 8);
};
@ -1245,7 +1239,7 @@ MACHINE_START_MEMBER(multigam_state,supergm3)
m_nt_page[2] = m_nt_ram + 0x800;
m_nt_page[3] = m_nt_ram + 0xc00;
machine().device("ppu")->memory().space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(multigam_state::multigam_nt_r),this), write8_delegate(FUNC(multigam_state::multigam_nt_w),this));
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(multigam_state::multigam_nt_r),this), write8_delegate(FUNC(multigam_state::multigam_nt_w),this));
m_vram = auto_alloc_array(machine(), UINT8, 0x2000);
m_multigmc_mmc3_6000_ram = auto_alloc_array(machine(), UINT8, 0x2000);
@ -1274,7 +1268,7 @@ static MACHINE_CONFIG_START( multigam, multigam_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("nes", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(multigam_interface_1)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)

20
src/mame/drivers/playch10.c
View File

@ -291,12 +291,10 @@ Notes & Todo:
#include "emu.h"
#include "cpu/m6502/n2a03.h"
#include "video/ppu2c0x.h"
#include "cpu/z80/z80.h"
#include "machine/rp5h01.h"
#include "machine/nvram.h"
#include "sound/dac.h"
#include "sound/nes_apu.h"
#include "rendlay.h"
#include "includes/playch10.h"
@ -331,8 +329,7 @@ WRITE8_MEMBER(playch10_state::ram_8w_w)
WRITE8_MEMBER(playch10_state::sprite_dma_w)
{
int source = ( data & 7 );
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu");
ppu->spriteram_dma(space, source);
m_ppu->spriteram_dma(space, source);
}
/* Only used in single monitor bios */
@ -349,20 +346,17 @@ WRITE8_MEMBER(playch10_state::time_w)
READ8_MEMBER(playch10_state::psg_4015_r)
{
device_t *device = machine().device("nes");
return nes_psg_r(device, space, 0x15);
return m_nesapu->read(space, 0x15);
}
WRITE8_MEMBER(playch10_state::psg_4015_w)
{
device_t *device = machine().device("nes");
nes_psg_w(device, space, 0x15, data);
m_nesapu->write(space, 0x15, data);
}
WRITE8_MEMBER(playch10_state::psg_4017_w)
{
device_t *device = machine().device("nes");
nes_psg_w(device, space, 0x17, data);
m_nesapu->write(space, 0x17, data);
}
/******************************************************************************/
@ -398,7 +392,7 @@ static ADDRESS_MAP_START( cart_map, AS_PROGRAM, 8, playch10_state )
AM_RANGE(0x0000, 0x07ff) AM_RAM AM_MIRROR(0x1800) AM_SHARE("work_ram")
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write)
AM_RANGE(0x4011, 0x4011) AM_DEVWRITE("dac", dac_device, write_unsigned8)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes", nes_psg_r, nes_psg_w)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nesapu", nesapu_device, read, write)
AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_w)
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg_4015_r, psg_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(pc10_in0_r, pc10_in0_w)
@ -666,7 +660,7 @@ INTERRUPT_GEN_MEMBER(playch10_state::playch10_interrupt){
device.execute().set_input_line(INPUT_LINE_NMI, PULSE_LINE);
}
static const nes_interface nes_config =
static const nesapu_interface nes_config =
{
"cart"
};
@ -707,7 +701,7 @@ static MACHINE_CONFIG_START( playch10, playch10_state )
// sound hardware
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("nes", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(nes_config)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)

6
src/mame/drivers/punchout.c
View File

@ -370,7 +370,7 @@ static ADDRESS_MAP_START( punchout_sound_map, AS_PROGRAM, 8, punchout_state )
AM_RANGE(0x0000, 0x07ff) AM_RAM
AM_RANGE(0x4016, 0x4016) AM_READ(soundlatch_byte_r)
AM_RANGE(0x4017, 0x4017) AM_READ(soundlatch2_byte_r)
AM_RANGE(0x4000, 0x4017) AM_DEVREADWRITE_LEGACY("nes", nes_psg_r,nes_psg_w)
AM_RANGE(0x4000, 0x4017) AM_DEVREADWRITE("nesapu", nesapu_device, read, write)
AM_RANGE(0xe000, 0xffff) AM_ROM
ADDRESS_MAP_END
@ -912,7 +912,7 @@ GFXDECODE_END
static const nes_interface nes_config =
static const nesapu_interface nes_config =
{
"audiocpu"
};
@ -968,7 +968,7 @@ static MACHINE_CONFIG_START( punchout, punchout_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("nes", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(nes_config)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)

44
src/mame/drivers/vsnes.c
View File

@ -142,9 +142,7 @@ Changes:
#include "cpu/z80/z80.h"
#include "sound/sn76496.h"
#include "rendlay.h"
#include "video/ppu2c0x.h"
#include "sound/dac.h"
#include "sound/nes_apu.h"
#include "includes/vsnes.h"
/******************************************************************************/
@ -153,15 +151,13 @@ Changes:
WRITE8_MEMBER(vsnes_state::sprite_dma_0_w)
{
int source = ( data & 7 );
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu1");
ppu->spriteram_dma( space, source );
m_ppu1->spriteram_dma( space, source );
}
WRITE8_MEMBER(vsnes_state::sprite_dma_1_w)
{
int source = ( data & 7 );
ppu2c0x_device *ppu = machine().device<ppu2c0x_device>("ppu2");
ppu->spriteram_dma( space, source );
m_ppu2->spriteram_dma( space, source );
}
WRITE8_MEMBER(vsnes_state::vsnes_coin_counter_w)
@ -196,44 +192,38 @@ WRITE8_MEMBER(vsnes_state::vsnes_coin_counter_1_w)
READ8_MEMBER(vsnes_state::psg1_4015_r)
{
device_t *device = machine().device("nes1");
return nes_psg_r(device, space, 0x15);
return m_nesapu1->read(space, 0x15);
}
WRITE8_MEMBER(vsnes_state::psg1_4015_w)
{
device_t *device = machine().device("nes1");
nes_psg_w(device, space, 0x15, data);
m_nesapu1->write(space, 0x15, data);
}
WRITE8_MEMBER(vsnes_state::psg1_4017_w)
{
device_t *device = machine().device("nes1");
nes_psg_w(device, space, 0x17, data);
m_nesapu1->write(space, 0x17, data);
}
READ8_MEMBER(vsnes_state::psg2_4015_r)
{
device_t *device = machine().device("nes2");
return nes_psg_r(device, space, 0x15);
return m_nesapu2->read(space, 0x15);
}
WRITE8_MEMBER(vsnes_state::psg2_4015_w)
{
device_t *device = machine().device("nes2");
nes_psg_w(device, space, 0x15, data);
m_nesapu2->write(space, 0x15, data);
}
WRITE8_MEMBER(vsnes_state::psg2_4017_w)
{
device_t *device = machine().device("nes2");
nes_psg_w(device, space, 0x17, data);
m_nesapu2->write(space, 0x17, data);
}
static ADDRESS_MAP_START( vsnes_cpu1_map, AS_PROGRAM, 8, vsnes_state )
AM_RANGE(0x0000, 0x07ff) AM_MIRROR(0x1800) AM_RAM AM_SHARE("work_ram")
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu1", ppu2c0x_device, read, write)
AM_RANGE(0x4011, 0x4011) AM_DEVWRITE("dac1", dac_device, write_unsigned8)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes1", nes_psg_r, nes_psg_w)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nesapu1", nesapu_device, read, write)
AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_0_w)
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg1_4015_r, psg1_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(vsnes_in0_r, vsnes_in0_w)
@ -247,7 +237,7 @@ static ADDRESS_MAP_START( vsnes_cpu2_map, AS_PROGRAM, 8, vsnes_state )
AM_RANGE(0x0000, 0x07ff) AM_MIRROR(0x1800) AM_RAM AM_SHARE("work_ram_1")
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu2", ppu2c0x_device, read, write)
AM_RANGE(0x4011, 0x4011) AM_DEVWRITE("dac2", dac_device, write_unsigned8)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes2", nes_psg_r, nes_psg_w)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nesapu2", nesapu_device, read, write)
AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_1_w)
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg2_4015_r, psg2_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(vsnes_in0_1_r, vsnes_in0_1_w)
@ -264,7 +254,7 @@ static ADDRESS_MAP_START( vsnes_cpu1_bootleg_map, AS_PROGRAM, 8, vsnes_state )
AM_RANGE(0x0000, 0x07ff) AM_MIRROR(0x1800) AM_RAM AM_SHARE("work_ram")
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu1", ppu2c0x_device, read, write)
AM_RANGE(0x4011, 0x4011) AM_DEVWRITE("dac1", dac_device, write_unsigned8)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nes1", nes_psg_r, nes_psg_w)
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nesapu1", nesapu_device, read, write)
AM_RANGE(0x4014, 0x4014) AM_WRITE(sprite_dma_0_w)
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg1_4015_r, psg1_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(vsnes_in0_r, vsnes_in0_w)
@ -1706,12 +1696,12 @@ static INPUT_PORTS_START( supxevs )
PORT_DIPSETTING( 0xc0, "RP2C04-0004" )
INPUT_PORTS_END
static const nes_interface nes_interface_1 =
static const nesapu_interface nes_interface_1 =
{
"maincpu"
};
static const nes_interface nes_interface_2 =
static const nesapu_interface nes_interface_2 =
{
"sub"
};
@ -1744,7 +1734,7 @@ static MACHINE_CONFIG_START( vsnes, vsnes_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("nes1", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu1", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(nes_interface_1)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
@ -1825,11 +1815,11 @@ static MACHINE_CONFIG_START( vsdual, vsnes_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("nes1", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu1", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(nes_interface_1)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
MCFG_SOUND_ADD("nes2", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu2", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(nes_interface_2)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
@ -1881,7 +1871,7 @@ static MACHINE_CONFIG_START( vsnes_bootleg, vsnes_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("nes1", NES, N2A03_DEFAULTCLOCK)
MCFG_SOUND_ADD("nesapu1", NES_APU, N2A03_DEFAULTCLOCK)
MCFG_SOUND_CONFIG(nes_interface_1)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)

6
src/mame/includes/playch10.h
View File

@ -1,4 +1,6 @@
#include "machine/rp5h01.h"
#include "sound/nes_apu.h"
#include "video/ppu2c0x.h"
struct chr_bank
{
@ -12,6 +14,8 @@ public:
playch10_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_nesapu(*this, "nesapu"),
m_ppu(*this, "ppu"),
m_rp5h01(*this, "rp5h01"),
m_ram_8w(*this, "ram_8w"),
m_videoram(*this, "videoram"),
@ -20,6 +24,8 @@ public:
{ }
required_device<cpu_device> m_maincpu;
required_device<nesapu_device> m_nesapu;
required_device<ppu2c0x_device> m_ppu;
optional_device<rp5h01_device> m_rp5h01;
required_shared_ptr<UINT8> m_ram_8w;

11
src/mame/includes/vsnes.h
View File

@ -1,3 +1,6 @@
#include "sound/nes_apu.h"
#include "video/ppu2c0x.h"
class vsnes_state : public driver_device
{
public:
@ -5,12 +8,20 @@ public:
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_subcpu(*this, "sub"),
m_nesapu1(*this, "nesapu1"),
m_nesapu2(*this, "nesapu2"),
m_ppu1(*this, "ppu1"),
m_ppu2(*this, "ppu2"),
m_work_ram(*this, "work_ram"),
m_work_ram_1(*this, "work_ram_1")
{ }
required_device<cpu_device> m_maincpu;
optional_device<cpu_device> m_subcpu;
required_device<nesapu_device> m_nesapu1;
optional_device<nesapu_device> m_nesapu2;
required_device<ppu2c0x_device> m_ppu1;
optional_device<ppu2c0x_device> m_ppu2;
required_shared_ptr<UINT8> m_work_ram;
optional_shared_ptr<UINT8> m_work_ram_1;

2
src/mame/mame.mak
View File

@ -176,7 +176,7 @@ SOUNDS += SN76477
SOUNDS += SN76496
SOUNDS += POKEY
SOUNDS += TIA
SOUNDS += NES
SOUNDS += NES_APU
SOUNDS += ASTROCADE
SOUNDS += NAMCO
SOUNDS += NAMCO_15XX

20
src/mess/drivers/nes.c
View File

@ -13,7 +13,6 @@
#include "emu.h"
#include "includes/nes.h"
#include "cpu/m6502/n2a03.h"
#include "sound/nes_apu.h"
#include "imagedev/flopdrv.h"
#include "formats/nes_dsk.h"
@ -22,20 +21,17 @@
READ8_MEMBER(nes_state::psg_4015_r)
{
device_t *device = machine().device("nessound");
return nes_psg_r(device, space, 0x15);
return m_sound->read(space, 0x15);
}
WRITE8_MEMBER(nes_state::psg_4015_w)
{
device_t *device = machine().device("nessound");
nes_psg_w(device, space, 0x15, data);
m_sound->write(space, 0x15, data);
}
WRITE8_MEMBER(nes_state::psg_4017_w)
{
device_t *device = machine().device("nessound");
nes_psg_w(device, space, 0x17, data);
m_sound->write(space, 0x17, data);
}
WRITE8_MEMBER(nes_state::nes_vh_sprite_dma_w)
@ -46,7 +42,7 @@ WRITE8_MEMBER(nes_state::nes_vh_sprite_dma_w)
static ADDRESS_MAP_START( nes_map, AS_PROGRAM, 8, nes_state )
AM_RANGE(0x0000, 0x07ff) AM_RAM AM_MIRROR(0x1800) /* RAM */
AM_RANGE(0x2000, 0x3fff) AM_DEVREADWRITE("ppu", ppu2c0x_device, read, write) /* PPU registers */
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE_LEGACY("nessound", nes_psg_r, nes_psg_w) /* PSG primary registers */
AM_RANGE(0x4000, 0x4013) AM_DEVREADWRITE("nessound", nesapu_device, read, write) /* PSG primary registers */
AM_RANGE(0x4014, 0x4014) AM_WRITE(nes_vh_sprite_dma_w) /* stupid address space hole */
AM_RANGE(0x4015, 0x4015) AM_READWRITE(psg_4015_r, psg_4015_w) /* PSG status / first control register */
AM_RANGE(0x4016, 0x4016) AM_READWRITE(nes_in0_r, nes_in0_w) /* IN0 - input port 1 */
@ -647,7 +643,7 @@ static INPUT_PORTS_START( famicom )
INPUT_PORTS_END
static const nes_interface nes_apu_interface =
static const nesapu_interface nes_apu_interface =
{
"maincpu"
};
@ -721,7 +717,7 @@ static MACHINE_CONFIG_START( nes, nes_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("nessound", NES, NTSC_CLOCK)
MCFG_SOUND_ADD("nessound", NES_APU, NTSC_CLOCK)
MCFG_SOUND_CONFIG(nes_apu_interface)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
@ -748,7 +744,7 @@ static MACHINE_CONFIG_DERIVED( nespal, nes )
MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 0*8, 30*8-1)
/* sound hardware */
MCFG_SOUND_REPLACE("nessound", NES, PAL_CLOCK)
MCFG_SOUND_REPLACE("nessound", NES_APU, PAL_CLOCK)
MCFG_SOUND_CONFIG(nes_apu_interface)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
MACHINE_CONFIG_END
@ -769,7 +765,7 @@ static MACHINE_CONFIG_DERIVED( dendy, nes )
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC((106.53/(PAL_CLOCK/1000000)) * (PPU_VBLANK_LAST_SCANLINE_PAL-PPU_VBLANK_FIRST_SCANLINE+1+2)))
/* sound hardware */
MCFG_SOUND_REPLACE("nessound", NES, 26601712/15) /* 26.601712MHz / 15 == 1.77344746666... MHz */
MCFG_SOUND_REPLACE("nessound", NES_APU, 26601712/15) /* 26.601712MHz / 15 == 1.77344746666... MHz */
MCFG_SOUND_CONFIG(nes_apu_interface)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90)
MACHINE_CONFIG_END

3
src/mess/includes/nes.h
View File

@ -12,6 +12,7 @@
#include "video/ppu2c0x.h"
#include "machine/nes_slot.h"
#include "sound/nes_apu.h"
#include "imagedev/cassette.h"
// official PCBs
@ -490,7 +491,7 @@ public:
required_device<cpu_device> m_maincpu;
required_device<ppu2c0x_device> m_ppu;
required_device<device_t> m_sound;
required_device<nesapu_device> m_sound;
optional_device<nes_cart_slot_device> m_cartslot;
optional_device<cassette_image_device> m_cassette;

8
src/mess/machine/nes_mmc5.c
View File

@ -41,13 +41,11 @@ const device_type NES_EXROM = &device_creator<nes_exrom_device>;
nes_exrom_device::nes_exrom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: nes_nrom_device(mconfig, NES_EXROM, "NES Cart ExROM (MMC-5) PCB", tag, owner, clock, "nes_exrom", __FILE__)
: nes_nrom_device(mconfig, NES_EXROM, "NES Cart ExROM (MMC-5) PCB", tag, owner, clock, "nes_exrom", __FILE__)
{
}
void nes_exrom_device::device_start()
{
common_start();
@ -333,8 +331,8 @@ WRITE8_MEMBER(nes_exrom_device::write_l)
/* Send $5000-$5015 to the sound chip */
if ((offset >= 0xf00) && (offset <= 0xf15))
{
device_t *m_sound = machine().device("nessound");
nes_psg_w(m_sound, space, offset & 0x1f, data);
nesapu_device *m_sound = machine().device<nesapu_device>("nessound");
m_sound->write(space, offset & 0x1f, data);
return;
}

2
src/mess/machine/nes_mmc5.h
View File

@ -63,7 +63,7 @@ protected:
// MMC-5 contains 1K of internal ram
UINT8 *m_exram;
// int m_nes_vram_sprite[8];
// int m_nes_vram_sprite[8];
};

2
src/mess/mess.mak
View File

@ -161,7 +161,7 @@ SOUNDS += SN76477
SOUNDS += SN76496
SOUNDS += POKEY
SOUNDS += TIA
SOUNDS += NES
SOUNDS += NES_APU
SOUNDS += ASTROCADE
#SOUNDS += NAMCO
#SOUNDS += NAMCO_15XX