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beep_device: removed set_volume

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This commit is contained in:
hap 2016-01-21 22:06:28 +01:00
parent 6965f6ddb4
commit 8acfdd7ee0
16 changed files with 67 additions and 61 deletions
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22
src/devices/sound/beep.cpp
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@ -107,12 +107,12 @@ void beep_device::sound_stream_update(sound_stream &stream, stream_sample_t **in
WRITE_LINE_MEMBER(beep_device::set_state)
{
/* only update if new state is not the same as old state */
state = (state) ? 1 : 0;
if (m_enable == state)
int on = (state) ? 1 : 0;
if (m_enable == on)
return;
m_stream->update();
m_enable = state;
m_enable = on;
/* restart wave from beginning */
m_incr = 0;
@ -120,12 +120,11 @@ WRITE_LINE_MEMBER(beep_device::set_state)
}
//-------------------------------------------------
// setting new frequency starts from beginning
//-------------------------------------------------
void beep_device::set_frequency(int frequency)
void beep_device::set_clock(UINT32 frequency)
{
if (m_frequency == frequency)
return;
@ -135,16 +134,3 @@ void beep_device::set_frequency(int frequency)
m_signal = 0x07fff;
m_incr = 0;
}
//-------------------------------------------------
// change a channel volume
//-------------------------------------------------
void beep_device::set_volume(int volume)
{
m_stream->update();
volume = 100 * volume / 7;
set_output_gain(0, volume);
}

5
src/devices/sound/beep.h
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@ -26,9 +26,8 @@ protected:
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples) override;
public:
DECLARE_WRITE_LINE_MEMBER(set_state); // enable(1)
void set_frequency(int frequency);
void set_volume(int volume);
DECLARE_WRITE_LINE_MEMBER(set_state); // enable/disable sound output
void set_clock(UINT32 frequency); // output frequency
private:
sound_stream *m_stream; /* stream number */

4
src/mame/drivers/byvid.cpp
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@ -559,7 +559,7 @@ READ8_MEMBER( by133_state::m6803_port2_r )
WRITE8_MEMBER( by133_state::m6803_port2_w )
{
//m_u7_b = data >> 1;
m_beep->set_frequency(600);
m_beep->set_clock(600);
m_beep->set_state(BIT(data, 0));
}
@ -581,7 +581,7 @@ WRITE_LINE_MEMBER( by133_state::u11_ca2_w )
WRITE_LINE_MEMBER( by133_state::u7_cb2_w )
{
// red led
m_beep->set_frequency(950);
m_beep->set_clock(950);
m_beep->set_state(state);
}

2
src/mame/drivers/d6800.cpp
View File

@ -281,7 +281,7 @@ WRITE8_MEMBER( d6800_state::d6800_cassette_w )
are in progress (DMA/CB2 line low).
*/
m_beeper->set_frequency(BIT(data, 0) ? 2400 : 1200);
m_beeper->set_clock(BIT(data, 0) ? 2400 : 1200);
m_beeper->set_state(BIT(data, 6) & (m_cb2 ? 1 : 0));
m_portb = data & 0x7f;

6
src/mame/drivers/jr100.cpp
View File

@ -119,7 +119,7 @@ WRITE8_MEMBER(jr100_state::jr100_via_w)
if(m_beep_en)
{
m_beeper->set_state(1);
m_beeper->set_frequency(894886.25 / (double)(m_t1latch) / 2.0);
m_beeper->set_clock(894886.25 / (double)(m_t1latch) / 2.0);
}
}
m_via->write(space,offset,data);
@ -203,8 +203,6 @@ INPUT_PORTS_END
void jr100_state::machine_start()
{
m_beeper->set_frequency(0);
m_beeper->set_state(0);
}
void jr100_state::machine_reset()
@ -365,11 +363,11 @@ QUICKLOAD_LOAD_MEMBER( jr100_state,jr100)
}
static MACHINE_CONFIG_START( jr100, jr100_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu",M6802, XTAL_14_31818MHz / 4) // clock devided internaly by 4
MCFG_CPU_PROGRAM_MAP(jr100_mem)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)

4
src/mame/drivers/jr200.cpp
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@ -312,7 +312,7 @@ WRITE8_MEMBER(jr200_state::jr200_beep_freq_w)
beep_freq = ((m_freq_reg[0]<<8) | (m_freq_reg[1] & 0xff)) + 1;
m_beeper->set_frequency(84000 / beep_freq);
m_beeper->set_clock(84000 / beep_freq);
}
WRITE8_MEMBER(jr200_state::jr200_border_col_w)
@ -512,8 +512,6 @@ GFXDECODE_END
void jr200_state::machine_start()
{
m_beeper->set_frequency(0);
m_beeper->set_state(0);
m_timer_d = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(jr200_state::timer_d_callback),this));
}

2
src/mame/drivers/micronic.cpp
View File

@ -159,7 +159,7 @@ WRITE8_MEMBER( micronic_state::beep_w )
500, 444, 400, 364, 333, 308, 286, 267
};
m_beep->set_frequency(frequency[data & 0x0f]);
m_beep->set_clock(frequency[data & 0x0f]);
m_beep->set_state((data & 0x0f) ? 1 : 0);
}

2
src/mame/drivers/micropin.cpp
View File

@ -225,7 +225,7 @@ WRITE_LINE_MEMBER( micropin_state::p50ca2_w )
WRITE8_MEMBER( micropin_state::p51a_w )
{
static UINT16 frequency[16] = { 387, 435, 488, 517, 581, 652, 691, 775, 870, 977, 1035, 1161, 1304, 1381, 1550, 1740 };
m_beep->set_frequency(frequency[data & 15]);
m_beep->set_clock(frequency[data & 15]);
m_beep_time = 10; // number of 10ms intervals before it is silenced
m_beep->set_state(1);
}

2
src/mame/drivers/nc.cpp
View File

@ -594,7 +594,7 @@ void nc_state::nc_sound_update(int channel)
/* set state */
beeper_device->set_state(on);
/* set frequency */
beeper_device->set_frequency(frequency);
beeper_device->set_clock(frequency);
}
WRITE8_MEMBER(nc_state::nc_sound_w)

5
src/mame/drivers/osi.cpp
View File

@ -349,7 +349,8 @@ WRITE8_MEMBER( c1p_state::osi630_ctrl_w )
WRITE8_MEMBER( c1p_state::osi630_sound_w )
{
if (data) m_beep->set_frequency(49152 / data);
if (data != 0)
m_beep->set_clock(49152 / data);
}
/* Disk Drive */
@ -885,7 +886,7 @@ void sb2m600_state::device_timer(emu_timer &timer, device_timer_id id, int param
{
case TIMER_SETUP_BEEP:
m_beeper->set_state(0);
m_beeper->set_frequency(300);
m_beeper->set_clock(300);
break;
default:
assert_always(FALSE, "Unknown id in sb2m600_state::device_timer");

2
src/mame/drivers/pcxt.cpp
View File

@ -409,7 +409,7 @@ WRITE8_MEMBER(pcxt_state::port_b_w)
// popmessage("%02x\n",data);
// beep->beep_set_state(0);
// beep->beep_set_state(1);
// beep->beep_set_frequency(m_port_b_data);
// beep->beep_set_clock(m_port_b_data);
}
WRITE8_MEMBER(pcxt_state::wss_1_w)

17
src/mame/drivers/rex6000.cpp
View File

@ -220,7 +220,7 @@ WRITE8_MEMBER( rex6000_state::beep_w )
switch (offset)
{
case 0: //alarm mode control
case 0: // alarm mode control
/*
---- ---x beep off
---- --x- continuous beep
@ -231,21 +231,24 @@ WRITE8_MEMBER( rex6000_state::beep_w )
-x-- ---- single alarm
x--- ---- single short beep
*/
//TODO: the beeper frequency and length in alarm mode need to be measured
// TODO: the beeper frequency and length in alarm mode need to be measured
break;
case 1: //tone mode control
case 1: // tone mode control
if (m_beep_mode)
{
m_beep->set_state(BIT(data, 0));
//the beeper frequency is update only if the bit 1 is set
// the beeper frequency is update only if the bit 1 is set
if (BIT(data, 1))
m_beep->set_frequency(16384 / (((m_beep_io[2] | (m_beep_io[3]<<8)) & 0x0fff) + 2));
{
UINT16 div = ((m_beep_io[2] | m_beep_io[3]<<8) & 0x0fff) + 2;
m_beep->set_clock(16384 / div);
}
}
break;
case 4: //select alarm/tone mode
case 4: // select alarm/tone mode
if (m_beep_mode != BIT(data, 0))
m_beep->set_state(0); //turned off when mode changes
m_beep->set_state(0); // turned off when mode changes
m_beep_mode = BIT(data, 0);
break;

2
src/mame/drivers/tmc1800.cpp
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@ -863,7 +863,7 @@ void tmc1800_state::device_timer(emu_timer &timer, device_timer_id id, int param
{
case TIMER_SETUP_BEEP:
m_beeper->set_state(0);
m_beeper->set_frequency(0);
m_beeper->set_clock(0);
break;
default:
assert_always(FALSE, "Unknown id in tmc1800_state::device_timer");

2
src/mame/drivers/x07.cpp
View File

@ -1189,7 +1189,7 @@ WRITE8_MEMBER( x07_state::x07_io_w )
if((data & 0x0e) == 0x0e)
{
UINT16 div = (m_regs_w[2] | m_regs_w[3] << 8) & 0x0fff;
m_beep->set_frequency((div == 0) ? 0 : 192000 / div);
m_beep->set_clock((div == 0) ? 0 : 192000 / div);
m_beep->set_state(1);
m_beep_stop->adjust(attotime::from_msec(m_ram->pointer()[0x450] * 0x20));

4
src/mame/machine/electron.cpp
View File

@ -252,7 +252,7 @@ WRITE8_MEMBER(electron_state::electron_ula_w)
* but the divider is wrong(?), says 16 but results in high pitch,
* 32 is more close
*/
m_beeper->set_frequency( 1000000 / ( 32 * ( data + 1 ) ) );
m_beeper->set_clock( 1000000 / ( 32 * ( data + 1 ) ) );
}
break;
case 0x07: /* Misc. */
@ -331,7 +331,7 @@ void electron_state::electron_interrupt_handler(int mode, int interrupt)
TIMER_CALLBACK_MEMBER(electron_state::setup_beep)
{
m_beeper->set_state( 0 );
m_beeper->set_frequency( 300 );
m_beeper->set_clock( 300 );
}
void electron_state::machine_reset()

47
src/mame/video/electron.cpp
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@ -1,6 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Wilbert Pol
/******************************************************************************
Acorn Electron driver
MESS Driver By:
@ -15,31 +16,51 @@
/*
From the ElectrEm site:
Timing is somewhat of a thorny issue on the Electron. It is almost certain the Electron could have been a much faster machine if BBC Micro OS level compatibility had not been not a design requirement.
Timing is somewhat of a thorny issue on the Electron. It is almost certain the
Electron could have been a much faster machine if BBC Micro OS level
compatibility had not been not a design requirement.
When accessing the ROM regions, the CPU always runs at 2MHz. When accessing the FC (1 MHz bus) or FD (JIM) pages, the CPU always runs at 1MHz.
When accessing the ROM regions, the CPU always runs at 2MHz. When accessing
the FC (1 MHz bus) or FD (JIM) pages, the CPU always runs at 1MHz.
The timing for RAM accesses varies depending on the graphics mode, and how many bytes are required to be read by the video circuits per scanline. When accessing RAM in modes 4-6, the CPU is simply moved to a 1MHz clock. This occurs for any RAM access at any point during the frame.
The timing for RAM accesses varies depending on the graphics mode, and how
many bytes are required to be read by the video circuits per scanline. When
accessing RAM in modes 4-6, the CPU is simply moved to a 1MHz clock. This
occurs for any RAM access at any point during the frame.
In modes 0-3, if the CPU tries to access RAM at any time during which the video circuits are fetching bytes, it is halted by means of receiving a stopped clock until the video circuits next stop fetching bytes.
In modes 0-3, if the CPU tries to access RAM at any time during which the
video circuits are fetching bytes, it is halted by means of receiving a
stopped clock until the video circuits next stop fetching bytes.
Each scanline is drawn in exactly 64us, and of that the video circuits fetch bytes for 40us. In modes 0, 1 and 2, 256 scanlines have pixels on, whereas in mode 3 only 250 scanlines are affected as mode 3 is a 'spaced' mode.
Each scanline is drawn in exactly 64us, and of that the video circuits fetch
bytes for 40us. In modes 0, 1 and 2, 256 scanlines have pixels on, whereas in
mode 3 only 250 scanlines are affected as mode 3 is a 'spaced' mode.
As opposed to one clock generator which changes pace, the 1MHz and 2MHz clocks are always available, so the ULA acts to simply change which clock is piped to the CPU. This means in half of all cases, a further 2MHz cycle is lost waiting for the 2MHz and 1MHz clocks to synchronise during a 2MHz to 1MHz step.
As opposed to one clock generator which changes pace, the 1MHz and 2MHz clocks
are always available, so the ULA acts to simply change which clock is piped to
the CPU. This means in half of all cases, a further 2MHz cycle is lost waiting
for the 2MHz and 1MHz clocks to synchronise during a 2MHz to 1MHz step.
The video circuits run from a constant 2MHz clock, and generate 312 scanlines a frame, one scanline every 128 cycles. This actually gives means the Electron is running at 50.08 frames a second.
The video circuits run from a constant 2MHz clock, and generate 312 scanlines
a frame, one scanline every 128 cycles. This actually gives means the Electron
is running at 50.08 frames a second.
Creating a scanline numbering scheme where the first scanline with pixels is scanline 0, in all modes the end of display interrupt is generated at the end of scanline 255, and the RTC interrupt is generated upon the end of scanline 99.
Creating a scanline numbering scheme where the first scanline with pixels is
scanline 0, in all modes the end of display interrupt is generated at the end
of scanline 255, and the RTC interrupt is generated upon the end of scanline 99.
From investigating some code for vertical split modes printed in Electron User volume 7, issue 7 it seems that the exact timing of the end of display interrupt is somewhere between 24 and 40 cycles after the end of pixels. This may coincide with HSYNC. I have no similarly accurate timing for the real time clock interrupt at this time.
From investigating some code for vertical split modes printed in Electron User
volume 7, issue 7 it seems that the exact timing of the end of display interrupt
is somewhere between 24 and 40 cycles after the end of pixels. This may coincide
with HSYNC. I have no similarly accurate timing for the real time clock
interrupt at this time.
Mode changes are 'immediate', so any change in RAM access timing occurs exactly after the write cycle of the changing instruction. Similarly palette changes take effect immediately. VSYNC is not signalled in any way.
Mode changes are 'immediate', so any change in RAM access timing occurs exactly
after the write cycle of the changing instruction. Similarly palette changes
take effect immediately. VSYNC is not signalled in any way.
*/
void electron_state::video_start()
{
int i;