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https://github.com/holub/mame
synced 2025-05-19 12:18:56 +03:00
small cleanup before next commit
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77b3b088b7
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@ -2064,57 +2064,57 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
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#endif
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#endif /* FLAG_SET_M */
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/* M37710 Transfer C to direct register */
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#undef OP_TCD
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/* M37710 Transfer accumulator to direct register */
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#undef OP_TAD
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#if FLAG_SET_M
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#define OP_TCD() \
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#define OP_TAD() \
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CLK(CLK_OP + CLK_IMPLIED); \
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REG_D = REG_A | REG_B
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#else
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#define OP_TCD() \
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#define OP_TAD() \
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CLK(CLK_OP + CLK_IMPLIED); \
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REG_D = REG_A
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#endif
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/* M37710 Transfer direct register to C */
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#undef OP_TDC
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/* M37710 Transfer direct register to accumulator */
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#undef OP_TDA
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#if FLAG_SET_M
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#define OP_TDC() \
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#define OP_TDA() \
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CLK(CLK_OP + CLK_IMPLIED); \
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FLAG_Z = REG_D; \
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FLAG_N = NFLAG_16(FLAG_Z); \
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REG_A = MAKE_UINT_8(REG_D); \
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REG_B = REG_D & 0xff00
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#else
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#define OP_TDC() \
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#define OP_TDA() \
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CLK(CLK_OP + CLK_IMPLIED); \
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FLAG_Z = REG_A = REG_D; \
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FLAG_N = NFLAG_16(FLAG_Z)
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#endif
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/* M37710 Transfer C to stack pointer */
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#undef OP_TCS
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/* M37710 Transfer accumulator to stack pointer */
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#undef OP_TAS
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#if FLAG_SET_M
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#define OP_TCS() \
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#define OP_TAS() \
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CLK(CLK_OP + CLK_IMPLIED); \
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REG_S = REG_A | REG_B
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#else
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#define OP_TCS() \
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#define OP_TAS() \
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CLK(CLK_OP + CLK_IMPLIED); \
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REG_S = REG_A
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#endif
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/* M37710 Transfer stack pointer to C */
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#undef OP_TSC
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/* M37710 Transfer stack pointer to accumulator */
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#undef OP_TSA
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#if FLAG_SET_M
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#define OP_TSC() \
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#define OP_TSA() \
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CLK(CLK_OP + CLK_IMPLIED); \
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FLAG_Z = REG_S; \
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FLAG_N = NFLAG_16(FLAG_Z); \
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REG_A = MAKE_UINT_8(REG_S); \
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REG_B = REG_S & 0xff00
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#else
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#define OP_TSC() \
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#define OP_TSA() \
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CLK(CLK_OP + CLK_IMPLIED); \
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FLAG_Z = REG_A = REG_S; \
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FLAG_N = NFLAG_16(FLAG_Z)
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@ -2325,7 +2325,7 @@ OP(17, OP_ORA ( DLIY ) ) /* ORA dliy(C) */
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OP(18, OP_CLC ( ) ) /* CLC */
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OP(19, OP_ORA ( AY ) ) /* ORA ay */
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OP(1a, OP_DEC ( ) ) /* DEA (C) */
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OP(1b, OP_TCS ( ) ) /* TCS (G) */
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OP(1b, OP_TAS ( ) ) /* TAS (G) */
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OP(1c, OP_CLB ( A ) ) /* CLB a (C) */
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OP(1d, OP_ORA ( AX ) ) /* ORA ax */
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OP(1e, OP_ASLM ( AX ) ) /* ASL ax */
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@ -2357,7 +2357,7 @@ OP(37, OP_AND ( DLIY ) ) /* AND dliy(G) */
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OP(38, OP_SEC ( ) ) /* SEC */
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OP(39, OP_AND ( AY ) ) /* AND ay */
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OP(3a, OP_INC ( ) ) /* INA (C) */
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OP(3b, OP_TSC ( ) ) /* TSC (G) */
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OP(3b, OP_TSA ( ) ) /* TSA (G) */
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OP(3c, OP_BBC ( A ) ) /* BBC a */
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OP(3d, OP_AND ( AX ) ) /* AND ax */
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OP(3e, OP_ROLM ( AX ) ) /* ROL ax */
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@ -2389,7 +2389,7 @@ OP(57, OP_EOR ( DLIY ) ) /* EOR dliy(G) */
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OP(58, OP_CLI ( ) ) /* CLI */
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OP(59, OP_EOR ( AY ) ) /* EOR ay */
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OP(5a, OP_PHX ( REG_Y ) ) /* PHY (C) */
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OP(5b, OP_TCD ( ) ) /* TCD (G) */
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OP(5b, OP_TAD ( ) ) /* TAD (G) */
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OP(5c, OP_JMPAL( ) ) /* JMP al (G) */
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OP(5d, OP_EOR ( AX ) ) /* EOR ax */
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OP(5e, OP_LSRM ( AX ) ) /* LSR ax */
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@ -2421,7 +2421,7 @@ OP(77, OP_ADC ( DLIY ) ) /* ADC dliy(G) */
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OP(78, OP_SEI ( ) ) /* SEI */
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OP(79, OP_ADC ( AY ) ) /* ADC ay */
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OP(7a, OP_PLX ( REG_Y ) ) /* PLY (C) */
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OP(7b, OP_TDC ( ) ) /* TDC (G) */
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OP(7b, OP_TDA ( ) ) /* TDA (G) */
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OP(7c, OP_JMPAXI( ) ) /* JMP axi (C) */
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OP(7d, OP_ADC ( AX ) ) /* ADC ax */
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OP(7e, OP_RORM ( AX ) ) /* ROR ax */
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