mirror of
https://github.com/holub/mame
synced 2025-05-29 00:53:09 +03:00
Pointer-ified the tms7000 core.
This commit is contained in:
Aaron Giles
parent
8aea6e2b4f
commit
8b670ddddd
@ -24,7 +24,7 @@
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*****************************************************************************/
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// SJE: Changed all references to ICount to icount (to match MAME requirements)
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// SJE: Changed RM/WM macros to reference newly created tms7000 read/write handlers & removed unused SRM() macro
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// SJE: Changed RM/WM macros to reference newly created tms7000 read/write handlers & removed unused SRM(cpustate) macro
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// SJE: Fixed a mistake in tms70x0_pf_w where the wrong register was referenced
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// SJE: Implemented internal register file
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@ -37,13 +37,13 @@
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#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
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typedef struct _tms7000_state tms7000_state;
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/* Private prototypes */
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static void tms7000_set_irq_line(int irqline, int state);
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static CPU_GET_CONTEXT( tms7000 );
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static CPU_SET_CONTEXT( tms7000 );
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static void tms7000_check_IRQ_lines( void );
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static void tms7000_do_interrupt( UINT16 address, UINT8 line );
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static void tms7000_set_irq_line(tms7000_state *cpustate, int irqline, int state);
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static void tms7000_check_IRQ_lines(tms7000_state *cpustate);
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static void tms7000_do_interrupt( tms7000_state *cpustate, UINT16 address, UINT8 line );
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static CPU_EXECUTE( tms7000 );
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static CPU_EXECUTE( tms7000_exl );
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static void tms7000_service_timer1( const device_config *device );
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@ -53,23 +53,19 @@ static UINT16 bcd_sub( UINT16 a, UINT16 b);
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/* Static variables */
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static int tms7000_icount;
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static int tms7000_div_by_16_trigger;
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static int tms7000_cycles_per_INT2;
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#define RM(Addr) ((unsigned)memory_read_byte_8be(cpustate->program, Addr))
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#define WM(Addr,Value) (memory_write_byte_8be(cpustate->program, Addr, Value))
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#define RM(Addr) ((unsigned)memory_read_byte_8be(tms7000.program, Addr))
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#define WM(Addr,Value) (memory_write_byte_8be(tms7000.program, Addr, Value))
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#define IMMBYTE(b) b = ((unsigned)memory_raw_read_byte(tms7000.program, pPC)); pPC++
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#define SIMMBYTE(b) b = ((signed)memory_raw_read_byte(tms7000.program, pPC)); pPC++
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#define IMMWORD(w) w.b.h = (unsigned)memory_raw_read_byte(tms7000.program, pPC++); w.b.l = (unsigned)memory_raw_read_byte(tms7000.program, pPC++)
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#define IMMBYTE(b) b = ((unsigned)memory_raw_read_byte(cpustate->program, pPC)); pPC++
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#define SIMMBYTE(b) b = ((signed)memory_raw_read_byte(cpustate->program, pPC)); pPC++
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#define IMMWORD(w) w.b.h = (unsigned)memory_raw_read_byte(cpustate->program, pPC++); w.b.l = (unsigned)memory_raw_read_byte(cpustate->program, pPC++)
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#define PUSHBYTE(b) pSP++; WM(pSP,b)
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#define PUSHWORD(w) pSP++; WM(pSP,w.b.h); pSP++; WM(pSP,w.b.l)
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#define PULLBYTE(b) b = RM(pSP); pSP--
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#define PULLWORD(w) w.b.l = RM(pSP); pSP--; w.b.h = RM(pSP); pSP--
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typedef struct
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struct _tms7000_state
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{
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PAIR pc; /* Program counter */
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UINT8 sp; /* Stack Pointer */
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@ -81,18 +77,19 @@ typedef struct
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const device_config *device;
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const address_space *program;
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const address_space *io;
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int icount;
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int div_by_16_trigger;
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int cycles_per_INT2;
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UINT8 t1_capture_latch; /* Timer 1 capture latch */
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INT8 t1_prescaler; /* Timer 1 prescaler (5 bits) */
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INT16 t1_decrementer; /* Timer 1 decrementer (8 bits) */
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UINT8 idle_state; /* Set after the execution of an idle instruction */
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} tms7000_Regs;
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};
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static tms7000_Regs tms7000;
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#define pPC tms7000.pc.w.l
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#define PC tms7000.pc
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#define pSP tms7000.sp
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#define pSR tms7000.sr
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#define pPC cpustate->pc.w.l
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#define PC cpustate->pc
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#define pSP cpustate->sp
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#define pSR cpustate->sr
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#define RDA RM(0x0000)
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#define RDB RM(0x0001)
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@ -133,21 +130,13 @@ static ADDRESS_MAP_START(tms7000_mem, ADDRESS_SPACE_PROGRAM, 8)
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ADDRESS_MAP_END
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INLINE UINT16 RM16( UINT32 mAddr ) /* Read memory (16-bit) */
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INLINE UINT16 RM16( tms7000_state *cpustate, UINT32 mAddr ) /* Read memory (16-bit) */
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{
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UINT32 result = RM(mAddr) << 8;
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return result | RM((mAddr+1)&0xffff);
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}
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#ifdef UNUSED_FUNCTION
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INLINE void WM16( UINT32 mAddr, PAIR p ) /*Write memory file (16 bit) */
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{
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WM( mAddr, p.b.h );
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WM( (mAddr+1)&0xffff, p.b.l );
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}
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#endif
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INLINE UINT16 RRF16( UINT32 mAddr ) /*Read register file (16 bit) */
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INLINE UINT16 RRF16( tms7000_state *cpustate, UINT32 mAddr ) /*Read register file (16 bit) */
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{
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PAIR result;
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result.b.h = RM((mAddr-1)&0xffff);
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@ -155,43 +144,24 @@ INLINE UINT16 RRF16( UINT32 mAddr ) /*Read register file (16 bit) */
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return result.w.l;
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}
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INLINE void WRF16( UINT32 mAddr, PAIR p ) /*Write register file (16 bit) */
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INLINE void WRF16( tms7000_state *cpustate, UINT32 mAddr, PAIR p ) /*Write register file (16 bit) */
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{
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WM( (mAddr-1)&0xffff, p.b.h );
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WM( mAddr, p.b.l );
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}
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/****************************************************************************
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* Get all registers in given buffer
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****************************************************************************/
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static CPU_GET_CONTEXT( tms7000 )
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{
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if( dst )
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*(tms7000_Regs*)dst = tms7000;
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}
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/****************************************************************************
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* Set all registers to given values
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****************************************************************************/
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static CPU_SET_CONTEXT( tms7000 )
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{
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if( src )
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tms7000 = *(tms7000_Regs*)src;
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tms7000_check_IRQ_lines();
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}
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static CPU_INIT( tms7000 )
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{
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tms7000.irq_callback = irqcallback;
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tms7000.device = device;
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tms7000.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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tms7000.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
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tms7000_state *cpustate = device->token;
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cpustate->irq_callback = irqcallback;
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cpustate->device = device;
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cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
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memset(tms7000.pf, 0, 0x100);
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memset(tms7000.rf, 0, 0x80);
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memset(cpustate->pf, 0, 0x100);
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memset(cpustate->rf, 0, 0x80);
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/* Save register state */
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state_save_register_device_item(device, 0, pPC);
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@ -199,33 +169,35 @@ static CPU_INIT( tms7000 )
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state_save_register_device_item(device, 0, pSR);
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/* Save Interrupt state */
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state_save_register_device_item_array(device, 0, tms7000.irq_state);
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state_save_register_device_item_array(device, 0, cpustate->irq_state);
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/* Save register and perpherial file state */
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state_save_register_device_item_array(device, 0, tms7000.rf);
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state_save_register_device_item_array(device, 0, tms7000.pf);
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state_save_register_device_item_array(device, 0, cpustate->rf);
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state_save_register_device_item_array(device, 0, cpustate->pf);
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/* Save timer state */
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state_save_register_device_item(device, 0, tms7000.t1_prescaler);
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state_save_register_device_item(device, 0, tms7000.t1_capture_latch);
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state_save_register_device_item(device, 0, tms7000.t1_decrementer);
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state_save_register_device_item(device, 0, cpustate->t1_prescaler);
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state_save_register_device_item(device, 0, cpustate->t1_capture_latch);
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state_save_register_device_item(device, 0, cpustate->t1_decrementer);
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state_save_register_device_item(device, 0, tms7000.idle_state);
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state_save_register_device_item(device, 0, cpustate->idle_state);
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}
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static CPU_RESET( tms7000 )
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{
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// tms7000.architecture = (int)param;
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tms7000_state *cpustate = device->token;
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tms7000.idle_state = 0;
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tms7000.irq_state[ TMS7000_IRQ1_LINE ] = CLEAR_LINE;
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tms7000.irq_state[ TMS7000_IRQ2_LINE ] = CLEAR_LINE;
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tms7000.irq_state[ TMS7000_IRQ3_LINE ] = CLEAR_LINE;
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// cpustate->architecture = (int)param;
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cpustate->idle_state = 0;
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cpustate->irq_state[ TMS7000_IRQ1_LINE ] = CLEAR_LINE;
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cpustate->irq_state[ TMS7000_IRQ2_LINE ] = CLEAR_LINE;
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cpustate->irq_state[ TMS7000_IRQ3_LINE ] = CLEAR_LINE;
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WM( 0x100 + 9, 0 ); /* Data direction regs are cleared */
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WM( 0x100 + 11, 0 );
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// if( tms7000.architecture == TMS7000_NMOS )
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// if( cpustate->architecture == TMS7000_NMOS )
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// {
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WM( 0x100 + 4, 0xff ); /* Output 0xff on port A */
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WM( 0x100 + 8, 0xff ); /* Output 0xff on port C */
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@ -242,11 +214,11 @@ static CPU_RESET( tms7000 )
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/* On TMS70x2 and TMS70Cx2 IOCNT1 is zero */
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WRA( tms7000.pc.b.h ); /* Write previous PC to A:B */
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WRB( tms7000.pc.b.l );
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pPC = RM16(0xfffe); /* Load reset vector */
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WRA( cpustate->pc.b.h ); /* Write previous PC to A:B */
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WRB( cpustate->pc.b.l );
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pPC = RM16(cpustate, 0xfffe); /* Load reset vector */
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tms7000_div_by_16_trigger = -16;
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cpustate->div_by_16_trigger = -16;
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}
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@ -257,22 +229,24 @@ static CPU_RESET( tms7000 )
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static CPU_SET_INFO( tms7000 )
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{
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tms7000_state *cpustate = device->token;
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switch (state)
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{
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/* --- the following bits of info are set as 64-bit signed integers --- */
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ1_LINE: tms7000_set_irq_line(TMS7000_IRQ1_LINE, info->i); break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ2_LINE: tms7000_set_irq_line(TMS7000_IRQ2_LINE, info->i); break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE: tms7000_set_irq_line(TMS7000_IRQ3_LINE, info->i); break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ1_LINE: tms7000_set_irq_line(cpustate, TMS7000_IRQ1_LINE, info->i); break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ2_LINE: tms7000_set_irq_line(cpustate, TMS7000_IRQ2_LINE, info->i); break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE: tms7000_set_irq_line(cpustate, TMS7000_IRQ3_LINE, info->i); break;
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case CPUINFO_INT_PC:
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case CPUINFO_INT_REGISTER + TMS7000_PC: pPC = info->i; break;
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case CPUINFO_INT_SP:
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case CPUINFO_INT_REGISTER + TMS7000_SP: pSP = info->i; break;
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case CPUINFO_INT_REGISTER + TMS7000_ST: pSR = info->i; tms7000_check_IRQ_lines(); break;
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case CPUINFO_INT_REGISTER + TMS7000_IDLE: tms7000.idle_state = info->i; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_CL: tms7000.t1_capture_latch = info->i; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_PS: tms7000.t1_prescaler = info->i; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_DEC: tms7000.t1_decrementer = info->i; break;
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case CPUINFO_INT_REGISTER + TMS7000_ST: pSR = info->i; tms7000_check_IRQ_lines(cpustate); break;
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case CPUINFO_INT_REGISTER + TMS7000_IDLE: cpustate->idle_state = info->i; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_CL: cpustate->t1_capture_latch = info->i; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_PS: cpustate->t1_prescaler = info->i; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_DEC: cpustate->t1_decrementer = info->i; break;
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}
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}
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@ -282,11 +256,12 @@ static CPU_SET_INFO( tms7000 )
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CPU_GET_INFO( tms7000 )
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{
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tms7000_state *cpustate = (device != NULL) ? device->token : NULL;
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switch( state )
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{
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/* --- the following bits of info are returned as 64-bit signed integers --- */
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case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms7000); break;
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case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms7000_state); break;
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case CPUINFO_INT_INPUT_LINES: info->i = 3; break;
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case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
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case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
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@ -307,9 +282,9 @@ CPU_GET_INFO( tms7000 )
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case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break;
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case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ1_LINE: info->i = tms7000.irq_state[TMS7000_IRQ1_LINE]; break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ2_LINE: info->i = tms7000.irq_state[TMS7000_IRQ2_LINE]; break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE: info->i = tms7000.irq_state[TMS7000_IRQ3_LINE]; break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ1_LINE: info->i = cpustate->irq_state[TMS7000_IRQ1_LINE]; break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ2_LINE: info->i = cpustate->irq_state[TMS7000_IRQ2_LINE]; break;
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case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE: info->i = cpustate->irq_state[TMS7000_IRQ3_LINE]; break;
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case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* Not supported */ break;
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@ -318,21 +293,21 @@ CPU_GET_INFO( tms7000 )
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case CPUINFO_INT_SP:
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case CPUINFO_INT_REGISTER + TMS7000_SP: info->i = pSP; break;
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case CPUINFO_INT_REGISTER + TMS7000_ST: info->i = pSR; break;
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case CPUINFO_INT_REGISTER + TMS7000_IDLE: info->i = tms7000.idle_state; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_CL: info->i = tms7000.t1_capture_latch; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_PS: info->i = tms7000.t1_prescaler; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_DEC: info->i = tms7000.t1_decrementer; break;
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case CPUINFO_INT_REGISTER + TMS7000_IDLE: info->i = cpustate->idle_state; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_CL: info->i = cpustate->t1_capture_latch; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_PS: info->i = cpustate->t1_prescaler; break;
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case CPUINFO_INT_REGISTER + TMS7000_T1_DEC: info->i = cpustate->t1_decrementer; break;
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/* --- the following bits of info are returned as pointers to data or functions --- */
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case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms7000); break;
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case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(tms7000); break;
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case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(tms7000); break;
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case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break;
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case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break;
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case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(tms7000); break;
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case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(tms7000); break;
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case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms7000); break;
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case CPUINFO_PTR_BURN: info->burn = NULL; /* Not supported */break;
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case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms7000); break;
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case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &tms7000_icount; break;
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case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
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case CPUINFO_PTR_INTERNAL_MEMORY_MAP: info->internal_map8 = ADDRESS_MAP_NAME(tms7000_mem); break;
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/* --- the following bits of info are returned as NULL-terminated strings --- */
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@ -344,23 +319,23 @@ CPU_GET_INFO( tms7000 )
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case CPUINFO_STR_FLAGS:
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sprintf(info->s, "%c%c%c%c%c%c%c%c",
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tms7000.sr & 0x80 ? 'C':'c',
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tms7000.sr & 0x40 ? 'N':'n',
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tms7000.sr & 0x20 ? 'Z':'z',
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tms7000.sr & 0x10 ? 'I':'i',
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tms7000.sr & 0x08 ? '?':'.',
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tms7000.sr & 0x04 ? '?':'.',
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tms7000.sr & 0x02 ? '?':'.',
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tms7000.sr & 0x01 ? '?':'.' );
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cpustate->sr & 0x80 ? 'C':'c',
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cpustate->sr & 0x40 ? 'N':'n',
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cpustate->sr & 0x20 ? 'Z':'z',
|
||||
cpustate->sr & 0x10 ? 'I':'i',
|
||||
cpustate->sr & 0x08 ? '?':'.',
|
||||
cpustate->sr & 0x04 ? '?':'.',
|
||||
cpustate->sr & 0x02 ? '?':'.',
|
||||
cpustate->sr & 0x01 ? '?':'.' );
|
||||
break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + TMS7000_PC: sprintf(info->s, "PC:%04X", tms7000.pc.w.l); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_SP: sprintf(info->s, "S:%02X", tms7000.sp); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_ST: sprintf(info->s, "ST:%02X", tms7000.sr); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_IDLE: sprintf(info->s, "Idle:%02X", tms7000.idle_state); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_T1_CL: sprintf(info->s, "T1CL:%02X", tms7000.t1_capture_latch); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_T1_PS: sprintf(info->s, "T1PS:%02X", tms7000.t1_prescaler & 0x1f); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_T1_DEC: sprintf(info->s, "T1DEC:%02X", tms7000.t1_decrementer & 0xff); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_PC: sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_SP: sprintf(info->s, "S:%02X", cpustate->sp); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_ST: sprintf(info->s, "ST:%02X", cpustate->sr); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_IDLE: sprintf(info->s, "Idle:%02X", cpustate->idle_state); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_T1_CL: sprintf(info->s, "T1CL:%02X", cpustate->t1_capture_latch); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_T1_PS: sprintf(info->s, "T1PS:%02X", cpustate->t1_prescaler & 0x1f); break;
|
||||
case CPUINFO_STR_REGISTER + TMS7000_T1_DEC: sprintf(info->s, "T1DEC:%02X", cpustate->t1_decrementer & 0xff); break;
|
||||
|
||||
}
|
||||
}
|
||||
@ -378,82 +353,82 @@ CPU_GET_INFO( tms7000_exl )
|
||||
}
|
||||
}
|
||||
|
||||
void tms7000_set_irq_line(int irqline, int state)
|
||||
void tms7000_set_irq_line(tms7000_state *cpustate, int irqline, int state)
|
||||
{
|
||||
if (tms7000.irq_state[irqline] != state)
|
||||
if (cpustate->irq_state[irqline] != state)
|
||||
{ /* check for transition */
|
||||
tms7000.irq_state[irqline] = state;
|
||||
cpustate->irq_state[irqline] = state;
|
||||
|
||||
LOG(("tms7000: (cpu '%s') set_irq_line (INT%d, state %d)\n", tms7000.device->tag, irqline+1, state));
|
||||
LOG(("tms7000: (cpu '%s') set_irq_line (INT%d, state %d)\n", cpustate->device->tag, irqline+1, state));
|
||||
|
||||
if (state == CLEAR_LINE)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
tms7000.pf[0] |= (0x02 << (irqline * 2)); /* Set INTx iocntl0 flag */
|
||||
cpustate->pf[0] |= (0x02 << (irqline * 2)); /* Set INTx iocntl0 flag */
|
||||
|
||||
if( irqline == TMS7000_IRQ3_LINE )
|
||||
{
|
||||
/* Latch the value in perpherial file register 3 */
|
||||
tms7000.t1_capture_latch = tms7000.t1_decrementer & 0x00ff;
|
||||
cpustate->t1_capture_latch = cpustate->t1_decrementer & 0x00ff;
|
||||
}
|
||||
|
||||
tms7000_check_IRQ_lines();
|
||||
tms7000_check_IRQ_lines(cpustate);
|
||||
}
|
||||
}
|
||||
|
||||
static void tms7000_check_IRQ_lines( void )
|
||||
static void tms7000_check_IRQ_lines(tms7000_state *cpustate)
|
||||
{
|
||||
if( pSR & SR_I ) /* Check Global Interrupt bit: Status register, bit 4 */
|
||||
{
|
||||
if ((tms7000.irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE) || (tms7000.pf[0] & 0x02))
|
||||
if ((cpustate->irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE) || (cpustate->pf[0] & 0x02))
|
||||
{
|
||||
if( tms7000.pf[0] & 0x01 ) /* INT1 Enable bit */
|
||||
if( cpustate->pf[0] & 0x01 ) /* INT1 Enable bit */
|
||||
{
|
||||
tms7000_do_interrupt( 0xfffc, TMS7000_IRQ1_LINE );
|
||||
tms7000.pf[0] &= ~0x02; /* Data Manual, page: 9-41 */
|
||||
tms7000_do_interrupt( cpustate, 0xfffc, TMS7000_IRQ1_LINE );
|
||||
cpustate->pf[0] &= ~0x02; /* Data Manual, page: 9-41 */
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if( tms7000.irq_state[ TMS7000_IRQ2_LINE ] == ASSERT_LINE )
|
||||
if( cpustate->irq_state[ TMS7000_IRQ2_LINE ] == ASSERT_LINE )
|
||||
{
|
||||
if( tms7000.pf[0] & 0x04 ) /* INT2 Enable bit */
|
||||
if( cpustate->pf[0] & 0x04 ) /* INT2 Enable bit */
|
||||
{
|
||||
tms7000_do_interrupt( 0xfffa, TMS7000_IRQ2_LINE );
|
||||
tms7000_do_interrupt( cpustate, 0xfffa, TMS7000_IRQ2_LINE );
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if ((tms7000.irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE) || (tms7000.pf[0] & 0x20))
|
||||
if ((cpustate->irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE) || (cpustate->pf[0] & 0x20))
|
||||
{
|
||||
if( tms7000.pf[0] & 0x10 ) /* INT3 Enable bit */
|
||||
if( cpustate->pf[0] & 0x10 ) /* INT3 Enable bit */
|
||||
{
|
||||
tms7000_do_interrupt( 0xfff8, TMS7000_IRQ3_LINE );
|
||||
tms7000.pf[0] &= ~0x20; /* Data Manual, page: 9-41 */
|
||||
tms7000_do_interrupt( cpustate, 0xfff8, TMS7000_IRQ3_LINE );
|
||||
cpustate->pf[0] &= ~0x20; /* Data Manual, page: 9-41 */
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void tms7000_do_interrupt( UINT16 address, UINT8 line )
|
||||
static void tms7000_do_interrupt( tms7000_state *cpustate, UINT16 address, UINT8 line )
|
||||
{
|
||||
PUSHBYTE( pSR ); /* Push Status register */
|
||||
PUSHWORD( PC ); /* Push Program Counter */
|
||||
pSR = 0; /* Clear Status register */
|
||||
pPC = RM16(address); /* Load PC with interrupt vector */
|
||||
pPC = RM16(cpustate, address); /* Load PC with interrupt vector */
|
||||
|
||||
if( tms7000.idle_state == 0 )
|
||||
tms7000_icount -= 19; /* 19 cycles used */
|
||||
if( cpustate->idle_state == 0 )
|
||||
cpustate->icount -= 19; /* 19 cycles used */
|
||||
else
|
||||
{
|
||||
tms7000_icount -= 17; /* 17 if idled */
|
||||
tms7000.idle_state = 0;
|
||||
cpustate->icount -= 17; /* 17 if idled */
|
||||
cpustate->idle_state = 0;
|
||||
}
|
||||
|
||||
(void)(*tms7000.irq_callback)(tms7000.device, line);
|
||||
(void)(*cpustate->irq_callback)(cpustate->device, line);
|
||||
}
|
||||
|
||||
#include "tms70op.c"
|
||||
@ -461,81 +436,87 @@ static void tms7000_do_interrupt( UINT16 address, UINT8 line )
|
||||
|
||||
static CPU_EXECUTE( tms7000 )
|
||||
{
|
||||
tms7000_state *cpustate = device->token;
|
||||
int op;
|
||||
|
||||
tms7000_icount = cycles;
|
||||
tms7000_div_by_16_trigger += cycles;
|
||||
cpustate->icount = cycles;
|
||||
cpustate->div_by_16_trigger += cycles;
|
||||
|
||||
tms7000_check_IRQ_lines(cpustate);
|
||||
|
||||
do
|
||||
{
|
||||
debugger_instruction_hook(device, pPC);
|
||||
|
||||
if( tms7000.idle_state == 0 )
|
||||
if( cpustate->idle_state == 0 )
|
||||
{
|
||||
op = memory_decrypted_read_byte(tms7000.program, pPC++);
|
||||
op = memory_decrypted_read_byte(cpustate->program, pPC++);
|
||||
|
||||
opfn[op]();
|
||||
opfn[op](cpustate);
|
||||
}
|
||||
else
|
||||
tms7000_icount -= 16;
|
||||
cpustate->icount -= 16;
|
||||
|
||||
/* Internal timer system */
|
||||
|
||||
while( tms7000_icount < tms7000_div_by_16_trigger )
|
||||
while( cpustate->icount < cpustate->div_by_16_trigger )
|
||||
{
|
||||
tms7000_div_by_16_trigger -= 16;
|
||||
cpustate->div_by_16_trigger -= 16;
|
||||
|
||||
if( (tms7000.pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
|
||||
if( (cpustate->pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
|
||||
{
|
||||
if( (tms7000.pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */
|
||||
if( (cpustate->pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */
|
||||
tms7000_service_timer1(device);
|
||||
}
|
||||
}
|
||||
|
||||
} while( tms7000_icount > 0 );
|
||||
} while( cpustate->icount > 0 );
|
||||
|
||||
tms7000_div_by_16_trigger -= tms7000_icount;
|
||||
return cycles - tms7000_icount;
|
||||
cpustate->div_by_16_trigger -= cpustate->icount;
|
||||
return cycles - cpustate->icount;
|
||||
}
|
||||
|
||||
static CPU_EXECUTE( tms7000_exl )
|
||||
{
|
||||
tms7000_state *cpustate = device->token;
|
||||
int op;
|
||||
|
||||
tms7000_icount = cycles;
|
||||
tms7000_div_by_16_trigger += cycles;
|
||||
cpustate->icount = cycles;
|
||||
cpustate->div_by_16_trigger += cycles;
|
||||
|
||||
tms7000_check_IRQ_lines(cpustate);
|
||||
|
||||
do
|
||||
{
|
||||
debugger_instruction_hook(device, pPC);
|
||||
|
||||
if( tms7000.idle_state == 0 )
|
||||
if( cpustate->idle_state == 0 )
|
||||
{
|
||||
|
||||
op = memory_decrypted_read_byte(tms7000.program, pPC++);
|
||||
op = memory_decrypted_read_byte(cpustate->program, pPC++);
|
||||
|
||||
opfn_exl[op]();
|
||||
opfn_exl[op](cpustate);
|
||||
}
|
||||
else
|
||||
tms7000_icount -= 16;
|
||||
cpustate->icount -= 16;
|
||||
|
||||
/* Internal timer system */
|
||||
|
||||
while( tms7000_icount < tms7000_div_by_16_trigger )
|
||||
while( cpustate->icount < cpustate->div_by_16_trigger )
|
||||
{
|
||||
tms7000_div_by_16_trigger -= 16;
|
||||
cpustate->div_by_16_trigger -= 16;
|
||||
|
||||
if( (tms7000.pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
|
||||
if( (cpustate->pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
|
||||
{
|
||||
if( (tms7000.pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */
|
||||
if( (cpustate->pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */
|
||||
tms7000_service_timer1(device);
|
||||
}
|
||||
}
|
||||
|
||||
} while( tms7000_icount > 0 );
|
||||
} while( cpustate->icount > 0 );
|
||||
|
||||
tms7000_div_by_16_trigger -= tms7000_icount;
|
||||
return cycles - tms7000_icount;
|
||||
cpustate->div_by_16_trigger -= cpustate->icount;
|
||||
return cycles - cpustate->icount;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -543,69 +524,72 @@ static CPU_EXECUTE( tms7000_exl )
|
||||
****************************************************************************/
|
||||
void tms7000_A6EC1( const device_config *device )
|
||||
{
|
||||
if( (tms7000.pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
|
||||
tms7000_state *cpustate = device->token;
|
||||
if( (cpustate->pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
|
||||
{
|
||||
if( (tms7000.pf[0x03] & 0x40) == 0x40) /* Is event counter the timer source? */
|
||||
if( (cpustate->pf[0x03] & 0x40) == 0x40) /* Is event counter the timer source? */
|
||||
tms7000_service_timer1(device);
|
||||
}
|
||||
}
|
||||
|
||||
static void tms7000_service_timer1( const device_config *device )
|
||||
{
|
||||
if( --tms7000.t1_prescaler < 0 ) /* Decrement prescaler and check for underflow */
|
||||
tms7000_state *cpustate = device->token;
|
||||
if( --cpustate->t1_prescaler < 0 ) /* Decrement prescaler and check for underflow */
|
||||
{
|
||||
tms7000.t1_prescaler = tms7000.pf[3] & 0x1f; /* Reload prescaler (5 bit) */
|
||||
cpustate->t1_prescaler = cpustate->pf[3] & 0x1f; /* Reload prescaler (5 bit) */
|
||||
|
||||
if( --tms7000.t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */
|
||||
if( --cpustate->t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */
|
||||
{
|
||||
tms7000.t1_decrementer = tms7000.pf[2]; /* Reload decrementer (8 bit) */
|
||||
cpustate->t1_decrementer = cpustate->pf[2]; /* Reload decrementer (8 bit) */
|
||||
cpu_set_input_line(device, TMS7000_IRQ2_LINE, HOLD_LINE);
|
||||
//LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", cpu_get_total_cycles(device), cpu_get_total_cycles(device) - tick, tms7000_cycles_per_INT2-(cpu_get_total_cycles(device) - tick) );
|
||||
//LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", cpu_get_total_cycles(device), cpu_get_total_cycles(device) - tick, cpustate->cycles_per_INT2-(cpu_get_total_cycles(device) - tick) );
|
||||
//tick = cpu_get_total_cycles(device) );
|
||||
/* Also, cascade out to timer 2 - timer 2 unimplemented */
|
||||
}
|
||||
}
|
||||
// LOG( ( "tms7000: service timer1. 0x%2.2x 0x%2.2x (cycles %d)\t%d\t\n", tms7000.t1_prescaler, tms7000.t1_decrementer, cpu_get_total_cycles(device), cpu_get_total_cycles(device) - tick2 ) );
|
||||
// LOG( ( "tms7000: service timer1. 0x%2.2x 0x%2.2x (cycles %d)\t%d\t\n", cpustate->t1_prescaler, cpustate->t1_decrementer, cpu_get_total_cycles(device), cpu_get_total_cycles(device) - tick2 ) );
|
||||
// tick2 = cpu_get_total_cycles(device);
|
||||
}
|
||||
|
||||
static WRITE8_HANDLER( tms70x0_pf_w ) /* Perpherial file write */
|
||||
{
|
||||
tms7000_state *cpustate = space->cpu->token;
|
||||
UINT8 temp1, temp2, temp3;
|
||||
|
||||
switch( offset )
|
||||
{
|
||||
case 0x00: /* IOCNT0, Input/Ouput control */
|
||||
temp1 = data & 0x2a; /* Record which bits to clear */
|
||||
temp2 = tms7000.pf[0x00] & 0x2a; /* Get copy of current bits */
|
||||
temp2 = cpustate->pf[0x00] & 0x2a; /* Get copy of current bits */
|
||||
temp3 = (~temp1) & temp2; /* Clear the requested bits */
|
||||
tms7000.pf[0x00] = temp3 | (data & (~0x2a) ); /* OR in the remaining data */
|
||||
cpustate->pf[0x00] = temp3 | (data & (~0x2a) ); /* OR in the remaining data */
|
||||
break;
|
||||
case 0x02:
|
||||
tms7000.t1_decrementer = tms7000.pf[0x02] = data;
|
||||
tms7000_cycles_per_INT2 = 0x10*((tms7000.pf[3] & 0x1f)+1)*(tms7000.pf[0x02]+1);
|
||||
LOG( ( "tms7000: Timer adjusted. Decrementer: 0x%2.2x (Cycles per interrupt: %d)\n", tms7000.t1_decrementer, tms7000_cycles_per_INT2 ) );
|
||||
cpustate->t1_decrementer = cpustate->pf[0x02] = data;
|
||||
cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
|
||||
LOG( ( "tms7000: Timer adjusted. Decrementer: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->t1_decrementer, cpustate->cycles_per_INT2 ) );
|
||||
break;
|
||||
case 0x03: /* T1CTL, timer 1 control */
|
||||
if( ((tms7000.pf[0x03] & 0x80) == 0) && ((data & 0x80) == 0x80 ) ) /* Start timer? */
|
||||
if( ((cpustate->pf[0x03] & 0x80) == 0) && ((data & 0x80) == 0x80 ) ) /* Start timer? */
|
||||
{
|
||||
tms7000.pf[0x03] = data;
|
||||
tms7000.t1_prescaler = tms7000.pf[3] & 0x1f; /* Reload prescaler (5 bit) */
|
||||
tms7000_cycles_per_INT2 = 0x10*((tms7000.pf[3] & 0x1f)+1)*(tms7000.pf[0x02]+1);
|
||||
LOG( ( "tms7000: Timer started. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", tms7000.pf[3] & 0x1f, tms7000_cycles_per_INT2 ) );
|
||||
cpustate->pf[0x03] = data;
|
||||
cpustate->t1_prescaler = cpustate->pf[3] & 0x1f; /* Reload prescaler (5 bit) */
|
||||
cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
|
||||
LOG( ( "tms7000: Timer started. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->pf[3] & 0x1f, cpustate->cycles_per_INT2 ) );
|
||||
}
|
||||
else if( ((data & 0x80) == 0x80 ) && ((tms7000.pf[0x03] & 0x80) == 0) ) /* Timer Stopped? */
|
||||
else if( ((data & 0x80) == 0x80 ) && ((cpustate->pf[0x03] & 0x80) == 0) ) /* Timer Stopped? */
|
||||
{
|
||||
tms7000.pf[0x03] = data;
|
||||
tms7000.t1_prescaler = tms7000.pf[3] & 0x1f; /* Reload prescaler (5 bit) */
|
||||
tms7000_cycles_per_INT2 = 0x10*((tms7000.pf[3] & 0x1f)+1)*(tms7000.pf[0x02]+1);
|
||||
LOG( ( "tms7000: Timer stopped. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", tms7000.pf[3] & 0x1f, tms7000_cycles_per_INT2 ) );
|
||||
cpustate->pf[0x03] = data;
|
||||
cpustate->t1_prescaler = cpustate->pf[3] & 0x1f; /* Reload prescaler (5 bit) */
|
||||
cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
|
||||
LOG( ( "tms7000: Timer stopped. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->pf[3] & 0x1f, cpustate->cycles_per_INT2 ) );
|
||||
}
|
||||
else /* Don't modify timer state, but still store data */
|
||||
{
|
||||
tms7000.pf[0x03] = data;
|
||||
tms7000_cycles_per_INT2 = 0x10*((tms7000.pf[3] & 0x1f)+1)*(tms7000.pf[0x02]+1);
|
||||
LOG( ( "tms7000: Timer adjusted. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", tms7000.pf[3] & 0x1f, tms7000_cycles_per_INT2 ) );
|
||||
cpustate->pf[0x03] = data;
|
||||
cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
|
||||
LOG( ( "tms7000: Timer adjusted. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->pf[3] & 0x1f, cpustate->cycles_per_INT2 ) );
|
||||
}
|
||||
break;
|
||||
|
||||
@ -614,79 +598,80 @@ static WRITE8_HANDLER( tms70x0_pf_w ) /* Perpherial file write */
|
||||
break;
|
||||
|
||||
case 0x06: /* Port B write */
|
||||
memory_write_byte_8be( tms7000.io, TMS7000_PORTB, data );
|
||||
tms7000.pf[ 0x06 ] = data;
|
||||
memory_write_byte_8be( cpustate->io, TMS7000_PORTB, data );
|
||||
cpustate->pf[ 0x06 ] = data;
|
||||
break;
|
||||
|
||||
case 0x08: /* Port C write */
|
||||
temp1 = data & tms7000.pf[ 0x09 ]; /* Mask off input bits */
|
||||
memory_write_byte_8be( tms7000.io, TMS7000_PORTC, temp1 );
|
||||
tms7000.pf[ 0x08 ] = temp1;
|
||||
temp1 = data & cpustate->pf[ 0x09 ]; /* Mask off input bits */
|
||||
memory_write_byte_8be( cpustate->io, TMS7000_PORTC, temp1 );
|
||||
cpustate->pf[ 0x08 ] = temp1;
|
||||
break;
|
||||
|
||||
case 0x0a: /* Port D write */
|
||||
temp1 = data & tms7000.pf[ 0x0b ]; /* Mask off input bits */
|
||||
memory_write_byte_8be( tms7000.io, TMS7000_PORTD, temp1 );
|
||||
tms7000.pf[ 0x0a ] = temp1;
|
||||
temp1 = data & cpustate->pf[ 0x0b ]; /* Mask off input bits */
|
||||
memory_write_byte_8be( cpustate->io, TMS7000_PORTD, temp1 );
|
||||
cpustate->pf[ 0x0a ] = temp1;
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Just stuff the other registers */
|
||||
tms7000.pf[ offset ] = data;
|
||||
cpustate->pf[ offset ] = data;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static READ8_HANDLER( tms70x0_pf_r ) /* Perpherial file read */
|
||||
{
|
||||
tms7000_state *cpustate = space->cpu->token;
|
||||
UINT8 result;
|
||||
UINT8 temp1, temp2, temp3;
|
||||
|
||||
switch( offset )
|
||||
{
|
||||
case 0x00: /* IOCNT0, Input/Ouput control */
|
||||
result = tms7000.pf[0x00];
|
||||
if (tms7000.irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE)
|
||||
result = cpustate->pf[0x00];
|
||||
if (cpustate->irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE)
|
||||
result |= 0x02;
|
||||
if (tms7000.irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE)
|
||||
if (cpustate->irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE)
|
||||
result |= 0x20;
|
||||
break;
|
||||
|
||||
case 0x02: /* T1DATA, timer 1 8-bit decrementer */
|
||||
result = (tms7000.t1_decrementer & 0x00ff);
|
||||
result = (cpustate->t1_decrementer & 0x00ff);
|
||||
break;
|
||||
|
||||
case 0x03: /* T1CTL, timer 1 capture (latched by INT3) */
|
||||
result = tms7000.t1_capture_latch;
|
||||
result = cpustate->t1_capture_latch;
|
||||
break;
|
||||
|
||||
case 0x04: /* Port A read */
|
||||
result = memory_read_byte_8be( tms7000.io, TMS7000_PORTA );
|
||||
result = memory_read_byte_8be( cpustate->io, TMS7000_PORTA );
|
||||
break;
|
||||
|
||||
|
||||
case 0x06: /* Port B read */
|
||||
/* Port B is write only, return a previous written value */
|
||||
result = tms7000.pf[ 0x06 ];
|
||||
result = cpustate->pf[ 0x06 ];
|
||||
break;
|
||||
|
||||
case 0x08: /* Port C read */
|
||||
temp1 = tms7000.pf[ 0x08 ] & tms7000.pf[ 0x09 ]; /* Get previous output bits */
|
||||
temp2 = memory_read_byte_8be( tms7000.io, TMS7000_PORTC ); /* Read port */
|
||||
temp3 = temp2 & (~tms7000.pf[ 0x09 ]); /* Mask off output bits */
|
||||
temp1 = cpustate->pf[ 0x08 ] & cpustate->pf[ 0x09 ]; /* Get previous output bits */
|
||||
temp2 = memory_read_byte_8be( cpustate->io, TMS7000_PORTC ); /* Read port */
|
||||
temp3 = temp2 & (~cpustate->pf[ 0x09 ]); /* Mask off output bits */
|
||||
result = temp1 | temp3; /* OR together */
|
||||
break;
|
||||
|
||||
case 0x0a: /* Port D read */
|
||||
temp1 = tms7000.pf[ 0x0a ] & tms7000.pf[ 0x0b ]; /* Get previous output bits */
|
||||
temp2 = memory_read_byte_8be( tms7000.io, TMS7000_PORTD ); /* Read port */
|
||||
temp3 = temp2 & (~tms7000.pf[ 0x0b ]); /* Mask off output bits */
|
||||
temp1 = cpustate->pf[ 0x0a ] & cpustate->pf[ 0x0b ]; /* Get previous output bits */
|
||||
temp2 = memory_read_byte_8be( cpustate->io, TMS7000_PORTD ); /* Read port */
|
||||
temp3 = temp2 & (~cpustate->pf[ 0x0b ]); /* Mask off output bits */
|
||||
result = temp1 | temp3; /* OR together */
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Just unstuff the other registers */
|
||||
result = tms7000.pf[ offset ];
|
||||
result = cpustate->pf[ offset ];
|
||||
break;
|
||||
}
|
||||
|
||||
@ -731,9 +716,11 @@ static UINT16 bcd_sub( UINT16 a, UINT16 b)
|
||||
}
|
||||
|
||||
static WRITE8_HANDLER( tms7000_internal_w ) {
|
||||
tms7000.rf[ offset ] = data;
|
||||
tms7000_state *cpustate = space->cpu->token;
|
||||
cpustate->rf[ offset ] = data;
|
||||
}
|
||||
|
||||
static READ8_HANDLER( tms7000_internal_r ) {
|
||||
return tms7000.rf[ offset ];
|
||||
tms7000_state *cpustate = space->cpu->token;
|
||||
return cpustate->rf[ offset ];
|
||||
}
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* tms7000.h (c header file)
|
||||
* cpustate->h (c header file)
|
||||
* Portable TMS7000 emulator (Texas Instruments 7000)
|
||||
*
|
||||
* Copyright tim lindner, all rights reserved.
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -17,7 +17,7 @@
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
static void (*const opfn[0x100])(void) = {
|
||||
static void (*const opfn[0x100])(tms7000_state *cpustate) = {
|
||||
/* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7,
|
||||
0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */
|
||||
|
||||
@ -70,7 +70,7 @@ static void (*const opfn[0x100])(void) = {
|
||||
trap_7, trap_6, trap_5, trap_4, trap_3, trap_2, trap_1, trap_0
|
||||
};
|
||||
|
||||
static void (*const opfn_exl[0x100])(void) = {
|
||||
static void (*const opfn_exl[0x100])(tms7000_state *cpustate) = {
|
||||
/* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7,
|
||||
0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user