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Pointer-ified the tms7000 core.

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This commit is contained in:
Aaron Giles 2008-12-10 14:55:39 +00:00
parent 8aea6e2b4f
commit 8b670ddddd
4 changed files with 743 additions and 756 deletions
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417
src/emu/cpu/tms7000/tms7000.c
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@ -24,7 +24,7 @@
*****************************************************************************/ *****************************************************************************/
// SJE: Changed all references to ICount to icount (to match MAME requirements) // SJE: Changed all references to ICount to icount (to match MAME requirements)
// SJE: Changed RM/WM macros to reference newly created tms7000 read/write handlers & removed unused SRM() macro // SJE: Changed RM/WM macros to reference newly created tms7000 read/write handlers & removed unused SRM(cpustate) macro
// SJE: Fixed a mistake in tms70x0_pf_w where the wrong register was referenced // SJE: Fixed a mistake in tms70x0_pf_w where the wrong register was referenced
// SJE: Implemented internal register file // SJE: Implemented internal register file
@ -37,13 +37,13 @@
#define LOG(x) do { if (VERBOSE) logerror x; } while (0) #define LOG(x) do { if (VERBOSE) logerror x; } while (0)
typedef struct _tms7000_state tms7000_state;
/* Private prototypes */ /* Private prototypes */
static void tms7000_set_irq_line(int irqline, int state); static void tms7000_set_irq_line(tms7000_state *cpustate, int irqline, int state);
static CPU_GET_CONTEXT( tms7000 ); static void tms7000_check_IRQ_lines(tms7000_state *cpustate);
static CPU_SET_CONTEXT( tms7000 ); static void tms7000_do_interrupt( tms7000_state *cpustate, UINT16 address, UINT8 line );
static void tms7000_check_IRQ_lines( void );
static void tms7000_do_interrupt( UINT16 address, UINT8 line );
static CPU_EXECUTE( tms7000 ); static CPU_EXECUTE( tms7000 );
static CPU_EXECUTE( tms7000_exl ); static CPU_EXECUTE( tms7000_exl );
static void tms7000_service_timer1( const device_config *device ); static void tms7000_service_timer1( const device_config *device );
@ -53,23 +53,19 @@ static UINT16 bcd_sub( UINT16 a, UINT16 b);
/* Static variables */ /* Static variables */
static int tms7000_icount; #define RM(Addr) ((unsigned)memory_read_byte_8be(cpustate->program, Addr))
static int tms7000_div_by_16_trigger; #define WM(Addr,Value) (memory_write_byte_8be(cpustate->program, Addr, Value))
static int tms7000_cycles_per_INT2;
#define RM(Addr) ((unsigned)memory_read_byte_8be(tms7000.program, Addr)) #define IMMBYTE(b) b = ((unsigned)memory_raw_read_byte(cpustate->program, pPC)); pPC++
#define WM(Addr,Value) (memory_write_byte_8be(tms7000.program, Addr, Value)) #define SIMMBYTE(b) b = ((signed)memory_raw_read_byte(cpustate->program, pPC)); pPC++
#define IMMWORD(w) w.b.h = (unsigned)memory_raw_read_byte(cpustate->program, pPC++); w.b.l = (unsigned)memory_raw_read_byte(cpustate->program, pPC++)
#define IMMBYTE(b) b = ((unsigned)memory_raw_read_byte(tms7000.program, pPC)); pPC++
#define SIMMBYTE(b) b = ((signed)memory_raw_read_byte(tms7000.program, pPC)); pPC++
#define IMMWORD(w) w.b.h = (unsigned)memory_raw_read_byte(tms7000.program, pPC++); w.b.l = (unsigned)memory_raw_read_byte(tms7000.program, pPC++)
#define PUSHBYTE(b) pSP++; WM(pSP,b) #define PUSHBYTE(b) pSP++; WM(pSP,b)
#define PUSHWORD(w) pSP++; WM(pSP,w.b.h); pSP++; WM(pSP,w.b.l) #define PUSHWORD(w) pSP++; WM(pSP,w.b.h); pSP++; WM(pSP,w.b.l)
#define PULLBYTE(b) b = RM(pSP); pSP-- #define PULLBYTE(b) b = RM(pSP); pSP--
#define PULLWORD(w) w.b.l = RM(pSP); pSP--; w.b.h = RM(pSP); pSP-- #define PULLWORD(w) w.b.l = RM(pSP); pSP--; w.b.h = RM(pSP); pSP--
typedef struct struct _tms7000_state
{ {
PAIR pc; /* Program counter */ PAIR pc; /* Program counter */
UINT8 sp; /* Stack Pointer */ UINT8 sp; /* Stack Pointer */
@ -81,18 +77,19 @@ typedef struct
const device_config *device; const device_config *device;
const address_space *program; const address_space *program;
const address_space *io; const address_space *io;
int icount;
int div_by_16_trigger;
int cycles_per_INT2;
UINT8 t1_capture_latch; /* Timer 1 capture latch */ UINT8 t1_capture_latch; /* Timer 1 capture latch */
INT8 t1_prescaler; /* Timer 1 prescaler (5 bits) */ INT8 t1_prescaler; /* Timer 1 prescaler (5 bits) */
INT16 t1_decrementer; /* Timer 1 decrementer (8 bits) */ INT16 t1_decrementer; /* Timer 1 decrementer (8 bits) */
UINT8 idle_state; /* Set after the execution of an idle instruction */ UINT8 idle_state; /* Set after the execution of an idle instruction */
} tms7000_Regs; };
static tms7000_Regs tms7000; #define pPC cpustate->pc.w.l
#define PC cpustate->pc
#define pPC tms7000.pc.w.l #define pSP cpustate->sp
#define PC tms7000.pc #define pSR cpustate->sr
#define pSP tms7000.sp
#define pSR tms7000.sr
#define RDA RM(0x0000) #define RDA RM(0x0000)
#define RDB RM(0x0001) #define RDB RM(0x0001)
@ -133,21 +130,13 @@ static ADDRESS_MAP_START(tms7000_mem, ADDRESS_SPACE_PROGRAM, 8)
ADDRESS_MAP_END ADDRESS_MAP_END
INLINE UINT16 RM16( UINT32 mAddr ) /* Read memory (16-bit) */ INLINE UINT16 RM16( tms7000_state *cpustate, UINT32 mAddr ) /* Read memory (16-bit) */
{ {
UINT32 result = RM(mAddr) << 8; UINT32 result = RM(mAddr) << 8;
return result | RM((mAddr+1)&0xffff); return result | RM((mAddr+1)&0xffff);
} }
#ifdef UNUSED_FUNCTION INLINE UINT16 RRF16( tms7000_state *cpustate, UINT32 mAddr ) /*Read register file (16 bit) */
INLINE void WM16( UINT32 mAddr, PAIR p ) /*Write memory file (16 bit) */
{
WM( mAddr, p.b.h );
WM( (mAddr+1)&0xffff, p.b.l );
}
#endif
INLINE UINT16 RRF16( UINT32 mAddr ) /*Read register file (16 bit) */
{ {
PAIR result; PAIR result;
result.b.h = RM((mAddr-1)&0xffff); result.b.h = RM((mAddr-1)&0xffff);
@ -155,43 +144,24 @@ INLINE UINT16 RRF16( UINT32 mAddr ) /*Read register file (16 bit) */
return result.w.l; return result.w.l;
} }
INLINE void WRF16( UINT32 mAddr, PAIR p ) /*Write register file (16 bit) */ INLINE void WRF16( tms7000_state *cpustate, UINT32 mAddr, PAIR p ) /*Write register file (16 bit) */
{ {
WM( (mAddr-1)&0xffff, p.b.h ); WM( (mAddr-1)&0xffff, p.b.h );
WM( mAddr, p.b.l ); WM( mAddr, p.b.l );
} }
/****************************************************************************
* Get all registers in given buffer
****************************************************************************/
static CPU_GET_CONTEXT( tms7000 )
{
if( dst )
*(tms7000_Regs*)dst = tms7000;
}
/****************************************************************************
* Set all registers to given values
****************************************************************************/
static CPU_SET_CONTEXT( tms7000 )
{
if( src )
tms7000 = *(tms7000_Regs*)src;
tms7000_check_IRQ_lines();
}
static CPU_INIT( tms7000 ) static CPU_INIT( tms7000 )
{ {
tms7000.irq_callback = irqcallback; tms7000_state *cpustate = device->token;
tms7000.device = device;
tms7000.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); cpustate->irq_callback = irqcallback;
tms7000.io = memory_find_address_space(device, ADDRESS_SPACE_IO); cpustate->device = device;
cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
memset(tms7000.pf, 0, 0x100); memset(cpustate->pf, 0, 0x100);
memset(tms7000.rf, 0, 0x80); memset(cpustate->rf, 0, 0x80);
/* Save register state */ /* Save register state */
state_save_register_device_item(device, 0, pPC); state_save_register_device_item(device, 0, pPC);
@ -199,33 +169,35 @@ static CPU_INIT( tms7000 )
state_save_register_device_item(device, 0, pSR); state_save_register_device_item(device, 0, pSR);
/* Save Interrupt state */ /* Save Interrupt state */
state_save_register_device_item_array(device, 0, tms7000.irq_state); state_save_register_device_item_array(device, 0, cpustate->irq_state);
/* Save register and perpherial file state */ /* Save register and perpherial file state */
state_save_register_device_item_array(device, 0, tms7000.rf); state_save_register_device_item_array(device, 0, cpustate->rf);
state_save_register_device_item_array(device, 0, tms7000.pf); state_save_register_device_item_array(device, 0, cpustate->pf);
/* Save timer state */ /* Save timer state */
state_save_register_device_item(device, 0, tms7000.t1_prescaler); state_save_register_device_item(device, 0, cpustate->t1_prescaler);
state_save_register_device_item(device, 0, tms7000.t1_capture_latch); state_save_register_device_item(device, 0, cpustate->t1_capture_latch);
state_save_register_device_item(device, 0, tms7000.t1_decrementer); state_save_register_device_item(device, 0, cpustate->t1_decrementer);
state_save_register_device_item(device, 0, tms7000.idle_state); state_save_register_device_item(device, 0, cpustate->idle_state);
} }
static CPU_RESET( tms7000 ) static CPU_RESET( tms7000 )
{ {
// tms7000.architecture = (int)param; tms7000_state *cpustate = device->token;
tms7000.idle_state = 0; // cpustate->architecture = (int)param;
tms7000.irq_state[ TMS7000_IRQ1_LINE ] = CLEAR_LINE;
tms7000.irq_state[ TMS7000_IRQ2_LINE ] = CLEAR_LINE; cpustate->idle_state = 0;
tms7000.irq_state[ TMS7000_IRQ3_LINE ] = CLEAR_LINE; cpustate->irq_state[ TMS7000_IRQ1_LINE ] = CLEAR_LINE;
cpustate->irq_state[ TMS7000_IRQ2_LINE ] = CLEAR_LINE;
cpustate->irq_state[ TMS7000_IRQ3_LINE ] = CLEAR_LINE;
WM( 0x100 + 9, 0 ); /* Data direction regs are cleared */ WM( 0x100 + 9, 0 ); /* Data direction regs are cleared */
WM( 0x100 + 11, 0 ); WM( 0x100 + 11, 0 );
// if( tms7000.architecture == TMS7000_NMOS ) // if( cpustate->architecture == TMS7000_NMOS )
// { // {
WM( 0x100 + 4, 0xff ); /* Output 0xff on port A */ WM( 0x100 + 4, 0xff ); /* Output 0xff on port A */
WM( 0x100 + 8, 0xff ); /* Output 0xff on port C */ WM( 0x100 + 8, 0xff ); /* Output 0xff on port C */
@ -242,11 +214,11 @@ static CPU_RESET( tms7000 )
/* On TMS70x2 and TMS70Cx2 IOCNT1 is zero */ /* On TMS70x2 and TMS70Cx2 IOCNT1 is zero */
WRA( tms7000.pc.b.h ); /* Write previous PC to A:B */ WRA( cpustate->pc.b.h ); /* Write previous PC to A:B */
WRB( tms7000.pc.b.l ); WRB( cpustate->pc.b.l );
pPC = RM16(0xfffe); /* Load reset vector */ pPC = RM16(cpustate, 0xfffe); /* Load reset vector */
tms7000_div_by_16_trigger = -16; cpustate->div_by_16_trigger = -16;
} }
@ -257,22 +229,24 @@ static CPU_RESET( tms7000 )
static CPU_SET_INFO( tms7000 ) static CPU_SET_INFO( tms7000 )
{ {
tms7000_state *cpustate = device->token;
switch (state) switch (state)
{ {
/* --- the following bits of info are set as 64-bit signed integers --- */ /* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ1_LINE: tms7000_set_irq_line(TMS7000_IRQ1_LINE, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ1_LINE: tms7000_set_irq_line(cpustate, TMS7000_IRQ1_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ2_LINE: tms7000_set_irq_line(TMS7000_IRQ2_LINE, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ2_LINE: tms7000_set_irq_line(cpustate, TMS7000_IRQ2_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE: tms7000_set_irq_line(TMS7000_IRQ3_LINE, info->i); break; case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE: tms7000_set_irq_line(cpustate, TMS7000_IRQ3_LINE, info->i); break;
case CPUINFO_INT_PC: case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + TMS7000_PC: pPC = info->i; break; case CPUINFO_INT_REGISTER + TMS7000_PC: pPC = info->i; break;
case CPUINFO_INT_SP: case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + TMS7000_SP: pSP = info->i; break; case CPUINFO_INT_REGISTER + TMS7000_SP: pSP = info->i; break;
case CPUINFO_INT_REGISTER + TMS7000_ST: pSR = info->i; tms7000_check_IRQ_lines(); break; case CPUINFO_INT_REGISTER + TMS7000_ST: pSR = info->i; tms7000_check_IRQ_lines(cpustate); break;
case CPUINFO_INT_REGISTER + TMS7000_IDLE: tms7000.idle_state = info->i; break; case CPUINFO_INT_REGISTER + TMS7000_IDLE: cpustate->idle_state = info->i; break;
case CPUINFO_INT_REGISTER + TMS7000_T1_CL: tms7000.t1_capture_latch = info->i; break; case CPUINFO_INT_REGISTER + TMS7000_T1_CL: cpustate->t1_capture_latch = info->i; break;
case CPUINFO_INT_REGISTER + TMS7000_T1_PS: tms7000.t1_prescaler = info->i; break; case CPUINFO_INT_REGISTER + TMS7000_T1_PS: cpustate->t1_prescaler = info->i; break;
case CPUINFO_INT_REGISTER + TMS7000_T1_DEC: tms7000.t1_decrementer = info->i; break; case CPUINFO_INT_REGISTER + TMS7000_T1_DEC: cpustate->t1_decrementer = info->i; break;
} }
} }
@ -282,11 +256,12 @@ static CPU_SET_INFO( tms7000 )
CPU_GET_INFO( tms7000 ) CPU_GET_INFO( tms7000 )
{ {
tms7000_state *cpustate = (device != NULL) ? device->token : NULL;
switch( state ) switch( state )
{ {
/* --- the following bits of info are returned as 64-bit signed integers --- */ /* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms7000); break; case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms7000_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 3; break; case CPUINFO_INT_INPUT_LINES: info->i = 3; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
@ -307,9 +282,9 @@ CPU_GET_INFO( tms7000 )
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break; case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ1_LINE: info->i = tms7000.irq_state[TMS7000_IRQ1_LINE]; break; case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ1_LINE: info->i = cpustate->irq_state[TMS7000_IRQ1_LINE]; break;
case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ2_LINE: info->i = tms7000.irq_state[TMS7000_IRQ2_LINE]; break; case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ2_LINE: info->i = cpustate->irq_state[TMS7000_IRQ2_LINE]; break;
case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE: info->i = tms7000.irq_state[TMS7000_IRQ3_LINE]; break; case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE: info->i = cpustate->irq_state[TMS7000_IRQ3_LINE]; break;
case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* Not supported */ break; case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* Not supported */ break;
@ -318,21 +293,21 @@ CPU_GET_INFO( tms7000 )
case CPUINFO_INT_SP: case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + TMS7000_SP: info->i = pSP; break; case CPUINFO_INT_REGISTER + TMS7000_SP: info->i = pSP; break;
case CPUINFO_INT_REGISTER + TMS7000_ST: info->i = pSR; break; case CPUINFO_INT_REGISTER + TMS7000_ST: info->i = pSR; break;
case CPUINFO_INT_REGISTER + TMS7000_IDLE: info->i = tms7000.idle_state; break; case CPUINFO_INT_REGISTER + TMS7000_IDLE: info->i = cpustate->idle_state; break;
case CPUINFO_INT_REGISTER + TMS7000_T1_CL: info->i = tms7000.t1_capture_latch; break; case CPUINFO_INT_REGISTER + TMS7000_T1_CL: info->i = cpustate->t1_capture_latch; break;
case CPUINFO_INT_REGISTER + TMS7000_T1_PS: info->i = tms7000.t1_prescaler; break; case CPUINFO_INT_REGISTER + TMS7000_T1_PS: info->i = cpustate->t1_prescaler; break;
case CPUINFO_INT_REGISTER + TMS7000_T1_DEC: info->i = tms7000.t1_decrementer; break; case CPUINFO_INT_REGISTER + TMS7000_T1_DEC: info->i = cpustate->t1_decrementer; break;
/* --- the following bits of info are returned as pointers to data or functions --- */ /* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms7000); break; case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms7000); break;
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(tms7000); break; case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break;
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(tms7000); break; case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break;
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(tms7000); break; case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(tms7000); break;
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(tms7000); break; case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(tms7000); break;
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms7000); break; case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms7000); break;
case CPUINFO_PTR_BURN: info->burn = NULL; /* Not supported */break; case CPUINFO_PTR_BURN: info->burn = NULL; /* Not supported */break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms7000); break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms7000); break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &tms7000_icount; break; case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
case CPUINFO_PTR_INTERNAL_MEMORY_MAP: info->internal_map8 = ADDRESS_MAP_NAME(tms7000_mem); break; case CPUINFO_PTR_INTERNAL_MEMORY_MAP: info->internal_map8 = ADDRESS_MAP_NAME(tms7000_mem); break;
/* --- the following bits of info are returned as NULL-terminated strings --- */ /* --- the following bits of info are returned as NULL-terminated strings --- */
@ -344,23 +319,23 @@ CPU_GET_INFO( tms7000 )
case CPUINFO_STR_FLAGS: case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c%c", sprintf(info->s, "%c%c%c%c%c%c%c%c",
tms7000.sr & 0x80 ? 'C':'c', cpustate->sr & 0x80 ? 'C':'c',
tms7000.sr & 0x40 ? 'N':'n', cpustate->sr & 0x40 ? 'N':'n',
tms7000.sr & 0x20 ? 'Z':'z', cpustate->sr & 0x20 ? 'Z':'z',
tms7000.sr & 0x10 ? 'I':'i', cpustate->sr & 0x10 ? 'I':'i',
tms7000.sr & 0x08 ? '?':'.', cpustate->sr & 0x08 ? '?':'.',
tms7000.sr & 0x04 ? '?':'.', cpustate->sr & 0x04 ? '?':'.',
tms7000.sr & 0x02 ? '?':'.', cpustate->sr & 0x02 ? '?':'.',
tms7000.sr & 0x01 ? '?':'.' ); cpustate->sr & 0x01 ? '?':'.' );
break; break;
case CPUINFO_STR_REGISTER + TMS7000_PC: sprintf(info->s, "PC:%04X", tms7000.pc.w.l); break; case CPUINFO_STR_REGISTER + TMS7000_PC: sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break;
case CPUINFO_STR_REGISTER + TMS7000_SP: sprintf(info->s, "S:%02X", tms7000.sp); break; case CPUINFO_STR_REGISTER + TMS7000_SP: sprintf(info->s, "S:%02X", cpustate->sp); break;
case CPUINFO_STR_REGISTER + TMS7000_ST: sprintf(info->s, "ST:%02X", tms7000.sr); break; case CPUINFO_STR_REGISTER + TMS7000_ST: sprintf(info->s, "ST:%02X", cpustate->sr); break;
case CPUINFO_STR_REGISTER + TMS7000_IDLE: sprintf(info->s, "Idle:%02X", tms7000.idle_state); break; case CPUINFO_STR_REGISTER + TMS7000_IDLE: sprintf(info->s, "Idle:%02X", cpustate->idle_state); break;
case CPUINFO_STR_REGISTER + TMS7000_T1_CL: sprintf(info->s, "T1CL:%02X", tms7000.t1_capture_latch); break; case CPUINFO_STR_REGISTER + TMS7000_T1_CL: sprintf(info->s, "T1CL:%02X", cpustate->t1_capture_latch); break;
case CPUINFO_STR_REGISTER + TMS7000_T1_PS: sprintf(info->s, "T1PS:%02X", tms7000.t1_prescaler & 0x1f); break; case CPUINFO_STR_REGISTER + TMS7000_T1_PS: sprintf(info->s, "T1PS:%02X", cpustate->t1_prescaler & 0x1f); break;
case CPUINFO_STR_REGISTER + TMS7000_T1_DEC: sprintf(info->s, "T1DEC:%02X", tms7000.t1_decrementer & 0xff); break; case CPUINFO_STR_REGISTER + TMS7000_T1_DEC: sprintf(info->s, "T1DEC:%02X", cpustate->t1_decrementer & 0xff); break;
} }
} }
@ -378,82 +353,82 @@ CPU_GET_INFO( tms7000_exl )
} }
} }
void tms7000_set_irq_line(int irqline, int state) void tms7000_set_irq_line(tms7000_state *cpustate, int irqline, int state)
{ {
if (tms7000.irq_state[irqline] != state) if (cpustate->irq_state[irqline] != state)
{ /* check for transition */ { /* check for transition */
tms7000.irq_state[irqline] = state; cpustate->irq_state[irqline] = state;
LOG(("tms7000: (cpu '%s') set_irq_line (INT%d, state %d)\n", tms7000.device->tag, irqline+1, state)); LOG(("tms7000: (cpu '%s') set_irq_line (INT%d, state %d)\n", cpustate->device->tag, irqline+1, state));
if (state == CLEAR_LINE) if (state == CLEAR_LINE)
{ {
return; return;
} }
tms7000.pf[0] |= (0x02 << (irqline * 2)); /* Set INTx iocntl0 flag */ cpustate->pf[0] |= (0x02 << (irqline * 2)); /* Set INTx iocntl0 flag */
if( irqline == TMS7000_IRQ3_LINE ) if( irqline == TMS7000_IRQ3_LINE )
{ {
/* Latch the value in perpherial file register 3 */ /* Latch the value in perpherial file register 3 */
tms7000.t1_capture_latch = tms7000.t1_decrementer & 0x00ff; cpustate->t1_capture_latch = cpustate->t1_decrementer & 0x00ff;
} }
tms7000_check_IRQ_lines(); tms7000_check_IRQ_lines(cpustate);
} }
} }
static void tms7000_check_IRQ_lines( void ) static void tms7000_check_IRQ_lines(tms7000_state *cpustate)
{ {
if( pSR & SR_I ) /* Check Global Interrupt bit: Status register, bit 4 */ if( pSR & SR_I ) /* Check Global Interrupt bit: Status register, bit 4 */
{ {
if ((tms7000.irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE) || (tms7000.pf[0] & 0x02)) if ((cpustate->irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE) || (cpustate->pf[0] & 0x02))
{ {
if( tms7000.pf[0] & 0x01 ) /* INT1 Enable bit */ if( cpustate->pf[0] & 0x01 ) /* INT1 Enable bit */
{ {
tms7000_do_interrupt( 0xfffc, TMS7000_IRQ1_LINE ); tms7000_do_interrupt( cpustate, 0xfffc, TMS7000_IRQ1_LINE );
tms7000.pf[0] &= ~0x02; /* Data Manual, page: 9-41 */ cpustate->pf[0] &= ~0x02; /* Data Manual, page: 9-41 */
return; return;
} }
} }
if( tms7000.irq_state[ TMS7000_IRQ2_LINE ] == ASSERT_LINE ) if( cpustate->irq_state[ TMS7000_IRQ2_LINE ] == ASSERT_LINE )
{ {
if( tms7000.pf[0] & 0x04 ) /* INT2 Enable bit */ if( cpustate->pf[0] & 0x04 ) /* INT2 Enable bit */
{ {
tms7000_do_interrupt( 0xfffa, TMS7000_IRQ2_LINE ); tms7000_do_interrupt( cpustate, 0xfffa, TMS7000_IRQ2_LINE );
return; return;
} }
} }
if ((tms7000.irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE) || (tms7000.pf[0] & 0x20)) if ((cpustate->irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE) || (cpustate->pf[0] & 0x20))
{ {
if( tms7000.pf[0] & 0x10 ) /* INT3 Enable bit */ if( cpustate->pf[0] & 0x10 ) /* INT3 Enable bit */
{ {
tms7000_do_interrupt( 0xfff8, TMS7000_IRQ3_LINE ); tms7000_do_interrupt( cpustate, 0xfff8, TMS7000_IRQ3_LINE );
tms7000.pf[0] &= ~0x20; /* Data Manual, page: 9-41 */ cpustate->pf[0] &= ~0x20; /* Data Manual, page: 9-41 */
return; return;
} }
} }
} }
} }
static void tms7000_do_interrupt( UINT16 address, UINT8 line ) static void tms7000_do_interrupt( tms7000_state *cpustate, UINT16 address, UINT8 line )
{ {
PUSHBYTE( pSR ); /* Push Status register */ PUSHBYTE( pSR ); /* Push Status register */
PUSHWORD( PC ); /* Push Program Counter */ PUSHWORD( PC ); /* Push Program Counter */
pSR = 0; /* Clear Status register */ pSR = 0; /* Clear Status register */
pPC = RM16(address); /* Load PC with interrupt vector */ pPC = RM16(cpustate, address); /* Load PC with interrupt vector */
if( tms7000.idle_state == 0 ) if( cpustate->idle_state == 0 )
tms7000_icount -= 19; /* 19 cycles used */ cpustate->icount -= 19; /* 19 cycles used */
else else
{ {
tms7000_icount -= 17; /* 17 if idled */ cpustate->icount -= 17; /* 17 if idled */
tms7000.idle_state = 0; cpustate->idle_state = 0;
} }
(void)(*tms7000.irq_callback)(tms7000.device, line); (void)(*cpustate->irq_callback)(cpustate->device, line);
} }
#include "tms70op.c" #include "tms70op.c"
@ -461,81 +436,87 @@ static void tms7000_do_interrupt( UINT16 address, UINT8 line )
static CPU_EXECUTE( tms7000 ) static CPU_EXECUTE( tms7000 )
{ {
tms7000_state *cpustate = device->token;
int op; int op;
tms7000_icount = cycles; cpustate->icount = cycles;
tms7000_div_by_16_trigger += cycles; cpustate->div_by_16_trigger += cycles;
tms7000_check_IRQ_lines(cpustate);
do do
{ {
debugger_instruction_hook(device, pPC); debugger_instruction_hook(device, pPC);
if( tms7000.idle_state == 0 ) if( cpustate->idle_state == 0 )
{ {
op = memory_decrypted_read_byte(tms7000.program, pPC++); op = memory_decrypted_read_byte(cpustate->program, pPC++);
opfn[op](); opfn[op](cpustate);
} }
else else
tms7000_icount -= 16; cpustate->icount -= 16;
/* Internal timer system */ /* Internal timer system */
while( tms7000_icount < tms7000_div_by_16_trigger ) while( cpustate->icount < cpustate->div_by_16_trigger )
{ {
tms7000_div_by_16_trigger -= 16; cpustate->div_by_16_trigger -= 16;
if( (tms7000.pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */ if( (cpustate->pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
{ {
if( (tms7000.pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */ if( (cpustate->pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */
tms7000_service_timer1(device); tms7000_service_timer1(device);
} }
} }
} while( tms7000_icount > 0 ); } while( cpustate->icount > 0 );
tms7000_div_by_16_trigger -= tms7000_icount; cpustate->div_by_16_trigger -= cpustate->icount;
return cycles - tms7000_icount; return cycles - cpustate->icount;
} }
static CPU_EXECUTE( tms7000_exl ) static CPU_EXECUTE( tms7000_exl )
{ {
tms7000_state *cpustate = device->token;
int op; int op;
tms7000_icount = cycles; cpustate->icount = cycles;
tms7000_div_by_16_trigger += cycles; cpustate->div_by_16_trigger += cycles;
tms7000_check_IRQ_lines(cpustate);
do do
{ {
debugger_instruction_hook(device, pPC); debugger_instruction_hook(device, pPC);
if( tms7000.idle_state == 0 ) if( cpustate->idle_state == 0 )
{ {
op = memory_decrypted_read_byte(tms7000.program, pPC++); op = memory_decrypted_read_byte(cpustate->program, pPC++);
opfn_exl[op](); opfn_exl[op](cpustate);
} }
else else
tms7000_icount -= 16; cpustate->icount -= 16;
/* Internal timer system */ /* Internal timer system */
while( tms7000_icount < tms7000_div_by_16_trigger ) while( cpustate->icount < cpustate->div_by_16_trigger )
{ {
tms7000_div_by_16_trigger -= 16; cpustate->div_by_16_trigger -= 16;
if( (tms7000.pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */ if( (cpustate->pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
{ {
if( (tms7000.pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */ if( (cpustate->pf[0x03] & 0x40) != 0x40) /* Is system clock (divided by 16) the timer source? */
tms7000_service_timer1(device); tms7000_service_timer1(device);
} }
} }
} while( tms7000_icount > 0 ); } while( cpustate->icount > 0 );
tms7000_div_by_16_trigger -= tms7000_icount; cpustate->div_by_16_trigger -= cpustate->icount;
return cycles - tms7000_icount; return cycles - cpustate->icount;
} }
/**************************************************************************** /****************************************************************************
@ -543,69 +524,72 @@ static CPU_EXECUTE( tms7000_exl )
****************************************************************************/ ****************************************************************************/
void tms7000_A6EC1( const device_config *device ) void tms7000_A6EC1( const device_config *device )
{ {
if( (tms7000.pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */ tms7000_state *cpustate = device->token;
if( (cpustate->pf[0x03] & 0x80) == 0x80 ) /* Is timer system active? */
{ {
if( (tms7000.pf[0x03] & 0x40) == 0x40) /* Is event counter the timer source? */ if( (cpustate->pf[0x03] & 0x40) == 0x40) /* Is event counter the timer source? */
tms7000_service_timer1(device); tms7000_service_timer1(device);
} }
} }
static void tms7000_service_timer1( const device_config *device ) static void tms7000_service_timer1( const device_config *device )
{ {
if( --tms7000.t1_prescaler < 0 ) /* Decrement prescaler and check for underflow */ tms7000_state *cpustate = device->token;
if( --cpustate->t1_prescaler < 0 ) /* Decrement prescaler and check for underflow */
{ {
tms7000.t1_prescaler = tms7000.pf[3] & 0x1f; /* Reload prescaler (5 bit) */ cpustate->t1_prescaler = cpustate->pf[3] & 0x1f; /* Reload prescaler (5 bit) */
if( --tms7000.t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */ if( --cpustate->t1_decrementer < 0 ) /* Decrement timer1 register and check for underflow */
{ {
tms7000.t1_decrementer = tms7000.pf[2]; /* Reload decrementer (8 bit) */ cpustate->t1_decrementer = cpustate->pf[2]; /* Reload decrementer (8 bit) */
cpu_set_input_line(device, TMS7000_IRQ2_LINE, HOLD_LINE); cpu_set_input_line(device, TMS7000_IRQ2_LINE, HOLD_LINE);
//LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", cpu_get_total_cycles(device), cpu_get_total_cycles(device) - tick, tms7000_cycles_per_INT2-(cpu_get_total_cycles(device) - tick) ); //LOG( ("tms7000: trigger int2 (cycles: %d)\t%d\tdelta %d\n", cpu_get_total_cycles(device), cpu_get_total_cycles(device) - tick, cpustate->cycles_per_INT2-(cpu_get_total_cycles(device) - tick) );
//tick = cpu_get_total_cycles(device) ); //tick = cpu_get_total_cycles(device) );
/* Also, cascade out to timer 2 - timer 2 unimplemented */ /* Also, cascade out to timer 2 - timer 2 unimplemented */
} }
} }
// LOG( ( "tms7000: service timer1. 0x%2.2x 0x%2.2x (cycles %d)\t%d\t\n", tms7000.t1_prescaler, tms7000.t1_decrementer, cpu_get_total_cycles(device), cpu_get_total_cycles(device) - tick2 ) ); // LOG( ( "tms7000: service timer1. 0x%2.2x 0x%2.2x (cycles %d)\t%d\t\n", cpustate->t1_prescaler, cpustate->t1_decrementer, cpu_get_total_cycles(device), cpu_get_total_cycles(device) - tick2 ) );
// tick2 = cpu_get_total_cycles(device); // tick2 = cpu_get_total_cycles(device);
} }
static WRITE8_HANDLER( tms70x0_pf_w ) /* Perpherial file write */ static WRITE8_HANDLER( tms70x0_pf_w ) /* Perpherial file write */
{ {
tms7000_state *cpustate = space->cpu->token;
UINT8 temp1, temp2, temp3; UINT8 temp1, temp2, temp3;
switch( offset ) switch( offset )
{ {
case 0x00: /* IOCNT0, Input/Ouput control */ case 0x00: /* IOCNT0, Input/Ouput control */
temp1 = data & 0x2a; /* Record which bits to clear */ temp1 = data & 0x2a; /* Record which bits to clear */
temp2 = tms7000.pf[0x00] & 0x2a; /* Get copy of current bits */ temp2 = cpustate->pf[0x00] & 0x2a; /* Get copy of current bits */
temp3 = (~temp1) & temp2; /* Clear the requested bits */ temp3 = (~temp1) & temp2; /* Clear the requested bits */
tms7000.pf[0x00] = temp3 | (data & (~0x2a) ); /* OR in the remaining data */ cpustate->pf[0x00] = temp3 | (data & (~0x2a) ); /* OR in the remaining data */
break; break;
case 0x02: case 0x02:
tms7000.t1_decrementer = tms7000.pf[0x02] = data; cpustate->t1_decrementer = cpustate->pf[0x02] = data;
tms7000_cycles_per_INT2 = 0x10*((tms7000.pf[3] & 0x1f)+1)*(tms7000.pf[0x02]+1); cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
LOG( ( "tms7000: Timer adjusted. Decrementer: 0x%2.2x (Cycles per interrupt: %d)\n", tms7000.t1_decrementer, tms7000_cycles_per_INT2 ) ); LOG( ( "tms7000: Timer adjusted. Decrementer: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->t1_decrementer, cpustate->cycles_per_INT2 ) );
break; break;
case 0x03: /* T1CTL, timer 1 control */ case 0x03: /* T1CTL, timer 1 control */
if( ((tms7000.pf[0x03] & 0x80) == 0) && ((data & 0x80) == 0x80 ) ) /* Start timer? */ if( ((cpustate->pf[0x03] & 0x80) == 0) && ((data & 0x80) == 0x80 ) ) /* Start timer? */
{ {
tms7000.pf[0x03] = data; cpustate->pf[0x03] = data;
tms7000.t1_prescaler = tms7000.pf[3] & 0x1f; /* Reload prescaler (5 bit) */ cpustate->t1_prescaler = cpustate->pf[3] & 0x1f; /* Reload prescaler (5 bit) */
tms7000_cycles_per_INT2 = 0x10*((tms7000.pf[3] & 0x1f)+1)*(tms7000.pf[0x02]+1); cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
LOG( ( "tms7000: Timer started. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", tms7000.pf[3] & 0x1f, tms7000_cycles_per_INT2 ) ); LOG( ( "tms7000: Timer started. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->pf[3] & 0x1f, cpustate->cycles_per_INT2 ) );
} }
else if( ((data & 0x80) == 0x80 ) && ((tms7000.pf[0x03] & 0x80) == 0) ) /* Timer Stopped? */ else if( ((data & 0x80) == 0x80 ) && ((cpustate->pf[0x03] & 0x80) == 0) ) /* Timer Stopped? */
{ {
tms7000.pf[0x03] = data; cpustate->pf[0x03] = data;
tms7000.t1_prescaler = tms7000.pf[3] & 0x1f; /* Reload prescaler (5 bit) */ cpustate->t1_prescaler = cpustate->pf[3] & 0x1f; /* Reload prescaler (5 bit) */
tms7000_cycles_per_INT2 = 0x10*((tms7000.pf[3] & 0x1f)+1)*(tms7000.pf[0x02]+1); cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
LOG( ( "tms7000: Timer stopped. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", tms7000.pf[3] & 0x1f, tms7000_cycles_per_INT2 ) ); LOG( ( "tms7000: Timer stopped. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->pf[3] & 0x1f, cpustate->cycles_per_INT2 ) );
} }
else /* Don't modify timer state, but still store data */ else /* Don't modify timer state, but still store data */
{ {
tms7000.pf[0x03] = data; cpustate->pf[0x03] = data;
tms7000_cycles_per_INT2 = 0x10*((tms7000.pf[3] & 0x1f)+1)*(tms7000.pf[0x02]+1); cpustate->cycles_per_INT2 = 0x10*((cpustate->pf[3] & 0x1f)+1)*(cpustate->pf[0x02]+1);
LOG( ( "tms7000: Timer adjusted. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", tms7000.pf[3] & 0x1f, tms7000_cycles_per_INT2 ) ); LOG( ( "tms7000: Timer adjusted. Prescaler: 0x%2.2x (Cycles per interrupt: %d)\n", cpustate->pf[3] & 0x1f, cpustate->cycles_per_INT2 ) );
} }
break; break;
@ -614,79 +598,80 @@ static WRITE8_HANDLER( tms70x0_pf_w ) /* Perpherial file write */
break; break;
case 0x06: /* Port B write */ case 0x06: /* Port B write */
memory_write_byte_8be( tms7000.io, TMS7000_PORTB, data ); memory_write_byte_8be( cpustate->io, TMS7000_PORTB, data );
tms7000.pf[ 0x06 ] = data; cpustate->pf[ 0x06 ] = data;
break; break;
case 0x08: /* Port C write */ case 0x08: /* Port C write */
temp1 = data & tms7000.pf[ 0x09 ]; /* Mask off input bits */ temp1 = data & cpustate->pf[ 0x09 ]; /* Mask off input bits */
memory_write_byte_8be( tms7000.io, TMS7000_PORTC, temp1 ); memory_write_byte_8be( cpustate->io, TMS7000_PORTC, temp1 );
tms7000.pf[ 0x08 ] = temp1; cpustate->pf[ 0x08 ] = temp1;
break; break;
case 0x0a: /* Port D write */ case 0x0a: /* Port D write */
temp1 = data & tms7000.pf[ 0x0b ]; /* Mask off input bits */ temp1 = data & cpustate->pf[ 0x0b ]; /* Mask off input bits */
memory_write_byte_8be( tms7000.io, TMS7000_PORTD, temp1 ); memory_write_byte_8be( cpustate->io, TMS7000_PORTD, temp1 );
tms7000.pf[ 0x0a ] = temp1; cpustate->pf[ 0x0a ] = temp1;
break; break;
default: default:
/* Just stuff the other registers */ /* Just stuff the other registers */
tms7000.pf[ offset ] = data; cpustate->pf[ offset ] = data;
break; break;
} }
} }
static READ8_HANDLER( tms70x0_pf_r ) /* Perpherial file read */ static READ8_HANDLER( tms70x0_pf_r ) /* Perpherial file read */
{ {
tms7000_state *cpustate = space->cpu->token;
UINT8 result; UINT8 result;
UINT8 temp1, temp2, temp3; UINT8 temp1, temp2, temp3;
switch( offset ) switch( offset )
{ {
case 0x00: /* IOCNT0, Input/Ouput control */ case 0x00: /* IOCNT0, Input/Ouput control */
result = tms7000.pf[0x00]; result = cpustate->pf[0x00];
if (tms7000.irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE) if (cpustate->irq_state[TMS7000_IRQ1_LINE] == ASSERT_LINE)
result |= 0x02; result |= 0x02;
if (tms7000.irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE) if (cpustate->irq_state[TMS7000_IRQ3_LINE] == ASSERT_LINE)
result |= 0x20; result |= 0x20;
break; break;
case 0x02: /* T1DATA, timer 1 8-bit decrementer */ case 0x02: /* T1DATA, timer 1 8-bit decrementer */
result = (tms7000.t1_decrementer & 0x00ff); result = (cpustate->t1_decrementer & 0x00ff);
break; break;
case 0x03: /* T1CTL, timer 1 capture (latched by INT3) */ case 0x03: /* T1CTL, timer 1 capture (latched by INT3) */
result = tms7000.t1_capture_latch; result = cpustate->t1_capture_latch;
break; break;
case 0x04: /* Port A read */ case 0x04: /* Port A read */
result = memory_read_byte_8be( tms7000.io, TMS7000_PORTA ); result = memory_read_byte_8be( cpustate->io, TMS7000_PORTA );
break; break;
case 0x06: /* Port B read */ case 0x06: /* Port B read */
/* Port B is write only, return a previous written value */ /* Port B is write only, return a previous written value */
result = tms7000.pf[ 0x06 ]; result = cpustate->pf[ 0x06 ];
break; break;
case 0x08: /* Port C read */ case 0x08: /* Port C read */
temp1 = tms7000.pf[ 0x08 ] & tms7000.pf[ 0x09 ]; /* Get previous output bits */ temp1 = cpustate->pf[ 0x08 ] & cpustate->pf[ 0x09 ]; /* Get previous output bits */
temp2 = memory_read_byte_8be( tms7000.io, TMS7000_PORTC ); /* Read port */ temp2 = memory_read_byte_8be( cpustate->io, TMS7000_PORTC ); /* Read port */
temp3 = temp2 & (~tms7000.pf[ 0x09 ]); /* Mask off output bits */ temp3 = temp2 & (~cpustate->pf[ 0x09 ]); /* Mask off output bits */
result = temp1 | temp3; /* OR together */ result = temp1 | temp3; /* OR together */
break; break;
case 0x0a: /* Port D read */ case 0x0a: /* Port D read */
temp1 = tms7000.pf[ 0x0a ] & tms7000.pf[ 0x0b ]; /* Get previous output bits */ temp1 = cpustate->pf[ 0x0a ] & cpustate->pf[ 0x0b ]; /* Get previous output bits */
temp2 = memory_read_byte_8be( tms7000.io, TMS7000_PORTD ); /* Read port */ temp2 = memory_read_byte_8be( cpustate->io, TMS7000_PORTD ); /* Read port */
temp3 = temp2 & (~tms7000.pf[ 0x0b ]); /* Mask off output bits */ temp3 = temp2 & (~cpustate->pf[ 0x0b ]); /* Mask off output bits */
result = temp1 | temp3; /* OR together */ result = temp1 | temp3; /* OR together */
break; break;
default: default:
/* Just unstuff the other registers */ /* Just unstuff the other registers */
result = tms7000.pf[ offset ]; result = cpustate->pf[ offset ];
break; break;
} }
@ -731,9 +716,11 @@ static UINT16 bcd_sub( UINT16 a, UINT16 b)
} }
static WRITE8_HANDLER( tms7000_internal_w ) { static WRITE8_HANDLER( tms7000_internal_w ) {
tms7000.rf[ offset ] = data; tms7000_state *cpustate = space->cpu->token;
cpustate->rf[ offset ] = data;
} }
static READ8_HANDLER( tms7000_internal_r ) { static READ8_HANDLER( tms7000_internal_r ) {
return tms7000.rf[ offset ]; tms7000_state *cpustate = space->cpu->token;
return cpustate->rf[ offset ];
} }

2
src/emu/cpu/tms7000/tms7000.h
View File

@ -1,6 +1,6 @@
/***************************************************************************** /*****************************************************************************
* *
* tms7000.h (c header file) * cpustate->h (c header file)
* Portable TMS7000 emulator (Texas Instruments 7000) * Portable TMS7000 emulator (Texas Instruments 7000)
* *
* Copyright tim lindner, all rights reserved. * Copyright tim lindner, all rights reserved.

1076
src/emu/cpu/tms7000/tms70op.c
View File

File diff suppressed because it is too large Load Diff

4
src/emu/cpu/tms7000/tms70tb.c
View File

@ -17,7 +17,7 @@
* *
*****************************************************************************/ *****************************************************************************/
static void (*const opfn[0x100])(void) = { static void (*const opfn[0x100])(tms7000_state *cpustate) = {
/* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7, /* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7,
0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */ 0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */
@ -70,7 +70,7 @@ static void (*const opfn[0x100])(void) = {
trap_7, trap_6, trap_5, trap_4, trap_3, trap_2, trap_1, trap_0 trap_7, trap_6, trap_5, trap_4, trap_3, trap_2, trap_1, trap_0
}; };
static void (*const opfn_exl[0x100])(void) = { static void (*const opfn_exl[0x100])(tms7000_state *cpustate) = {
/* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7, /* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7,
0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */ 0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */