mirror of
https://github.com/holub/mame
synced 2025-06-22 12:28:33 +03:00
configurable ram, improved system regs, enum masks
also initial implementation of unmapped memory handler
This commit is contained in:
Patrick Mackinlay
parent
d4b5731dd9
commit
8bb75751d2
@ -3,7 +3,7 @@
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#include "emu.h"
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#define NEW_SCSI 0
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#define NEW_SCSI 1
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#include "includes/interpro.h"
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#include "debugger.h"
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@ -20,91 +20,81 @@
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// machine start
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void interpro_state::machine_start()
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{
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m_system_reg[SREG_CTRL2] = CTRL2_COLDSTART | CTRL2_PWRENA | CTRL2_PWRUP;
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m_sreg_ctrl2 = CTRL2_COLDSTART | CTRL2_PWRENA | CTRL2_PWRUP;
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}
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void interpro_state::machine_reset()
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{
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// flash rom requires the following values
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m_system_reg[SREG_ERROR] = 0x00;
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m_system_reg[SREG_STATUS] = 0x400;
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m_system_reg[SREG_CTRL1] = CTRL1_FLOPRDY;
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m_sreg_error = 0x00;
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m_sreg_status = 0x400;
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m_sreg_ctrl1 = CTRL1_FLOPRDY;
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}
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WRITE16_MEMBER(interpro_state::system_w)
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WRITE16_MEMBER(interpro_state::sreg_ctrl1_w)
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{
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switch (offset)
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{
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case SREG_LED:
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LOG_SYSTEM("LED value %d at %s\n", data, machine().describe_context());
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break;
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LOG_SYSTEM("system control register 1 write data 0x%x (%s)\n", data, machine().describe_context());
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case SREG_STATUS: // not sure if writable?
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break;
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case SREG_CTRL1:
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LOG_SYSTEM("system control register 1 write data 0x%x pc %s\n", data, machine().describe_context());
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if ((data ^ m_system_reg[offset]) & CTRL1_LEDDP)
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if ((data ^ m_sreg_ctrl1) & CTRL1_LEDDP)
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LOG_SYSTEM("LED decimal point %s\n", data & CTRL1_LEDDP ? "on" : "off");
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m_system_reg[offset] = data;
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break;
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m_sreg_ctrl1 = data;
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}
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case SREG_CTRL2:
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LOG_SYSTEM("system control register 2 write data 0x%x at %s\n", data, machine().describe_context());
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WRITE16_MEMBER(interpro_state::sreg_ctrl2_w)
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{
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LOG_SYSTEM("system control register 2 write data 0x%x (%s)\n", data, machine().describe_context());
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if (data & CTRL2_RESET)
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{
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m_system_reg[SREG_CTRL2] &= ~CTRL2_COLDSTART;
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m_sreg_ctrl1 &= ~CTRL2_COLDSTART;
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machine().schedule_soft_reset();
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}
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else
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m_system_reg[offset] = data & 0x0f; // top four bits are not persistent
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break;
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}
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m_sreg_ctrl1 = data & CTRL2_WMASK;
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}
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READ16_MEMBER(interpro_state::system_r)
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READ16_MEMBER(interpro_state::sreg_error_r)
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{
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LOG_SYSTEM("system register read offset %d at %s\n", offset, machine().describe_context());
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switch (offset)
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{
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case SREG_ERROR:
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case SREG_STATUS:
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case SREG_CTRL1:
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case SREG_CTRL2:
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default:
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return m_system_reg[offset];
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break;
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}
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u16 result = m_sreg_error;
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// clear error register on read
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m_sreg_error = 0;
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return result;
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}
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READ32_MEMBER(interpro_state::idprom_r)
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READ8_MEMBER(interpro_state::idprom_r)
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{
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LOG_IDPROM("idprom read offset 0x%x mask 0x%08x at %s\n", offset, mem_mask, machine().describe_context());
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// abitrary fake number for now, not working properly
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u32 speed = 20000000;
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u32 speed1 = speed >> 24;
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u32 speed2 = speed >> 16;
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u32 speed3 = speed >> 8;
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// compute femtoseconds per cycle from main cpu clock
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u32 speed = 1'000'000'000'000'000 / m_maincpu->clock();
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static uint8_t idprom[] = {
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static u8 idprom[] = {
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// module type id
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'M', 'P', 'C', 'B',
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'0', '1', '4', '5',
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0x00, 0x00, 0x00, 0x00, // board type MSMT/MPCB - detected by feature[3]
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'1', '2', '3', // board number
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'A', // board revision
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// ECO bytes
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0x87, 0x65, 0x43, 0x21,
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0xbb, 0xcc, 0xdd, 0xee,
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// the following 8 bytes are "feature bytes"
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// the feature bytes contain a 32 bit word which is divided by 40000
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// if they're empty, a default value of 50 000 000 is used
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// perhaps this is a system speed (50MHz)?
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0x2, 0x34, 0x56, 0x78,
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(u8)speed, (u8)speed3, (u8)speed2, (u8)speed1,
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// for a 2700/2800/2500 system board, the first feature byte selects the variant
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// model = (feature[0] & 0x2) ? (feature[0] & 0x8 ? 2700 : 2800) : 2500
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// 0x0a, // 2700 series
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0x02, // 2800 series
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// 0x00, // 2500 series
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0x00, 0x00,
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0x80, // board type, 0x80 = MPCB, 0x00 = MSMT
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// for the system boards, these bytes contain cpu clock speed (as femtoseconds per cycle, big-endian)
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(u8)(speed >> 24), (u8)(speed >> 16), (u8)(speed >> 8), (u8)(speed >> 0),
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// reserved bytes
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0xff, 0xff,
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@ -113,8 +103,14 @@ READ32_MEMBER(interpro_state::idprom_r)
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// boot rom tests for family == 0x41 or 0x42
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// if so, speed read from feature bytes 2 & 3
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// if not, read speed from feature bytes 4-7
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0x41, 0x00, // 2800-series CPU
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//0x24, 0x00, // 2000-series system board
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//0x24, 0x00, // 2000
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// 0x31, 0x00, // 2400
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0x39, 0x00, // 2700/2800/2500 depending on first feature byte (0xa, 0x2, 0x0)
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// 0x40, 0x00, // 6700
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// 0x41, 0x00, // idprom reports as 2800 series cpu?
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//0x42, 0x00, // 6800 series
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// footprint and checksum
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0x55, 0xaa, 0x55, 0x00
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@ -124,13 +120,13 @@ READ32_MEMBER(interpro_state::idprom_r)
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{
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case 0x1f:
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{
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uint8_t sum = 0;
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u8 sum = 0;
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// compute the checksum (sum of all bytes must be == 0x00)
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for (int i = 0; i < 0x20; i++)
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sum += idprom[i];
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return 0x100 - (sum & 0xff);
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return 0x100 - sum;
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}
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default:
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@ -138,19 +134,74 @@ READ32_MEMBER(interpro_state::idprom_r)
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}
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}
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READ32_MEMBER(interpro_state::slot0_r)
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READ8_MEMBER(interpro_state::slot0_r)
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{
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#if 0
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// a known graphics board idprom
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static uint8_t slot0[] = {
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static u8 slot0[] = {
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0x00, 0x00, 0x00, 0x00, '9', '6', '3', 'A', // board
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0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // eco
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // features
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0xff, 0xff, // reserved
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0x22, 0x00, // family
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0x55, 0xaa, 0x55, 0x00
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0x55, 0xaa, 0x55, // footprint
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0x00 // checksum
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};
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#else
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static u8 slot0[] = {
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0x00, 0x00, 0x00, 0x00, '1', '1', '1', 'A', // board
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0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // eco
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0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, // features
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0xff, 0xff, // reserved
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0x05, 0x00, // family
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0x55, 0xaa, 0x55, // footprint
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0x00 // checksum
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};
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#endif
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switch (offset)
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{
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case 0x1f:
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{
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u8 sum = 0;
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return ((uint8_t *)&slot0)[offset % 32];
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// compute the checksum (sum of all bytes must be == 0x00)
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for (int i = 0; i < 0x20; i++)
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sum += slot0[i];
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return 0x100 - sum;
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}
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default:
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return slot0[offset];
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}
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}
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READ32_MEMBER(interpro_state::unmapped_r)
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{
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// check if non-existent memory errors are enabled
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if (m_srarb->tmctrl_r(space, offset, mem_mask) & interpro_srarb_device::TMCTRL_ENNEM)
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{
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// flag non-existent memory error in system error register
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m_sreg_error |= (ERROR_SRXNEM | ERROR_SRXVALID);
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// tell ioga to raise a bus error
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m_ioga->bus_error(space, interpro_ioga_device::BINFO_BERR | interpro_ioga_device::BINFO_SNAPOK, offset << 2);
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}
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return space.unmap();
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}
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WRITE32_MEMBER(interpro_state::unmapped_w)
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{
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// check if non-existent memory errors are enabled
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if (m_srarb->tmctrl_r(space, offset, mem_mask) & interpro_srarb_device::TMCTRL_ENNEM)
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{
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// flag non-existent memory error in system error register
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m_sreg_error |= (ERROR_SRXNEM | ERROR_SRXVALID);
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// tell ioga to raise a bus error
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m_ioga->bus_error(space, interpro_ioga_device::BINFO_BERR | interpro_ioga_device::BINFO_SNAPOK, offset << 2);
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}
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}
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WRITE8_MEMBER(interpro_state::rtc_w)
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@ -271,6 +322,19 @@ WRITE8_MEMBER(interpro_state::scsi_dma_w)
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DRIVER_INIT_MEMBER(interpro_state, ip2800)
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{
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// FIXME: not all memory sizes are reported properly using fdm "5 inqhw" and "optimum_memory" commands
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// 16 = reports 16M, banks empty?
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// 32 = reports 16M, banks empty?
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// 64 = reports 128M, 16x8
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// 128 = reports 128M, 16x8
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// 256 = reports 256M, 32x8
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// grab the main memory space from the mmu
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address_space &space = m_mmu->space(AS_0);
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// map the configured ram
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space.install_ram(0, m_ram->mask(), m_ram->pointer());
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}
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#if NEW_SCSI
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@ -280,7 +344,7 @@ static SLOT_INTERFACE_START(interpro_scsi_devices)
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SLOT_INTERFACE_INTERNAL(INTERPRO_SCSI_ADAPTER_TAG, NCR53C94)
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SLOT_INTERFACE_END
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static MACHINE_CONFIG_FRAGMENT(interpro_scsi_adapter)
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static MACHINE_CONFIG_START(interpro_scsi_adapter)
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MCFG_DEVICE_CLOCK(XTAL_12_5MHz)
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MCFG_NCR5390_IRQ_HANDLER(DEVWRITELINE(":" INTERPRO_IOGA_TAG, interpro_ioga_device, ir0_w))
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MCFG_NCR5390_DRQ_HANDLER(DEVWRITELINE(":" INTERPRO_IOGA_TAG, interpro_ioga_device, drq_scsi))
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@ -296,50 +360,49 @@ static ADDRESS_MAP_START(clipper_data_map, AS_DATA, 32, interpro_state)
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AM_RANGE(0x00000000, 0xffffffff) AM_DEVREADWRITE32(INTERPRO_MMU_TAG, cammu_device, data_r, data_w, 0xffffffff)
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ADDRESS_MAP_END
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// these maps represent the real main, i/o and boot spaces of the system
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static ADDRESS_MAP_START(interpro_main_map, AS_0, 32, interpro_state)
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AM_RANGE(0x00000000, 0x00ffffff) AM_RAM // 16M RAM
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AM_RANGE(0x40000000, 0x4000003f) AM_DEVICE(INTERPRO_MCGA_TAG, interpro_fmcc_device, map)
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AM_RANGE(0x4f007e00, 0x4f007eff) AM_DEVICE(INTERPRO_SGA_TAG, interpro_sga_device, map)
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AM_RANGE(0x7f000100, 0x7f00011f) AM_DEVICE8(INTERPRO_FDC_TAG, n82077aa_device, map, 0xff)
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AM_RANGE(0x7f000200, 0x7f0002ff) AM_DEVICE(INTERPRO_SRARB_TAG, interpro_srarb_device, map)
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AM_RANGE(0x7f000300, 0x7f00030f) AM_READWRITE16(system_r, system_w, 0xffff)
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AM_RANGE(0x7f000400, 0x7f00040f) AM_DEVREADWRITE8(INTERPRO_SCC1_TAG, scc85c30_device, ba_cd_inv_r, ba_cd_inv_w, 0xff)
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AM_RANGE(0x7f000410, 0x7f00041f) AM_DEVREADWRITE8(INTERPRO_SCC2_TAG, scc85230_device, ba_cd_inv_r, ba_cd_inv_w, 0xff)
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AM_RANGE(0x7f000500, 0x7f0006ff) AM_READWRITE8(rtc_r, rtc_w, 0xff)
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AM_RANGE(0x7f000700, 0x7f00077f) AM_READ(idprom_r)
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AM_RANGE(0x7f001000, 0x7f001fff) AM_READWRITE8(scsi_r, scsi_w, 0x0000ff00)
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AM_RANGE(0x7f0fff00, 0x7f0fffff) AM_DEVICE(INTERPRO_IOGA_TAG, interpro_ioga_device, map)
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AM_RANGE(0x7f100000, 0x7f11ffff) AM_ROM AM_REGION(INTERPRO_EPROM_TAG, 0)
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AM_RANGE(0x7f180000, 0x7f1bffff) AM_ROM AM_REGION(INTERPRO_FLASH_TAG, 0)
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AM_RANGE(0x08000000, 0x08000fff) AM_NOP // bogus
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AM_RANGE(0x8f000000, 0x8f0fffff) AM_NOP // AM_READ(slot0_r)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(interpro_io_map, AS_1, 32, interpro_state)
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AM_RANGE(0x00000000, 0x00001fff) AM_DEVICE(INTERPRO_MMU_TAG, cammu_device, map)
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static ADDRESS_MAP_START(interpro_common_map, AS_0, 32, interpro_state)
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AM_RANGE(0x40000000, 0x4000004f) AM_DEVICE(INTERPRO_MCGA_TAG, interpro_fmcc_device, map)
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AM_RANGE(0x4f007e00, 0x4f007eff) AM_DEVICE(INTERPRO_SGA_TAG, interpro_sga_device, map)
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AM_RANGE(0x7f000100, 0x7f00011f) AM_DEVICE8(INTERPRO_FDC_TAG, n82077aa_device, map, 0xff)
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AM_RANGE(0x7f000200, 0x7f0002ff) AM_DEVICE(INTERPRO_SRARB_TAG, interpro_srarb_device, map)
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AM_RANGE(0x7f000300, 0x7f00030f) AM_READWRITE16(system_r, system_w, 0xffff)
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AM_RANGE(0x7f000300, 0x7f000303) AM_READ16(sreg_error_r, 0xffff)
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AM_RANGE(0x7f000304, 0x7f000307) AM_READWRITE16(sreg_status_r, sreg_led_w, 0xffff)
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AM_RANGE(0x7f000308, 0x7f00030b) AM_READWRITE16(sreg_ctrl1_r, sreg_ctrl1_w, 0xffff)
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AM_RANGE(0x7f00030c, 0x7f00030f) AM_READWRITE16(sreg_ctrl2_r, sreg_ctrl2_w, 0xffff)
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AM_RANGE(0x7f00031c, 0x7f00031f) AM_READWRITE16(sreg_ctrl3_r, sreg_ctrl3_w, 0xffff)
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AM_RANGE(0x7f000400, 0x7f00040f) AM_DEVREADWRITE8(INTERPRO_SCC1_TAG, scc85c30_device, ba_cd_inv_r, ba_cd_inv_w, 0xff)
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AM_RANGE(0x7f000410, 0x7f00041f) AM_DEVREADWRITE8(INTERPRO_SCC2_TAG, scc85230_device, ba_cd_inv_r, ba_cd_inv_w, 0xff)
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AM_RANGE(0x7f000500, 0x7f0006ff) AM_READWRITE8(rtc_r, rtc_w, 0xff)
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AM_RANGE(0x7f000700, 0x7f00077f) AM_READ(idprom_r)
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AM_RANGE(0x7f000700, 0x7f00077f) AM_READ8(idprom_r, 0xff)
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AM_RANGE(0x7f001000, 0x7f001fff) AM_READWRITE8(scsi_r, scsi_w, 0x0000ff00)
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AM_RANGE(0x7f0fff00, 0x7f0fffff) AM_DEVICE(INTERPRO_IOGA_TAG, interpro_ioga_device, map)
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AM_RANGE(0x08000000, 0x08000fff) AM_NOP // bogus
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AM_RANGE(0x8f000000, 0x8f0fffff) AM_NOP // AM_READ(slot0_r)
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AM_RANGE(0x87000000, 0x8700007f) AM_READ8(slot0_r, 0xff)
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// 2800 (CBUS?) slots are mapped as follows
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AM_RANGE(0x87000000, 0x8700007f) AM_MIRROR(0x78000000) AM_READWRITE(unmapped_r, unmapped_w)
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ADDRESS_MAP_END
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// these maps represent the real main, i/o and boot spaces of the system
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static ADDRESS_MAP_START(interpro_main_map, AS_0, 32, interpro_state)
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AM_RANGE(0x00000000, 0x00ffffff) AM_RAM AM_SHARE(RAM_TAG)
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AM_RANGE(0x7f100000, 0x7f11ffff) AM_ROM AM_REGION(INTERPRO_EPROM_TAG, 0)
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AM_RANGE(0x7f180000, 0x7f1bffff) AM_ROM AM_REGION(INTERPRO_FLASH_TAG, 0)
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AM_IMPORT_FROM(interpro_common_map)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(interpro_io_map, AS_1, 32, interpro_state)
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AM_RANGE(0x00000000, 0x00001fff) AM_DEVICE(INTERPRO_MMU_TAG, cammu_device, map)
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AM_IMPORT_FROM(interpro_common_map)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(interpro_boot_map, AS_2, 32, interpro_state)
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@ -360,7 +423,7 @@ static INPUT_PORTS_START(ip2800)
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INPUT_PORTS_END
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static MACHINE_CONFIG_START(ip2800)
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MCFG_CPU_ADD(INTERPRO_CPU_TAG, CLIPPER_C400, XTAL_10MHz)
|
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MCFG_CPU_ADD(INTERPRO_CPU_TAG, CLIPPER_C400, XTAL_12_5MHz)
|
||||
MCFG_CPU_PROGRAM_MAP(clipper_insn_map)
|
||||
MCFG_CPU_DATA_MAP(clipper_data_map)
|
||||
MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE(INTERPRO_IOGA_TAG, interpro_ioga_device, inta_cb)
|
||||
@ -371,26 +434,47 @@ static MACHINE_CONFIG_START(ip2800)
|
||||
MCFG_DEVICE_ADDRESS_MAP(AS_2, interpro_boot_map)
|
||||
MCFG_CAMMU_SSW_CB(DEVREAD32(INTERPRO_CPU_TAG, clipper_device, ssw))
|
||||
|
||||
// serial controllers and rs232 bus
|
||||
MCFG_RAM_ADD(RAM_TAG)
|
||||
MCFG_RAM_DEFAULT_SIZE("16M")
|
||||
MCFG_RAM_EXTRA_OPTIONS("32M,64M,128M,256M")
|
||||
|
||||
// TODO: work out serial port assignments for mouse, console, keyboard and ?
|
||||
// first serial controller and devices
|
||||
MCFG_SCC85C30_ADD(INTERPRO_SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
|
||||
|
||||
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE("rs232a", rs232_port_device, write_txd))
|
||||
MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_txd))
|
||||
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(INTERPRO_SERIAL1_TAG, rs232_port_device, write_txd))
|
||||
MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE(INTERPRO_SERIAL2_TAG, rs232_port_device, write_txd))
|
||||
MCFG_Z80SCC_OUT_INT_CB(DEVWRITELINE(INTERPRO_IOGA_TAG, interpro_ioga_device, ir11_w))
|
||||
|
||||
MCFG_RS232_PORT_ADD("rs232a", default_rs232_devices, nullptr)
|
||||
// is this the keyboard port?
|
||||
MCFG_RS232_PORT_ADD(INTERPRO_SERIAL1_TAG, default_rs232_devices, nullptr) // "keyboard"
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, rxa_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, dcda_w))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, ctsa_w))
|
||||
|
||||
// the following port is known as "port 2"
|
||||
MCFG_RS232_PORT_ADD("rs232b", default_rs232_devices, "terminal")
|
||||
// eprom uses this serial port for console (show_config calls "port 2")
|
||||
MCFG_RS232_PORT_ADD(INTERPRO_SERIAL2_TAG, default_rs232_devices, "terminal")
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, rxb_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, dcdb_w))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, ctsb_w))
|
||||
|
||||
// second serial controller and devices
|
||||
MCFG_SCC85230_ADD(INTERPRO_SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0)
|
||||
|
||||
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(INTERPRO_SERIAL3_TAG, rs232_port_device, write_txd))
|
||||
MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE(INTERPRO_SERIAL4_TAG, rs232_port_device, write_txd))
|
||||
MCFG_Z80SCC_OUT_INT_CB(DEVWRITELINE(INTERPRO_IOGA_TAG, interpro_ioga_device, ir11_w))
|
||||
|
||||
MCFG_RS232_PORT_ADD(INTERPRO_SERIAL3_TAG, default_rs232_devices, nullptr)
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, rxa_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, dcda_w))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, ctsa_w))
|
||||
|
||||
MCFG_RS232_PORT_ADD(INTERPRO_SERIAL4_TAG, default_rs232_devices, nullptr) //"terminal")
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, rxb_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, dcdb_w))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, ctsb_w))
|
||||
|
||||
// real-time clock/non-volatile memory
|
||||
MCFG_MC146818_ADD(INTERPRO_RTC_TAG, XTAL_32_768kHz)
|
||||
MCFG_MC146818_UTC(true)
|
||||
@ -408,9 +492,9 @@ static MACHINE_CONFIG_START(ip2800)
|
||||
#if NEW_SCSI
|
||||
MCFG_NSCSI_BUS_ADD(INTERPRO_SCSI_TAG)
|
||||
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":0", interpro_scsi_devices, "harddisk", false)
|
||||
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":1", interpro_scsi_devices, "cdrom", false)
|
||||
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":1", interpro_scsi_devices, nullptr, false)
|
||||
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":2", interpro_scsi_devices, nullptr, false)
|
||||
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":3", interpro_scsi_devices, nullptr, false)
|
||||
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":3", interpro_scsi_devices, "cdrom", false)
|
||||
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":4", interpro_scsi_devices, nullptr, false)
|
||||
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":5", interpro_scsi_devices, nullptr, false)
|
||||
MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":6", interpro_scsi_devices, nullptr, false)
|
||||
@ -419,7 +503,7 @@ static MACHINE_CONFIG_START(ip2800)
|
||||
#else
|
||||
MCFG_DEVICE_ADD(INTERPRO_SCSI_TAG, SCSI_PORT, 0)
|
||||
MCFG_SCSIDEV_ADD(INTERPRO_SCSI_TAG ":" SCSI_PORT_DEVICE1, "harddisk", SCSIHD, SCSI_ID_0)
|
||||
MCFG_SCSIDEV_ADD(INTERPRO_SCSI_TAG ":" SCSI_PORT_DEVICE2, "cdrom", SCSICD, SCSI_ID_3)
|
||||
MCFG_SCSIDEV_ADD(INTERPRO_SCSI_TAG ":" SCSI_PORT_DEVICE3, "cdrom", SCSICD, SCSI_ID_3)
|
||||
|
||||
MCFG_DEVICE_ADD(INTERPRO_SCSI_ADAPTER_TAG, NCR539X, XTAL_12_5MHz)
|
||||
MCFG_LEGACY_SCSI_PORT(INTERPRO_SCSI_TAG)
|
||||
|
||||
@ -9,6 +9,8 @@
|
||||
#include "cpu/clipper/clipper.h"
|
||||
#include "machine/cammu.h"
|
||||
|
||||
#include "machine/ram.h"
|
||||
|
||||
#include "machine/interpro_ioga.h"
|
||||
#include "machine/interpro_mcga.h"
|
||||
#include "machine/interpro_sga.h"
|
||||
@ -39,7 +41,11 @@
|
||||
|
||||
#define INTERPRO_RTC_TAG "rtc"
|
||||
#define INTERPRO_SCC1_TAG "scc1"
|
||||
#define INTERPRO_SERIAL1_TAG "serial1"
|
||||
#define INTERPRO_SERIAL2_TAG "serial2"
|
||||
#define INTERPRO_SCC2_TAG "scc2"
|
||||
#define INTERPRO_SERIAL3_TAG "serial3"
|
||||
#define INTERPRO_SERIAL4_TAG "serial4"
|
||||
#define INTERPRO_EPROM_TAG "eprom"
|
||||
#define INTERPRO_FLASH_TAG "flash"
|
||||
#define INTERPRO_TERMINAL_TAG "terminal"
|
||||
@ -52,36 +58,6 @@
|
||||
#define INTERPRO_SGA_TAG "sga"
|
||||
#define INTERPRO_SRARB_TAG "srarb"
|
||||
|
||||
// system board register offsets
|
||||
#define SREG_LED 0
|
||||
#define SREG_ERROR 0
|
||||
#define SREG_STATUS 1
|
||||
#define SREG_CTRL1 2
|
||||
#define SREG_CTRL2 3
|
||||
|
||||
// control register 1
|
||||
#define CTRL1_FLOPLOW 0x0001
|
||||
#define CTRL1_FLOPRDY 0x0002
|
||||
#define CTRL1_LEDENA 0x0004
|
||||
#define CTRL1_LEDDP 0x0008
|
||||
#define CTRL1_ETHLOOP 0x0010
|
||||
#define CTRL1_ETHDTR 0x0020
|
||||
#define CTRL1_ETHRMOD 0x0040
|
||||
#define CTRL1_CLIPRESET 0x0040
|
||||
#define CTRL1_FIFOACTIVE 0x0080
|
||||
|
||||
// control register 2
|
||||
#define CTRL2_PWRUP 0x0001
|
||||
#define CTRL2_PWRENA 0x0002
|
||||
#define CTRL2_HOLDOFF 0x0004
|
||||
#define CTRL2_EXTNMIENA 0x0008
|
||||
#define CTRL2_COLDSTART 0x0010
|
||||
#define CTRL2_RESET 0x0020
|
||||
#define CTRL2_BUSENA 0x0040
|
||||
#define CTRL2_FRCPARITY 0x0080
|
||||
#define CTRL2_FLASHEN 0x0080
|
||||
#define CTRL2_WMASK 0x000f
|
||||
|
||||
class interpro_state : public driver_device
|
||||
{
|
||||
public:
|
||||
@ -89,6 +65,7 @@ public:
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_maincpu(*this, INTERPRO_CPU_TAG),
|
||||
m_mmu(*this, INTERPRO_MMU_TAG),
|
||||
m_ram(*this, RAM_TAG),
|
||||
m_scc1(*this, INTERPRO_SCC1_TAG),
|
||||
m_scc2(*this, INTERPRO_SCC2_TAG),
|
||||
m_rtc(*this, INTERPRO_RTC_TAG),
|
||||
@ -108,6 +85,8 @@ public:
|
||||
required_device<clipper_device> m_maincpu;
|
||||
required_device<cammu_device> m_mmu;
|
||||
|
||||
required_device<ram_device> m_ram;
|
||||
|
||||
// FIXME: not sure which one is the escc
|
||||
required_device<z80scc_device> m_scc1;
|
||||
required_device<z80scc_device> m_scc2;
|
||||
@ -127,14 +106,73 @@ public:
|
||||
|
||||
DECLARE_DRIVER_INIT(ip2800);
|
||||
|
||||
DECLARE_WRITE16_MEMBER(system_w);
|
||||
DECLARE_READ16_MEMBER(system_r);
|
||||
enum sreg_error_mask
|
||||
{
|
||||
ERROR_BPID4 = 0x0001,
|
||||
ERROR_SRXMMBE = 0x0002,
|
||||
ERROR_SRXHOG = 0x0004,
|
||||
ERROR_SRXNEM = 0x0008,
|
||||
ERROR_SRXVALID = 0x0010,
|
||||
ERROR_CBUSNMI = 0x0020,
|
||||
ERROR_CBUSBG = 0x00c0,
|
||||
ERROR_BG = 0x0070,
|
||||
ERROR_BUSHOG = 0x0080
|
||||
};
|
||||
DECLARE_READ16_MEMBER(sreg_error_r);
|
||||
DECLARE_WRITE16_MEMBER(sreg_led_w) { m_sreg_led = data; }
|
||||
|
||||
enum sreg_status_mask
|
||||
{
|
||||
STATUS_YELLOW_ZONE = 0x0001,
|
||||
STATUS_SRNMI = 0x0002,
|
||||
STATUS_PWRLOSS = 0x0004,
|
||||
STATUS_RED_ZONE = 0x0008,
|
||||
STATUS_BP = 0x00f0
|
||||
};
|
||||
DECLARE_READ16_MEMBER(sreg_status_r) { return m_sreg_status; }
|
||||
|
||||
enum sreg_ctrl1_mask
|
||||
{
|
||||
CTRL1_FLOPLOW = 0x0001,
|
||||
CTRL1_FLOPRDY = 0x0002,
|
||||
CTRL1_LEDENA = 0x0004,
|
||||
CTRL1_LEDDP = 0x0008,
|
||||
CTRL1_ETHLOOP = 0x0010,
|
||||
CTRL1_ETHDTR = 0x0020,
|
||||
CTRL1_ETHRMOD = 0x0040,
|
||||
CTRL1_CLIPRESET = 0x0040,
|
||||
CTRL1_FIFOACTIVE = 0x0080
|
||||
};
|
||||
DECLARE_READ16_MEMBER(sreg_ctrl1_r) { return m_sreg_ctrl1; }
|
||||
DECLARE_WRITE16_MEMBER(sreg_ctrl1_w);
|
||||
|
||||
enum sreg_ctrl2_mask
|
||||
{
|
||||
CTRL2_PWRUP = 0x0001,
|
||||
CTRL2_PWRENA = 0x0002,
|
||||
CTRL2_HOLDOFF = 0x0004,
|
||||
CTRL2_EXTNMIENA = 0x0008,
|
||||
CTRL2_COLDSTART = 0x0010,
|
||||
CTRL2_RESET = 0x0020,
|
||||
CTRL2_BUSENA = 0x0040,
|
||||
CTRL2_FRCPARITY = 0x0080,
|
||||
CTRL2_FLASHEN = 0x0080,
|
||||
|
||||
CTRL2_WMASK = 0x000f
|
||||
};
|
||||
DECLARE_READ16_MEMBER(sreg_ctrl2_r) { return m_sreg_ctrl2; }
|
||||
DECLARE_WRITE16_MEMBER(sreg_ctrl2_w);
|
||||
DECLARE_READ16_MEMBER(sreg_ctrl3_r) { return m_sreg_ctrl3; }
|
||||
DECLARE_WRITE16_MEMBER(sreg_ctrl3_w) { m_sreg_ctrl3 = data; }
|
||||
|
||||
DECLARE_WRITE8_MEMBER(rtc_w);
|
||||
DECLARE_READ8_MEMBER(rtc_r);
|
||||
|
||||
DECLARE_READ32_MEMBER(idprom_r);
|
||||
DECLARE_READ32_MEMBER(slot0_r);
|
||||
DECLARE_READ8_MEMBER(idprom_r);
|
||||
DECLARE_READ8_MEMBER(slot0_r);
|
||||
|
||||
DECLARE_READ32_MEMBER(unmapped_r);
|
||||
DECLARE_WRITE32_MEMBER(unmapped_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(scsi_r);
|
||||
DECLARE_WRITE8_MEMBER(scsi_w);
|
||||
@ -148,7 +186,13 @@ protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
u16 m_system_reg[4];
|
||||
u16 m_sreg_error;
|
||||
u16 m_sreg_led;
|
||||
u16 m_sreg_status;
|
||||
u16 m_sreg_ctrl1;
|
||||
u16 m_sreg_ctrl2;
|
||||
|
||||
u16 m_sreg_ctrl3;
|
||||
};
|
||||
|
||||
#endif // MAME_INCLUDES_INTERPRO_H
|
||||
|
||||
Loading…
Reference in New Issue
Block a user