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https://github.com/holub/mame
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Merge branch 'master' of https://github.com/mamedev/mame.git
This commit is contained in:
Brad Hughes
commit
8c7bcae500
@ -1,6 +1,10 @@
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// license:BSD-3-Clause
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// copyright-holders:MetalliC
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// Communication board used by Sega in Model3, NAOMI and Hikaru, uses mostly same design
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// interface to main board LATTICE ICs: Model3 - 315-5958, Hikaru - 315-5958A, NAOMI - 315-6194A
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/*
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MODEL3 COMMUNICATION BOARD
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@ -71,15 +75,22 @@ SEGA 1998
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#define M68K_TAG "m3commcpu"
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//////// Model 3 (main CPU @ C00xxxxx) and Hikaru (MMctrl bank 0E) interface
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DEVICE_ADDRESS_MAP_START(m3_map, 32, m3comm_device)
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AM_RANGE(0x0000000, 0x000ffff) AM_READWRITE8(m3_comm_ram_r, m3_comm_ram_w, 0xffffffff)
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AM_RANGE(0x0010000, 0x00101ff) AM_READWRITE16(m3_ioregs_r, m3_ioregs_w, 0xffff0000)
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AM_RANGE(0x0020000, 0x003ffff) AM_READWRITE16(m3_m68k_ram_r, m3_m68k_ram_w, 0xffff0000)
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ADDRESS_MAP_END
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/*************************************
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* M3COMM Memory Map
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*************************************/
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static ADDRESS_MAP_START( m3comm_mem, AS_PROGRAM, 16, m3comm_device )
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AM_RANGE(0x0000000, 0x000ffff) AM_RAM AM_SHARE("m68k_ram")
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AM_RANGE(0x0080000, 0x008ffff) AM_RAMBANK("comm_ram")
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AM_RANGE(0x0040000, 0x0040001) AM_READWRITE(commbank_r, commbank_w)
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AM_RANGE(0x00C0088, 0x00C0089) AM_READWRITE(status0_r, status0_w)
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AM_RANGE(0x00C008A, 0x00C008B) AM_READWRITE(status1_r, status1_w)
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AM_RANGE(0x0080000, 0x008ffff) AM_RAMBANK("comm_ram")
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AM_RANGE(0x00C0000, 0x00C00ff) AM_READWRITE(ioregs_r, ioregs_w)
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ADDRESS_MAP_END
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@ -153,8 +164,8 @@ void m3comm_device::device_start()
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void m3comm_device::device_reset()
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{
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m_control = 0xC000;
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m_offset = 0;
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naomi_control = 0xC000;
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naomi_offset = 0;
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m_status0 = 0;
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m_status1 = 0;
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m_commbank = 0;
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@ -166,6 +177,14 @@ void m3comm_device::device_reset_after_children()
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m_commcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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}
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/////////////
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UINT16 swapb16(UINT16 data)
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{
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return (data >> 8) | (data >> 8);
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}
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///////////// Internal MMIO
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READ16_MEMBER(m3comm_device::commbank_r)
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{
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@ -176,43 +195,115 @@ WRITE16_MEMBER(m3comm_device::commbank_w)
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m_commbank = data;
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membank("comm_ram")->set_base(m_ram->pointer() + (m_commbank ? 0x10000 : 0));
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}
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READ16_MEMBER(m3comm_device::status0_r)
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READ16_MEMBER(m3comm_device::ioregs_r)
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{
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return m_status0;
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switch (offset) {
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case 0x88 / 2:
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return m_status0;
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case 0x8A / 2:
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return m_status1;
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default:
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logerror("M3COMM IOread from %02x mask %04x\n", offset * 2, mem_mask);
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return 0;
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}
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}
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WRITE16_MEMBER(m3comm_device::status0_w)
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WRITE16_MEMBER(m3comm_device::ioregs_w)
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{
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m_status0 = data;
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switch (offset) {
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case 0x16 / 2:
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if ((data & 0xFF) == 0x8C) {
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logerror("M3COMM Receive offs %04x size %04x\n", recv_offset, recv_size);
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}
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m_commcpu->set_input_line(M68K_IRQ_6, ((data & 0xFF) == 0x8C) ? ASSERT_LINE : CLEAR_LINE); // debug hack
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break;
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case 0x1C / 2:
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if ((data & 0xFF) == 0x8C) {
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logerror("M3COMM Send offs %04x size %04x\n", send_offset, send_size);
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}
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m_commcpu->set_input_line(M68K_IRQ_4, ((data & 0xFF) == 0x8C) ? ASSERT_LINE : CLEAR_LINE); // debug hack
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break;
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case 0x40 / 2:
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recv_offset = (recv_offset >> 8) | (data << 8);
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break;
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case 0x42 / 2:
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recv_size = (recv_size >> 8) | (data << 8);
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break;
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case 0x44 / 2:
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send_offset = (send_offset >> 8) | (data << 8);
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break;
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case 0x46 / 2:
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send_size = (send_size >> 8) | (data << 8);
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break;
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case 0x88 / 2:
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m_status0 = data;
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break;
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case 0x8A / 2:
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m_status1 = data;
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break;
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case 0xC0 / 2:
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m_commcpu->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE);
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break;
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default:
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logerror("M3COMM IOwrite to %02x %04x mask %04x\n", offset * 2, data, mem_mask);
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return;
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}
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}
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READ16_MEMBER(m3comm_device::status1_r)
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////////////// Model3 interface
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READ16_MEMBER(m3comm_device::m3_m68k_ram_r)
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{
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return m_status1;
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UINT16 value = m68k_ram[offset];
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return swapb16(value);
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}
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WRITE16_MEMBER(m3comm_device::status1_w)
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WRITE16_MEMBER(m3comm_device::m3_m68k_ram_w)
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{
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m_status1 = data;
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m68k_ram[offset] = swapb16(data);
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}
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READ8_MEMBER(m3comm_device::m3_comm_ram_r)
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{
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UINT8 *commram = (UINT8*)membank("comm_ram")->base();
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return commram[offset ^ 3];
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}
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WRITE8_MEMBER(m3comm_device::m3_comm_ram_w)
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{
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UINT8 *commram = (UINT8*)membank("comm_ram")->base();
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commram[offset ^ 3] = data;
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}
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READ16_MEMBER(m3comm_device::m3_ioregs_r)
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{
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UINT16 value = ioregs_r(space, offset, swapb16(mem_mask));
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return swapb16(value);
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}
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WRITE16_MEMBER(m3comm_device::m3_ioregs_w)
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{
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UINT16 value = swapb16(data);
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ioregs_w(space, offset, value, swapb16(mem_mask));
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}
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////////////// NAOMI inerface
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READ16_MEMBER(m3comm_device::naomi_r)
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{
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switch (offset)
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{
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case 0: // 5F7018
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return m_control;
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return naomi_control;
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case 1: // 5F701C
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return m_offset;
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return naomi_offset;
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case 2: // 5F7020
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{
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logerror("M3COMM read @ %08x\n", (m_control << 16) | m_offset);
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logerror("M3COMM read @ %08x\n", (naomi_control << 16) | naomi_offset);
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UINT16 value;
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if (m_control & 1)
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value = m68k_ram[m_offset / 2];
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if (naomi_control & 1)
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value = m68k_ram[naomi_offset / 2];
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else {
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UINT16 *commram = (UINT16*)membank("comm_ram")->base();
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value = commram[m_offset / 2];
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value = commram[naomi_offset / 2];
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}
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m_offset+= 2;
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naomi_offset+= 2;
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return value;
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}
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case 3: // 5F7024
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@ -223,28 +314,27 @@ READ16_MEMBER(m3comm_device::naomi_r)
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return 0;
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}
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}
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WRITE16_MEMBER(m3comm_device::naomi_w)
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{
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switch (offset)
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{
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case 0: // 5F7018
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logerror("M3COMM control write %04x\n", data);
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m_control = data;
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m_commcpu->set_input_line(INPUT_LINE_RESET, (m_control & 0x20) ? CLEAR_LINE : ASSERT_LINE);
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naomi_control = data;
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m_commcpu->set_input_line(INPUT_LINE_RESET, (naomi_control & 0x20) ? CLEAR_LINE : ASSERT_LINE);
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break;
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case 1: // 5F701C
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m_offset = data;
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naomi_offset = data;
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break;
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case 2: // 5F7020
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logerror("M3COMM write @ %08x %04x\n", (m_control << 16) | m_offset, data);
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if (m_control & 1)
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m68k_ram[m_offset / 2] = data;
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logerror("M3COMM write @ %08x %04x\n", (naomi_control << 16) | naomi_offset, data);
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if (naomi_control & 1)
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m68k_ram[naomi_offset / 2] = data;
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else {
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UINT16 *commram = (UINT16*)membank("comm_ram")->base();
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commram[m_offset / 2] = data;
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commram[naomi_offset / 2] = data;
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}
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m_offset += 2;
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naomi_offset += 2;
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break;
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case 3: // 5F7024
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m_status0 = data;
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@ -27,15 +27,24 @@ public:
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required_shared_ptr<UINT16> m68k_ram;
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required_device<m68000_device> m_commcpu;
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DECLARE_READ16_MEMBER(naomi_r);
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DECLARE_WRITE16_MEMBER(naomi_w);
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DECLARE_READ16_MEMBER(status0_r);
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DECLARE_WRITE16_MEMBER(status0_w);
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DECLARE_READ16_MEMBER(status1_r);
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DECLARE_WRITE16_MEMBER(status1_w);
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DECLARE_ADDRESS_MAP(m3_map, 32);
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DECLARE_READ16_MEMBER(commbank_r);
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DECLARE_WRITE16_MEMBER(commbank_w);
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DECLARE_READ16_MEMBER(ioregs_r);
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DECLARE_WRITE16_MEMBER(ioregs_w);
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DECLARE_READ16_MEMBER(m3_m68k_ram_r);
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DECLARE_WRITE16_MEMBER(m3_m68k_ram_w);
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DECLARE_READ8_MEMBER(m3_comm_ram_r);
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DECLARE_WRITE8_MEMBER(m3_comm_ram_w);
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DECLARE_READ16_MEMBER(m3_ioregs_r);
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DECLARE_WRITE16_MEMBER(m3_ioregs_w);
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DECLARE_READ16_MEMBER(naomi_r);
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DECLARE_WRITE16_MEMBER(naomi_w);
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protected:
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required_device<ram_device> m_ram;
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@ -45,12 +54,17 @@ protected:
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virtual void device_reset_after_children() override;
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private:
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UINT16 m_control;
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UINT16 m_offset;
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UINT16 naomi_control;
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UINT16 naomi_offset;
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UINT16 m_status0;
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UINT16 m_status1;
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UINT16 m_commbank;
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UINT16 recv_offset;
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UINT16 recv_size;
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UINT16 send_offset;
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UINT16 send_size;
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emu_file m_line_rx; // rx line - can be either differential, simple serial or toslink
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emu_file m_line_tx; // tx line - is differential, simple serial and toslink
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