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Rewrote IOX key matrix device implementation, used by Super Real Mahjong Part 2/3 [Angelo Salese]

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This commit is contained in:
Angelo Salese 2011-02-09 22:12:06 +00:00
parent 02529f5f88
commit 8d5cea7423
1 changed files with 323 additions and 31 deletions
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354
src/mame/drivers/srmp2.c
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@ -36,7 +36,7 @@ System specs :
Known issues :
===============
- I/O port isn't fully analized. Currently avoid I/O error message with hack.
- Update IOX handling in all games with the one hooked up in rmgoldyh and remove ROM patches.
- AY-3-8910 sound may be wrong.
- CPU clock of srmp3 does not match the real machine.
- MSM5205 clock frequency in srmp3 is wrong.
@ -549,6 +549,121 @@ static ADDRESS_MAP_START( srmp3_io_map, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_END
static ADDRESS_MAP_START( rmgoldyh_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x7fff) AM_ROM
AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("bank1") /* rom bank */
AM_RANGE(0xa000, 0xafff) AM_RAM AM_SHARE("nvram") /* work ram */
AM_RANGE(0xb000, 0xb303) AM_RAM AM_BASE_MEMBER(srmp2_state,spriteram1.u8) /* Sprites Y */
AM_RANGE(0xb800, 0xb800) AM_WRITENOP /* flag ? */
AM_RANGE(0xc000, 0xdfff) AM_RAM AM_BASE_MEMBER(srmp2_state,spriteram2.u8) /* Sprites Code + X + Attr */
AM_RANGE(0xe000, 0xffff) AM_RAM AM_BASE_MEMBER(srmp2_state,spriteram3.u8)
ADDRESS_MAP_END
static READ8_HANDLER( vox_status_r )
{
return 1;
}
static WRITE8_HANDLER( rmgoldyh_rombank_w )
{
/*
---x xxxx : MAIN ROM bank
xxx- ---- : ADPCM ROM bank
*/
srmp2_state *state = space->machine->driver_data<srmp2_state>();
UINT8 *ROM = space->machine->region("maincpu")->base();
int addr;
state->adpcm_bank = ((data & 0xe0) >> 5);
if (data & 0x1f) addr = ((0x10000 + (0x2000 * (data & 0x1f))) - 0x8000);
else addr = 0x10000;
memory_set_bankptr(space->machine, "bank1", &ROM[addr]);
}
static UINT8 iox_data,iox_mux,iox_ff;
static UINT8 iox_key_matrix_calc(running_machine *machine,UINT8 p_side)
{
static const char *const keynames[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4", "KEY5", "KEY6", "KEY7" };
int i, j, t;
for (i = 0x00 ; i < 0x20 ; i += 8)
{
j = (i / 0x08);
for (t = 0 ; t < 8 ; t ++)
{
if (!(input_port_read(machine, keynames[j+p_side]) & ( 1 << t )))
{
return (i + t) | (p_side ? 0x20 : 0x00);
}
}
}
return 0xff;
}
static READ8_HANDLER( iox_mux_r )
{
switch(iox_data)
{
case 0x43: return 0x9a;
case 0x45: return 0x00;
}
if(iox_ff == 0)
{
if(iox_mux != 2 && iox_mux != 4) //unknown command
return 0xff;
return iox_key_matrix_calc(space->machine,(iox_mux == 2) ? 0 : 4);
}
return input_port_read(space->machine,"SERVICE") & 0xff;
}
static READ8_HANDLER( iox_status_r )
{
return 1;
}
static WRITE8_HANDLER( iox_command_w )
{
iox_mux = data;
iox_ff = 0;
}
static WRITE8_HANDLER( iox_data_w )
{
iox_data = data;
if(data == 0xc8) //resets device
iox_ff = 0;
if(data == 0xff)
iox_ff ^= 1;
}
static ADDRESS_MAP_START( rmgoldyh_io_map, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_UNMAP_HIGH
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x00) AM_WRITENOP /* watchdog */
AM_RANGE(0x20, 0x20) AM_WRITENOP /* elapsed interrupt signal */
AM_RANGE(0x40, 0x40) AM_READ_PORT("SYSTEM") AM_WRITE(srmp3_flags_w) /* coin, service | GFX bank, counter, lockout */
AM_RANGE(0x60, 0x60) AM_WRITE(rmgoldyh_rombank_w) /* ROM bank select */
AM_RANGE(0x80, 0x80) AM_READ_PORT("DSW4")
AM_RANGE(0x81, 0x81) AM_READ_PORT("DSW3")
AM_RANGE(0xa0, 0xa0) AM_DEVWRITE("msm", srmp3_adpcm_code_w) /* ADPCM number */
AM_RANGE(0xa1, 0xa1) AM_READ(vox_status_r) /* vox status */
AM_RANGE(0xc0, 0xc0) AM_READWRITE(iox_mux_r, iox_command_w) /* key matrix | I/O */
AM_RANGE(0xc1, 0xc1) AM_READWRITE(iox_status_r,iox_data_w)
AM_RANGE(0xe0, 0xe1) AM_DEVWRITE("aysnd", ay8910_address_data_w)
AM_RANGE(0xe2, 0xe2) AM_DEVREAD("aysnd", ay8910_r)
ADDRESS_MAP_END
/***************************************************************************
Input Port(s)
@ -557,46 +672,90 @@ ADDRESS_MAP_END
static INPUT_PORTS_START( seta_mjctrl )
PORT_START("KEY0") /* KEY MATRIX INPUT (3) */
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL )
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_BIG )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE )
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_PLAYER(1)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(1)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(1)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(1)
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(1)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_PLAYER(1)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(1)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("KEY1") /* KEY MATRIX INPUT (4) */
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_K )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_RON )
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_G )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_CHI )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_C )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_L )
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(1)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(1)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(1)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) PORT_PLAYER(1)
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(1)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_PLAYER(1)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(1)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("KEY2") /* KEY MATRIX INPUT (5) */
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_H )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_PON )
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_D )
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(1)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_PON ) PORT_PLAYER(1)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(1)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_I )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_MAHJONG_KAN )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_E )
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_MAHJONG_M )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(1)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(1)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(1)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_MAHJONG_M ) PORT_PLAYER(1)
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("KEY3") /* KEY MATRIX INPUT (6) */
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_A )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_BET )
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_J )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_REACH )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_F )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_MAHJONG_N )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_B )
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(1)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(1)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(1)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(1)
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(1)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_MAHJONG_N ) PORT_PLAYER(1)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(1)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("KEY4") /* KEY MATRIX INPUT (3) */
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_SMALL ) PORT_PLAYER(2)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_DOUBLE_UP ) PORT_PLAYER(2)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_BIG ) PORT_PLAYER(2)
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_SCORE ) PORT_PLAYER(2)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_MAHJONG_FLIP_FLOP ) PORT_PLAYER(2)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_LAST_CHANCE ) PORT_PLAYER(2)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("KEY5") /* KEY MATRIX INPUT (4) */
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_K ) PORT_PLAYER(2)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_RON ) PORT_PLAYER(2)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_G ) PORT_PLAYER(2)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_CHI ) PORT_PLAYER(2)
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_C ) PORT_PLAYER(2)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_L ) PORT_PLAYER(2)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("KEY6") /* KEY MATRIX INPUT (5) */
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_H ) PORT_PLAYER(2)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_PON ) PORT_PLAYER(2)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_D ) PORT_PLAYER(2)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_START2 )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_I ) PORT_PLAYER(2)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_MAHJONG_KAN ) PORT_PLAYER(2)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_E ) PORT_PLAYER(2)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_MAHJONG_M ) PORT_PLAYER(2)
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("KEY7") /* KEY MATRIX INPUT (6) */
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_MAHJONG_A ) PORT_PLAYER(2)
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_MAHJONG_BET ) PORT_PLAYER(2)
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_MAHJONG_J ) PORT_PLAYER(2)
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_MAHJONG_REACH ) PORT_PLAYER(2)
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_MAHJONG_F ) PORT_PLAYER(2)
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_MAHJONG_N ) PORT_PLAYER(2)
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_MAHJONG_B ) PORT_PLAYER(2)
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END
@ -750,6 +909,136 @@ static INPUT_PORTS_START( srmp3 )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END
static INPUT_PORTS_START( rmgoldyh )
PORT_START("SYSTEM")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("SERVICE")
PORT_DIPNAME( 0x01, 0x01, "SERVICE" )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("Memory Clear")
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Test Mode")
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_SERVICE3 ) PORT_NAME("Analyzer")
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_INCLUDE( seta_mjctrl )
PORT_START("DSW1")
PORT_DIPNAME( 0x01, 0x01, "DSWC" )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW2")
PORT_DIPNAME( 0x01, 0x01, "DSWC" )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW3")
PORT_DIPNAME( 0x01, 0x01, "DSWC" )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_START("DSW4")
PORT_DIPNAME( 0x01, 0x01, "DSWC" )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
INPUT_PORTS_END
static INPUT_PORTS_START( mjyuugi )
PORT_START("SYSTEM") /* Coinage (0) */
@ -1102,8 +1391,11 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( rmgoldyh, srmp3 )
MCFG_GFXDECODE(rmgoldyh)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(rmgoldyh_map)
MCFG_CPU_IO_MAP(rmgoldyh_io_map)
MCFG_GFXDECODE(rmgoldyh)
MACHINE_CONFIG_END
static MACHINE_CONFIG_START( mjyuugi, srmp2_state )
@ -1416,7 +1708,7 @@ ROM_END
GAME( 1987, srmp1, 0, srmp2, srmp2, 0, ROT0, "Seta", "Super Real Mahjong Part 1 (Japan)", 0 )
GAME( 1987, srmp2, 0, srmp2, srmp2, srmp2, ROT0, "Seta", "Super Real Mahjong Part 2 (Japan)", 0 )
GAME( 1988, srmp3, 0, srmp3, srmp3, srmp3, ROT0, "Seta", "Super Real Mahjong Part 3 (Japan)", 0 )
GAME( 1988, rmgoldyh, srmp3, rmgoldyh, srmp3, 0, ROT0, "Seta / Alba", "Real Mahjong Gold Yumehai (Japan)", GAME_NOT_WORKING )
GAME( 1988, rmgoldyh, srmp3, rmgoldyh, rmgoldyh, 0, ROT0, "Seta / Alba", "Real Mahjong Gold Yumehai (Japan)", GAME_NOT_WORKING )
GAME( 1990, mjyuugi, 0, mjyuugi, mjyuugi, 0, ROT0, "Visco", "Mahjong Yuugi (Japan set 1)", 0 )
GAME( 1990, mjyuugia, mjyuugi, mjyuugi, mjyuugi, 0, ROT0, "Visco", "Mahjong Yuugi (Japan set 2)", 0 )
GAME( 1991, ponchin, 0, mjyuugi, ponchin, 0, ROT0, "Visco", "Mahjong Pon Chin Kan (Japan set 1)", 0 )