mirror of
https://github.com/holub/mame
synced 2025-04-20 23:42:22 +03:00
more pedantic fixes (NW)
This commit is contained in:
Cowering
parent
1a32c4b760
commit
8db46d73a2
@ -221,7 +221,7 @@ void a2bus_corvfdc02_device::write_c0nx(address_space &space, UINT8 offset, UINT
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break;
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}
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logerror("corvfdc02: selecting drive %d: %p\n", data & 3, floppy);
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logerror("corvfdc02: selecting drive %d: %p\n", data & 3, (void *) floppy);
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if (floppy != m_curfloppy)
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{
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@ -116,7 +116,7 @@ private:
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UINT8 m_fakemem;
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enum {
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TIMER_CR,
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TIMER_CR
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};
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};
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@ -879,7 +879,7 @@ UINT8 grip_device::ecbbus_io_r(offs_t offset)
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}
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return data;
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};
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}
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//-------------------------------------------------
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@ -38,7 +38,7 @@ public:
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enum {
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MODE_16M_64k = 0, /// 16Mbit ROM, 64kBit RAM
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MODE_4M_256k = 1, /// 4Mbit ROM, 256kBit RAM
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MODE_4M_256k = 1 /// 4Mbit ROM, 256kBit RAM
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};
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// construction/destruction
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@ -44,7 +44,7 @@ enum
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PC_IRQ_TIMERA,
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PC_IRQ_TIMERB,
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PC_IRQ_RXRDY,
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PC_IRQ_TXRDY,
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PC_IRQ_TXRDY
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};
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enum
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@ -53,7 +53,7 @@ enum
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Z80_IRQ_RXRDY,
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Z80_IRQ_TXRDY,
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Z80_IRQ_MIDI_RXRDY,
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Z80_IRQ_MIDI_TXRDY,
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Z80_IRQ_MIDI_TXRDY
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};
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@ -140,7 +140,7 @@ enum {
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OMTI_STATE_SELECTION,
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OMTI_STATE_COMMAND,
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OMTI_STATE_DATA,
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OMTI_STATE_STATUS,
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OMTI_STATE_STATUS
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};
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// OMTI commands
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@ -1285,7 +1285,7 @@ omti_disk_image_device::omti_disk_image_device(const machine_config &mconfig, co
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void omti_disk_image_device::device_config_complete()
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{
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update_names(OMTI_DISK, "disk", "disk");
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};
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}
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/***************************************************************************
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@ -1287,7 +1287,7 @@ sc499_ctape_image_device::sc499_ctape_image_device(const machine_config &mconfig
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void sc499_ctape_image_device::device_config_complete()
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{
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update_names(SC499_CTAPE, "ctape", "ct");
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};
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}
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UINT8 *sc499_ctape_image_device::read_block(int block_num)
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@ -77,7 +77,7 @@ messimg_disk_image_device::messimg_disk_image_device(const machine_config &mconf
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void messimg_disk_image_device::device_config_complete()
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{
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update_names(MESSIMG_DISK, "disk", "disk");
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};
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}
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/*-------------------------------------------------
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@ -97,7 +97,7 @@ void nubus_radiustpd_device::device_start()
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slotspace = get_slotspace();
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printf("[radiustpd %p] slotspace = %x\n", this, slotspace);
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printf("[radiustpd %p] slotspace = %x\n", (void *)this, slotspace);
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m_vram.resize(VRAM_SIZE);
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m_vram32 = (UINT32 *)&m_vram[0];
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@ -100,7 +100,7 @@ void nubus_wsportrait_device::device_start()
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slotspace = get_slotspace();
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printf("[wsportrait %p] slotspace = %x\n", this, slotspace);
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printf("[wsportrait %p] slotspace = %x\n", (void *)this, slotspace);
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m_vram.resize(VRAM_SIZE);
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m_vram32 = (UINT32 *)&m_vram[0];
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@ -39,7 +39,7 @@ protected:
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enum
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{
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QUERY_PAD_STATE = 0x42,
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CONFIG_MODE = 0x43,
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CONFIG_MODE = 0x43
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};
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private:
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@ -450,7 +450,7 @@ peribox_gen_device::peribox_gen_device(const machine_config &mconfig, const char
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// a maximum address space of 512 KiB in the box. With the Genmod
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// modification, the full 2 MiB space is available.
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m_address_prefix = 0x00000;
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};
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}
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// The BwG controller will not run with the Geneve due to its wait state
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// logic; it assumes that before reading 5FF6 (data register), address 5FF7
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@ -501,7 +501,7 @@ peribox_998_device::peribox_998_device(const machine_config &mconfig, const char
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: peribox_device(mconfig, PERIBOX_998, "Peripheral expansion box 99/8", tag, owner, clock, "peribox_998", __FILE__)
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{
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m_address_prefix = 0x70000;
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};
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}
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// The BwG controller will not run with the TI-99/8 for the same reason why
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// it won't work with the Geneve.
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@ -540,7 +540,7 @@ peribox_sg_device::peribox_sg_device(const machine_config &mconfig, const char *
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: peribox_device(mconfig, PERIBOX_SG, "Peripheral expansion box SGCPU", tag, owner, clock, "peribox_sg", __FILE__)
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{
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m_address_prefix = 0x70000;
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};
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}
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SLOT_INTERFACE_START( peribox_slotp )
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SLOT_INTERFACE("pcode", TI99_P_CODE)
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@ -581,7 +581,7 @@ peribox_ev_device::peribox_ev_device(const machine_config &mconfig, const char *
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: peribox_device(mconfig, PERIBOX_EV, "Peripheral expansion box EVPC", tag, owner, clock, "peribox_ev", __FILE__)
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{
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m_address_prefix = 0x70000;
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};
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}
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MACHINE_CONFIG_FRAGMENT( peribox_ev_device )
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MCFG_PERIBOX_SLOT_ADD_DEF( PEBSLOT2, peribox_ev_slot, "evpc" )
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@ -332,11 +332,11 @@ WRITE8_MEMBER( wangpc_wdc_device::status_w )
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}
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READ8_MEMBER( wangpc_wdc_device::ctc_ch0_r ) { return m_ctc->read(space, 0); };
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WRITE8_MEMBER( wangpc_wdc_device::ctc_ch0_w ) { m_ctc->write(space, 0, data); };
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READ8_MEMBER( wangpc_wdc_device::ctc_ch1_r ) { return m_ctc->read(space, 1); };
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WRITE8_MEMBER( wangpc_wdc_device::ctc_ch1_w ) { m_ctc->write(space, 1, data); };
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READ8_MEMBER( wangpc_wdc_device::ctc_ch2_r ) { return m_ctc->read(space, 2); };
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WRITE8_MEMBER( wangpc_wdc_device::ctc_ch2_w ) { m_ctc->write(space, 2, data); };
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READ8_MEMBER( wangpc_wdc_device::ctc_ch3_r ) { return m_ctc->read(space, 3); };
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WRITE8_MEMBER( wangpc_wdc_device::ctc_ch3_w ) { m_ctc->write(space, 3, data); };
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READ8_MEMBER( wangpc_wdc_device::ctc_ch0_r ) { return m_ctc->read(space, 0); }
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WRITE8_MEMBER( wangpc_wdc_device::ctc_ch0_w ) { m_ctc->write(space, 0, data); }
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READ8_MEMBER( wangpc_wdc_device::ctc_ch1_r ) { return m_ctc->read(space, 1); }
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WRITE8_MEMBER( wangpc_wdc_device::ctc_ch1_w ) { m_ctc->write(space, 1, data); }
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READ8_MEMBER( wangpc_wdc_device::ctc_ch2_r ) { return m_ctc->read(space, 2); }
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WRITE8_MEMBER( wangpc_wdc_device::ctc_ch2_w ) { m_ctc->write(space, 2, data); }
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READ8_MEMBER( wangpc_wdc_device::ctc_ch3_r ) { return m_ctc->read(space, 3); }
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WRITE8_MEMBER( wangpc_wdc_device::ctc_ch3_w ) { m_ctc->write(space, 3, data); }
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@ -22,7 +22,7 @@
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#define ARCOMPACT_OPERATION ((op & 0xf800) >> 11)
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extern char *output;;
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extern char *output;
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CPU_DISASSEMBLE(arcompact)
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{
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@ -38,7 +38,7 @@ enum
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OP_REG8_,
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OP_REGIM8,
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OP_RMSIM3,
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OP_RSIR,
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OP_RSIR
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};
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struct hd61700_dasm
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@ -85,7 +85,7 @@ enum Ins
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OFF, // clears bf flip flop
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RDP, SDP,// reset display flip flop
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RPU, SPU,// flip flop pu off
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RPV, SPV,// flip flop pv off
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RPV, SPV // flip flop pv off
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};
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static const char *const InsNames[]={
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@ -25,7 +25,7 @@ enum
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EA_IND_Y_IMM8_REL,
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PAGE2,
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PAGE3,
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PAGE4,
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PAGE4
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};
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struct M68HC11_OPCODE {
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@ -34,7 +34,7 @@ enum
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FEATURE_CMOS = 0x02,
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FEATURE_I80C52 = 0x04,
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FEATURE_DS5002FP = 0x08,
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FEATURE_I83C751 = 0x08,
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FEATURE_I83C751 = 0x08
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};
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@ -80,7 +80,7 @@ enum
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F_FRT_FRA_FRC, // frT, frA, frC
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F_RA_RT_SH_MB_ME, // rA, rT, SH, MB, ME
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F_RLWNMx, // rT, rA, rB, MB, ME only used by RLWNMx
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F_RT_RB, // rT, rB
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F_RT_RB // rT, rB
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};
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/*
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@ -27,7 +27,7 @@ enum e_mnemonics
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z5A, z5B,
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/* more complicated instructions */
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z1A, z1B, z4F,
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z1A, z1B, z4F
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};
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/* instructions not found:
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@ -86,7 +86,7 @@ enum e_addrmodes {
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AM_R=1, AM_rr, AM_r1, AM_S, AM_rmb, AM_mbr, AM_Ri, AM_rmw, AM_mwr, AM_smw, AM_mws,
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AM_Sw, AM_iR, AM_rbr, AM_riw, AM_cjp, AM_rib, AM_pi, AM_cbr, AM_i, AM_ii,
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AM_ss, AM_RR, AM_2, AM_SS, AM_bR, AM_Rbr, AM_Rb, AM_rR, AM_Rr, AM_Rii, AM_RiR,
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AM_riB, AM_iS, AM_CALS, AM_bid, AM_1A, AM_1B, AM_4F,
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AM_riB, AM_iS, AM_CALS, AM_bid, AM_1A, AM_1B, AM_4F
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};
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static const sm8500dasm mnemonic[256] = {
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@ -86,7 +86,7 @@ enum e_operand
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O_M8, /* (8) */
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O_M16, /* (i16) */
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O_R, /* register */
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O_SR, /* status register */
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O_SR /* status register */
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};
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@ -98,14 +98,14 @@ private:
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{
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STATE_MASK = 0x00ff,
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SUB_SHIFT = 8,
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SUB_MASK = 0xff00,
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SUB_MASK = 0xff00
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};
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enum
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{
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MODE_I,
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MODE_T,
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MODE_D,
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MODE_D
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};
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enum scsi_state
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@ -131,7 +131,7 @@ private:
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SEND_WAIT_SETTLE,
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RECV_WAIT_SETTLE,
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RECV_WAIT_REQ_0,
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RECV_WAIT_REQ_1,
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RECV_WAIT_REQ_1
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};
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void update_irqs();
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@ -148,7 +148,7 @@ private:
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SCRIPTS_IDLE,
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SCRIPTS_WAIT_MANUAL_START,
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SCRIPTS_FETCH,
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SCRIPTS_EXECUTE,
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SCRIPTS_EXECUTE
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};
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void set_scripts_state(scripts_state state);
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@ -258,7 +258,7 @@ WRITE8_MEMBER( acia6850_device::data_w )
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/// TODO: find out if data stored during master reset is sent after divider is set
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if (m_divide == 0)
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{
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logerror("%s:ACIA %p: Data write while in reset!\n", machine().describe_context(), this);
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logerror("%s:ACIA %p: Data write while in reset!\n", machine().describe_context(), (void *)this);
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}
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/// TODO: find out what happens if TDRE is already clear when you write
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@ -28,7 +28,7 @@ public:
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IRQ_A_TX,
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IRQ_B_TX,
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IRQ_A_EXT,
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IRQ_B_EXT,
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IRQ_B_EXT
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};
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mpcc68561_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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@ -26,7 +26,7 @@ public:
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IRQ_A_TX,
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IRQ_B_TX,
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IRQ_A_EXT,
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IRQ_B_EXT,
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IRQ_B_EXT
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};
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scc8530_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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@ -120,7 +120,7 @@ eeprom_parallel_##_lowercase##_device::eeprom_parallel_##_lowercase##_device(con
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: eeprom_parallel_##_baseclass##_device(mconfig, EEPROM_PARALLEL_##_uppercase, "Parallel EEPROM " #_uppercase " (" #_cells "x" #_bits ")", tag, owner, #_lowercase, __FILE__) \
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{ \
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static_set_size(*this, _cells, _bits); \
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}; \
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} \
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const device_type EEPROM_PARALLEL_##_uppercase = &device_creator<eeprom_parallel_##_lowercase##_device>;
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// standard 28XX class of 8-bit EEPROMs
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DEFINE_PARALLEL_EEPROM_DEVICE(28xx, 2804, 2804, 8, 512)
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@ -1132,7 +1132,7 @@ eeprom_serial_##_lowercase##_##_bits##bit_device::eeprom_serial_##_lowercase##_#
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{ \
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static_set_size(*this, _cells, _bits); \
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static_set_address_bits(*this, _addrbits); \
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}; \
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} \
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const device_type EEPROM_SERIAL_##_uppercase##_##_bits##BIT = &device_creator<eeprom_serial_##_lowercase##_##_bits##bit_device>;
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// standard 93CX6 class of 16-bit EEPROMs
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DEFINE_SERIAL_EEPROM_DEVICE(93cxx, 93c06, 93C06, 16, 16, 6)
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@ -46,7 +46,7 @@ enum
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REG_DAY_OF_THE_WEEK_ALARM,
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REG_DAY_ALARM,
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REG_CRA,
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REG_CRB,
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REG_CRB
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};
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@ -44,7 +44,7 @@ enum
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enum
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{
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MODE_OUTPUT = 0,
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MODE_INPUT,
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MODE_INPUT
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};
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@ -53,7 +53,7 @@ enum
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STATE_S2,
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STATE_S3,
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STATE_SW,
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STATE_S4,
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STATE_S4
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};
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@ -107,7 +107,7 @@ protected:
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enum
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{
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TID_NULL = TID_BUSY + 1,
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TID_NULL = TID_BUSY + 1
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};
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private:
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@ -56,7 +56,7 @@ protected:
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TYPE_INS8250A,
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TYPE_NS16450,
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TYPE_NS16550,
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TYPE_NS16550A,
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TYPE_NS16550A
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};
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int m_device_type;
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struct {
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@ -113,7 +113,7 @@ private:
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REG_B_UIE = 16,
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REG_B_AIE = 32,
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REG_B_PIE = 64,
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REG_B_SET = 128,
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REG_B_SET = 128
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};
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enum
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@ -174,7 +174,7 @@ void mc68681_device::update_interrupts()
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write_irq(CLEAR_LINE);
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m_read_vector = false; // clear IACK too
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}
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};
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}
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double mc68681_device::duart68681_get_ct_rate()
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{
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@ -286,7 +286,7 @@ TIMER_CALLBACK_MEMBER( mc68681_device::duart_timer_callback )
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duart68681_start_ct(0xffff);
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}
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};
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}
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READ8_MEMBER( mc68681_device::read )
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{
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@ -630,7 +630,7 @@ int mc68681_device::calc_baud(int ch, UINT8 data)
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}
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return baud_rate;
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};
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}
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void mc68681_device::clear_ISR_bits(int mask)
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{
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@ -901,7 +901,7 @@ UINT8 mc68681_channel::read_rx_fifo()
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// printf("Rx read %02x\n", rv);
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return rv;
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};
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}
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UINT8 mc68681_channel::read_chan_reg(int reg)
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{
|
||||
@ -976,7 +976,7 @@ void mc68681_channel::write_MR(UINT8 data)
|
||||
}
|
||||
recalc_framing();
|
||||
update_interrupts();
|
||||
};
|
||||
}
|
||||
|
||||
void mc68681_channel::recalc_framing()
|
||||
{
|
||||
@ -1114,7 +1114,7 @@ void mc68681_channel::write_CR(UINT8 data)
|
||||
}
|
||||
|
||||
update_interrupts();
|
||||
};
|
||||
}
|
||||
|
||||
void mc68681_channel::write_TX(UINT8 data)
|
||||
{
|
||||
@ -1139,7 +1139,7 @@ void mc68681_channel::write_TX(UINT8 data)
|
||||
transmit_register_setup(tx_data);
|
||||
|
||||
update_interrupts();
|
||||
};
|
||||
}
|
||||
|
||||
void mc68681_channel::ACR_updated()
|
||||
{
|
||||
|
||||
@ -275,63 +275,61 @@ inline void mcf5206e_peripheral_device::CSCR_w(int which, int offset, UINT16 dat
|
||||
|
||||
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR0_r) { return CSAR_r(0, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR0_w) { CSAR_w(0, offset, data, mem_mask); }
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR0_r) { return CSMR_r(0, mem_mask); }
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR0_w) { CSMR_w(0, data, mem_mask); }
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR0_r) { return CSCR_r(0, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR0_w) { CSCR_w(0, offset, data, mem_mask); }
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR1_r) { return CSAR_r(1, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR1_w) { CSAR_w(1, offset, data, mem_mask); }
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR1_r) { return CSMR_r(1, mem_mask); }
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR1_w) { CSMR_w(1, data, mem_mask); }
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR1_r) { return CSCR_r(1, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR1_w) { CSCR_w(1, offset, data, mem_mask); }
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR0_r) { return CSAR_r(0, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR0_w) { CSAR_w(0, offset, data, mem_mask); };
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR0_r) { return CSMR_r(0, mem_mask); };
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR0_w) { CSMR_w(0, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR0_r) { return CSCR_r(0, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR0_w) { CSCR_w(0, offset, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR2_r) { return CSAR_r(2, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR2_w) { CSAR_w(2, offset, data, mem_mask); }
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR2_r) { return CSMR_r(2, mem_mask); }
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR2_w) { CSMR_w(2, data, mem_mask); }
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR2_r) { return CSCR_r(2, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR2_w) { CSCR_w(2, offset, data, mem_mask); }
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR1_r) { return CSAR_r(1, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR1_w) { CSAR_w(1, offset, data, mem_mask); };
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR1_r) { return CSMR_r(1, mem_mask); };
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR1_w) { CSMR_w(1, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR1_r) { return CSCR_r(1, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR1_w) { CSCR_w(1, offset, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR3_r) { return CSAR_r(3, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR3_w) { CSAR_w(3, offset, data, mem_mask); }
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR3_r) { return CSMR_r(3, mem_mask); }
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR3_w) { CSMR_w(3, data, mem_mask); }
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR3_r) { return CSCR_r(3, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR3_w) { CSCR_w(3, offset, data, mem_mask); }
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR2_r) { return CSAR_r(2, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR2_w) { CSAR_w(2, offset, data, mem_mask); };
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR2_r) { return CSMR_r(2, mem_mask); };
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR2_w) { CSMR_w(2, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR2_r) { return CSCR_r(2, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR2_w) { CSCR_w(2, offset, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR4_r) { return CSAR_r(4, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR4_w) { CSAR_w(4, offset, data, mem_mask); }
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR4_r) { return CSMR_r(4, mem_mask); }
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR4_w) { CSMR_w(4, data, mem_mask); }
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR4_r) { return CSCR_r(4, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR4_w) { CSCR_w(4, offset, data, mem_mask); }
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR3_r) { return CSAR_r(3, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR3_w) { CSAR_w(3, offset, data, mem_mask); };
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR3_r) { return CSMR_r(3, mem_mask); };
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR3_w) { CSMR_w(3, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR3_r) { return CSCR_r(3, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR3_w) { CSCR_w(3, offset, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR5_r) { return CSAR_r(5, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR5_w) { CSAR_w(5, offset, data, mem_mask); }
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR5_r) { return CSMR_r(5, mem_mask); }
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR5_w) { CSMR_w(5, data, mem_mask); }
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR5_r) { return CSCR_r(5, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR5_w) { CSCR_w(5, offset, data, mem_mask); }
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR4_r) { return CSAR_r(4, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR4_w) { CSAR_w(4, offset, data, mem_mask); };
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR4_r) { return CSMR_r(4, mem_mask); };
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR4_w) { CSMR_w(4, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR4_r) { return CSCR_r(4, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR4_w) { CSCR_w(4, offset, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR6_r) { return CSAR_r(6, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR6_w) { CSAR_w(6, offset, data, mem_mask); }
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR6_r) { return CSMR_r(6, mem_mask); }
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR6_w) { CSMR_w(6, data, mem_mask); }
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR6_r) { return CSCR_r(6, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR6_w) { CSCR_w(6, offset, data, mem_mask); }
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR5_r) { return CSAR_r(5, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR5_w) { CSAR_w(5, offset, data, mem_mask); };
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR5_r) { return CSMR_r(5, mem_mask); };
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR5_w) { CSMR_w(5, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR5_r) { return CSCR_r(5, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR5_w) { CSCR_w(5, offset, data, mem_mask); };
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR6_r) { return CSAR_r(6, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR6_w) { CSAR_w(6, offset, data, mem_mask); };
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR6_r) { return CSMR_r(6, mem_mask); };
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR6_w) { CSMR_w(6, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR6_r) { return CSCR_r(6, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR6_w) { CSCR_w(6, offset, data, mem_mask); };
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR7_r) { return CSAR_r(7, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR7_w) { CSAR_w(7, offset, data, mem_mask); };
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR7_r) { return CSMR_r(7, mem_mask); };
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR7_w) { CSMR_w(7, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR7_r) { return CSCR_r(7, offset, mem_mask); };
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR7_w) { CSCR_w(7, offset, data, mem_mask); };
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSAR7_r) { return CSAR_r(7, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSAR7_w) { CSAR_w(7, offset, data, mem_mask); }
|
||||
READ32_MEMBER( mcf5206e_peripheral_device::CSMR7_r) { return CSMR_r(7, mem_mask); }
|
||||
WRITE32_MEMBER( mcf5206e_peripheral_device::CSMR7_w) { CSMR_w(7, data, mem_mask); }
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::CSCR7_r) { return CSCR_r(7, offset, mem_mask); }
|
||||
WRITE16_MEMBER( mcf5206e_peripheral_device::CSCR7_w) { CSCR_w(7, offset, data, mem_mask); }
|
||||
|
||||
|
||||
READ16_MEMBER( mcf5206e_peripheral_device::DMCR_r)
|
||||
|
||||
@ -268,7 +268,7 @@ void microtouch_device::rcv_complete()
|
||||
m_tx_buffer[m_tx_buffer_num++] = 0x0d;
|
||||
m_rx_buffer_ptr = 0;
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER( microtouch_device::touch )
|
||||
{
|
||||
|
||||
@ -147,7 +147,7 @@ attotime mm58274c_device::interrupt_period_table(int val)
|
||||
case 7: return attotime::from_seconds(60);
|
||||
default: fatalerror("out of range\n");
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
READ8_MEMBER( mm58274c_device::read )
|
||||
{
|
||||
|
||||
@ -115,7 +115,7 @@ private:
|
||||
INIT_XFR_WAIT_REQ,
|
||||
INIT_CPT_RECV_BYTE_ACK,
|
||||
INIT_CPT_RECV_WAIT_REQ,
|
||||
INIT_CPT_RECV_BYTE_NACK,
|
||||
INIT_CPT_RECV_BYTE_NACK
|
||||
};
|
||||
|
||||
enum {
|
||||
@ -134,13 +134,13 @@ private:
|
||||
SEND_WAIT_REQ_0,
|
||||
RECV_WAIT_REQ_1,
|
||||
RECV_WAIT_SETTLE,
|
||||
RECV_WAIT_REQ_0,
|
||||
RECV_WAIT_REQ_0
|
||||
};
|
||||
|
||||
enum {
|
||||
STATE_MASK = 0x00ff,
|
||||
SUB_SHIFT = 8,
|
||||
SUB_MASK = 0xff00,
|
||||
SUB_MASK = 0xff00
|
||||
};
|
||||
|
||||
enum { BUS_BUSY, BUS_FREE_WAIT, BUS_FREE };
|
||||
@ -182,7 +182,7 @@ private:
|
||||
MODE_EOPIRQ = 0x08,
|
||||
MODE_BSYIRQ = 0x04,
|
||||
MODE_DMA = 0x02,
|
||||
MODE_ARBITRATE = 0x01,
|
||||
MODE_ARBITRATE = 0x01
|
||||
};
|
||||
|
||||
enum { DMA_NONE, DMA_IN, DMA_OUT };
|
||||
|
||||
@ -107,7 +107,7 @@ private:
|
||||
INIT_XFR_WAIT_REQ,
|
||||
INIT_CPT_RECV_BYTE_ACK,
|
||||
INIT_CPT_RECV_WAIT_REQ,
|
||||
INIT_CPT_RECV_BYTE_NACK,
|
||||
INIT_CPT_RECV_BYTE_NACK
|
||||
};
|
||||
|
||||
enum {
|
||||
@ -126,13 +126,13 @@ private:
|
||||
SEND_WAIT_REQ_0,
|
||||
RECV_WAIT_REQ_1,
|
||||
RECV_WAIT_SETTLE,
|
||||
RECV_WAIT_REQ_0,
|
||||
RECV_WAIT_REQ_0
|
||||
};
|
||||
|
||||
enum {
|
||||
STATE_MASK = 0x00ff,
|
||||
SUB_SHIFT = 8,
|
||||
SUB_MASK = 0xff00,
|
||||
SUB_MASK = 0xff00
|
||||
};
|
||||
|
||||
enum { BUS_BUSY, BUS_FREE_WAIT, BUS_FREE };
|
||||
@ -177,7 +177,7 @@ private:
|
||||
CI_COMPLETE = 0x11,
|
||||
CI_MSG_ACCEPT = 0x12,
|
||||
CI_PAD = 0x18,
|
||||
CI_SET_ATN = 0x1a,
|
||||
CI_SET_ATN = 0x1a
|
||||
};
|
||||
|
||||
enum { DMA_NONE, DMA_IN, DMA_OUT };
|
||||
|
||||
@ -35,7 +35,7 @@ enum
|
||||
EWDS = 0, // erase/write disable
|
||||
WRAL, // write all registers
|
||||
ERAL, // erase all registers
|
||||
EWEN, // erase/write enable
|
||||
EWEN // erase/write enable
|
||||
};
|
||||
|
||||
// states
|
||||
|
||||
@ -83,7 +83,7 @@ public:
|
||||
S_PHASE_STATUS = S_CTL|S_INP,
|
||||
S_PHASE_MSG_OUT = S_MSG|S_CTL,
|
||||
S_PHASE_MSG_IN = S_MSG|S_CTL|S_INP,
|
||||
S_PHASE_MASK = S_MSG|S_CTL|S_INP,
|
||||
S_PHASE_MASK = S_MSG|S_CTL|S_INP
|
||||
};
|
||||
|
||||
nscsi_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
|
||||
@ -117,7 +117,7 @@ protected:
|
||||
SS_INT_CONDITION_MET = 0x14,
|
||||
SS_RESV_CONFLICT = 0x18,
|
||||
SS_TERMINATED = 0x22,
|
||||
SS_QUEUE_FULL = 0x28,
|
||||
SS_QUEUE_FULL = 0x28
|
||||
};
|
||||
|
||||
// SCSI commands
|
||||
@ -238,7 +238,7 @@ protected:
|
||||
SC_PLAY_CD = 0xbc,
|
||||
SC_MECHANISM_STATUS = 0xbd,
|
||||
SC_READ_CD = 0xbe,
|
||||
SC_SEND_DVD_STRUCTURE = 0xbf,
|
||||
SC_SEND_DVD_STRUCTURE = 0xbf
|
||||
};
|
||||
|
||||
// SCSI Messages
|
||||
@ -264,12 +264,12 @@ protected:
|
||||
SM_SIMPLE_QUEUE = 0x20,
|
||||
SM_HEAD_QUEUE = 0x21,
|
||||
SM_ORDERED_QUEUE = 0x22,
|
||||
SM_IGNORE_WIDE_RES = 0x23,
|
||||
SM_IGNORE_WIDE_RES = 0x23
|
||||
};
|
||||
|
||||
enum {
|
||||
SBUF_MAIN,
|
||||
SBUF_SENSE,
|
||||
SBUF_SENSE
|
||||
};
|
||||
|
||||
UINT8 scsi_cmdbuf[4096], scsi_sense_buffer[8];
|
||||
@ -359,7 +359,7 @@ protected:
|
||||
|
||||
private:
|
||||
enum {
|
||||
IDLE,
|
||||
IDLE
|
||||
};
|
||||
|
||||
enum {
|
||||
@ -370,20 +370,20 @@ private:
|
||||
TARGET_WAIT_MSG_BYTE,
|
||||
TARGET_WAIT_CMD_BYTE,
|
||||
TARGET_WAIT_DATA_IN_BYTE,
|
||||
TARGET_WAIT_DATA_OUT_BYTE,
|
||||
TARGET_WAIT_DATA_OUT_BYTE
|
||||
};
|
||||
|
||||
enum {
|
||||
RECV_BYTE_T_WAIT_ACK_0 = 1,
|
||||
RECV_BYTE_T_WAIT_ACK_1,
|
||||
SEND_BYTE_T_WAIT_ACK_0,
|
||||
SEND_BYTE_T_WAIT_ACK_1,
|
||||
SEND_BYTE_T_WAIT_ACK_1
|
||||
};
|
||||
|
||||
enum {
|
||||
STATE_MASK = 0x00ff,
|
||||
SUB_SHIFT = 8,
|
||||
SUB_MASK = 0xff00,
|
||||
SUB_MASK = 0xff00
|
||||
};
|
||||
|
||||
enum {
|
||||
@ -393,7 +393,7 @@ private:
|
||||
BC_MESSAGE_2,
|
||||
BC_DATA_IN,
|
||||
BC_DATA_OUT,
|
||||
BC_BUS_FREE,
|
||||
BC_BUS_FREE
|
||||
};
|
||||
|
||||
struct control {
|
||||
|
||||
@ -724,7 +724,7 @@ void pit8253_device::update(pit8253_timer *timer)
|
||||
attotime elapsed_time = now - timer->last_updated;
|
||||
INT64 elapsed_cycles = elapsed_time.as_double() * timer->clockin;
|
||||
|
||||
LOG1(("pit8253: update(): timer %d, %" I64FMT "d elapsed_cycles\n", timer->index, elapsed_cycles));
|
||||
LOG1(("pit8253: update(): timer %d, %s elapsed_cycles\n", timer->index, I64_to_base10(elapsed_cycles)));
|
||||
|
||||
if (timer->clockin)
|
||||
timer->last_updated += elapsed_cycles * attotime::from_hz(timer->clockin);
|
||||
@ -1091,7 +1091,7 @@ void pit8253_device::set_clockin(int timerno, double new_clockin)
|
||||
pit8253_timer *timer = get_timer(timerno);
|
||||
assert(timer != NULL);
|
||||
|
||||
LOG2(("pit8253_set_clockin(): PIT timer=%d, clockin = %lf\n", timerno, new_clockin));
|
||||
LOG2(("pit8253_set_clockin(): PIT timer=%d, clockin = %f\n", timerno, new_clockin));
|
||||
|
||||
update(timer);
|
||||
timer->clockin = new_clockin;
|
||||
|
||||
@ -34,7 +34,7 @@ enum rtc9701_state_t
|
||||
RTC9701_RTC_WRITE,
|
||||
RTC9701_EEPROM_READ,
|
||||
RTC9701_EEPROM_WRITE,
|
||||
RTC9701_AFTER_WRITE_ENABLE,
|
||||
RTC9701_AFTER_WRITE_ENABLE
|
||||
|
||||
};
|
||||
|
||||
|
||||
@ -35,7 +35,7 @@ protected:
|
||||
T10MMC_CMD_PAUSE_RESUME = 0x4b,
|
||||
T10MMC_CMD_STOP_PLAY_SCAN = 0x4e,
|
||||
T10MMC_CMD_PLAY_AUDIO_12 = 0xa5,
|
||||
T10MMC_CMD_SET_CD_SPEED = 0xbb,
|
||||
T10MMC_CMD_SET_CD_SPEED = 0xbb
|
||||
};
|
||||
|
||||
enum toc_format_t
|
||||
|
||||
@ -335,7 +335,7 @@ void tms9902_device::set_receive_data_rate()
|
||||
// Thus the callback function should add up this value on each poll
|
||||
// and deliver a data input not before it sums up to 1.
|
||||
m_baudpoll = (double)(baud / (10*POLLING_FREQ));
|
||||
if (VERBOSE>3) LOG ("TMS9902: baudpoll = %lf\n", m_baudpoll);
|
||||
if (VERBOSE>3) LOG ("TMS9902: baudpoll = %f\n", m_baudpoll);
|
||||
|
||||
m_last_config_value = value;
|
||||
m_ctrl_cb((offs_t)CONFIG, RATERECV);
|
||||
|
||||
@ -52,7 +52,7 @@ private:
|
||||
CONFIG_BCR2 = 1,
|
||||
CONFIG_CR = 2,
|
||||
CONFIG_RR = 3,
|
||||
CONFIG_RC = 4,
|
||||
CONFIG_RC = 4
|
||||
};
|
||||
|
||||
enum bcr_t
|
||||
|
||||
@ -1100,7 +1100,7 @@ void pokey_device::pokey_potgo(void)
|
||||
{
|
||||
int pot;
|
||||
|
||||
LOG(("POKEY #%p pokey_potgo\n", this));
|
||||
LOG(("POKEY #%p pokey_potgo\n", (void *) this));
|
||||
|
||||
m_ALLPOT = 0x00;
|
||||
m_pot_counter = 0;
|
||||
|
||||
@ -176,7 +176,7 @@ enum
|
||||
{
|
||||
NON_INTERLACED = 0,
|
||||
ENHANCED_VIDEO_INTERFACE,
|
||||
NORMAL_VIDEO_INTERFACE,
|
||||
NORMAL_VIDEO_INTERFACE
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -69,15 +69,14 @@ protected:
|
||||
enum
|
||||
{
|
||||
CHARSET_HD44780_A00,
|
||||
CHARSET_KS0066_F05,
|
||||
/*
|
||||
CHARSET_KS0066_F05 /*,
|
||||
CHARSET_HD44780_A01,
|
||||
CHARSET_HD44780_A02,
|
||||
CHARSET_KS0066_F00,
|
||||
CHARSET_KS0066_F03,
|
||||
CHARSET_KS0066_F04,
|
||||
CHARSET_KS0066_F06,
|
||||
CHARSET_KS0066_F59,
|
||||
CHARSET_KS0066_F59
|
||||
*/
|
||||
};
|
||||
|
||||
|
||||
@ -1479,7 +1479,7 @@ PALETTE_INIT_MEMBER(mos8563_device, mos8563)
|
||||
palette.set_pen_color(13, rgb_t(0xff, 0xff, 0x55));
|
||||
palette.set_pen_color(14, rgb_t(0xaa, 0xaa, 0xaa));
|
||||
palette.set_pen_color(15, rgb_t::white);
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
void mos8563_device::update_cursor_state()
|
||||
|
||||
@ -172,7 +172,7 @@ protected:
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
private:
|
||||
struct entry
|
||||
@ -370,7 +370,7 @@ protected:
|
||||
result = true;
|
||||
}
|
||||
return result;
|
||||
};
|
||||
}
|
||||
|
||||
// template function for emitting graphics bytes
|
||||
template<int bits_per_pixel, int xscale>
|
||||
|
||||
@ -39,7 +39,7 @@ public:
|
||||
}
|
||||
|
||||
DECLARE_READ32_MEMBER(decathlt_prot1_r);
|
||||
DECLARE_READ32_MEMBER(decathlt_prot2_r);;
|
||||
DECLARE_READ32_MEMBER(decathlt_prot2_r);
|
||||
UINT32 genericdecathlt_prot_r(UINT32 mem_mask, int channel);
|
||||
|
||||
void write_prot_data(UINT32 data, UINT32 mem_mask, int channel, int rev_words);
|
||||
|
||||
@ -218,7 +218,7 @@ private:
|
||||
{
|
||||
TID_SCANLINE_INT,
|
||||
TID_TILEROW_UPDATE,
|
||||
TID_EOF,
|
||||
TID_EOF
|
||||
};
|
||||
|
||||
// internal helpers
|
||||
|
||||
@ -542,7 +542,7 @@ void cdicdic_device::sample_trigger()
|
||||
|
||||
if(m_decode_addr == 0xffff)
|
||||
{
|
||||
verboselog(machine(), 0, "Decode stop requested, stopping playback\n" );
|
||||
verboselog(machine(), 0, "%s", "Decode stop requested, stopping playback\n" );
|
||||
m_audio_sample_timer->adjust(attotime::never);
|
||||
return;
|
||||
}
|
||||
@ -550,11 +550,11 @@ void cdicdic_device::sample_trigger()
|
||||
if(!m_decode_delay)
|
||||
{
|
||||
// Indicate that data has been decoded
|
||||
verboselog(machine(), 0, "Flagging that audio data has been decoded\n" );
|
||||
verboselog(machine(), 0, "%s", "Flagging that audio data has been decoded\n" );
|
||||
m_audio_buffer |= 0x8000;
|
||||
|
||||
// Set the CDIC interrupt line
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for soundmap decode\n" );
|
||||
verboselog(machine(), 0, "%s", "Setting CDIC interrupt line for soundmap decode\n" );
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
}
|
||||
@ -576,7 +576,7 @@ void cdicdic_device::sample_trigger()
|
||||
verboselog(machine(), 0, "Updated m_decode_addr, new value is %04x\n", m_decode_addr );
|
||||
|
||||
//// Delay for Frequency * (18*28*2*size in bytes) before requesting more data
|
||||
verboselog(machine(), 0, "Data is valid, setting up a new callback\n" );
|
||||
verboselog(machine(), 0, "%s", "Data is valid, setting up a new callback\n" );
|
||||
m_decode_period = attotime::from_hz(CDIC_SAMPLE_BUF_FREQ(m_ram, m_decode_addr & 0x3ffe)) * (18*28*2*CDIC_SAMPLE_BUF_SIZE(m_ram, m_decode_addr & 0x3ffe));
|
||||
m_audio_sample_timer->adjust(m_decode_period);
|
||||
//dmadac_enable(&dmadac[0], 2, 0);
|
||||
@ -586,7 +586,7 @@ void cdicdic_device::sample_trigger()
|
||||
// Swap buffer positions to indicate our new buffer position at the next read
|
||||
m_decode_addr ^= 0x1a00;
|
||||
|
||||
verboselog(machine(), 0, "Data is not valid, indicating to shut down on the next audio sample\n" );
|
||||
verboselog(machine(), 0, "%s", "Data is not valid, indicating to shut down on the next audio sample\n" );
|
||||
m_decode_addr = 0xffff;
|
||||
m_audio_sample_timer->adjust(m_decode_period);
|
||||
}
|
||||
@ -695,7 +695,7 @@ void cdicdic_device::process_delayed_command()
|
||||
if(((buffer[CDIC_SECTOR_SUBMODE2] & (CDIC_SUBMODE_FORM | CDIC_SUBMODE_DATA | CDIC_SUBMODE_AUDIO | CDIC_SUBMODE_VIDEO)) == (CDIC_SUBMODE_FORM | CDIC_SUBMODE_AUDIO)) &&
|
||||
(m_channel & m_audio_channel & (1 << buffer[CDIC_SECTOR_CHAN2])))
|
||||
{
|
||||
verboselog(machine(), 0, "Audio sector\n" );
|
||||
verboselog(machine(), 0, "%s", "Audio sector\n" );
|
||||
|
||||
m_x_buffer |= 0x8000;
|
||||
//m_data_buffer |= 0x4000;
|
||||
@ -709,7 +709,7 @@ void cdicdic_device::process_delayed_command()
|
||||
decode_audio_sector(((UINT8*)m_ram) + ((m_data_buffer & 5) * 0xa00 + 4), 0);
|
||||
|
||||
//printf( "Setting CDIC interrupt line\n" );
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for audio sector\n" );
|
||||
verboselog(machine(), 0, "%s", "Setting CDIC interrupt line for audio sector\n" );
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
}
|
||||
@ -728,13 +728,13 @@ void cdicdic_device::process_delayed_command()
|
||||
(buffer[CDIC_SECTOR_SUBMODE2] & CDIC_SUBMODE_EOF) == CDIC_SUBMODE_EOF)
|
||||
{
|
||||
//printf( "Setting CDIC interrupt line\n" );
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for message sector\n" );
|
||||
verboselog(machine(), 0, "%s", "Setting CDIC interrupt line for message sector\n" );
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
}
|
||||
else
|
||||
{
|
||||
verboselog(machine(), 0, "Message sector, ignored\n" );
|
||||
verboselog(machine(), 0, "%s", "Message sector, ignored\n" );
|
||||
}
|
||||
}
|
||||
else
|
||||
@ -748,7 +748,7 @@ void cdicdic_device::process_delayed_command()
|
||||
}
|
||||
|
||||
//printf( "Setting CDIC interrupt line\n" );
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for data sector\n" );
|
||||
verboselog(machine(), 0, "%s", "Setting CDIC interrupt line for data sector\n" );
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
}
|
||||
@ -843,7 +843,7 @@ void cdicdic_device::process_delayed_command()
|
||||
m_ram[(m_data_buffer & 5) * (0xa00/2) + (index - 6)] = (buffer[index*2] << 8) | buffer[index*2 + 1];
|
||||
}
|
||||
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for CDDA sector\n" );
|
||||
verboselog(machine(), 0, "%s", "Setting CDIC interrupt line for CDDA sector\n" );
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
break;
|
||||
@ -894,7 +894,7 @@ void cdicdic_device::process_delayed_command()
|
||||
|
||||
m_time = next_msf << 8;
|
||||
|
||||
verboselog(machine(), 0, "Setting CDIC interrupt line for Seek sector\n" );
|
||||
verboselog(machine(), 0, "%s", "Setting CDIC interrupt line for Seek sector\n" );
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_4, 128);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, ASSERT_LINE);
|
||||
break;
|
||||
@ -944,7 +944,7 @@ READ16_MEMBER( cdicdic_device::regs_r )
|
||||
if(!((m_audio_buffer | m_x_buffer) & 0x8000))
|
||||
{
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
|
||||
verboselog(machine(), 0, "Clearing CDIC interrupt line\n" );
|
||||
verboselog(machine(), 0, "%s", "Clearing CDIC interrupt line\n" );
|
||||
////printf("Clearing CDIC interrupt line\n" );
|
||||
}
|
||||
verboselog(machine(), 0, "cdic_r: Audio Buffer Register = %04x & %04x\n", temp, mem_mask);
|
||||
@ -958,7 +958,7 @@ READ16_MEMBER( cdicdic_device::regs_r )
|
||||
if(!((m_audio_buffer | m_x_buffer) & 0x8000))
|
||||
{
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
|
||||
verboselog(machine(), 0, "Clearing CDIC interrupt line\n" );
|
||||
verboselog(machine(), 0, "%s", "Clearing CDIC interrupt line\n" );
|
||||
////printf("Clearing CDIC interrupt line\n" );
|
||||
}
|
||||
verboselog(machine(), 0, "cdic_r: X-Buffer Register = %04x & %04x\n", temp, mem_mask);
|
||||
|
||||
@ -56,7 +56,7 @@ TIMER_CALLBACK_MEMBER( cdislave_device::trigger_readback_int )
|
||||
{
|
||||
cdi_state *state = machine().driver_data<cdi_state>();
|
||||
|
||||
verboselog(machine(), 0, "Asserting IRQ2\n" );
|
||||
verboselog(machine(), 0, "%s", "Asserting IRQ2\n" );
|
||||
state->m_maincpu->set_input_line_vector(M68K_IRQ_2, 26);
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_2, ASSERT_LINE);
|
||||
m_interrupt_timer->adjust(attotime::never);
|
||||
@ -140,7 +140,7 @@ READ16_MEMBER( cdislave_device::slave_r )
|
||||
case 0xf3:
|
||||
case 0xf4:
|
||||
case 0xf7:
|
||||
verboselog(machine(), 0, "slave_r: De-asserting IRQ2\n" );
|
||||
verboselog(machine(), 0, "%s", "slave_r: De-asserting IRQ2\n" );
|
||||
state->m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -126,7 +126,7 @@ private:
|
||||
// timer IDs
|
||||
enum
|
||||
{
|
||||
TID_FORCE_UPDATE,
|
||||
TID_FORCE_UPDATE
|
||||
};
|
||||
|
||||
// internal helpers
|
||||
|
||||
@ -819,7 +819,7 @@ void mcd212_device::process_vsr(int channel, UINT8 *pixels_r, UINT8 *pixels_g, U
|
||||
if(m_channel[channel].dcr & MCD212_DCR_CM)
|
||||
{
|
||||
// 4-bit Bitmap
|
||||
verboselog(machine, 0, "Unsupported display mode: 4-bit Bitmap\n" );
|
||||
verboselog(machine, 0, "%s", "Unsupported display mode: 4-bit Bitmap\n" );
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -1000,7 +1000,7 @@ void mcd212_device::process_vsr(int channel, UINT8 *pixels_r, UINT8 *pixels_g, U
|
||||
case MCD212_DDR_FT_RLE:
|
||||
if(m_channel[channel].dcr & MCD212_DCR_CM)
|
||||
{
|
||||
verboselog(machine, 0, "Unsupported display mode: 4-bit RLE\n" );
|
||||
verboselog(machine, 0, "%s", "Unsupported display mode: 4-bit RLE\n" );
|
||||
done = 1;
|
||||
}
|
||||
else
|
||||
@ -1427,7 +1427,7 @@ TIMER_CALLBACK_MEMBER( mcd212_device::perform_scan )
|
||||
if(scanline == 0)
|
||||
{
|
||||
// Process ICA
|
||||
verboselog(machine, 6, "Frame Start\n" );
|
||||
verboselog(machine, 6, "%s", "Frame Start\n" );
|
||||
m_channel[0].csrr &= 0x7f;
|
||||
for(int index = 0; index < 2; index++)
|
||||
{
|
||||
|
||||
@ -30,7 +30,7 @@ enum {
|
||||
A_ZR,
|
||||
A_Z,
|
||||
A_AUDIO,
|
||||
A_Y,
|
||||
A_Y
|
||||
};
|
||||
|
||||
/*********************************************************************
|
||||
|
||||
@ -35,7 +35,7 @@ enum mea8000_state
|
||||
MEA8000_STOPPED, /* nothing to do, timer disabled */
|
||||
MEA8000_WAIT_FIRST, /* received pitch, wait for first full trame, timer disabled */
|
||||
MEA8000_STARTED, /* playing a frame, timer on */
|
||||
MEA8000_SLOWING, /* repating last frame with decreasing amplitude, timer on */
|
||||
MEA8000_SLOWING /* repeating last frame with decreasing amplitude, timer on */
|
||||
};
|
||||
|
||||
ALLOW_SAVE_TYPE( mea8000_state );
|
||||
|
||||
@ -269,7 +269,7 @@ READ8_MEMBER( abc80_state::pio_pa_r )
|
||||
data |= (m_key_strobe << 7);
|
||||
|
||||
return data;
|
||||
};
|
||||
}
|
||||
|
||||
READ8_MEMBER( abc80_state::pio_pb_r )
|
||||
{
|
||||
@ -305,7 +305,7 @@ READ8_MEMBER( abc80_state::pio_pb_r )
|
||||
if (LOG) logerror("%s %s read tape latch %u\n", machine().time().as_string(), machine().describe_context(), m_tape_in_latch);
|
||||
|
||||
return data;
|
||||
};
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( abc80_state::pio_pb_w )
|
||||
{
|
||||
@ -356,7 +356,7 @@ WRITE8_MEMBER( abc80_state::pio_pb_w )
|
||||
|
||||
m_pio->pb7_w(m_tape_in_latch);
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
|
||||
@ -599,7 +599,7 @@ READ8_MEMBER( ace_state::pio_pa_r )
|
||||
*/
|
||||
|
||||
return 0;
|
||||
};
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( ace_state::pio_pa_w )
|
||||
{
|
||||
@ -620,7 +620,7 @@ WRITE8_MEMBER( ace_state::pio_pa_w )
|
||||
|
||||
// centronics strobe
|
||||
m_centronics->write_strobe(!BIT(data, 6));
|
||||
};
|
||||
}
|
||||
|
||||
//**************************************************************************
|
||||
// MACHINE INITIALIZATION
|
||||
|
||||
@ -54,7 +54,7 @@ class alphatro_state : public driver_device
|
||||
public:
|
||||
enum
|
||||
{
|
||||
TIMER_SYSTEM,
|
||||
TIMER_SYSTEM
|
||||
};
|
||||
|
||||
alphatro_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
|
||||
@ -200,7 +200,7 @@ WRITE8_MEMBER( chessmst_state::pio1_port_b_w )
|
||||
m_led_sel = (m_led_sel & 0xff) | ((data & 0x03)<<8);
|
||||
|
||||
m_speaker->level_w(BIT(data, 6));
|
||||
};
|
||||
}
|
||||
|
||||
READ8_MEMBER( chessmst_state::pio2_port_a_r )
|
||||
{
|
||||
|
||||
@ -349,7 +349,7 @@ WRITE_LINE_MEMBER(dectalk_state::dectalk_duart_irq_handler)
|
||||
m_maincpu->set_input_line_and_vector(M68K_IRQ_6, state, M68K_INT_ACK_AUTOVECTOR);
|
||||
//drvstate->m_maincpu->set_input_line_and_vector(M68K_IRQ_6, CLEAR_LINE, M68K_INT_ACK_AUTOVECTOR);
|
||||
//drvstate->m_maincpu->set_input_line_and_vector(M68K_IRQ_6, HOLD_LINE, vector);
|
||||
};
|
||||
}
|
||||
|
||||
READ8_MEMBER(dectalk_state::dectalk_duart_input)
|
||||
{
|
||||
|
||||
@ -537,7 +537,7 @@ ADDRESS_MAP_END
|
||||
WRITE_LINE_MEMBER(esq1_state::duart_irq_handler)
|
||||
{
|
||||
m_maincpu->set_input_line(M6809_IRQ_LINE, state);
|
||||
};
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(esq1_state::duart_output)
|
||||
{
|
||||
|
||||
@ -181,7 +181,7 @@ READ16_MEMBER(esqkt_state::esq5506_read_adc)
|
||||
WRITE_LINE_MEMBER(esqkt_state::duart_irq_handler)
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_IRQ_3, state);
|
||||
};
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(esqkt_state::duart_output)
|
||||
{
|
||||
|
||||
@ -665,12 +665,12 @@ WRITE8_MEMBER( fidelz80_state::fidelz80_portb_w )
|
||||
}
|
||||
|
||||
// ignoring the language switch enable for now, is bit 0x40
|
||||
};
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( fidelz80_state::fidelz80_portc_w )
|
||||
{
|
||||
m_kp_matrix = data;
|
||||
};
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( fidelz80_state::cc10_porta_w )
|
||||
{
|
||||
|
||||
@ -234,7 +234,7 @@ SNAPSHOT_LOAD_MEMBER( nascom_state, nascom1 )
|
||||
|
||||
while (image.fread( &line, sizeof(line)) == sizeof(line))
|
||||
{
|
||||
int addr, b0, b1, b2, b3, b4, b5, b6, b7, dummy;
|
||||
unsigned int addr, b0, b1, b2, b3, b4, b5, b6, b7, dummy;
|
||||
|
||||
if (sscanf((char *)line, "%x %x %x %x %x %x %x %x %x %x\010\010\n",
|
||||
&addr, &b0, &b1, &b2, &b3, &b4, &b5, &b6, &b7, &dummy) == 10)
|
||||
|
||||
@ -118,7 +118,7 @@ enum flash_state
|
||||
F_AUTO_PROGRAM, /* 5555 AA 2AAA 55 5555 A0 address data */
|
||||
F_AUTO_CHIP_ERASE, /* 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 */
|
||||
F_AUTO_BLOCK_ERASE, /* 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 block_address 30 */
|
||||
F_BLOCK_PROTECT, /* 5555 AA 2AAA 55 5555 9A 5555 AA 2AAA 55 5555 9A */
|
||||
F_BLOCK_PROTECT /* 5555 AA 2AAA 55 5555 9A 5555 AA 2AAA 55 5555 9A */
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -52,7 +52,7 @@ enum
|
||||
GAH40M_CTLR1 = 0,
|
||||
GAH40M_CMDR,
|
||||
GAH40M_CTLR2,
|
||||
GAH40M_IER = 4,
|
||||
GAH40M_IER = 4
|
||||
};
|
||||
|
||||
enum
|
||||
|
||||
@ -193,7 +193,7 @@ WRITE8_MEMBER( sc2_state::pio_port_b_w )
|
||||
}
|
||||
else
|
||||
m_kp_matrix = data;
|
||||
};
|
||||
}
|
||||
|
||||
static MACHINE_CONFIG_START( sc2, sc2_state )
|
||||
/* basic machine hardware */
|
||||
|
||||
@ -403,12 +403,12 @@ ADDRESS_MAP_END
|
||||
WRITE_LINE_MEMBER(sgi_ip2_state::duarta_irq_handler)
|
||||
{
|
||||
m_maincpu->set_input_line_and_vector(M68K_IRQ_6, state, M68K_INT_ACK_AUTOVECTOR);
|
||||
};
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(sgi_ip2_state::duartb_irq_handler)
|
||||
{
|
||||
m_maincpu->set_input_line_and_vector(M68K_IRQ_6, state, M68K_INT_ACK_AUTOVECTOR);
|
||||
};
|
||||
}
|
||||
|
||||
static DEVICE_INPUT_DEFAULTS_START( ip2_terminal )
|
||||
DEVICE_INPUT_DEFAULTS( "RS232_TXBAUD", 0xff, RS232_BAUD_19200 )
|
||||
|
||||
@ -181,7 +181,7 @@ enum
|
||||
SPG243_BATMAN,
|
||||
SPG243_VSMILE,
|
||||
|
||||
SPG243_MODEL_COUNT,
|
||||
SPG243_MODEL_COUNT
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -244,7 +244,7 @@ READ8_MEMBER( xerox820_state::kbpio_pa_r )
|
||||
data |= m_400_460 << 5;
|
||||
|
||||
return data;
|
||||
};
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( xerox820_state::kbpio_pa_w )
|
||||
{
|
||||
@ -327,7 +327,7 @@ READ8_MEMBER( xerox820_state::kbpio_pb_r )
|
||||
*/
|
||||
|
||||
return m_kb->read() ^ 0xff;
|
||||
};
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( xerox820ii_state::rdpio_pb_w )
|
||||
{
|
||||
|
||||
@ -188,7 +188,7 @@ private:
|
||||
HIRES_RIGHT = 0x01,
|
||||
HIRES_RIGHT_COCOMAX3 = 0x02,
|
||||
HIRES_LEFT = 0x03,
|
||||
HIRES_LEFT_COCOMAX3 = 0x04,
|
||||
HIRES_LEFT_COCOMAX3 = 0x04
|
||||
};
|
||||
|
||||
struct analog_input_t
|
||||
|
||||
@ -16,7 +16,7 @@ typedef enum {
|
||||
HP48_G,
|
||||
HP48_GX,
|
||||
HP48_GP,
|
||||
HP49_G,
|
||||
HP49_G
|
||||
} hp48_models;
|
||||
|
||||
/* memory module configuration */
|
||||
|
||||
@ -2162,7 +2162,7 @@ MAC_DRIVER_INIT(macpd210, MODEL_MAC_PBDUO_210)
|
||||
MAC_DRIVER_INIT(macquadra700, MODEL_MAC_QUADRA_700)
|
||||
MAC_DRIVER_INIT(maciicx, MODEL_MAC_IICX)
|
||||
MAC_DRIVER_INIT(maciifdhd, MODEL_MAC_II_FDHD)
|
||||
MAC_DRIVER_INIT(maciix, MODEL_MAC_IIX);
|
||||
MAC_DRIVER_INIT(maciix, MODEL_MAC_IIX)
|
||||
MAC_DRIVER_INIT(maclc520, MODEL_MAC_LC_520)
|
||||
|
||||
void mac_state::nubus_slot_interrupt(UINT8 slot, UINT32 state)
|
||||
|
||||
@ -352,7 +352,8 @@ static void mbc55x_debug(running_machine &machine, int ref, int params, const ch
|
||||
mbc55x_state *state = machine.driver_data<mbc55x_state>();
|
||||
if(params>0)
|
||||
{
|
||||
sscanf(param[0],"%d",&state->m_debug_machine);
|
||||
int temp;
|
||||
sscanf(param[0],"%d",&temp); state->m_debug_machine = temp;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
@ -53,7 +53,7 @@ WRITE8_MEMBER( mbee_state::pio_port_b_w )
|
||||
|
||||
m_cassette->output(BIT(data, 1) ? -1.0 : +1.0);
|
||||
m_speaker->level_w(BIT(data, 6));
|
||||
};
|
||||
}
|
||||
|
||||
READ8_MEMBER( mbee_state::pio_port_b_r )
|
||||
{
|
||||
|
||||
@ -244,7 +244,8 @@ static void nimbus_debug(running_machine &machine, int ref, int params, const ch
|
||||
rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
|
||||
if(params>0)
|
||||
{
|
||||
sscanf(param[0],"%d",&state->m_debug_machine);
|
||||
int temp;
|
||||
sscanf(param[0],"%d",&temp); state->m_debug_machine = temp;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
@ -2066,7 +2066,7 @@ rpk::rpk(emu_options& options, const char* sysname)
|
||||
//,m_system_name(sysname)
|
||||
{
|
||||
m_sockets.reset();
|
||||
};
|
||||
}
|
||||
|
||||
rpk::~rpk()
|
||||
{
|
||||
@ -2126,12 +2126,12 @@ void rpk::close()
|
||||
rpk_socket::rpk_socket(const char* id, int length, UINT8* contents, const char *pathname)
|
||||
: m_id(id), m_length(length), m_next(NULL), m_contents(contents), m_pathname(pathname)
|
||||
{
|
||||
};
|
||||
}
|
||||
|
||||
rpk_socket::rpk_socket(const char* id, int length, UINT8* contents)
|
||||
: m_id(id), m_length(length), m_next(NULL), m_contents(contents), m_pathname(NULL)
|
||||
{
|
||||
};
|
||||
}
|
||||
|
||||
/*
|
||||
Locate a file in the ZIP container
|
||||
@ -2234,7 +2234,7 @@ rpk_socket* rpk_reader::load_ram_resource(emu_options &options, xml_data_node* r
|
||||
const char* ram_type;
|
||||
const char* ram_filename;
|
||||
const char* ram_pname;
|
||||
int length;
|
||||
unsigned int length;
|
||||
UINT8* contents;
|
||||
|
||||
// find the length attribute
|
||||
|
||||
@ -79,7 +79,7 @@ enum
|
||||
|
||||
REG_RXD = 0xe0, // UART receive data register
|
||||
REG_RXE = 0xe1, // UART extended receiver data
|
||||
REG_UIT = 0xe5, // UART interrupt status
|
||||
REG_UIT = 0xe5 // UART interrupt status
|
||||
};
|
||||
|
||||
//mode
|
||||
|
||||
@ -183,7 +183,7 @@ private:
|
||||
MODE_SER2 = 0x08,
|
||||
MODE_MDV = 0x10,
|
||||
MODE_NET = 0x18,
|
||||
MODE_MASK = 0x18,
|
||||
MODE_MASK = 0x18
|
||||
};
|
||||
|
||||
enum
|
||||
@ -192,7 +192,7 @@ private:
|
||||
INT_INTERFACE = 0x02,
|
||||
INT_TRANSMIT = 0x04,
|
||||
INT_FRAME = 0x08,
|
||||
INT_EXTERNAL = 0x10,
|
||||
INT_EXTERNAL = 0x10
|
||||
};
|
||||
|
||||
enum
|
||||
@ -200,7 +200,7 @@ private:
|
||||
STATUS_NETWORK_PORT = 0x01,
|
||||
STATUS_TX_BUFFER_FULL = 0x02,
|
||||
STATUS_RX_BUFFER_FULL = 0x04,
|
||||
STATUS_MICRODRIVE_GAP = 0x08,
|
||||
STATUS_MICRODRIVE_GAP = 0x08
|
||||
};
|
||||
|
||||
int m_rtc_clock; // the RTC clock (pin 30) of the chip
|
||||
|
||||
@ -1875,7 +1875,7 @@ void apollo_graphics_15i::device_reset()
|
||||
= auto_alloc_array(machine(), UINT16, m_image_memory_size);
|
||||
assert(m_image_memory != NULL);
|
||||
|
||||
MLOG1(("device reset apollo graphics: buffer=%p size=%0x", m_image_memory, m_image_memory_size));
|
||||
MLOG1(("device reset apollo graphics: buffer=%p size=%0x", (void *) m_image_memory, m_image_memory_size));
|
||||
}
|
||||
|
||||
memset(m_color_lookup_table, 0, sizeof(m_color_lookup_table));
|
||||
|
||||
@ -34,7 +34,7 @@ PALETTE_INIT_MEMBER(cgc7900_state, cgc7900)
|
||||
palette.set_pen_color(5, rgb_t(0xff, 0x00, 0xff));
|
||||
palette.set_pen_color(6, rgb_t(0xff, 0xff, 0x00));
|
||||
palette.set_pen_color(7, rgb_t::white);
|
||||
};
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
READ/WRITE HANDLERS
|
||||
|
||||
@ -80,7 +80,8 @@ static void video_debug(running_machine &machine, int ref, int params, const cha
|
||||
mbc55x_state *mstate = machine.driver_data<mbc55x_state>();
|
||||
if(params>0)
|
||||
{
|
||||
sscanf(param[0],"%d",&mstate->m_debug_video);
|
||||
int temp;
|
||||
sscanf(param[0],"%d",&temp); mstate->m_debug_video = temp;;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
@ -461,7 +461,7 @@ int pc1512_state::get_color(UINT8 data)
|
||||
}
|
||||
|
||||
return color;
|
||||
};
|
||||
}
|
||||
|
||||
MC6845_UPDATE_ROW( pc1512_state::draw_graphics_1 )
|
||||
{
|
||||
|
||||
@ -475,7 +475,8 @@ static void video_debug(running_machine &machine, int ref, int params, const cha
|
||||
rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
|
||||
if(params>0)
|
||||
{
|
||||
sscanf(param[0],"%d",&state->m_debug_video);
|
||||
int temp;
|
||||
sscanf(param[0],"%d",&temp); state->m_debug_video = temp;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user