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Merge branch 'master' of https://github.com/mamedev/mame.git

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This commit is contained in:
couriersud 2015-05-01 11:23:02 +02:00
commit 8dbc55a85b
47 changed files with 1442 additions and 302 deletions
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1
scripts/genie.lua
View File

@ -1,6 +1,7 @@
premake.check_paths = true
premake.make.override = { "TARGET" }
MAME_DIR = (path.getabsolute("..") .. "/")
MAME_DIR = string.gsub(MAME_DIR, "(%s)", "\\%1")
local MAME_BUILD_DIR = (MAME_DIR .. "build/")
local naclToolchain = ""

1
scripts/target/mess/mess.lua
View File

@ -1875,6 +1875,7 @@ files {
MAME_DIR .. "src/mess/drivers/m20.c",
MAME_DIR .. "src/mess/drivers/m24.c",
MAME_DIR .. "src/mess/machine/m24_kbd.c",
MAME_DIR .. "src/mess/machine/m24_z8000.c"
}
createMESSProjects(_target, _subtarget, "omnibyte")

121
src/emu/bus/isa/cga.c
View File

@ -844,7 +844,7 @@ MC6845_UPDATE_ROW( isa8_cga_device::cga_gfx_2bpp_update_row )
if ( y == 0 ) CGA_LOG(1,"cga_gfx_2bpp_update_row",("\n"));
for ( i = 0; i < x_count; i++ )
{
UINT16 offset = ( ( ( ma + i ) << 1 ) & 0x1fff ) | ( ( y & 1 ) << 13 );
UINT16 offset = ( ( ( ma + i ) << 1 ) & 0x1fff ) | ( ( ra & 1 ) << 13 );
UINT8 data = videoram[ offset ];
*p = palette[m_palette_lut_2bpp[ ( data >> 6 ) & 0x03 ]]; p++;
@ -1888,3 +1888,122 @@ const rom_entry *isa8_cga_mc1502_device::device_rom_region() const
{
return ROM_NAME( mc1502 );
}
const device_type ISA8_CGA_M24 = &device_creator<isa8_cga_m24_device>;
isa8_cga_m24_device::isa8_cga_m24_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
isa8_cga_device( mconfig, ISA8_CGA_M24, "Olivetti M24 CGA", tag, owner, clock, "cga_m24", __FILE__)
{
m_vram_size = 0x8000;
}
void isa8_cga_m24_device::device_reset()
{
isa8_cga_device::device_reset();
m_mode2 = 0;
m_start_offset = 0;
}
WRITE8_MEMBER( isa8_cga_m24_device::io_write )
{
mc6845_device *mc6845 = subdevice<mc6845_device>(CGA_MC6845_NAME);
switch(offset)
{
case 0: case 2: case 4: case 6:
m_index = data;
mc6845->address_w( space, offset, data );
break;
case 1: case 3: case 5: case 7:
switch(m_index & 0x1f) // TODO: this is handled by a pal and prom
{
case 0:
data &= 0x7f;
break;
case 9:
if((data < 0x80) && (data != 3))
data = (data << 1) + 1;
break;
case 10:
data = ((data << 1) & 0x1f) | (data & 0x60);
break;
case 11:
data <<= 1;
break;
}
mc6845->register_w( space, offset, data );
break;
case 0x0e:
m_mode2 = data;
if((data & 8) && !(data & 1))
m_start_offset = 0x4000;
else
m_start_offset = 0;
break;
default:
isa8_cga_device::io_write(space, offset, data);
break;
}
}
READ8_MEMBER( isa8_cga_m24_device::io_read )
{
UINT8 data = 0xff;
switch(offset)
{
case 0x0a:
data = 0xc0 | m_vsync | ( ( data & 0x40 ) >> 4 ) | m_hsync; // 0xc0 == no expansion
break;
case 0x0e:
data = m_mode2;
break;
default:
data = isa8_cga_device::io_read(space, offset);
break;
}
return data;
}
MC6845_UPDATE_ROW( isa8_cga_m24_device::crtc_update_row )
{
if(m_mode2 & 1)
m24_gfx_1bpp_m24_update_row(bitmap, cliprect, ma, ra, y, x_count, cursor_x, de, hbp, vbp);
else
isa8_cga_device::crtc_update_row(bitmap, cliprect, ma, ra >> 1, y, x_count, cursor_x, de, hbp, vbp);
}
MC6845_UPDATE_ROW( isa8_cga_m24_device::m24_gfx_1bpp_m24_update_row )
{
UINT8 *videoram = &m_vram[m_start_offset];
UINT32 *p = &bitmap.pix32(y);
const rgb_t *palette = m_palette->palette()->entry_list_raw();
UINT8 fg = m_color_select & 0x0F;
int i;
if ( y == 0 ) CGA_LOG(1,"m24_gfx_1bpp_m24_update_row",("\n"));
for ( i = 0; i < x_count; i++ )
{
UINT16 offset = ( ( ( ma + i ) << 1 ) & 0x1fff ) | ( ( ra & 3 ) << 13 );
UINT8 data = videoram[ offset ];
*p = palette[( data & 0x80 ) ? fg : 0]; p++;
*p = palette[( data & 0x40 ) ? fg : 0]; p++;
*p = palette[( data & 0x20 ) ? fg : 0]; p++;
*p = palette[( data & 0x10 ) ? fg : 0]; p++;
*p = palette[( data & 0x08 ) ? fg : 0]; p++;
*p = palette[( data & 0x04 ) ? fg : 0]; p++;
*p = palette[( data & 0x02 ) ? fg : 0]; p++;
*p = palette[( data & 0x01 ) ? fg : 0]; p++;
data = videoram[ offset + 1 ];
*p = palette[( data & 0x80 ) ? fg : 0]; p++;
*p = palette[( data & 0x40 ) ? fg : 0]; p++;
*p = palette[( data & 0x20 ) ? fg : 0]; p++;
*p = palette[( data & 0x10 ) ? fg : 0]; p++;
*p = palette[( data & 0x08 ) ? fg : 0]; p++;
*p = palette[( data & 0x04 ) ? fg : 0]; p++;
*p = palette[( data & 0x02 ) ? fg : 0]; p++;
*p = palette[( data & 0x01 ) ? fg : 0]; p++;
}
}

21
src/emu/bus/isa/cga.h
View File

@ -260,4 +260,25 @@ public:
extern const device_type ISA8_CGA_MC1502;
class isa8_cga_m24_device :
public isa8_cga_device
{
public:
// construction/destruction
isa8_cga_m24_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// optional information overrides
//virtual const rom_entry *device_rom_region() const;
virtual DECLARE_READ8_MEMBER( io_read );
virtual DECLARE_WRITE8_MEMBER( io_write );
virtual MC6845_UPDATE_ROW( crtc_update_row );
MC6845_UPDATE_ROW( m24_gfx_1bpp_m24_update_row );
protected:
virtual void device_reset();
private:
UINT8 m_mode2, m_index;
};
// device type definition
extern const device_type ISA8_CGA_M24;
#endif /* __ISA_CGA_H__ */

1
src/emu/bus/isa/isa_cards.c
View File

@ -15,6 +15,7 @@ SLOT_INTERFACE_START( pc_isa8_cards )
SLOT_INTERFACE("cga_ec1841", ISA8_EC1841_0002)
SLOT_INTERFACE("cga_poisk2", ISA8_CGA_POISK2)
SLOT_INTERFACE("cga_mc1502", ISA8_CGA_MC1502)
SLOT_INTERFACE("cga_m24", ISA8_CGA_M24)
SLOT_INTERFACE("aga", ISA8_AGA)
SLOT_INTERFACE("aga_pc200", ISA8_AGA_PC200)
SLOT_INTERFACE("ega", ISA8_EGA)

47
src/emu/cpu/cop400/cop400.c
View File

@ -104,20 +104,18 @@ const device_type COP445 = &device_creator<cop445_cpu_device>;
#define ROM(a) m_direct->read_decrypted_byte(a)
#define RAM_R(a) m_data->read_byte(a)
#define RAM_W(a, v) m_data->write_byte(a, v)
#define IN(a) m_io->read_byte(a)
#define OUT(a, v) m_io->write_byte(a, v)
#define IN_G() (IN(COP400_PORT_G) & m_g_mask)
#define IN_L() IN(COP400_PORT_L)
#define IN_SI() BIT(IN(COP400_PORT_SIO), 0)
#define IN_CKO() BIT(IN(COP400_PORT_CKO), 0)
#define IN_IN() (m_in_mask ? IN(COP400_PORT_IN) : 0)
#define IN_G() (m_read_g(0, 0xff) & m_g_mask)
#define IN_L() m_read_l(0, 0xff)
#define IN_SI() BIT(m_read_si(), 0)
#define IN_CKO() BIT(m_read_cko(), 0)
#define IN_IN() (m_in_mask ? m_read_in(0, 0xff) : 0)
#define OUT_G(v) OUT(COP400_PORT_G, (v) & m_g_mask)
#define OUT_L(v) OUT(COP400_PORT_L, (v))
#define OUT_D(v) OUT(COP400_PORT_D, (v) & m_d_mask)
#define OUT_SK(v) OUT(COP400_PORT_SK, (v))
#define OUT_SO(v) OUT(COP400_PORT_SIO, (v))
#define OUT_G(v) m_write_g(0, (v) & m_g_mask, 0xff)
#define OUT_L(v) m_write_l(0, v, 0xff)
#define OUT_D(v) m_write_d(0, (v) & m_d_mask, 0xff)
#define OUT_SK(v) m_write_sk(v)
#define OUT_SO(v) m_write_so(v)
#define PC m_pc
#define A m_a
@ -176,7 +174,16 @@ cop400_cpu_device::cop400_cpu_device(const machine_config &mconfig, device_type
: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
, m_program_config("program", ENDIANNESS_LITTLE, 8, program_addr_bits, 0, internal_map_program)
, m_data_config("data", ENDIANNESS_LITTLE, 8, data_addr_bits, 0, internal_map_data) // data width is really 4
, m_io_config("io", ENDIANNESS_LITTLE, 8, 9, 0)
, m_read_l(*this)
, m_write_l(*this)
, m_read_g(*this)
, m_write_g(*this)
, m_write_d(*this)
, m_read_in(*this)
, m_read_si(*this)
, m_write_so(*this)
, m_write_sk(*this)
, m_read_cko(*this)
, m_cki(COP400_CKI_DIVISOR_16)
, m_cko(COP400_CKO_OSCILLATOR_OUTPUT)
, m_microbus(COP400_MICROBUS_DISABLED)
@ -952,7 +959,19 @@ void cop400_cpu_device::device_start()
m_program = &space(AS_PROGRAM);
m_direct = &m_program->direct();
m_data = &space(AS_DATA);
m_io = &space(AS_IO);
/* find i/o handlers */
m_read_l.resolve_safe(0);
m_write_l.resolve_safe();
m_read_g.resolve_safe(0);
m_write_g.resolve_safe();
m_write_d.resolve_safe();
m_read_in.resolve_safe(0);
m_read_si.resolve_safe(0);
m_write_so.resolve_safe();
m_write_sk.resolve_safe();
m_read_cko.resolve_safe(0);
/* allocate serial timer */

82
src/emu/cpu/cop400/cop400.h
View File

@ -16,6 +16,43 @@
#ifndef __COP400__
#define __COP400__
// i/o pins
// L pins: 8-bit bi-directional
#define MCFG_COP400_READ_L_CB(_devcb) \
cop400_cpu_device::set_read_l_callback(*device, DEVCB_##_devcb);
#define MCFG_COP400_WRITE_L_CB(_devcb) \
cop400_cpu_device::set_write_l_callback(*device, DEVCB_##_devcb);
// G pins: 4-bit bi-directional
#define MCFG_COP400_READ_G_CB(_devcb) \
cop400_cpu_device::set_read_g_callback(*device, DEVCB_##_devcb);
#define MCFG_COP400_WRITE_G_CB(_devcb) \
cop400_cpu_device::set_write_g_callback(*device, DEVCB_##_devcb);
// D outputs: 4-bit general purpose output
#define MCFG_COP400_WRITE_D_CB(_devcb) \
cop400_cpu_device::set_write_d_callback(*device, DEVCB_##_devcb);
// IN inputs: 4-bit general purpose input
#define MCFG_COP400_READ_IN_CB(_devcb) \
cop400_cpu_device::set_read_in_callback(*device, DEVCB_##_devcb);
// SI/SO lines: serial in/out or counter/gen.purpose
#define MCFG_COP400_READ_SI_CB(_devcb) \
cop400_cpu_device::set_read_si_callback(*device, DEVCB_##_devcb);
#define MCFG_COP400_WRITE_SO_CB(_devcb) \
cop400_cpu_device::set_write_so_callback(*device, DEVCB_##_devcb);
// SK output line: logic-controlled clock or gen.purpose
#define MCFG_COP400_WRITE_SK_CB(_devcb) \
cop400_cpu_device::set_write_sk_callback(*device, DEVCB_##_devcb);
// CKI/CKO lines: only CKO input here
#define MCFG_COP400_READ_CKO_CB(_devcb) \
cop400_cpu_device::set_read_cko_callback(*device, DEVCB_##_devcb);
/***************************************************************************
CONSTANTS
***************************************************************************/
@ -44,20 +81,6 @@ enum
COP400_GENSP = STATE_GENSP
};
/* special I/O space ports */
enum
{
COP400_PORT_L = 0x100,
COP400_PORT_G,
COP400_PORT_D,
COP400_PORT_H,
COP400_PORT_R,
COP400_PORT_IN,
COP400_PORT_SK,
COP400_PORT_SIO,
COP400_PORT_CKO
};
/* input lines */
enum
{
@ -112,6 +135,18 @@ public:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
// static configuration helpers
template<class _Object> static devcb_base &set_read_l_callback(device_t &device, _Object object) { return downcast<cop400_cpu_device &>(device).m_read_l.set_callback(object); }
template<class _Object> static devcb_base &set_write_l_callback(device_t &device, _Object object) { return downcast<cop400_cpu_device &>(device).m_write_l.set_callback(object); }
template<class _Object> static devcb_base &set_read_g_callback(device_t &device, _Object object) { return downcast<cop400_cpu_device &>(device).m_read_g.set_callback(object); }
template<class _Object> static devcb_base &set_write_g_callback(device_t &device, _Object object) { return downcast<cop400_cpu_device &>(device).m_write_g.set_callback(object); }
template<class _Object> static devcb_base &set_write_d_callback(device_t &device, _Object object) { return downcast<cop400_cpu_device &>(device).m_write_d.set_callback(object); }
template<class _Object> static devcb_base &set_read_in_callback(device_t &device, _Object object) { return downcast<cop400_cpu_device &>(device).m_read_in.set_callback(object); }
template<class _Object> static devcb_base &set_read_si_callback(device_t &device, _Object object) { return downcast<cop400_cpu_device &>(device).m_read_si.set_callback(object); }
template<class _Object> static devcb_base &set_write_so_callback(device_t &device, _Object object) { return downcast<cop400_cpu_device &>(device).m_write_so.set_callback(object); }
template<class _Object> static devcb_base &set_write_sk_callback(device_t &device, _Object object) { return downcast<cop400_cpu_device &>(device).m_write_sk.set_callback(object); }
template<class _Object> static devcb_base &set_read_cko_callback(device_t &device, _Object object) { return downcast<cop400_cpu_device &>(device).m_read_cko.set_callback(object); }
static void set_cki(device_t &device, cop400_cki_bond cki) { downcast<cop400_cpu_device &>(device).m_cki = cki; }
static void set_cko(device_t &device, cop400_cko_bond cko) { downcast<cop400_cpu_device &>(device).m_cko = cko; }
static void set_microbus(device_t &device, cop400_microbus microbus) { downcast<cop400_cpu_device &>(device).m_microbus = microbus; }
@ -132,8 +167,7 @@ protected:
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
{
return (spacenum == AS_PROGRAM) ? &m_program_config :
( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) );
return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL );
}
// device_state_interface overrides
@ -148,7 +182,18 @@ protected:
address_space_config m_program_config;
address_space_config m_data_config;
address_space_config m_io_config;
// i/o handlers
devcb_read8 m_read_l;
devcb_write8 m_write_l;
devcb_read8 m_read_g;
devcb_write8 m_write_g;
devcb_write8 m_write_d;
devcb_read8 m_read_in;
devcb_read_line m_read_si;
devcb_write_line m_write_so;
devcb_write_line m_write_sk;
devcb_read_line m_read_cko;
cop400_cki_bond m_cki;
cop400_cko_bond m_cko;
@ -160,7 +205,6 @@ protected:
address_space *m_program;
direct_read_data *m_direct;
address_space *m_data;
address_space *m_io;
UINT8 m_featuremask;
@ -174,7 +218,7 @@ protected:
UINT8 m_en; /* 4-bit enable register */
UINT8 m_g; /* 4-bit general purpose I/O port */
UINT8 m_q; /* 8-bit latch for L port */
UINT16 m_sa, m_sb, m_sc; /* subroutine save registers (not present in COP440) */
UINT16 m_sa, m_sb, m_sc; /* subroutine save registers (not present in COP440) */
UINT8 m_sio; /* 4-bit shift register and counter */
int m_skl; /* 1-bit latch for SK output */
UINT8 m_h; /* 4-bit general purpose I/O port (COP440 only) */

13
src/emu/cpu/z8000/z8000.c
View File

@ -72,6 +72,7 @@ z8002_device::z8002_device(const machine_config &mconfig, const char *tag, devic
: cpu_device(mconfig, Z8002, "Z8002", tag, owner, clock, "z8002", __FILE__)
, m_program_config("program", ENDIANNESS_BIG, 16, 16, 0)
, m_io_config("io", ENDIANNESS_BIG, 8, 16, 0)
, m_mo_out(*this)
, m_vector_mult(1)
{
}
@ -81,6 +82,7 @@ z8002_device::z8002_device(const machine_config &mconfig, device_type type, cons
: cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
, m_program_config("program", ENDIANNESS_BIG, 16, 20, 0)
, m_io_config("io", ENDIANNESS_BIG, 16, 16, 0)
, m_mo_out(*this)
, m_vector_mult(2)
{
}
@ -316,8 +318,8 @@ UINT8 z8002_device::RDPORT_B(int mode, UINT16 addr)
}
else
{
/* how to handle MMU reads? */
return 0x00;
/* how to handle MMU reads? for now just do it */
return m_io->read_byte(addr);
}
}
@ -356,7 +358,8 @@ void z8002_device::WRPORT_B(int mode, UINT16 addr, UINT8 value)
}
else
{
/* how to handle MMU writes? */
/* how to handle MMU writes? for now just do it */
m_io->write_byte(addr,value);
}
}
@ -701,6 +704,8 @@ void z8001_device::device_start()
register_debug_state();
m_icountptr = &m_icount;
m_mo_out.resolve_safe();
m_mi = CLEAR_LINE;
}
void z8002_device::device_start()
@ -726,6 +731,8 @@ void z8002_device::device_start()
register_debug_state();
m_icountptr = &m_icount;
m_mo_out.resolve_safe();
m_mi = CLEAR_LINE;
}
void z8001_device::device_reset()

7
src/emu/cpu/z8000/z8000.h
View File

@ -26,6 +26,8 @@ enum
#define Z8000_SYSCALL 0x0200 /* system call (lsb is vector) */
#define Z8000_HALT 0x0100 /* halted flag */
#define MCFG_Z8000_MO(_devcb) \
devcb = &z8002_device::set_mo_callback(*device, DEVCB_##_devcb);
class z8002_device : public cpu_device
{
@ -35,6 +37,9 @@ public:
z8002_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
~z8002_device();
template<class _Object> static devcb_base &set_mo_callback(device_t &device, _Object object) { return downcast<z8002_device &>(device).m_mo_out.set_callback(object); }
DECLARE_WRITE_LINE_MEMBER(mi_w) { m_mi = state; } // XXX: this has to apply in the middle of an insn for now
protected:
// device-level overrides
virtual void device_start();
@ -69,6 +74,7 @@ protected:
address_space_config m_program_config;
address_space_config m_io_config;
devcb_write_line m_mo_out;
UINT32 m_op[4]; /* opcodes/data of current instruction */
UINT32 m_ppc; /* previous program counter */
@ -91,6 +97,7 @@ protected:
} m_regs; /* registers */
int m_nmi_state; /* NMI line state */
int m_irq_state[2]; /* IRQ line states (NVI, VI) */
int m_mi;
address_space *m_program;
address_space *m_data;
direct_read_data *m_direct;

18
src/emu/cpu/z8000/z8000ops.inc
View File

@ -4674,6 +4674,24 @@ void z8002_device::Z7B_dddd_1101()
{
CHECK_PRIVILEGED_INSTR();
/* test mu-I line, invert cascade to mu-0 */
if (m_mi)
{
CLR_Z;
CLR_S;
m_mo_out(CLEAR_LINE);
return;
}
SET_Z;
m_mo_out(ASSERT_LINE);
if (m_mi)
{
SET_S;
}
else
{
CLR_S;
m_mo_out(CLEAR_LINE);
}
}
/******************************************

2
src/emu/machine/upd765.c
View File

@ -379,7 +379,7 @@ void upd765_family_device::set_rate(int rate)
READ8_MEMBER(upd765_family_device::fifo_r)
{
UINT8 r = 0;
UINT8 r = 0xff;
switch(main_phase) {
case PHASE_EXEC:
if(internal_drq)

109
src/emu/video/clgd542x.c
View File

@ -6,6 +6,8 @@
#include "clgd542x.h"
#define LOG_REG 0
#define LOG_BLIT 1
#define CRTC_PORT_ADDR ((vga.miscellaneous_output&1)?0x3d0:0x3b0)
@ -126,7 +128,7 @@ void cirrus_gd5428_device::device_reset()
m_blt_source = m_blt_dest = m_blt_source_current = m_blt_dest_current = 0;
memset(m_ext_palette, 0, sizeof(m_ext_palette));
m_ext_palette_enabled = false;
// m_ext_palette[15].red = m_ext_palette[15].green = m_ext_palette[15].blue = 0xff; // default? Win3.1 doesn't seem to touch the extended DAC, or at least, it enables it, then immediately disables it then sets a palette...
m_blt_system_transfer = false;
}
UINT32 cirrus_gd5428_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
@ -255,45 +257,98 @@ void cirrus_gd5428_device::start_bitblt()
{
UINT32 x,y;
logerror("CL: BitBLT started: Src: %06x Dst: %06x Width: %i Height %i ROP: %02x Mode: %02x\n",m_blt_source,m_blt_dest,m_blt_width,m_blt_height,m_blt_rop,m_blt_mode);
if(LOG_BLIT) logerror("CL: BitBLT started: Src: %06x Dst: %06x Width: %i Height %i ROP: %02x Mode: %02x\n",m_blt_source,m_blt_dest,m_blt_width,m_blt_height,m_blt_rop,m_blt_mode);
m_blt_source_current = m_blt_source;
m_blt_dest_current = m_blt_dest;
for(y=0;y<m_blt_height;y++)
for(y=0;y<=m_blt_height;y++)
{
for(x=0;x<m_blt_width;x++)
for(x=0;x<=m_blt_width;x++)
{
copy_pixel();
if(m_blt_mode & 0x80) // colour expand
{
UINT8 pixel = (vga.memory[m_blt_source_current % vga.svga_intf.vram_size] >> (7-(x % 8)) & 0x01) ? vga.gc.enable_set_reset : vga.gc.set_reset; // use GR0/1/10/11 background/foreground regs
copy_pixel(pixel, vga.memory[m_blt_dest_current % vga.svga_intf.vram_size]);
if(x % 8)
m_blt_source_current++;
}
else
{
copy_pixel(vga.memory[m_blt_source_current % vga.svga_intf.vram_size], vga.memory[m_blt_dest_current % vga.svga_intf.vram_size]);
m_blt_source_current++;
}
m_blt_dest_current++;
if(m_blt_mode & 0x40 && (x % 8) == 7) // 8x8 pattern - reset pattern source location
m_blt_source_current = m_blt_source + (m_blt_source_pitch*(y % 8));
m_blt_source_current = m_blt_source + (8*(y % 8)); // patterns are linear data
}
if(m_blt_mode & 0x40) // 8x8 pattern
m_blt_source_current = m_blt_source + (m_blt_source_pitch*(y % 8));
m_blt_source_current = m_blt_source + (8*(y % 8)); // patterns are linear data
else
m_blt_source_current = m_blt_source + (m_blt_source_pitch*y);
m_blt_dest_current = m_blt_dest + (m_blt_dest_pitch*y);
m_blt_dest_current = m_blt_dest + (m_blt_dest_pitch*(y+1));
}
m_blt_status &= ~0x02;
}
void cirrus_gd5428_device::copy_pixel()
void cirrus_gd5428_device::start_system_bitblt()
{
UINT8 src = vga.memory[m_blt_source_current % vga.svga_intf.vram_size];
UINT8 dst = vga.memory[m_blt_dest_current % vga.svga_intf.vram_size];
if(LOG_BLIT) logerror("CL: BitBLT from system memory started: Src: %06x Dst: %06x Width: %i Height %i ROP: %02x Mode: %02x\n",m_blt_source,m_blt_dest,m_blt_width,m_blt_height,m_blt_rop,m_blt_mode);
m_blt_system_transfer = true;
m_blt_system_count = 0;
m_blt_system_buffer = 0;
m_blt_pixel_count = m_blt_scan_count = 0;
m_blt_source_current = m_blt_source;
m_blt_dest_current = m_blt_dest;
m_blt_status |= 0x01;
}
void cirrus_gd5428_device::blit_dword()
{
// TODO: add support for reverse direction
UINT8 x,pixel;
if(m_blt_mode & 0x80) // colour expand
{
for(x=0;x<32;x++)
{
pixel = ((m_blt_system_buffer & (0x00000001 << x)) >> x) ? vga.gc.enable_set_reset : vga.gc.set_reset; // use GR0/1/10/11 background/foreground regs
if(m_blt_pixel_count <= m_blt_width)
copy_pixel(pixel,vga.memory[m_blt_dest_current % vga.svga_intf.vram_size]);
m_blt_dest_current++;
m_blt_pixel_count++;
}
}
else
{
for(x=0;x<32;x+=8)
{
pixel = ((m_blt_system_buffer & (0x000000ff << x)) >> x);
if(m_blt_pixel_count <= m_blt_width)
copy_pixel(pixel,vga.memory[m_blt_dest_current % vga.svga_intf.vram_size]);
m_blt_dest_current++;
m_blt_pixel_count++;
}
}
if(m_blt_pixel_count > m_blt_width)
{
m_blt_pixel_count = 0;
m_blt_scan_count++;
m_blt_dest_current = m_blt_dest + (m_blt_dest_pitch*m_blt_scan_count);
}
if(m_blt_scan_count > m_blt_height)
{
m_blt_system_transfer = false; // BitBLT complete
m_blt_status &= ~0x03;
}
}
void cirrus_gd5428_device::copy_pixel(UINT8 src, UINT8 dst)
{
if(m_blt_mode & 0x40) // enable 8x8 pattern
{
if(m_blt_mode & 0x80) // colour expand
src = (vga.memory[m_blt_source % vga.svga_intf.vram_size] >> (abs((int)(m_blt_source_current - m_blt_source)) % 8)) & 0x01 ? 0xff : 0x00;
src = (vga.memory[m_blt_source % vga.svga_intf.vram_size] >> (abs((int)(m_blt_source_current - m_blt_source)) % 8)) & 0x01 ? vga.gc.enable_set_reset : vga.gc.set_reset;
}
switch(m_blt_rop)
@ -301,7 +356,7 @@ void cirrus_gd5428_device::copy_pixel()
case 0x00: // BLACK
vga.memory[m_blt_dest_current % vga.svga_intf.vram_size] = 0x00;
break;
case 0x0b: // NOT DST
case 0x0b: // DSTINVERT
vga.memory[m_blt_dest_current % vga.svga_intf.vram_size] = ~dst;
break;
case 0x0d: // SRC
@ -379,7 +434,7 @@ UINT8 cirrus_gd5428_device::cirrus_seq_reg_read(UINT8 index)
void cirrus_gd5428_device::cirrus_seq_reg_write(UINT8 index, UINT8 data)
{
logerror("CL: SEQ write %02x to SR%02x\n",data,index);
if(LOG_REG) logerror("CL: SEQ write %02x to SR%02x\n",data,index);
switch(index)
{
case 0x02:
@ -579,7 +634,7 @@ UINT8 cirrus_gd5428_device::cirrus_gc_reg_read(UINT8 index)
void cirrus_gd5428_device::cirrus_gc_reg_write(UINT8 index, UINT8 data)
{
logerror("CL: GC write %02x to GR%02x\n",data,index);
if(LOG_REG) logerror("CL: GC write %02x to GR%02x\n",data,index);
switch(index)
{
case 0x00: // if extended writes are enabled (bit 2 of index 0bh), then index 0 and 1 are extended to 8 bits
@ -681,9 +736,14 @@ void cirrus_gd5428_device::cirrus_gc_reg_write(UINT8 index, UINT8 data)
m_blt_mode = data;
break;
case 0x31: // BitBLT Start / Status
m_blt_status = data & 0xf2;
m_blt_status = data & ~0xf2;
if(data & 0x02)
start_bitblt();
{
if(m_blt_mode & 0x04) // blit source is system memory
start_system_bitblt();
else
start_bitblt();
}
break;
case 0x32: // BitBLT ROP mode
m_blt_rop = data;
@ -892,7 +952,7 @@ UINT8 cirrus_gd5428_device::cirrus_crtc_reg_read(UINT8 index)
void cirrus_gd5428_device::cirrus_crtc_reg_write(UINT8 index, UINT8 data)
{
logerror("CL: CRTC write %02x to CR%02x\n",data,index);
if(LOG_REG) logerror("CL: CRTC write %02x to CR%02x\n",data,index);
switch(index)
{
case 0x16: // VGA Vertical Blank end - some SVGA chipsets use all 8 bits, and this is one of them (according to MFGTST CRTC tests)
@ -1101,6 +1161,19 @@ WRITE8_MEMBER(cirrus_gd5428_device::mem_w)
UINT8 bank;
UINT8 cur_mode = pc_vga_choosevideomode();
if(m_blt_system_transfer)
{
m_blt_system_buffer &= ~(0x000000ff << (m_blt_system_count * 8));
m_blt_system_buffer |= (data << (m_blt_system_count * 8));
m_blt_system_count++;
if(m_blt_system_count >= 4)
{
blit_dword();
m_blt_system_count = 0;
}
return;
}
if(gc_locked || offset >= 0x10000 || cur_mode == TEXT_MODE || cur_mode == SCREEN_OFF)
{
vga_device::mem_w(space,offset,data,mem_mask);

10
src/emu/video/clgd542x.h
View File

@ -65,6 +65,12 @@ protected:
UINT32 m_blt_source_current;
UINT32 m_blt_dest_current;
bool m_blt_system_transfer; // blit from system memory
UINT8 m_blt_system_count;
UINT32 m_blt_system_buffer;
UINT16 m_blt_pixel_count;
UINT16 m_blt_scan_count;
UINT8 m_scratchpad1;
UINT8 m_scratchpad2;
UINT8 m_scratchpad3;
@ -82,7 +88,9 @@ private:
void cirrus_crtc_reg_write(UINT8 index, UINT8 data);
void start_bitblt();
void copy_pixel();
void start_system_bitblt();
void blit_dword();
void copy_pixel(UINT8 src, UINT8 dst);
};
class cirrus_gd5430_device : public cirrus_gd5428_device

4
src/mame/drivers/24cdjuke.c
View File

@ -84,7 +84,7 @@ public:
DECLARE_WRITE8_MEMBER(kb_col_w);
DECLARE_WRITE8_MEMBER(digit_w);
DECLARE_READ8_MEMBER(rand_r){ return machine().rand(); }
DECLARE_READ8_MEMBER(unknown_r) { return machine().rand(); }
private:
UINT8 m_kb_col;
@ -134,7 +134,7 @@ static ADDRESS_MAP_START( midcoin24cdjuke_io, AS_IO, 8, midcoin24cdjuke_state )
AM_RANGE(0x04, 0x07) AM_DEVREADWRITE("ic11", i8255_device, read, write)
AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE("ic25", i8255_device, read, write)
AM_RANGE(0x0c, 0x0c) AM_WRITENOP
AM_RANGE(0x10, 0x1f) AM_READ(rand_r)
AM_RANGE(0x10, 0x1f) AM_READ(unknown_r)
ADDRESS_MAP_END
static INPUT_PORTS_START( midcoin24cdjuke )

14
src/mame/drivers/bingoc.c
View File

@ -46,10 +46,10 @@ public:
m_upd7759(*this, "upd") { }
UINT8 m_x;
DECLARE_READ16_MEMBER(bingoc_rand_r);
DECLARE_READ16_MEMBER(unknown_r);
DECLARE_READ8_MEMBER(sound_test_r);
DECLARE_WRITE16_MEMBER(main_sound_latch_w);
DECLARE_WRITE8_MEMBER(bingoc_play_w);
DECLARE_WRITE8_MEMBER(sound_play_w);
virtual void video_start();
UINT32 screen_update_bingoc(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
required_device<cpu_device> m_maincpu;
@ -69,7 +69,7 @@ UINT32 bingoc_state::screen_update_bingoc(screen_device &screen, bitmap_ind16 &b
return 0;
}
READ16_MEMBER(bingoc_state::bingoc_rand_r)
READ16_MEMBER(bingoc_state::unknown_r)
{
return 0xffff;
}
@ -103,7 +103,7 @@ WRITE16_MEMBER(bingoc_state::main_sound_latch_w)
}
#endif
WRITE8_MEMBER(bingoc_state::bingoc_play_w)
WRITE8_MEMBER(bingoc_state::sound_play_w)
{
/*
---- --x- sound rom banking
@ -117,8 +117,8 @@ WRITE8_MEMBER(bingoc_state::bingoc_play_w)
static ADDRESS_MAP_START( main_map, AS_PROGRAM, 16, bingoc_state )
AM_RANGE(0x000000, 0x03ffff) AM_ROM
AM_RANGE(0x100000, 0x10007f) AM_READ(bingoc_rand_r) //comms? lamps?
AM_RANGE(0x180000, 0x18007f) AM_READ(bingoc_rand_r) //comms? lamps?
AM_RANGE(0x100000, 0x10007f) AM_READ(unknown_r) //comms? lamps?
AM_RANGE(0x180000, 0x18007f) AM_READ(unknown_r) //comms? lamps?
#if !SOUND_TEST
AM_RANGE(0x180010, 0x180011) AM_WRITE(main_sound_latch_w) //WRONG there...
#endif
@ -133,7 +133,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_io, AS_IO, 8, bingoc_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x01) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write)
AM_RANGE(0x40, 0x40) AM_WRITE(bingoc_play_w)
AM_RANGE(0x40, 0x40) AM_WRITE(sound_play_w)
AM_RANGE(0x80, 0x80) AM_DEVWRITE("upd", upd7759_device, port_w)
#if !SOUND_TEST
AM_RANGE(0xc0, 0xc0) AM_READ(soundlatch_byte_r) //soundlatch

8
src/mame/drivers/centiped.c
View File

@ -619,7 +619,7 @@ WRITE8_MEMBER(centiped_state::led_w)
}
READ8_MEMBER(centiped_state::caterplr_rand_r)
READ8_MEMBER(centiped_state::caterplr_unknown_r)
{
return machine().rand() % 0xff;
}
@ -712,7 +712,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( caterplr_map, AS_PROGRAM, 8, centiped_state )
AM_IMPORT_FROM(centiped_base_map)
AM_RANGE(0x1780, 0x1780) AM_READ(caterplr_rand_r)
AM_RANGE(0x1780, 0x1780) AM_READ(caterplr_unknown_r)
AM_RANGE(0x1000, 0x100f) AM_READWRITE(caterplr_AY8910_r, caterplr_AY8910_w)
ADDRESS_MAP_END
@ -1743,7 +1743,7 @@ static MACHINE_CONFIG_DERIVED( centipdb, centiped )
/* sound hardware */
MCFG_SOUND_REPLACE("pokey", AY8910, 12096000/8)
MCFG_AY8910_PORT_A_READ_CB(READ8(centiped_state, caterplr_rand_r))
MCFG_AY8910_PORT_A_READ_CB(READ8(centiped_state, caterplr_unknown_r))
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 2.0)
MACHINE_CONFIG_END
@ -1759,7 +1759,7 @@ static MACHINE_CONFIG_DERIVED( magworm, centiped_base )
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("pokey", AY8910, 12096000/8)
MCFG_AY8910_PORT_A_READ_CB(READ8(centiped_state, caterplr_rand_r))
MCFG_AY8910_PORT_A_READ_CB(READ8(centiped_state, caterplr_unknown_r))
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 2.0)
MACHINE_CONFIG_END

15
src/mame/drivers/cidelsa.c
View File

@ -196,15 +196,6 @@ static ADDRESS_MAP_START( draco_sound_map, AS_PROGRAM, 8, draco_state )
AM_RANGE(0x000, 0x3ff) AM_ROMBANK("bank1")
ADDRESS_MAP_END
static ADDRESS_MAP_START( draco_sound_io_map, AS_IO, 8, draco_state )
AM_RANGE(COP400_PORT_D, COP400_PORT_D) AM_WRITE(sound_bankswitch_w)
AM_RANGE(COP400_PORT_G, COP400_PORT_G) AM_WRITE(sound_g_w)
AM_RANGE(COP400_PORT_L, COP400_PORT_L) AM_READWRITE(psg_r, psg_w)
AM_RANGE(COP400_PORT_IN, COP400_PORT_IN) AM_READ(sound_in_r)
AM_RANGE(COP400_PORT_SIO, COP400_PORT_SIO) AM_NOP
AM_RANGE(COP400_PORT_SK, COP400_PORT_SK) AM_WRITENOP
ADDRESS_MAP_END
/* Input Ports */
READ_LINE_MEMBER( cidelsa_state::cdp1869_pcb_r )
@ -469,8 +460,12 @@ static MACHINE_CONFIG_START( draco, draco_state )
MCFG_CPU_ADD(COP402N_TAG, COP402, DRACO_SND_CHR1)
MCFG_CPU_PROGRAM_MAP(draco_sound_map)
MCFG_CPU_IO_MAP(draco_sound_io_map)
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_DISABLED )
MCFG_COP400_WRITE_D_CB(WRITE8(draco_state, sound_bankswitch_w))
MCFG_COP400_WRITE_G_CB(WRITE8(draco_state, sound_g_w))
MCFG_COP400_READ_L_CB(READ8(draco_state, psg_r))
MCFG_COP400_WRITE_L_CB(WRITE8(draco_state, psg_w))
MCFG_COP400_READ_IN_CB(READ8(draco_state, sound_in_r))
/* input/output hardware */
MCFG_DEVICE_ADD("ic29", CDP1852, 0) // clock is really tied to CDP1869 CMSEL (pin 37)

205
src/mame/drivers/gambl186.c
View File

@ -20,10 +20,15 @@ U3 Max691cpe
U300 Nec D7759GC (10Mhz xtal near it)
TODO:
- No idea about how to surpass the "No Funzione" (sic) screen. According to the bad settings almost
surely it wants EEPROM hooked up (i/o at 0x680/0x682?)
In order to get the game to run, follow these steps:
- enable service mode
- run all of the tests (press '1' repeatedly to progress)
- at the "cancellare la memoria" prompt, press 'X' to allow it
- when the line of '*' appears, press the buttons in the following sequence:
1 1 X X 1 1 1 X X X 1 1 X 1 1 1 1 X 1 1 1 1 1 X 1 1 1 1 1 1 X
(This is the "password" for the EEPROM. You have three attempts to get it correct, otherwise the service mode will restart)
- if accepted, disable service mode DIP switch
- reset machine (press 'F3')
*/
@ -41,9 +46,13 @@ public:
m_maincpu(*this, "maincpu") { }
required_device<cpu_device> m_maincpu;
int m_comms_state;
int m_comms_state;
int m_comms_ind;
UINT8 m_comms_data[1002];
int m_comms_cmd;
int m_comms_expect;
int m_comms_blocks;
bool m_comms_ack;
DECLARE_READ16_MEMBER(comms_r);
DECLARE_WRITE16_MEMBER(comms_w);
@ -58,54 +67,162 @@ static ADDRESS_MAP_START( gambl186_map, AS_PROGRAM, 16, gambl186_state )
AM_RANGE(0xc0000, 0xfffff) AM_ROM AM_REGION("ipl",0)
ADDRESS_MAP_END
static const UINT8 password[] = {5, 2, 0, 3, 0, 0, 2, 4, 5, 6, 0x16};
READ16_MEMBER(gambl186_state::comms_r)
{
if ((offset == 0) && ACCESSING_BITS_0_7) //port 680 == data
{
if ((m_comms_state == 0x16) && (m_comms_ind < sizeof(m_comms_data)))
{
return m_comms_data[m_comms_ind++];
}
}
else if (offset == 1) //port 681 == status
{
if (m_comms_state == 0x16) //read mode?
{
return 2;
}
else if (m_comms_state == 0x31) //write mode?
{
return 4;
}
}
UINT16 retval = 0;
return 0;
if ((offset == 0) && ACCESSING_BITS_0_7) //port 680 == data
{
if (m_comms_state == 0x16) //read mode, just in case
{
if (!m_comms_ind && (m_comms_cmd == 0xff))
{
m_comms_cmd = m_comms_data[1];
switch (m_comms_cmd)
{
case 0:
{
m_comms_expect = 4;
break;
}
case 1: //unverified
case 3: //unverified
{
m_comms_expect = 8;
break;
}
case 2:
{
m_comms_expect = 408;
m_comms_data[401] = 0x34; //precalc
m_comms_blocks = 4;
break;
}
case 4:
{
m_comms_expect = 4;
break;
}
case 5: //unverified
{
m_comms_expect = 7;
break;
}
case 6:
{
m_comms_expect = 1003;
m_comms_data[1001] = 0xec; //precalc
break;
}
default: //unverified
{
m_comms_expect = 1;
}
}
}
if (m_comms_ind < sizeof(m_comms_data))
{
if ((m_comms_cmd == 4) && (m_comms_ind == 1) && !memcmp(m_comms_data, password, sizeof(password)))
{
m_comms_data[1] = 0x55;
m_comms_data[2] = 0x55;
}
retval = m_comms_data[m_comms_ind++];
if (m_comms_expect && !--m_comms_expect)
{
if (!m_comms_blocks || !--m_comms_blocks)
{
m_comms_cmd = 0xff;
}
else if (m_comms_cmd == 2)
{
if (m_comms_blocks == 3)
{
m_comms_expect = 5;
m_comms_data[4] = 0x17; //precalc
}
else
{
m_comms_expect = 3;
m_comms_data[2] = 5; //precalc
}
}
m_comms_ack = true;
}
}
}
}
else if (offset == 1) //port 681 == status
{
if (m_comms_state == 0x16) //read mode
{
retval = 2; //read ready
}
else if (m_comms_state == 0x31) //write mode
{
retval = 4; //write ready
}
}
return retval;
}
WRITE16_MEMBER(gambl186_state::comms_w)
{
if (offset == 0)
{
if ((m_comms_state == 0x31) && (m_comms_ind < (sizeof(m_comms_data) - 2)))
{
m_comms_data[++m_comms_ind] = (UINT8) ~data;
}
}
else if (offset == 1)
{
if (m_comms_state != data)
{
m_comms_ind = 0;
}
if (offset == 0)
{
if ((m_comms_state == 0x31) && (m_comms_ind < 1000))
{
if (!m_comms_ack || (data == 0x15)) //validation failure
{
if (m_comms_cmd == 6) //1000 bytes transfer
{
data = ~data;
}
else if (m_comms_ack)
{
m_comms_cmd = 0xfe;
m_comms_expect = 2;
data = 5;
}
m_comms_state = data;
m_comms_data[++m_comms_ind] = (UINT8) data;
}
if (data == 0x4e) //reset?
{
m_comms_data[0] = 5;
m_comms_data[sizeof(m_comms_data) - 1] = 0xec;
}
}
m_comms_ack = false;
}
}
else if (offset == 1)
{
if (m_comms_state != data) //detect transition
{
m_comms_ind = 0;
if (data == 0x4e) //reset
{
m_comms_data[0] = 5; //operation complete
m_comms_cmd = 0xff; //none
m_comms_expect = 0;
m_comms_blocks = 0;
m_comms_ack = false;
}
}
m_comms_state = data;
}
}
static ADDRESS_MAP_START( gambl186_io, AS_IO, 16, gambl186_state )

51
src/mame/drivers/looping.c
View File

@ -113,7 +113,7 @@ public:
required_shared_ptr<UINT8> m_videoram;
required_shared_ptr<UINT8> m_colorram;
required_shared_ptr<UINT8> m_spriteram;
UINT8 * m_cop_io;
UINT8 m_cop_port_l;
/* tilemaps */
tilemap_t * m_bg_tilemap;
@ -137,8 +137,9 @@ public:
DECLARE_READ8_MEMBER(adc_r);
DECLARE_WRITE8_MEMBER(adc_w);
DECLARE_WRITE8_MEMBER(plr2_w);
DECLARE_READ8_MEMBER(cop_io_r);
DECLARE_WRITE8_MEMBER(cop_io_w);
DECLARE_READ8_MEMBER(cop_unk_r);
DECLARE_READ_LINE_MEMBER(cop_serial_r);
DECLARE_WRITE8_MEMBER(cop_l_w);
DECLARE_READ8_MEMBER(protection_r);
DECLARE_WRITE_LINE_MEMBER(looping_spcint);
DECLARE_WRITE8_MEMBER(looping_sound_sw);
@ -479,16 +480,20 @@ WRITE8_MEMBER(looping_state::plr2_w)
*
*************************************/
READ8_MEMBER(looping_state::cop_io_r)
READ8_MEMBER(looping_state::cop_unk_r)
{
// if (offset == 1) return machine().rand() & 0x01;
return 1; // m_cop_io[offset];
return 1;
}
WRITE8_MEMBER(looping_state::cop_io_w)
READ_LINE_MEMBER(looping_state::cop_serial_r)
{
m_cop_io[offset] = data;
if (offset == 0) logerror("%02x ",data);
return 1;
}
WRITE8_MEMBER(looping_state::cop_l_w)
{
m_cop_port_l = data;
logerror("%02x ",data);
}
READ8_MEMBER(looping_state::protection_r)
@ -511,7 +516,7 @@ READ8_MEMBER(looping_state::protection_r)
// cop write randomly fc (unfortunatly) but 61,67,b7,bf,db,e1,f3,fd,ff too and only these values
// missing something
if(m_cop_io[0] != 0xfc) return m_cop_io[0];
if(m_cop_port_l != 0xfc) return m_cop_port_l;
return 0xff;
}
@ -579,20 +584,6 @@ static ADDRESS_MAP_START( looping_sound_io_map, AS_IO, 8, looping_state )
ADDRESS_MAP_END
/* standard COP420 map */
static ADDRESS_MAP_START( looping_cop_map, AS_PROGRAM, 8, looping_state )
AM_RANGE(0x0000, 0x03ff) AM_ROM
ADDRESS_MAP_END
static ADDRESS_MAP_START( looping_cop_data_map, AS_DATA, 8, looping_state )
AM_RANGE(0x0000, 0x003f) AM_RAM
ADDRESS_MAP_END
static ADDRESS_MAP_START( looping_cop_io_map, AS_IO, 8, looping_state )
AM_RANGE(0x0100, 0x0107) AM_READWRITE(cop_io_r, cop_io_w)
ADDRESS_MAP_END
/*************************************
*
* Graphics definitions
@ -633,10 +624,12 @@ static MACHINE_CONFIG_START( looping, looping_state )
MCFG_TMS99xx_ADD("audiocpu", TMS9980A, SOUND_CLOCK/4, looping_sound_map, looping_sound_io_map)
MCFG_CPU_ADD("mcu", COP420, COP_CLOCK)
MCFG_CPU_PROGRAM_MAP(looping_cop_map)
MCFG_CPU_DATA_MAP(looping_cop_data_map)
MCFG_CPU_IO_MAP(looping_cop_io_map)
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_DISABLED )
MCFG_COP400_WRITE_L_CB(WRITE8(looping_state, cop_l_w))
MCFG_COP400_READ_L_CB(READ8(looping_state, cop_unk_r))
MCFG_COP400_READ_G_CB(READ8(looping_state, cop_unk_r))
MCFG_COP400_READ_IN_CB(READ8(looping_state, cop_unk_r))
MCFG_COP400_READ_SI_CB(READLINE(looping_state, cop_serial_r))
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@ -892,8 +885,8 @@ DRIVER_INIT_MEMBER(looping_state,looping)
int length = memregion("maincpu")->bytes();
UINT8 *rom = memregion("maincpu")->base();
int i;
m_cop_io = auto_alloc_array(machine(), UINT8, 0x08);
m_cop_port_l = 0;
/* bitswap the TMS9995 ROMs */
for (i = 0; i < length; i++)

6
src/mame/drivers/magictg.c
View File

@ -192,7 +192,7 @@ public:
DECLARE_WRITE32_MEMBER( f0_w );
DECLARE_READ32_MEMBER( unk_r );
DECLARE_READ32_MEMBER( rand_r );
DECLARE_READ32_MEMBER( unk2_r );
DECLARE_READ32_MEMBER( serial_r );
DECLARE_WRITE32_MEMBER( serial_w );
@ -523,7 +523,7 @@ READ32_MEMBER( magictg_state::unk_r )
return 0x6000;
}
READ32_MEMBER( magictg_state::rand_r )
READ32_MEMBER( magictg_state::unk2_r )
{
return 0xffffffff;
}
@ -833,7 +833,7 @@ static ADDRESS_MAP_START( magictg_map, AS_PROGRAM, 32, magictg_state )
AM_RANGE(0x1b001024, 0x1b001027) AM_READ(adsp_status_r)
AM_RANGE(0x1b001108, 0x1b00110b) AM_READ(unk_r)
AM_RANGE(0x1e000000, 0x1e002fff) AM_RAM // NVRAM?
AM_RANGE(0x1e800000, 0x1e800007) AM_READWRITE(rand_r, serial_w)
AM_RANGE(0x1e800000, 0x1e800007) AM_READWRITE(unk2_r, serial_w)
AM_RANGE(0x1fc00000, 0x1fffffff) AM_ROM AM_REGION("mips", 0)
ADDRESS_MAP_END

9
src/mame/drivers/naomi.c
View File

@ -4132,6 +4132,15 @@ ROM_START( mtkob2 )
ROM_COPY( "rom_board", 0x1000000, 0x400000, 0xc00000 )
// MUSHIKING
// The King of Beetle
// TYPE-1
// 800
// note: this dump from "empty/dead" Management Chip with no game run count left
ROM_REGION( 0x80, "rf_tag", 0 )
ROM_LOAD( "mushi_type1.bin", 0, 0x80, CRC(8f36572b) SHA1(87e00e56d07a961e9180c7da02e35f7fd216dbae) )
// 840-0150 2003 317-0394-COM Naomi
ROM_PARAMETER( ":rom_board:key", "3892fb3a" )
ROM_END

119
src/mame/drivers/segasp.c
View File

@ -14,7 +14,7 @@ differences with Naomi in SH4 memory map only:
as for ROM board - unlike regular Naomi M4 it have not only ROM itself,
but the other hardware too*:
0x00000000 - 0x1fffffff - FlashROM, like in regular Naomi M4 cart
0x39xxxxxx - SRAM(32Kb)**
0x39xxxxxx - SRAM(128KB)**
0x3axxxxxx - CF IDE registers (0 - data, 4 - error, 8 - sector count, etc)
0x3bxxxxxx - CF IDE AltStatus/Device Ctrl register
0x3dxxxxxx - Network aka Media board shared buffer/RAM
@ -74,6 +74,23 @@ G 171-8278G 315-6416 2x 512Mbit RMI
#include "debugger.h"
#include "includes/segasp.h"
READ64_MEMBER(segasp_state::sp_bank_r)
{
if (mem_mask & U64(0xffffffff00000000))
return -1;
return m_sp_bank;
}
WRITE64_MEMBER(segasp_state::sp_bank_w)
{
if (mem_mask & U64(0xffffffff00000000))
return;
UINT16 bank = data & 0xffff;
if (bank != m_sp_bank)
logerror("SystemSP: G2 Bank set to %08X%s\n", (bank & 0x3fff) << 16, (bank & 0x4000) ? " decrypt ON" :"" );
m_sp_bank = bank;
}
READ64_MEMBER(segasp_state::sn_93c46a_r)
{
int res;
@ -96,11 +113,15 @@ WRITE64_MEMBER(segasp_state::sn_93c46a_w)
READ64_MEMBER(segasp_state::sp_eeprom_r)
{
if (mem_mask & U64(0xffffffff00000000))
return -1;
return m_sp_eeprom->do_read() << 4;
}
WRITE64_MEMBER(segasp_state::sp_eeprom_w)
{
if (mem_mask & U64(0xffffffff00000000))
return;
m_sp_eeprom->di_write(data & 1);
m_sp_eeprom->cs_write((data & 2) ? ASSERT_LINE : CLEAR_LINE);
m_sp_eeprom->clk_write((data & 4) ? ASSERT_LINE : CLEAR_LINE);
@ -109,8 +130,8 @@ WRITE64_MEMBER(segasp_state::sp_eeprom_w)
READ64_MEMBER(segasp_state::sp_rombdflg_r)
{
// bit 0 - romboard type, 1 = M4
// bit 1 - debug mode
return 0x01;
// bit 1 - debug mode (enable easter eggs in BIOS, can boot game without proper eeproms/settings)
return ioport("CFG")->read();
}
READ64_MEMBER(segasp_state::sp_io_r)
@ -120,7 +141,7 @@ READ64_MEMBER(segasp_state::sp_io_r)
int reg = offset * 2;
int shift = 0;
if (mem_mask & U64(0x000000ff00000000))
if (mem_mask & U64(0xffffffff00000000))
{
reg++;
shift = 32;
@ -169,11 +190,14 @@ static ADDRESS_MAP_START( segasp_map, AS_PROGRAM, 64, segasp_state )
AM_RANGE(0x00800000, 0x00ffffff) AM_MIRROR(0x02000000) AM_READWRITE(naomi_arm_r, naomi_arm_w ) // sound RAM (8 MB)
/* External Device */
AM_RANGE(0x01000000, 0x0100ffff) AM_RAM // - banked access to ROM board address space
AM_RANGE(0x01000000, 0x0100ffff) AM_RAM // banked access to ROM/NET board address space, mainly backup SRAM and ATA
AM_RANGE(0x01010000, 0x01010007) AM_READWRITE(sp_bank_r, sp_bank_w )
// AM_RANGE(0x01010080, 0x01010087) IRQ pending/reset, ATA control
AM_RANGE(0x01010100, 0x01010127) AM_READ(sp_io_r)
AM_RANGE(0x01010128, 0x0101012f) AM_READWRITE(sp_eeprom_r, sp_eeprom_w )
AM_RANGE(0x01010150, 0x01010157) AM_READ(sp_rombdflg_r)
// AM_RANGE(0x01010000, 0x010101ff) // I/O regs
// AM_RANGE(0x01010180, 0x010101af) custom UART 1
// AM_RANGE(0x010101c0, 0x010101ef) custom UART 2
/* Area 1 */
AM_RANGE(0x04000000, 0x04ffffff) AM_MIRROR(0x02000000) AM_RAM AM_SHARE("dc_texture_ram") // texture memory 64 bit access
@ -210,6 +234,14 @@ ADDRESS_MAP_END
INPUT_PORTS_START( segasp )
PORT_INCLUDE( naomi_debug )
PORT_START("CFG")
PORT_DIPNAME( 0x01, 0x01, "ROM Board type" )
PORT_DIPSETTING( 0x00, "other" )
PORT_DIPSETTING( 0x01, "M4-type" )
PORT_DIPNAME( 0x02, 0x00, "BIOS Debug mode" )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x02, DEF_STR( On ) )
PORT_START("DSW")
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW:1")
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
@ -220,7 +252,7 @@ INPUT_PORTS_START( segasp )
PORT_DIPNAME( 0x04, 0x04, "Monitor" ) PORT_DIPLOCATION("SW:3")
PORT_DIPSETTING( 0x04, "31 kHz" )
PORT_DIPSETTING( 0x00, "15 kHz" )
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW:4") // Must be ON, with off BIOS bootstrap will deadloop
PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW:4") // Must be ON, with off BIOS bootstrap will deadloop with green screen
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@ -275,23 +307,24 @@ MACHINE_CONFIG_END
#define SEGASP_BIOS \
ROM_REGION( 0x200000, "maincpu", 0) \
ROM_SYSTEM_BIOS( 0, "bios0", "BOOT VER 1.01" ) \
ROM_SYSTEM_BIOS( 0, "v101", "BOOT VER 1.01" ) \
ROM_LOAD16_WORD_SWAP_BIOS( 0, "epr-24236a.ic50", 0x000000, 0x200000, CRC(ca7df0de) SHA1(504c74d5fc96c53ef9f7753e9e37fb8b39cb628c) ) \
ROM_SYSTEM_BIOS( 1, "bios1", "BOOT VER 2.00" ) \
ROM_SYSTEM_BIOS( 1, "v200", "BOOT VER 2.00" ) \
ROM_LOAD16_WORD_SWAP_BIOS( 1, "epr-24328.ic50", 0x000000, 0x200000, CRC(25f2ef00) SHA1(e58dec9f171e52b3ded213b3fcd9a0de8a438076) ) \
ROM_SYSTEM_BIOS( 2, "bios2", "BOOT VER 2.01" ) \
ROM_LOAD16_WORD_SWAP_BIOS( 2, "epr-24328a.ic50", 0x000000, 0x200000, CRC(03ec3805) SHA1(a8fbaea826ca257be0b2b86952f247254929e046) )
ROM_SYSTEM_BIOS( 2, "v201", "BOOT VER 2.01" ) \
ROM_LOAD16_WORD_SWAP_BIOS( 2, "epr-24328a.ic50", 0x000000, 0x200000, CRC(03ec3805) SHA1(a8fbaea826ca257be0b2b86952f247254929e046) ) \
ROM_REGION16_BE( 0x80, "main_eeprom", 0 ) \
ROM_LOAD16_WORD( "mb_serial.ic57", 0x0000, 0x0080, CRC(e1e3c009) SHA1(66bc636c527389c3338f631d78c788b4bd4e93be) )
// Network/Media Board firmware VER 1.19(VxWorks), 1st half contain original 1.10 version
#define SEGASP_NETFIRM \
ROM_REGION( 0x200000, "netcpu", 0) \
ROM_LOAD( "net_eeprom.ic74s", 0x00000000, 0x200, CRC(77cc5a6c) SHA1(cbfba546256b70bce6c6fd0030d7e2e410a25526) ) \
ROM_LOAD( "net_firm_119.ic72", 0x00000000, 0x200000, CRC(a738ea1c) SHA1(d25187a973a7e166e70334f964363adf2be87257) )
// keep M4 board code happy for now
#define SEGASP_MISC \
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x04)) \
ROM_REGION( 0x84, "naomibd_eeprom", ROMREGION_ERASEFF ) \
ROM_REGION16_BE( 0x80, "main_eeprom", 0 ) \
ROM_LOAD16_WORD( "mb_serial.ic57", 0x0000, 0x0080, CRC(e1e3c009) SHA1(66bc636c527389c3338f631d78c788b4bd4e93be) )
ROM_REGION( 0x84, "naomibd_eeprom", ROMREGION_ERASEFF )
#define SEGASPEE_US \
ROM_LOAD16_WORD( "mb_eeprom_us.ic54s", 0x0000, 0x0080, CRC(4186d7ab) SHA1(fc23da69a511a7643b6a066161bcfc3cdeeacf04) )
@ -307,18 +340,26 @@ MACHINE_CONFIG_END
ROM_REGION16_BE(0x80, "sp_eeprom", 0) \
SEGASPEE_EXP
#define SEGASP_JP \
ROM_REGION16_BE(0x80, "sp_eeprom", ROMREGION_ERASEFF)
ROM_START( segasp )
SEGASP_BIOS
SEGASP_NETFIRM
SEGASP_MISC
ROM_REGION16_BE(0x80, "sp_eeprom", 0)
SEGASP_JP
SEGASPEE_US
SEGASPEE_EXP
ROM_REGION( 0x08000000, "rom_board", ROMREGION_ERASEFF)
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02))
ROM_REGION( 0x800, "pic_readout", ROMREGION_ERASE00 )
ROM_END
ROM_START( brickppl )
SEGASP_BIOS
SEGASP_EXP
ROM_DEFAULT_BIOS( "v201" )
SEGASP_JP
SEGASP_MISC
ROM_REGION( 0x10000000, "rom_board", ROMREGION_ERASE)
@ -327,6 +368,8 @@ ROM_START( brickppl )
ROM_LOAD( "ic64", 0x08000000, 0x4000000, CRC(383e90d9) SHA1(eeca4b1bd0cd1fed7b85f045d71e0c7258d4350b) )
ROM_LOAD( "ic65", 0x0c000000, 0x4000000, CRC(4c29b5ac) SHA1(9e6a79ad2d2498eed5b2590c8764222e7d6c0229) )
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
ROM_REGION( 0x800, "pic_readout", 0 )
ROM_LOAD( "317-0558-com.ic15", 0, 0x800, BAD_DUMP CRC(7592d004) SHA1(632373d807f54953d68c95a9f874ed3e8011f085) )
ROM_END
@ -346,6 +389,9 @@ ROM_START( dinoking )
ROM_LOAD( "ic68s", 0x06000000, 0x01000000, CRC(4a787a44) SHA1(4d8f348466187fb67ffff8605be151cea1f77ec6) )
ROM_LOAD( "ic69s", 0x07000000, 0x01000000, CRC(c78e46c2) SHA1(b8224c68face23010414d13ebb4cc05a2a9dce8a) )
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // actually 8x 128Mbit FlashROMs
ROM_REGION( 0x800, "pic_readout", 0 )
ROM_LOAD( "317-0408-com.ic15", 0, 0x800, BAD_DUMP CRC(0e94daba) SHA1(4e9722333a29afd0dbadba78b16344b77a689610) )
ROM_END
@ -365,12 +411,15 @@ ROM_START( dinokior )
ROM_LOAD( "ic68s", 0x06000000, 0x01000000, CRC(ff5ed2b8) SHA1(d8d86b3ed976c8c8fc51d225ae661e5f237b6e1d) )
ROM_LOAD( "ic69s", 0x07000000, 0x01000000, CRC(ab8ac4eb) SHA1(e6b3ce796ae4887011e2764261f3f437dc9939f9) )
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // actually 8x 128Mbit FlashROMs
ROM_REGION( 0x800, "pic_readout", 0 )
ROM_LOAD( "317-0408-com.ic15", 0, 0x800, BAD_DUMP CRC(0e94daba) SHA1(4e9722333a29afd0dbadba78b16344b77a689610) )
ROM_END
ROM_START( lovebery )
SEGASP_BIOS
ROM_DEFAULT_BIOS( "v201" )
SEGASP_EXP
SEGASP_MISC
@ -378,12 +427,23 @@ ROM_START( lovebery )
ROM_LOAD( "ic62", 0x00000000, 0x4000000, CRC(1bd80ed0) SHA1(d50307573389ebe71e381a75deb83811fa397b94) )
ROM_LOAD( "ic63", 0x04000000, 0x4000000, CRC(d3870287) SHA1(efd3630d54068f5a8caf242a48db410bedf48e7a) )
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
ROM_REGION( 0x800, "pic_readout", 0 )
ROM_LOAD( "317-0446-com.ic15", 0, 0x800, BAD_DUMP CRC(60f56bf2) SHA1(35e697aca7213e3fb1ebe75bb8991b1b992af6d9) )
// LOVE AND BERRY
// Dress up and Dance!
// Type-3
// 800
// note: this dump from "empty/dead" Management Chip with no game run count left
ROM_REGION( 0x80, "rf_tag", 0 )
ROM_LOAD( "berry_type3.bin", 0, 0x80, CRC(0c58aabd) SHA1(8e5d8c9fd2c84e93b442192682930cf4da3fcf79) )
ROM_END
ROM_START( lovebero )
SEGASP_BIOS
ROM_DEFAULT_BIOS( "v201" )
SEGASP_EXP
SEGASP_MISC
@ -391,19 +451,24 @@ ROM_START( lovebero )
ROM_LOAD( "ic62", 0x00000000, 0x4000000, CRC(0a23cea3) SHA1(1780d935b0d641769859b2022df8e4262e7bafd8) )
ROM_LOAD( "ic63", 0x04000000, 0x4000000, CRC(d3870287) SHA1(efd3630d54068f5a8caf242a48db410bedf48e7a) )
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
ROM_REGION( 0x800, "pic_readout", 0 )
ROM_LOAD( "317-0446-com.ic15", 0, 0x800, BAD_DUMP CRC(60f56bf2) SHA1(35e697aca7213e3fb1ebe75bb8991b1b992af6d9) )
ROM_END
ROM_START( tetgiant )
SEGASP_BIOS
SEGASP_EXP
ROM_DEFAULT_BIOS( "v201" )
SEGASP_JP
SEGASP_MISC
ROM_REGION( 0x08000000, "rom_board", ROMREGION_ERASE)
ROM_LOAD( "ic62", 0x00000000, 0x4000000, CRC(31ba1938) SHA1(9b5a05193b3df13cd7617a38913e0b0fbd61da44) )
ROM_LOAD( "ic63", 0x04000000, 0x4000000, CRC(cb946213) SHA1(6195e33c44a1e8eb464dfc3558dc1c9b4d910ef3) )
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // 2x 512Mbit FlashROMs
ROM_REGION( 0x800, "pic_readout", 0 )
ROM_LOAD( "317-0604-com.ic15", 0, 0x800, BAD_DUMP CRC(e8dd2b86) SHA1(765ffd2e4a36302b1db0815e842c9656e29f2457) )
ROM_END
@ -411,6 +476,7 @@ ROM_END
ROM_START( dinoki25 )
SEGASP_BIOS
ROM_DEFAULT_BIOS( "v200" )
SEGASP_EXP
SEGASP_MISC
@ -419,12 +485,22 @@ ROM_START( dinoki25 )
DISK_REGION( "cflash" )
DISK_IMAGE( "mda-c0047", 0, SHA1(0f97291d9c5dbe3e66a5220da05aebdfaa78b35d) )
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
ROM_REGION( 0x800, "pic_readout", 0 )
ROM_LOAD( "317-0408-com.ic15", 0, 0x800, BAD_DUMP CRC(0e94daba) SHA1(4e9722333a29afd0dbadba78b16344b77a689610) )
// DINOSAUR KING
// TYPE-3
// 800
// note: this dump from "empty/dead" Management Chip with no game run count left
ROM_REGION( 0x80, "rf_tag", 0 )
ROM_LOAD( "dino_type3.bin", 0, 0x80, CRC(1b6c9ea7) SHA1(2e56a1969c49c347f7facda187e5bf787c74328c) )
ROM_END
ROM_START( loveber3 )
SEGASP_BIOS
ROM_DEFAULT_BIOS( "v200" )
SEGASP_US
SEGASP_MISC
@ -433,13 +509,16 @@ ROM_START( loveber3 )
DISK_REGION( "cflash" )
DISK_IMAGE( "mda-c0042", 0, SHA1(9992d90dae8ce7636e4153e02b779c27931b3be6) )
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
ROM_REGION( 0x800, "pic_readout", 0 )
ROM_LOAD( "317-0446-com.ic15", 0, 0x800, BAD_DUMP CRC(60f56bf2) SHA1(35e697aca7213e3fb1ebe75bb8991b1b992af6d9) )
ROM_END
ROM_START( tetgiano )
SEGASP_BIOS
SEGASP_EXP
ROM_DEFAULT_BIOS( "v201" )
SEGASP_JP
SEGASP_MISC
ROM_REGION( 0x08000000, "rom_board", ROMREGION_ERASEFF)
@ -447,6 +526,8 @@ ROM_START( tetgiano )
DISK_REGION( "cflash" )
DISK_IMAGE( "mda-c0076", 0, SHA1(6987c888d2a3ada2d07f6396d47fdba507ca859d) )
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // 2x 512Mbit FlashROMs
ROM_REGION( 0x800, "pic_readout", 0 )
ROM_LOAD( "317-0604-com.ic15", 0, 0x800, BAD_DUMP CRC(e8dd2b86) SHA1(765ffd2e4a36302b1db0815e842c9656e29f2457) )
ROM_END

7
src/mame/drivers/ssv.c
View File

@ -411,11 +411,12 @@ READ16_MEMBER(ssv_state::fake_r){ return ssv_scroll[offset]; }
AM_RANGE(0x260000, 0x260001) AM_WRITE(irq_enable_w) /* IRQ En */ \
AM_RANGE(0x300000, 0x30007f) AM_DEVREADWRITE8("ensoniq", es5506_device, read, write, 0x00ff) /* Sound */ \
AM_RANGE(_ROM, 0xffffff) AM_ROM AM_REGION("maincpu", 0) /* ROM */
/***************************************************************************
Drift Out '94
***************************************************************************/
READ16_MEMBER(ssv_state::drifto94_rand_r)
READ16_MEMBER(ssv_state::drifto94_unknown_r)
{
return machine().rand() & 0xffff;
}
@ -427,8 +428,8 @@ static ADDRESS_MAP_START( drifto94_map, AS_PROGRAM, 16, ssv_state )
AM_RANGE(0x482000, 0x482fff) AM_READWRITE(dsp_r, dsp_w)
AM_RANGE(0x483000, 0x485fff) AM_WRITENOP // ?
AM_RANGE(0x500000, 0x500001) AM_WRITENOP // ??
AM_RANGE(0x510000, 0x510001) AM_READ(drifto94_rand_r ) // ??
AM_RANGE(0x520000, 0x520001) AM_READ(drifto94_rand_r ) // ??
AM_RANGE(0x510000, 0x510001) AM_READ(drifto94_unknown_r) // ??
AM_RANGE(0x520000, 0x520001) AM_READ(drifto94_unknown_r) // ??
AM_RANGE(0x580000, 0x5807ff) AM_RAM AM_SHARE("nvram") // NVRAM
SSV_MAP( 0xc00000 )
ADDRESS_MAP_END

41
src/mame/drivers/taitotx.c
View File

@ -23,58 +23,81 @@
- Taito's NESiCA Live platform probably comes after this, but as it's likely
impossible to ever emulate it.
- Prelim game lists (system16.com)
- Preliminary game lists (mainly from system16.com)
Taito Type X games
Chaos Breaker / Dark Awake
Datacarddass Dragon Ball Z
Dinoking III
Dinoking III Allosaurus
Dinomax
Dragon Quest Monster: Battle Road
Dragon Quest - Monster Battle Road
Dragon Quest - Monster Battle Road II Legends
Gigawing Generations
Goketsuji Ichizoku: Matsuri Senzo Kuyou
Harakari Professional Baseball
Homura
King Of Jurassic
KOF Sky Stage
Matrimelee Matsuri / Power Instinct V
Raiden III
Raiden IV
Shikigami No Shiro III / The Castle of Shikigami III
Spica Adventure
Taisen Hot Gimmick 5
Taisen Hot Gimmick Mix Party
Tetris The Grand Master 3 : Terror Instinct
Tetris The Grand Master 3 - Terror-Instinct
The King of Fighters 98 Ultimate Match
Trouble Witches
Trouble Witches AC
Usagi Online
Valve Limit R
Zoids Card Colosseum
Taito Type X+ games
Battle Gear 4
Battle Gear 4 Tuned
Half Life 2 Survivor
Mobile Suit Gundam - Spirits of Zeon Senshi no Kioku
War Of The Grail
Taito Type X2 games
Battle Fantasia
BlazBlue: Calamity Trigger
BlazBlue: Chrono Phantasma
BlazBlue: Continuum Shift
BlazBlue: Continuum Shift Extend
BlazBlue: Continuum Shift II
Chase H.Q. 2 / Chase H. Q. : Nancy Yori Kinkyuu Renraku
Chou Chabudai Gaeshi!
Chou Chabudai Gaeshi! 2
Chou Chabudai Gaeshi! Kyojin No Hoshi
Cyber Diver
D1GP Arcade
Dariusburst AC
Dariusburst - Another Chronicle
Dariusburst - Another Chronicle EX
Elevator Action Death Parade
Gunslinger Stratos
Half Life 2: Survivor Ver. 2.0
Haunted Museum / Panic Museum
Haunted Museum II / Panic Museum II
Hopping Kids
Hopping Road
KOF Maximum Impact: Regulation A
KOF Maximum Impact: Regulation A2
Lord Of Vermilion Re:2
Matrimelee Matsuri / Power Instinct V
P4U - Persona 4 The Ultimate In Mayonaka Arena
P4U - Persona 4 The Ultimax Ultra Suplex Hold
Samurai Spirits Sen / Samurai Shodown: Edge of Destiny
Senko no Ronde DUO : Dis-United Order
Street Fighter IV
Super Street Fighter IV Arcade Edition
The King of Fighters XII
The King of Fighters XIII
The King Of Fighters XIII Climax
Top Speed
Wacky Races
Taito Type X2 satellite terminal games
@ -82,7 +105,7 @@
Aquarian Age Alternative
Eternal Wheel
Lord of Vermilion
Lord of Vermilion II
Taito Type X Zero games

28
src/mame/drivers/thayers.c
View File

@ -75,8 +75,8 @@ public:
DECLARE_READ8_MEMBER(cop_g_r);
DECLARE_WRITE8_MEMBER(control_w);
DECLARE_WRITE8_MEMBER(cop_g_w);
DECLARE_READ8_MEMBER(cop_si_r);
DECLARE_WRITE8_MEMBER(cop_so_w);
DECLARE_READ_LINE_MEMBER(cop_si_r);
DECLARE_WRITE_LINE_MEMBER(cop_so_w);
DECLARE_WRITE8_MEMBER(control2_w);
DECLARE_READ8_MEMBER(dsw_b_r);
DECLARE_READ8_MEMBER(laserdsc_data_r);
@ -294,7 +294,7 @@ WRITE8_MEMBER(thayers_state::cop_g_w)
/* Keyboard */
READ8_MEMBER(thayers_state::cop_si_r)
READ_LINE_MEMBER(thayers_state::cop_si_r)
{
/* keyboard data */
@ -327,11 +327,11 @@ READ8_MEMBER(thayers_state::cop_si_r)
}
}
WRITE8_MEMBER(thayers_state::cop_so_w)
WRITE_LINE_MEMBER(thayers_state::cop_so_w)
{
/* keyboard clock */
if (data)
if (state)
{
m_rx_bit++;
@ -622,14 +622,6 @@ static ADDRESS_MAP_START( thayers_io_map, AS_IO, 8, thayers_state )
AM_RANGE(0xf7, 0xf7) AM_WRITE(den2_w)
ADDRESS_MAP_END
static ADDRESS_MAP_START( thayers_cop_io_map, AS_IO, 8, thayers_state )
AM_RANGE(COP400_PORT_L, COP400_PORT_L) AM_READWRITE(cop_l_r, cop_l_w)
AM_RANGE(COP400_PORT_G, COP400_PORT_G) AM_READWRITE(cop_g_r, cop_g_w)
AM_RANGE(COP400_PORT_D, COP400_PORT_D) AM_WRITE(cop_d_w)
AM_RANGE(COP400_PORT_SK, COP400_PORT_SK) AM_WRITENOP
AM_RANGE(COP400_PORT_SIO, COP400_PORT_SIO) AM_READ(cop_si_r) AM_WRITE(cop_so_w)
ADDRESS_MAP_END
/* Input Ports */
CUSTOM_INPUT_MEMBER(thayers_state::laserdisc_enter_r)
@ -780,15 +772,21 @@ void thayers_state::machine_reset()
/* Machine Driver */
static MACHINE_CONFIG_START( thayers, thayers_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", Z80, XTAL_4MHz)
MCFG_CPU_PROGRAM_MAP(thayers_map)
MCFG_CPU_IO_MAP(thayers_io_map)
MCFG_CPU_ADD("mcu", COP421, XTAL_4MHz/2) // COP421L-PCA/N
MCFG_CPU_IO_MAP(thayers_cop_io_map)
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_4, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_DISABLED )
MCFG_COP400_READ_L_CB(READ8(thayers_state, cop_l_r))
MCFG_COP400_WRITE_L_CB(WRITE8(thayers_state, cop_l_w))
MCFG_COP400_READ_G_CB(READ8(thayers_state, cop_g_r))
MCFG_COP400_WRITE_G_CB(WRITE8(thayers_state, cop_g_w))
MCFG_COP400_WRITE_D_CB(WRITE8(thayers_state, cop_d_w))
MCFG_COP400_READ_SI_CB(READLINE(thayers_state, cop_si_r))
MCFG_COP400_WRITE_SO_CB(WRITELINE(thayers_state, cop_so_w))
MCFG_LASERDISC_PR7820_ADD("laserdisc")

2
src/mame/includes/centiped.h
View File

@ -53,7 +53,7 @@ public:
DECLARE_WRITE8_MEMBER(led_w);
DECLARE_WRITE8_MEMBER(coin_count_w);
DECLARE_WRITE8_MEMBER(bullsdrt_coin_count_w);
DECLARE_READ8_MEMBER(caterplr_rand_r);
DECLARE_READ8_MEMBER(caterplr_unknown_r);
DECLARE_WRITE8_MEMBER(caterplr_AY8910_w);
DECLARE_READ8_MEMBER(caterplr_AY8910_r);
DECLARE_READ8_MEMBER(multiped_eeprom_r);

3
src/mame/includes/segasp.h
View File

@ -21,6 +21,9 @@ public:
DECLARE_READ64_MEMBER(sp_io_r);
DECLARE_READ64_MEMBER(sn_93c46a_r);
DECLARE_WRITE64_MEMBER(sn_93c46a_w);
DECLARE_READ64_MEMBER(sp_bank_r);
DECLARE_WRITE64_MEMBER(sp_bank_w);
UINT16 m_sp_bank;
protected:
};

2
src/mame/includes/ssv.h
View File

@ -76,7 +76,7 @@ public:
DECLARE_READ16_MEMBER(dsp_r);
DECLARE_WRITE16_MEMBER(dsp_w);
DECLARE_READ16_MEMBER(fake_r);
DECLARE_READ16_MEMBER(drifto94_rand_r);
DECLARE_READ16_MEMBER(drifto94_unknown_r);
DECLARE_READ16_MEMBER(gdfs_gfxram_r);
DECLARE_WRITE16_MEMBER(gdfs_gfxram_w);
DECLARE_READ16_MEMBER(gdfs_blitram_r);

7
src/mame/machine/awboard.c
View File

@ -257,11 +257,8 @@ void aw_rom_board::device_reset()
READ16_MEMBER(aw_rom_board::pio_r)
{
UINT16 retval;
if (epr_offset == 0x7fffff)
retval = adjust_off;
else
retval = m_region->u16(epr_offset * 2);
// FIXME: this must return original encrypted data, used by Extreme Hunt 2 in ROM TEST
UINT16 retval = m_region->u16(epr_offset * 2);
epr_offset++;
return retval;
}

12
src/mess/drivers/advision.c
View File

@ -42,14 +42,6 @@ static ADDRESS_MAP_START( io_map, AS_IO, 8, advision_state )
AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ(vsync_r)
ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_io_map, AS_IO, 8, advision_state )
AM_RANGE(COP400_PORT_L, COP400_PORT_L) AM_READ(sound_cmd_r)
AM_RANGE(COP400_PORT_G, COP400_PORT_G) AM_WRITE(sound_g_w)
AM_RANGE(COP400_PORT_D, COP400_PORT_D) AM_WRITE(sound_d_w)
AM_RANGE(COP400_PORT_SIO, COP400_PORT_SIO) AM_NOP
AM_RANGE(COP400_PORT_SK, COP400_PORT_SK) AM_NOP
ADDRESS_MAP_END
/* Input Ports */
static INPUT_PORTS_START( advision )
@ -74,7 +66,9 @@ static MACHINE_CONFIG_START( advision, advision_state )
MCFG_CPU_ADD(COP411_TAG, COP411, 52631*16) // COP411L-KCN/N
MCFG_COP400_CONFIG(COP400_CKI_DIVISOR_4, COP400_CKO_RAM_POWER_SUPPLY, COP400_MICROBUS_DISABLED)
MCFG_CPU_IO_MAP(sound_io_map)
MCFG_COP400_READ_L_CB(READ8(advision_state, sound_cmd_r))
MCFG_COP400_WRITE_G_CB(WRITE8(advision_state, sound_g_w))
MCFG_COP400_WRITE_D_CB(WRITE8(advision_state, sound_d_w))
/* video hardware */
MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)

4
src/mess/drivers/fidelz80.c
View File

@ -898,7 +898,7 @@ READ8_MEMBER(fidelz80_state::unknown_r)
return 0;
}
READ8_MEMBER(fidelz80_state::rand_r)
READ8_MEMBER(fidelz80_state::unknown2_r)
{
return machine().rand();
}
@ -1040,7 +1040,7 @@ static ADDRESS_MAP_START(bridgec_mcu_io, AS_IO, 8, fidelz80_state)
// related to the card scanner, probably clock and data optical
AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_READ(unknown_r)
AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ(rand_r)
AM_RANGE(MCS48_PORT_T1, MCS48_PORT_T1) AM_READ(unknown2_r)
ADDRESS_MAP_END
/******************************************************************************

1
src/mess/drivers/hh_hmcs40.c
View File

@ -58,6 +58,7 @@
- vinvader locks up at boot
- gckong random lockups (tap the jump button repeatedly): mcu stack overflow,
works ok if stack levels is increased, 38800 B rev. has more stack levels?
Or it could be a race condition: irq happening too late/early.
- epacman booting the game in demo mode, pacman should go straight to the
upper-left power pill: mcu cycle/interrupt timing related
- Though very uncommon when compared to games with LED/lamp display,

20
src/mess/drivers/hh_ucom4.c
View File

@ -57,7 +57,9 @@
#include "sound/speaker.h"
// internal artwork
#include "efball.lh"
#include "mvbfree.lh"
#include "hh_ucom4_test.lh" // test-layout - use external artwork
@ -1114,8 +1116,6 @@ MACHINE_CONFIG_END
- USA: Electronic Football (aka Pro-Bowl Football)
- Japan: American Football
NOTE!: MESS external artwork is recommended
***************************************************************************/
class efball_state : public hh_ucom4_state
@ -1169,20 +1169,20 @@ static INPUT_PORTS_START( efball )
PORT_CONFNAME( 0x02, 0x02, "Players" )
PORT_CONFSETTING( 0x02, "1" )
PORT_CONFSETTING( 0x00, "2" )
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P1 Down Field")
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_NAME("P1 Score/Time")
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_START ) PORT_NAME("P1 Down-Field")
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SELECT ) PORT_NAME("P1 Score-Time")
PORT_START("IN.1") // port B
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_16WAY
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_16WAY
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P1 Pass")
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON4 ) PORT_NAME("P1 Kick")
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_16WAY PORT_NAME("P1 Left/Right")
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("P1 Pass")
PORT_START("IN.2") // port C
PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_COCKTAIL PORT_16WAY
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_COCKTAIL PORT_16WAY
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_COCKTAIL PORT_NAME("P2 Return")
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_16WAY PORT_NAME("P1 Left/Right")
PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_COCKTAIL PORT_NAME("P2 Kick Return")
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("P1 Kick")
INPUT_PORTS_END
static MACHINE_CONFIG_START( efball, efball_state )
@ -1200,7 +1200,7 @@ static MACHINE_CONFIG_START( efball, efball_state )
MCFG_UCOM4_WRITE_I_CB(WRITE8(efball_state, plate_w))
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_ucom4_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_ucom4_test)
MCFG_DEFAULT_LAYOUT(layout_efball)
/* no video! */
@ -2446,7 +2446,7 @@ CONS( 1980, splasfgt, 0, 0, splasfgt, splasfgt, driver_device, 0, "Bambin
CONS( 1982, bcclimbr, 0, 0, bcclimbr, bcclimbr, driver_device, 0, "Bandai", "Crazy Climber (Bandai)", GAME_SUPPORTS_SAVE | GAME_REQUIRES_ARTWORK )
CONS( 1980, invspace, 0, 0, invspace, invspace, driver_device, 0, "Epoch", "Invader From Space", GAME_SUPPORTS_SAVE | GAME_REQUIRES_ARTWORK )
CONS( 1980, efball, 0, 0, efball, efball, driver_device, 0, "Epoch", "Electronic Football (Epoch)", GAME_SUPPORTS_SAVE | GAME_REQUIRES_ARTWORK )
CONS( 1980, efball, 0, 0, efball, efball, driver_device, 0, "Epoch", "Electronic Football (Epoch)", GAME_SUPPORTS_SAVE )
CONS( 1981, galaxy2, 0, 0, galaxy2, galaxy2, driver_device, 0, "Epoch", "Galaxy II", GAME_SUPPORTS_SAVE | GAME_REQUIRES_ARTWORK )
CONS( 1982, astrocmd, 0, 0, astrocmd, astrocmd, driver_device, 0, "Epoch", "Astro Command", GAME_SUPPORTS_SAVE | GAME_REQUIRES_ARTWORK )
CONS( 1982, edracula, 0, 0, edracula, edracula, driver_device, 0, "Epoch", "Dracula (Epoch)", GAME_SUPPORTS_SAVE | GAME_REQUIRES_ARTWORK )

22
src/mess/drivers/lisa.c
View File

@ -23,26 +23,6 @@ static ADDRESS_MAP_START(lisa_map, AS_PROGRAM, 16, lisa_state )
AM_RANGE(0x000000, 0xffffff) AM_READWRITE(lisa_r, lisa_w) /* no fixed map, we use an MMU */
ADDRESS_MAP_END
static ADDRESS_MAP_START( lisa_cop_io_map, AS_IO, 8, lisa_state )
AM_RANGE(COP400_PORT_L, COP400_PORT_L) AM_NOP
AM_RANGE(COP400_PORT_G, COP400_PORT_G) AM_NOP
AM_RANGE(COP400_PORT_D, COP400_PORT_D) AM_NOP
AM_RANGE(COP400_PORT_IN, COP400_PORT_IN) AM_NOP
AM_RANGE(COP400_PORT_SK, COP400_PORT_SK) AM_WRITENOP
AM_RANGE(COP400_PORT_SIO, COP400_PORT_SIO) AM_NOP
AM_RANGE(COP400_PORT_CKO, COP400_PORT_CKO) AM_READNOP
ADDRESS_MAP_END
static ADDRESS_MAP_START( kb_cop_io_map, AS_IO, 8, lisa_state )
AM_RANGE(COP400_PORT_L, COP400_PORT_L) AM_NOP
AM_RANGE(COP400_PORT_G, COP400_PORT_G) AM_NOP
AM_RANGE(COP400_PORT_D, COP400_PORT_D) AM_NOP
AM_RANGE(COP400_PORT_IN, COP400_PORT_IN) AM_NOP
AM_RANGE(COP400_PORT_SK, COP400_PORT_SK) AM_WRITENOP
AM_RANGE(COP400_PORT_SIO, COP400_PORT_SIO) AM_NOP
AM_RANGE(COP400_PORT_CKO, COP400_PORT_CKO) AM_READNOP
ADDRESS_MAP_END
static ADDRESS_MAP_START(lisa_fdc_map, AS_PROGRAM, 8, lisa_state )
ADDRESS_MAP_GLOBAL_MASK(0x1fff) // only 8k of address space
AM_RANGE(0x0000, 0x03ff) AM_RAM AM_SHARE("fdc_ram") /* RAM (shared with 68000) */
@ -120,11 +100,9 @@ static MACHINE_CONFIG_START( lisa, lisa_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", lisa_state, lisa_interrupt)
MCFG_CPU_ADD(COP421_TAG, COP421, 3900000)
MCFG_CPU_IO_MAP(lisa_cop_io_map)
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED )
MCFG_CPU_ADD(KB_COP421_TAG, COP421, 3900000) // ?
MCFG_CPU_IO_MAP(kb_cop_io_map)
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED )
MCFG_CPU_ADD("fdccpu", M6504, 2000000) /* 16.000 MHz / 8 in when DIS asserted, 16.000 MHz / 9 otherwise (?) */

67
src/mess/drivers/m24.c
View File

@ -5,6 +5,7 @@
#include "bus/isa/isa.h"
#include "bus/isa/isa_cards.h"
#include "machine/m24_kbd.h"
#include "machine/m24_z8000.h"
#include "machine/mm58274c.h"
#include "includes/genpc.h"
@ -16,12 +17,14 @@ public:
m_maincpu(*this, "maincpu"),
m_mb(*this, "mb"),
m_kbc(*this, "kbc"),
m_keyboard(*this, "keyboard")
m_keyboard(*this, "keyboard"),
m_z8000_apb(*this, "z8000_apb")
{ }
required_device<cpu_device> m_maincpu;
required_device<pc_noppi_mb_device> m_mb;
required_device<cpu_device> m_kbc;
required_device<m24_keyboard_device> m_keyboard;
optional_device<m24_z8000_device> m_z8000_apb;
DECLARE_READ8_MEMBER(keyboard_r);
DECLARE_WRITE8_MEMBER(keyboard_w);
@ -30,11 +33,14 @@ public:
DECLARE_READ8_MEMBER(kbcdata_r);
DECLARE_WRITE8_MEMBER(kbcdata_w);
DECLARE_WRITE_LINE_MEMBER(kbcin_w);
DECLARE_WRITE_LINE_MEMBER(dma_hrq_w);
DECLARE_WRITE_LINE_MEMBER(int_w);
DECLARE_WRITE_LINE_MEMBER(halt_i86_w);
void machine_reset();
UINT8 m_sysctl, m_pa, m_kbcin, m_kbcout;
bool m_kbcibf, m_kbdata;
bool m_kbcibf, m_kbdata, m_i86_halt, m_i86_halt_perm;
};
void m24_state::machine_reset()
@ -43,6 +49,10 @@ void m24_state::machine_reset()
m_pa = 0x40;
m_kbcibf = false;
m_kbdata = true;
m_i86_halt = false;
m_i86_halt_perm = false;
if(m_z8000_apb)
m_z8000_apb->m_z8000->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
}
READ8_MEMBER(m24_state::keyboard_r)
@ -58,7 +68,7 @@ READ8_MEMBER(m24_state::keyboard_r)
case 2:
return 0;
case 4:
return m_kbcibf ? 2 : 0;
return (m_kbcibf ? 2 : 0) | ((m_pa & 0x40) ? 0 : 1);
}
return 0xff;
}
@ -81,6 +91,10 @@ WRITE8_MEMBER(m24_state::keyboard_w)
else
m_pa &= ~4;
break;
case 5:
m_maincpu->set_input_line(INPUT_LINE_HALT, (data & 0x40) ? ASSERT_LINE : CLEAR_LINE);
m_i86_halt = true;
m_i86_halt_perm = true;
}
}
@ -115,6 +129,33 @@ WRITE_LINE_MEMBER(m24_state::kbcin_w)
m_kbdata = state;
}
WRITE_LINE_MEMBER(m24_state::dma_hrq_w)
{
if(!m_i86_halt)
m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
if(m_z8000_apb && !m_z8000_apb->halted())
m_z8000_apb->m_z8000->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
/* Assert HLDA */
m_mb->m_dma8237->hack_w(state);
}
WRITE_LINE_MEMBER(m24_state::int_w)
{
if(!m_i86_halt)
m_maincpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
if(m_z8000_apb && !m_z8000_apb->halted())
m_z8000_apb->m_z8000->set_input_line(INPUT_LINE_IRQ1, state ? ASSERT_LINE : CLEAR_LINE);
}
WRITE_LINE_MEMBER(m24_state::halt_i86_w)
{
if(m_i86_halt_perm)
return;
m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
m_i86_halt = state ? true : false;
}
static ADDRESS_MAP_START( m24_map, AS_PROGRAM, 16, m24_state )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x00000, 0x9ffff) AM_RAMBANK("bank10")
@ -127,6 +168,7 @@ static ADDRESS_MAP_START(m24_io, AS_IO, 16, m24_state )
AM_RANGE(0x0060, 0x0065) AM_READWRITE8(keyboard_r, keyboard_w, 0xffff)
AM_RANGE(0x0066, 0x0067) AM_READ_PORT("DSW0")
AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("mm58174an", mm58274c_device, read, write, 0xffff)
AM_RANGE(0x80c0, 0x80c1) AM_DEVREADWRITE8("z8000_apb", m24_z8000_device, handshake_r, handshake_w, 0xff00)
ADDRESS_MAP_END
static ADDRESS_MAP_START(kbc_map, AS_PROGRAM, 8, m24_state)
@ -191,10 +233,14 @@ static MACHINE_CONFIG_START( olivetti, m24_state )
MCFG_PCNOPPI_MOTHERBOARD_ADD("mb", "maincpu")
MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", pc_isa8_cards, "cga", false)
MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", pc_isa8_cards, "fdc_xt", false)
MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", pc_isa8_cards, "lpt", false)
MCFG_ISA8_SLOT_ADD("mb:isa", "isa4", pc_isa8_cards, "com", false)
MCFG_ISA8_SLOT_ADD("mb:isa", "mb1", pc_isa8_cards, "cga_m24", true)
MCFG_ISA8_SLOT_ADD("mb:isa", "mb2", pc_isa8_cards, "fdc_xt", true)
MCFG_ISA8_SLOT_ADD("mb:isa", "mb3", pc_isa8_cards, "lpt", true)
MCFG_ISA8_SLOT_ADD("mb:isa", "mb4", pc_isa8_cards, "com", true)
MCFG_ISA8_SLOT_ADD("mb:isa", "isa1", pc_isa8_cards, NULL, false)
MCFG_ISA8_SLOT_ADD("mb:isa", "isa2", pc_isa8_cards, NULL, false)
MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", pc_isa8_cards, NULL, false)
/* internal ram */
MCFG_RAM_ADD(RAM_TAG)
@ -211,6 +257,13 @@ static MACHINE_CONFIG_START( olivetti, m24_state )
MCFG_MM58274C_MODE24(1) // ?
MCFG_MM58274C_DAY1(1) // ?
MCFG_DEVICE_ADD("z8000_apb", M24_Z8000, 0)
MCFG_M24_Z8000_HALT(WRITELINE(m24_state, halt_i86_w))
MCFG_DEVICE_MODIFY("mb:dma8237")
MCFG_I8237_OUT_HREQ_CB(DEVWRITELINE(":", m24_state, dma_hrq_w))
MCFG_DEVICE_MODIFY("mb:pic8259")
devcb = &pic8259_device::static_set_out_int_callback(*device, DEVCB_DEVWRITELINE(":", m24_state, int_w));
/* software lists */
MCFG_SOFTWARE_LIST_ADD("disk_list","ibm5150")
MACHINE_CONFIG_END

28
src/mess/drivers/newbrain.c
View File

@ -492,20 +492,20 @@ READ8_MEMBER( newbrain_state::cop_in_r )
return (m_cop_wr << 3) | (m_cop_access << 2) | (m_cop_rd << 1) | BIT(m_keydata, 2);
}
WRITE8_MEMBER( newbrain_state::cop_so_w )
WRITE_LINE_MEMBER( newbrain_state::cop_so_w )
{
// connected to K1
m_cop_so = data;
m_cop_so = state;
}
WRITE8_MEMBER( newbrain_state::cop_sk_w )
WRITE_LINE_MEMBER( newbrain_state::cop_sk_w )
{
// connected to K2
m_segment_data[m_keylatch] >>= 1;
m_segment_data[m_keylatch] = (m_cop_so << 15) | (m_segment_data[m_keylatch] & 0x7fff);
}
READ8_MEMBER( newbrain_state::cop_si_r )
READ_LINE_MEMBER( newbrain_state::cop_si_r )
{
// connected to TDI
m_cop_tdi = (((m_cassette1)->input() > +1.0) || ((m_cassette2)->input() > +1.0)) ^ m_cop_tdo;
@ -1019,16 +1019,6 @@ static ADDRESS_MAP_START( newbrain_a_io_map, AS_IO, 8, newbrain_state )
AM_RANGE(0x16, 0x16) AM_MIRROR(0xffc0) AM_READ(user_r)
ADDRESS_MAP_END
static ADDRESS_MAP_START( newbrain_cop_io_map, AS_IO, 8, newbrain_state )
AM_RANGE(COP400_PORT_L, COP400_PORT_L) AM_READWRITE(cop_l_r, cop_l_w)
AM_RANGE(COP400_PORT_G, COP400_PORT_G) AM_READWRITE(cop_g_r, cop_g_w)
AM_RANGE(COP400_PORT_D, COP400_PORT_D) AM_WRITE(cop_d_w)
AM_RANGE(COP400_PORT_IN, COP400_PORT_IN) AM_READ(cop_in_r)
AM_RANGE(COP400_PORT_SK, COP400_PORT_SK) AM_WRITE(cop_sk_w)
AM_RANGE(COP400_PORT_SIO, COP400_PORT_SIO) AM_READWRITE(cop_si_r, cop_so_w)
AM_RANGE(COP400_PORT_CKO, COP400_PORT_CKO) AM_READNOP
ADDRESS_MAP_END
static ADDRESS_MAP_START( newbrain_fdc_map, AS_PROGRAM, 8, newbrain_eim_state )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x0000, 0x1fff) AM_ROM
@ -1321,8 +1311,16 @@ static MACHINE_CONFIG_START( newbrain_a, newbrain_state )
MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_TAG, newbrain_state, newbrain_interrupt)
MCFG_CPU_ADD(COP420_TAG, COP420, XTAL_16MHz/8) // COP420-GUW/N
MCFG_CPU_IO_MAP(newbrain_cop_io_map)
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED )
MCFG_COP400_READ_L_CB(READ8(newbrain_state, cop_l_r))
MCFG_COP400_WRITE_L_CB(WRITE8(newbrain_state, cop_l_w))
MCFG_COP400_READ_G_CB(READ8(newbrain_state, cop_g_r))
MCFG_COP400_WRITE_G_CB(WRITE8(newbrain_state, cop_g_w))
MCFG_COP400_WRITE_D_CB(WRITE8(newbrain_state, cop_d_w))
MCFG_COP400_READ_IN_CB(READ8(newbrain_state, cop_in_r))
MCFG_COP400_WRITE_SK_CB(WRITELINE(newbrain_state, cop_sk_w))
MCFG_COP400_READ_SI_CB(READLINE(newbrain_state, cop_si_r))
MCFG_COP400_WRITE_SO_CB(WRITELINE(newbrain_state, cop_so_w))
MCFG_GFXDECODE_ADD("gfxdecode", "palette", newbrain)

2
src/mess/drivers/rvoice.c
View File

@ -1,3 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Jonathan Gevaryahu, Kevin Horton
/******************************************************************************
*
* Bare bones Realvoice PC driver

11
src/mess/drivers/test_t400.c
View File

@ -27,23 +27,16 @@ WRITE8_MEMBER( t400_test_suite_state::port_l_w )
// printf("L: %u\n", data);
}
static ADDRESS_MAP_START( cop_io, AS_IO, 8, t400_test_suite_state )
AM_RANGE(COP400_PORT_L, COP400_PORT_L) AM_WRITE(port_l_w)
AM_RANGE(COP400_PORT_SK, COP400_PORT_SK) AM_NOP
AM_RANGE(COP400_PORT_SIO, COP400_PORT_SIO) AM_NOP
AM_RANGE(COP400_PORT_CKO, COP400_PORT_CKO) AM_NOP
ADDRESS_MAP_END
static MACHINE_CONFIG_START( test_t410, t400_test_suite_state )
MCFG_CPU_ADD("maincpu", COP410, 1000000)
MCFG_CPU_IO_MAP(cop_io)
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED )
MCFG_COP400_WRITE_L_CB(WRITE8(t400_test_suite_state, port_l_w))
MACHINE_CONFIG_END
static MACHINE_CONFIG_START( test_t420, t400_test_suite_state )
MCFG_CPU_ADD("maincpu", COP420, 1000000)
MCFG_CPU_IO_MAP(cop_io)
MCFG_COP400_CONFIG( COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED )
MCFG_COP400_WRITE_L_CB(WRITE8(t400_test_suite_state, port_l_w))
MACHINE_CONFIG_END
ROM_START( test410 )

43
src/mess/drivers/vt100.c
View File

@ -564,13 +564,16 @@ MACHINE_CONFIG_END
* The AVO itself can hold up to four character set roms on it (see http://www.bitsavers.org/pdf/dec/terminal/vt100/MP00633_VT100_Mar80.pdf
and http://vt100.net/dec/ek-vt1ac-ug-002.pdf )
at least eight of these AVO roms were made, and are used as such:
at least sixteen of these AVO roms were made, and are used as such:
(based on EK-VT100-TM-003_VT100_Technical_Manual_Jul82.pdf)
* No roms - normal vt100 system with AVO installed
* 23-069E2 (location e21) - meant for vt100-wa and -wb 'LA120' 'word processing' systems (the mapping of the rom for this system is different than for the ones below)
* 23-099E2 (location e21) and 23-100E2 (location e17) - meant for vt132
* 23-099E2 (location e21) and 23-100E2 (location e17) - meant for vt132 but only with the OLD vt132 main romset of 095,096,097,098E2
* 23-093E2 (location e21) - meant for vt100 wc through wz 'foreign language' word processing systems
* 23-184E2 and 23-185E2 - meant for vt100 with STP printer option board installed, version 1, comes with vt1xx-ac kit
* 23-186E2 and 23-187E2 - meant for vt100 with STP printer option board installed, version 2, comes with vt1xx-ac kit
* 23-224E2, 23-225E2, 23-226E2, 23-227E2 - meant for vt132 but only with the NEW vt132 main romset of 180,181,182,183E2
* 23-236E2, 23-237E2, 23-238E2, 23-239E2 - meant for vt132 but only with the NEW vt132 main romset of 180,181,182,183E2, unknown difference to above (PROM VS MASK ROM? same contents?)
*/
/* ROM definition */
@ -596,7 +599,7 @@ ROM_END
ROM_START( vt100wp ) // This is from the schematics at http://www.bitsavers.org/pdf/dec/terminal/vt100/MP00633_VT100_Mar80.pdf
// This is the standard vt100 cpu board, with the ?word processing? romset, included in the VT1xx-CE kit?
// the vt103 can also use this rom set (-04 and -05 revs have it by default, -05 rev also has the optional alt charset rom by default)
// NOTE: this is actually the same as the VT132 romset; vt132 has different AVO roms as well.
// NOTE: this is actually the same as the newer VT132 romset; vt132 has different AVO roms as well.
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
ROM_LOAD( "23-180e2-00.e56", 0x0000, 0x0800, NO_DUMP)
ROM_LOAD( "23-181e2-00.e52", 0x0800, 0x0800, NO_DUMP)
@ -618,16 +621,34 @@ ROM_START( vt132 ) // This is from anecdotal evidence and vt100.net, as the vt13
// but is pretty much confirmed by page 433 in http://bitsavers.trailing-edge.com/www.computer.museum.uq.edu.au/pdf/EK-VT100-TM-003%20VT100%20Series%20Video%20Terminal%20Technical%20Manual.pdf
// VT100 board with block serial roms, AVO with special roms, STP, custom firmware with block serial mode
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
// OLDER vt132 romset
ROM_LOAD( "23-095e2-00.e56", 0x0000, 0x0800, NO_DUMP)
ROM_LOAD( "23-096e2-00.e52", 0x0800, 0x0800, NO_DUMP)
ROM_LOAD( "23-097e2-00.e45", 0x1000, 0x0800, NO_DUMP)
ROM_LOAD( "23-098e2-00.e40", 0x1800, 0x0800, NO_DUMP)
// NEWER vt132 (and STP?) romset
ROM_LOAD( "23-180e2-00.e56", 0x0000, 0x0800, NO_DUMP)
ROM_LOAD( "23-181e2-00.e52", 0x0800, 0x0800, NO_DUMP)
ROM_LOAD( "23-182e2-00.e45", 0x1000, 0x0800, NO_DUMP)
ROM_LOAD( "23-183e2-00.e40", 0x1800, 0x0800, NO_DUMP)
// AVO roms for OLDER romset only
ROM_REGION(0x1000, "avo", 0)
ROM_LOAD( "23-236e2-00.bin", 0x0000, 0x0800, NO_DUMP)
ROM_LOAD( "23-237e2-00.bin", 0x0800, 0x0800, NO_DUMP)
ROM_LOAD( "23-238e2-00.bin", 0x1000, 0x0800, NO_DUMP)
ROM_LOAD( "23-239e2-00.bin", 0x1800, 0x0800, NO_DUMP)
ROM_LOAD( "23-099e2-00.e21", 0x0000, 0x0800, NO_DUMP)
ROM_LOAD( "23-100e2-00.e17", 0x0800, 0x0800, NO_DUMP)
// other 2 sockets are empty
// AVO roms for NEWER romset only
ROM_LOAD( "23-224e2-00.e21", 0x0000, 0x0800, NO_DUMP)
ROM_LOAD( "23-225e2-00.e17", 0x0800, 0x0800, NO_DUMP)
ROM_LOAD( "23-226e2-00.e15", 0x1000, 0x0800, NO_DUMP) // loc is a guess
ROM_LOAD( "23-227e2-00.e13", 0x1800, 0x0800, NO_DUMP) // loc is a guess
// alt rev of newer avo roms, tech manual implies above are PROMS below are MASK ROMS? same data?
ROM_LOAD( "23-236e2-00.e21", 0x0000, 0x0800, NO_DUMP)
ROM_LOAD( "23-237e2-00.e17", 0x0800, 0x0800, NO_DUMP)
ROM_LOAD( "23-238e2-00.e15", 0x1000, 0x0800, NO_DUMP) // loc is a guess
ROM_LOAD( "23-239e2-00.e13", 0x1800, 0x0800, NO_DUMP) // loc is a guess
ROM_REGION(0x1000, "chargen", 0)
ROM_LOAD( "23-018e2-00.e4", 0x0000, 0x0800, CRC(6958458b) SHA1(103429674fc01c215bbc2c91962ae99231f8ae53))
@ -636,7 +657,7 @@ ROM_END
ROM_START( vt100stp ) // This is from the VT180 technical manual at http://www.bitsavers.org/pdf/dec/terminal/vt180/EK-VT18X-TM-001_VT180_Technical_Man_Feb83.pdf
// This is the standard vt100 cpu board, but with the rom set included with the VT1xx-AC kit
// which is only used when the STP 'printer port expansion' card is installed into the terminal board.
// which is only used when the part 54-14260-00 STP 'printer port expansion' card is installed into the terminal board.
// Or as http://bitsavers.trailing-edge.com/www.computer.museum.uq.edu.au/pdf/EK-VT100-TM-003%20VT100%20Series%20Video%20Terminal%20Technical%20Manual.pdf
// on page 433: VT100 WC or WK uses these as well.
// This romset adds the Set-up C page to the setup menu (press keypad 5 twice once you hit set-up)
@ -720,8 +741,8 @@ ROM_END
ROM_START( vt125 ) // This is from bitsavers and vt100.net, as the vt125 schematics are not scanned
// This is the standard VT100 cpu board with the 'normal' roms (but later rev of eprom 0) populated but with a
// special "GPO" ReGIS cpu+ram card installed which provides a framebuffer, text rotation, custom ram fonts, and many other features.
// Comes with a custom STP card as well.
// special "GPO" ReGIS cpu+ram card 54-14277 installed which provides a framebuffer, text rotation, custom ram fonts, and many other features.
// Comes with a custom 'dumb' STP card 54-14275 as well.
// VT125 upgrade kit (upgrade from vt100 or vt105) was called VT1xx-CB or CL
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
ROM_LOAD( "23-061e2-00.e56", 0x0000, 0x0800, CRC(3dae97ff) SHA1(e3437850c33565751b86af6c2fe270a491246d15)) // version 2 1980 'later rom'
@ -736,7 +757,7 @@ ROM_START( vt125 ) // This is from bitsavers and vt100.net, as the vt125 schemat
// "GPO" aka vt125 "mono board" roms and proms
ROM_REGION(0x10000, "monocpu", ROMREGION_ERASEFF) // roms for the 8085 subcpu
ROM_LOAD( "23-043e4-00.e22", 0x0000, 0x2000, NO_DUMP) // 2364/MK36xxx mask rom
ROM_LOAD( "23-043e4-00.e23", 0x2000, 0x2000, NO_DUMP) // 2364/MK36xxx mask rom
ROM_LOAD( "23-044e4-00.e23", 0x2000, 0x2000, NO_DUMP) // 2364/MK36xxx mask rom
ROM_LOAD( "23-045e4-00.e24", 0x4000, 0x2000, NO_DUMP) // 2364/MK36xxx mask rom
// E25 socket is empty

6
src/mess/drivers/vt320.c
View File

@ -105,7 +105,11 @@ MACHINE_CONFIG_END
/* ROM definition */
ROM_START( vt320 )
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
ROM_LOAD( "23-054e7.bin", 0x0000, 0x10000, CRC(be98f9a4) SHA1(b8044d42ffaadb734fbd047fbca9c8aadeb0bf6c))
ROM_DEFAULT_BIOS( "vt320" )
ROM_SYSTEM_BIOS( 0, "vt320o", "VT320 older version" )
ROMX_LOAD( "23-054e7.e9", 0x0000, 0x10000, CRC(be98f9a4) SHA1(b8044d42ffaadb734fbd047fbca9c8aadeb0bf6c), ROM_BIOS(1))
ROM_SYSTEM_BIOS( 1, "vt320", "VT320 newer version" )
ROMX_LOAD( "23-104e7.e9", 0x0000, 0x10000, CRC(5f419b5a) SHA1(dbc429b32d6baefd8a56862717d6e7fea1fb0c1c), ROM_BIOS(2))
ROM_END
/* Driver */

2
src/mess/drivers/vt520.c
View File

@ -31,7 +31,7 @@ static ADDRESS_MAP_START(vt520_mem, AS_PROGRAM, 8, vt520_state)
ADDRESS_MAP_END
/*
On the boardthere is TC160G41AF (1222) custom chip
On the board there is TC160G41AF (1222) custom chip
doing probably all video/uart logic
there is 43.430MHz xtal near by
*/

4
src/mess/drivers/zrt80.c
View File

@ -302,7 +302,7 @@ static MACHINE_CONFIG_START( zrt80, zrt80_state )
MCFG_MC6845_UPDATE_ROW_CB(zrt80_state, crtc_update_row)
MCFG_DEVICE_ADD( "ins8250", INS8250, 2457600 )
MCFG_INS8250_OUT_RTS_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
MCFG_INS8250_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
MCFG_DEVICE_ADD(KEYBOARD_TAG, GENERIC_KEYBOARD, 0)
MCFG_GENERIC_KEYBOARD_CB(WRITE8(zrt80_state, kbd_put))
MACHINE_CONFIG_END
@ -319,5 +319,5 @@ ROM_END
/* Driver */
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
COMP( 1982, zrt80, 0, 0, zrt80, zrt80, driver_device, 0, "Digital Research Computers", "ZRT-80", 0)

2
src/mess/includes/fidelz80.h
View File

@ -53,9 +53,9 @@ public:
DECLARE_WRITE8_MEMBER(bridgec_speech_w );
DECLARE_WRITE8_MEMBER(kp_matrix_w);
DECLARE_READ8_MEMBER(unknown_r);
DECLARE_READ8_MEMBER(unknown2_r);
DECLARE_READ8_MEMBER(exp_i8243_p2_r);
DECLARE_WRITE8_MEMBER(exp_i8243_p2_w);
DECLARE_READ8_MEMBER(rand_r);
DECLARE_WRITE8_MEMBER(mcu_data_w);
DECLARE_WRITE8_MEMBER(mcu_command_w);
DECLARE_READ8_MEMBER(mcu_data_r);

6
src/mess/includes/newbrain.h
View File

@ -103,9 +103,9 @@ public:
DECLARE_READ8_MEMBER( cop_g_r );
DECLARE_WRITE8_MEMBER( cop_d_w );
DECLARE_READ8_MEMBER( cop_in_r );
DECLARE_WRITE8_MEMBER( cop_sk_w );
DECLARE_READ8_MEMBER( cop_si_r );
DECLARE_WRITE8_MEMBER( cop_so_w );
DECLARE_WRITE_LINE_MEMBER( cop_sk_w );
DECLARE_READ_LINE_MEMBER( cop_si_r );
DECLARE_WRITE_LINE_MEMBER( cop_so_w );
DECLARE_READ8_MEMBER( tvl_r );
DECLARE_WRITE8_MEMBER( tvl_w );
DECLARE_WRITE8_MEMBER( tvctl_w );

279
src/mess/layout/efball.lay Normal file
View File

@ -0,0 +1,279 @@
<?xml version="1.0"?>
<mamelayout version="2">
<!-- define elements -->
<element name="static_black"><rect><color red="0.0" green="0.0" blue="0.0" /></rect></element>
<element name="static_white"><rect><color red="0.81" green="0.82" blue="0.81" /></rect></element>
<element name="static_green"><rect><color red="0.03" green="0.7" blue="0.22" /></rect></element>
<element name="text_down">
<rect><color red="0.81" green="0.82" blue="0.81" /></rect>
<text string="DOWN"><color red="0.16" green="0.17" blue="0.16" /></text>
</element>
<element name="text_home">
<rect><color red="0.81" green="0.82" blue="0.81" /></rect>
<text string="HOME"><color red="0.16" green="0.17" blue="0.16" /></text>
</element>
<element name="text_yards">
<rect><color red="0.81" green="0.82" blue="0.81" /></rect>
<text string="YARDS TO GO"><color red="0.16" green="0.17" blue="0.16" /></text>
</element>
<element name="text_time">
<rect><color red="0.81" green="0.82" blue="0.81" /></rect>
<text string="TIME REMAINING"><color red="0.16" green="0.17" blue="0.16" /></text>
</element>
<element name="text_field">
<rect><color red="0.81" green="0.82" blue="0.81" /></rect>
<text string="FIELD POSITION"><color red="0.16" green="0.17" blue="0.16" /></text>
</element>
<element name="text_visitor">
<rect><color red="0.81" green="0.82" blue="0.81" /></rect>
<text string="VISITOR"><color red="0.16" green="0.17" blue="0.16" /></text>
</element>
<element name="text_10"><text string="10"><color red="0.83" green="0.84" blue="0.83" /></text></element>
<element name="text_20"><text string="20"><color red="0.83" green="0.84" blue="0.83" /></text></element>
<element name="text_30"><text string="30"><color red="0.83" green="0.84" blue="0.83" /></text></element>
<element name="text_40"><text string="40"><color red="0.83" green="0.84" blue="0.83" /></text></element>
<element name="text_50"><text string="50"><color red="0.83" green="0.84" blue="0.83" /></text></element>
<!-- 7segs are not italic here, so let's make custom ones -->
<element name="seg" defstate="0">
<rect state="0"><color red="0.1" green="0.1" blue="0.1" /></rect>
<rect state="1"><color red="0.2" green="1.0" blue="0.9" /></rect>
</element>
<element name="led" defstate="0">
<disk state="0"><color red="0.1" green="0.1" blue="0.1" /></disk>
<disk state="1"><color red="0.2" green="1.0" blue="0.9" /></disk>
</element>
<element name="ind" defstate="0">
<text state="0" string="^"><color red="0.1" green="0.1" blue="0.1" /></text>
<text state="1" string="^"><color red="0.2" green="1.0" blue="0.9" /></text>
</element>
<!-- build screen -->
<view name="Internal Layout">
<bounds left="-8" right="298" top="-46" bottom="121" />
<bezel element="static_green">
<bounds left="-8" right="298" top="-46" bottom="121" />
</bezel>
<!-- outer bezel -->
<bezel element="static_white"><bounds left="-8" right="298" top="-42" bottom="117" /></bezel>
<bezel element="static_green"><bounds left="-8" right="298" top="-22" bottom="-20" /></bezel>
<bezel element="static_green"><bounds left="-8" right="298" top="95" bottom="97" /></bezel>
<bezel element="static_black"><bounds left="-5" right="295" top="-3" bottom="78" /></bezel>
<bezel element="static_black"><bounds x="-5" y="-17" width="300" height="12" /></bezel>
<bezel element="static_black"><bounds x="-5" y="80" width="300" height="12" /></bezel>
<bezel element="text_10"><bounds x="10" y="-17" width="30" height="12" /></bezel>
<bezel element="text_20"><bounds x="40" y="-17" width="30" height="12" /></bezel>
<bezel element="text_30"><bounds x="70" y="-17" width="30" height="12" /></bezel>
<bezel element="text_40"><bounds x="100" y="-17" width="30" height="12" /></bezel>
<bezel element="text_50"><bounds x="130" y="-17" width="30" height="12" /></bezel>
<bezel element="text_40"><bounds x="160" y="-17" width="30" height="12" /></bezel>
<bezel element="text_30"><bounds x="190" y="-17" width="30" height="12" /></bezel>
<bezel element="text_20"><bounds x="220" y="-17" width="30" height="12" /></bezel>
<bezel element="text_10"><bounds x="250" y="-17" width="30" height="12" /></bezel>
<bezel element="text_down"><bounds x="-5" y="-39" width="74" height="14" /></bezel>
<bezel element="text_field"><bounds x="71" y="-39" width="148" height="14" /></bezel>
<bezel element="text_yards"><bounds x="221" y="-39" width="77" height="14" /></bezel>
<bezel element="text_home"><bounds x="-5" y="100" width="74" height="14" /></bezel>
<bezel element="text_time"><bounds x="71" y="100" width="148" height="14" /></bezel>
<bezel element="text_visitor"><bounds x="221" y="100" width="77" height="14" /></bezel>
<bezel element="static_green"><bounds x="69" y="-43" width="2" height="22" /></bezel>
<bezel element="static_green"><bounds x="69" y="96" width="2" height="22" /></bezel>
<bezel element="static_green"><bounds x="219" y="-43" width="2" height="22" /></bezel>
<bezel element="static_green"><bounds x="219" y="96" width="2" height="22" /></bezel>
<!-- vfd -->
<bezel name="0.0" element="ind"><bounds x="0" y="1" width="20" height="17" /></bezel>
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src/mess/machine/m24_z8000.c Normal file
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#include "m24_z8000.h"
const device_type M24_Z8000 = &device_creator<m24_z8000_device>;
m24_z8000_device::m24_z8000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
device_t(mconfig, M24_Z8000, "Olivetti M24 Z8000 Adapter", tag, owner, clock, "m24_z8000", __FILE__),
m_z8000(*this, "z8000"),
m_maincpu(*this, ":maincpu"),
m_pic(*this, ":mb:pic8259"),
m_halt_out(*this),
m_z8000_halt(true)
{
}
void m24_z8000_device::device_start()
{
m_halt_out.resolve_safe();
}
void m24_z8000_device::device_reset()
{
m_z8000_halt = true;
m_z8000_mem = false;
m_timer_irq = false;
m_irq = 0;
m_z8000->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
}
ROM_START( m24_z8000 )
ROM_REGION(0x4000, "z8000", 0)
ROM_LOAD("m24apb.bin", 0x0000, 0x4000, CRC(3b3d2895) SHA1(ff048cf61b090b147be7e29a929a0be7b3ac8409))
ROM_END
const rom_entry *m24_z8000_device::device_rom_region() const
{
return ROM_NAME( m24_z8000 );
}
static ADDRESS_MAP_START(z8000_prog, AS_PROGRAM, 16, m24_z8000_device)
AM_RANGE(0x40000, 0x43fff) AM_ROM AM_REGION("z8000", 0)
AM_RANGE(0x50000, 0x53fff) AM_ROM AM_REGION("z8000", 0)
AM_RANGE(0x70000, 0x73fff) AM_ROM AM_REGION("z8000", 0)
AM_RANGE(0x00000, 0xfffff) AM_READWRITE(pmem_r, pmem_w)
ADDRESS_MAP_END
static ADDRESS_MAP_START(z8000_data, AS_DATA, 16, m24_z8000_device)
AM_RANGE(0x40000, 0x43fff) AM_ROM AM_REGION("z8000", 0)
AM_RANGE(0x70000, 0x73fff) AM_ROM AM_REGION("z8000", 0)
AM_RANGE(0x00000, 0xfffff) AM_READWRITE(dmem_r, dmem_w)
ADDRESS_MAP_END
static ADDRESS_MAP_START(z8000_io, AS_IO, 16, m24_z8000_device)
AM_RANGE(0x0080, 0x0081) AM_WRITE8(irqctl_w, 0x00ff)
AM_RANGE(0x00a0, 0x00a1) AM_WRITE8(serctl_w, 0x00ff)
AM_RANGE(0x00c0, 0x00c1) AM_DEVREADWRITE8("i8251", i8251_device, data_r, data_w, 0x00ff)
AM_RANGE(0x00c2, 0x00c3) AM_DEVREADWRITE8("i8251", i8251_device, status_r, control_w, 0x00ff)
AM_RANGE(0x0120, 0x0127) AM_DEVREADWRITE8("pit8253", pit8253_device, read, write, 0x00ff)
AM_RANGE(0x80c0, 0x80c1) AM_READWRITE8(handshake_r, handshake_w, 0x00ff)
AM_RANGE(0x8000, 0x83ff) AM_READWRITE(i86_io_r, i86_io_w)
ADDRESS_MAP_END
static MACHINE_CONFIG_FRAGMENT( m24_z8000 )
MCFG_CPU_ADD("z8000", Z8001, XTAL_8MHz/2)
MCFG_CPU_PROGRAM_MAP(z8000_prog)
MCFG_CPU_DATA_MAP(z8000_data)
MCFG_CPU_IO_MAP(z8000_io)
MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(m24_z8000_device, int_cb)
MCFG_Z8000_MO(WRITELINE(m24_z8000_device, mo_w))
MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
MCFG_PIT8253_CLK0(19660000/15)
MCFG_PIT8253_OUT0_HANDLER(NULL) //8251
MCFG_PIT8253_CLK1(19660000/15)
MCFG_PIT8253_OUT1_HANDLER(NULL)
MCFG_PIT8253_CLK2(19660000/15)
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(m24_z8000_device, timer_irq_w))
MCFG_DEVICE_ADD("i8251", I8251, 0)
MACHINE_CONFIG_END
machine_config_constructor m24_z8000_device::device_mconfig_additions() const
{
return MACHINE_CONFIG_NAME( m24_z8000 );
}
const UINT8 m24_z8000_device::pmem_table[16][4] =
{{0, 1, 2, 3}, {1, 2, 3, 255}, {4, 5, 6, 7}, {46, 40, 41, 42},
{255, 255, 255, 255}, {255, 255, 255, 47}, {1, 2, 3, 255}, {255, 255, 255, 255},
{1, 2, 8, 9}, {5, 6, 10, 11}, {1, 2, 8, 9}, {12, 13, 14, 15},
{16, 17, 18, 19}, {20, 21, 22, 23}, {24, 25, 26, 27}, {28, 29, 30, 31}};
READ16_MEMBER(m24_z8000_device::pmem_r)
{
UINT16 ret;
UINT8 hostseg;
offset <<= 1;
if(!m_z8000_mem)
return memregion(subtag("z8000").c_str())->u16(offset >> 1);
hostseg = pmem_table[(offset >> 16) & 0xf][(offset >> 14) & 3];
if(hostseg == 255)
return 0;
offset = (offset & 0x3fff) | (hostseg << 14);
if((hostseg >= 40) && (hostseg <= 47))
offset = (offset & 0xf0000) | BITSWAP16(offset,15,7,6,14,13,12,11,10,9,8,5,4,3,2,1,0); // move A6/A7 so CGA framebuffer appears linear
ret = m_maincpu->space(AS_PROGRAM).read_word(offset, (mem_mask << 8) | (mem_mask >> 8));
return (ret << 8) | (ret >> 8);
}
WRITE16_MEMBER(m24_z8000_device::pmem_w)
{
UINT8 hostseg;
data = (data << 8) | (data >> 8);
offset <<= 1;
hostseg = pmem_table[(offset >> 16) & 0xf][(offset >> 14) & 3];
if(hostseg == 255)
return;
offset = (offset & 0x3fff) | (hostseg << 14);
if((hostseg >= 40) && (hostseg <= 47))
offset = (offset & 0xf0000) | BITSWAP16(offset,15,7,6,14,13,12,11,10,9,8,5,4,3,2,1,0);
m_maincpu->space(AS_PROGRAM).write_word(offset, data, (mem_mask << 8) | (mem_mask >> 8));
}
const UINT8 m24_z8000_device::dmem_table[16][4] =
{{0, 1, 2, 3}, {4, 5, 6, 7}, {4, 5, 6, 7}, {46, 40, 41, 42},
{255, 255, 255, 255}, {1, 2, 3, 47}, {1, 2, 3, 255}, {255, 255, 255, 255},
{5, 6, 10, 11}, {5, 6, 10, 11}, {1, 2, 8, 9}, {12, 13, 14, 15},
{16, 17, 18, 19}, {20, 21, 22, 23}, {24, 25, 26, 27}, {28, 29, 30, 31}};
READ16_MEMBER(m24_z8000_device::dmem_r)
{
UINT16 ret;
UINT8 hostseg;
offset <<= 1;
hostseg = dmem_table[(offset >> 16) & 0xf][(offset >> 14) & 3];
if(hostseg == 255)
return 0;
offset = (offset & 0x3fff) | (hostseg << 14);
if((hostseg >= 40) && (hostseg <= 47))
offset = (offset & 0xf0000) | BITSWAP16(offset,15,7,6,14,13,12,11,10,9,8,5,4,3,2,1,0);
ret = m_maincpu->space(AS_PROGRAM).read_word(offset, (mem_mask << 8) | (mem_mask >> 8));
return (ret << 8) | (ret >> 8);
}
WRITE16_MEMBER(m24_z8000_device::dmem_w)
{
UINT8 hostseg;
data = (data << 8) | (data >> 8);
offset <<= 1;
hostseg = dmem_table[(offset >> 16) & 0xf][(offset >> 14) & 3];
if(hostseg == 255)
return;
offset = (offset & 0x3fff) | (hostseg << 14);
if((hostseg >= 40) && (hostseg <= 47))
offset = (offset & 0xf0000) | BITSWAP16(offset,15,7,6,14,13,12,11,10,9,8,5,4,3,2,1,0);
m_maincpu->space(AS_PROGRAM).write_word(offset, data, (mem_mask << 8) | (mem_mask >> 8));
}
READ16_MEMBER(m24_z8000_device::i86_io_r)
{
UINT16 ret = m_maincpu->space(AS_IO).read_word(offset << 1, (mem_mask << 8) | (mem_mask >> 8));
return (ret << 8) | (ret >> 8);
}
WRITE16_MEMBER(m24_z8000_device::i86_io_w)
{
data = (data << 8) | (data >> 8);
m_maincpu->space(AS_IO).write_word(offset << 1, data, (mem_mask << 8) | (mem_mask >> 8));
}
WRITE8_MEMBER(m24_z8000_device::irqctl_w)
{
m_irq = data;
}
WRITE8_MEMBER(m24_z8000_device::serctl_w)
{
m_z8000_mem = (data & 0x20) ? true : false;
}
IRQ_CALLBACK_MEMBER(m24_z8000_device::int_cb)
{
if (!irqline)
{
m_z8000->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
return 0xff; // NVI, value ignored
}
else
return m_pic->acknowledge();
}
READ8_MEMBER(m24_z8000_device::handshake_r)
{
return 0;
}
WRITE8_MEMBER(m24_z8000_device::handshake_w)
{
m_handshake = data;
if(data & 1)
{
m_z8000->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
m_z8000->set_input_line(INPUT_LINE_RESET, PULSE_LINE);
m_z8000->mi_w(CLEAR_LINE);
m_z8000_halt = false;
}
else
{
m_z8000->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
m_z8000_halt = true;
m_z8000_mem = false;
m_halt_out(CLEAR_LINE);
}
}
WRITE_LINE_MEMBER(m24_z8000_device::mo_w)
{
m_z8000->mi_w(state ? ASSERT_LINE : CLEAR_LINE);
m_halt_out(state);
}
WRITE_LINE_MEMBER(m24_z8000_device::timer_irq_w)
{
m_timer_irq = state ? true : false;
m_z8000->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
}

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src/mess/machine/m24_z8000.h Normal file
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#ifndef M24_Z8000_H_
#define M24_Z8000_H_
#include "emu.h"
#include "cpu/z8000/z8000.h"
#include "machine/i8251.h"
#include "machine/pit8253.h"
#include "machine/pic8259.h"
#define MCFG_M24_Z8000_HALT(_devcb) \
devcb = &m24_z8000_device::set_halt_callback(*device, DEVCB_##_devcb);
class m24_z8000_device : public device_t
{
public:
m24_z8000_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
virtual const rom_entry *device_rom_region() const;
virtual machine_config_constructor device_mconfig_additions() const;
template<class _Object> static devcb_base &set_halt_callback(device_t &device, _Object object) { return downcast<m24_z8000_device &>(device).m_halt_out.set_callback(object); }
DECLARE_READ16_MEMBER(pmem_r);
DECLARE_WRITE16_MEMBER(pmem_w);
DECLARE_READ16_MEMBER(dmem_r);
DECLARE_WRITE16_MEMBER(dmem_w);
DECLARE_READ16_MEMBER(i86_io_r);
DECLARE_WRITE16_MEMBER(i86_io_w);
DECLARE_WRITE8_MEMBER(irqctl_w);
DECLARE_WRITE8_MEMBER(serctl_w);
DECLARE_READ8_MEMBER(handshake_r);
DECLARE_WRITE8_MEMBER(handshake_w);
DECLARE_WRITE_LINE_MEMBER(mo_w);
DECLARE_WRITE_LINE_MEMBER(timer_irq_w);
IRQ_CALLBACK_MEMBER(int_cb);
bool halted() { return m_z8000_halt; }
required_device<z8001_device> m_z8000;
protected:
void device_start();
void device_reset();
private:
required_device<cpu_device> m_maincpu;
required_device<pic8259_device> m_pic;
devcb_write_line m_halt_out;
static const UINT8 pmem_table[16][4];
static const UINT8 dmem_table[16][4];
UINT8 m_handshake, m_irq;
bool m_z8000_halt, m_z8000_mem, m_timer_irq;
};
extern const device_type M24_Z8000;
#endif /* M24_Z8000_H_ */