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https://github.com/holub/mame
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video/pc_vga_paradise.cpp: fetch configuration pins when entering VGA setup mode
* fix macpb180c setting the wrong monitor type on restarts & waking up from sleep mode
This commit is contained in:
parent
70325b7ad6
commit
8dbd36390c
@ -369,6 +369,7 @@ void vga_device::io_3cx_map(address_map &map)
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map(0x00, 0x00).rw(FUNC(vga_device::atc_address_r), FUNC(vga_device::atc_address_data_w));
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map(0x00, 0x00).rw(FUNC(vga_device::atc_address_r), FUNC(vga_device::atc_address_data_w));
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map(0x01, 0x01).r(FUNC(vga_device::atc_data_r));
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map(0x01, 0x01).r(FUNC(vga_device::atc_data_r));
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map(0x02, 0x02).rw(FUNC(vga_device::input_status_0_r), FUNC(vga_device::miscellaneous_output_w));
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map(0x02, 0x02).rw(FUNC(vga_device::input_status_0_r), FUNC(vga_device::miscellaneous_output_w));
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// map(0x03, 0x03).w(FUNC(vga_device::wakeup_w));
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map(0x04, 0x04).rw(FUNC(vga_device::sequencer_address_r), FUNC(vga_device::sequencer_address_w));
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map(0x04, 0x04).rw(FUNC(vga_device::sequencer_address_r), FUNC(vga_device::sequencer_address_w));
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map(0x05, 0x05).rw(FUNC(vga_device::sequencer_data_r), FUNC(vga_device::sequencer_data_w));
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map(0x05, 0x05).rw(FUNC(vga_device::sequencer_data_r), FUNC(vga_device::sequencer_data_w));
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map(0x06, 0x06).rw(FUNC(vga_device::ramdac_mask_r), FUNC(vga_device::ramdac_mask_w));
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map(0x06, 0x06).rw(FUNC(vga_device::ramdac_mask_r), FUNC(vga_device::ramdac_mask_w));
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@ -1841,6 +1842,33 @@ TIMER_CALLBACK_MEMBER(vga_device::vblank_timer_cb)
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m_vblank_timer->adjust( screen().time_until_pos(vga.crtc.vert_blank_start + vga.crtc.vert_blank_end) );
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m_vblank_timer->adjust( screen().time_until_pos(vga.crtc.vert_blank_start + vga.crtc.vert_blank_end) );
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}
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}
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// ISA bus bindings
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void vga_device::enter_setup_mode()
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{
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// ...
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}
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/*
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* ---x ---- setup mode (only $102 accessible if this is on)
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* ---- x--- Enable $03xx I/O and memory accesses
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* ---- -xxx BIOS ROM page select for lowest 4 Kbyte range
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*
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* The generic ISA sequence is:
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* $46e8 0x10 (setup mode)
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* $0102 0x01 (wakeup core)
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* $46e8 0x0e
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*
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*/
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void vga_device::mode_setup_w(offs_t offset, u8 data)
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{
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LOG("mode_setup_w %02x\n", data);
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if (BIT(data, 4))
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{
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enter_setup_mode();
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}
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}
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/**************************************
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/**************************************
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*
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*
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* SVGA overrides
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* SVGA overrides
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@ -36,6 +36,11 @@ public:
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void io_map(address_map &map) ATTR_COLD;
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void io_map(address_map &map) ATTR_COLD;
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// $46e8, $56e8, $66e8, $76e8 for ISA bus
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void mode_setup_w(offs_t offset, uint8_t data);
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// $102 / $3c3, MCA bus
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//void wakeup_w(offs_t offset, uint8_t data);
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virtual uint8_t mem_r(offs_t offset);
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virtual uint8_t mem_r(offs_t offset);
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virtual void mem_w(offs_t offset, uint8_t data);
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virtual void mem_w(offs_t offset, uint8_t data);
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virtual uint8_t mem_linear_r(offs_t offset);
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virtual uint8_t mem_linear_r(offs_t offset);
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@ -83,6 +88,7 @@ protected:
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void recompute_params_clock(int divisor, int xtal);
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void recompute_params_clock(int divisor, int xtal);
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virtual void recompute_params();
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virtual void recompute_params();
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uint8_t vga_vblank();
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uint8_t vga_vblank();
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virtual void enter_setup_mode();
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virtual space_config_vector memory_space_config() const override;
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virtual space_config_vector memory_space_config() const override;
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@ -321,14 +321,22 @@ void wd90c00_vga_device::device_reset()
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m_pr10_scratch = 0;
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m_pr10_scratch = 0;
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m_ext_crtc_read_unlock = false;
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m_ext_crtc_read_unlock = false;
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m_ext_crtc_write_unlock = false;
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m_ext_crtc_write_unlock = false;
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// egasw
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m_pr11 = (m_cnf15_read_cb() << 7) | (m_cnf14_read_cb() << 6) | m_cnf13_read_cb() << 5 | m_cnf12_read_cb() << 4;
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m_interlace_start = 0;
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m_interlace_start = 0;
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m_interlace_end = 0;
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m_interlace_end = 0;
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m_interlace_mode = false;
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m_interlace_mode = false;
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m_pr15 = 0;
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m_pr15 = 0;
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}
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}
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// Make sure fetching happens in setup mode
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// macpb180c reads then writes 0xf4 to PR11 when waking up from sleep or restart
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// (the intention is locking VCLK), assume config refetch happening here.
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void wd90c00_vga_device::enter_setup_mode()
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{
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vga_device::enter_setup_mode();
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// egasw
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m_pr11 = (m_cnf15_read_cb() << 7) | (m_cnf14_read_cb() << 6) | m_cnf13_read_cb() << 5 | m_cnf12_read_cb() << 4;
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}
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ioport_value wd90c00_vga_device::egasw1_r() { return BIT(m_pr11, 4); }
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ioport_value wd90c00_vga_device::egasw1_r() { return BIT(m_pr11, 4); }
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ioport_value wd90c00_vga_device::egasw2_r() { return BIT(m_pr11, 5); }
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ioport_value wd90c00_vga_device::egasw2_r() { return BIT(m_pr11, 5); }
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ioport_value wd90c00_vga_device::egasw3_r() { return BIT(m_pr11, 6); }
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ioport_value wd90c00_vga_device::egasw3_r() { return BIT(m_pr11, 6); }
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@ -347,9 +355,12 @@ ioport_constructor wd90c00_vga_device::device_input_ports() const
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return INPUT_PORTS_NAME(paradise_vga_sense);
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return INPUT_PORTS_NAME(paradise_vga_sense);
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}
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}
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// NOTE: make sure that PR10 just unlocks PR11~PR17 for wd90c26
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// (that has different unlock mechanism for flat panel regs)
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// TODO: 'C11 and beyond are unchecked.
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u8 wd90c00_vga_device::crtc_data_r(offs_t offset)
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u8 wd90c00_vga_device::crtc_data_r(offs_t offset)
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{
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{
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if (!m_ext_crtc_read_unlock && vga.crtc.index >= 0x2a && !machine().side_effects_disabled())
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if (!m_ext_crtc_read_unlock && vga.crtc.index >= 0x2a && vga.crtc.index <= 0x30 && !machine().side_effects_disabled())
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{
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{
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LOGLOCKED("Attempt to read ext. CRTC register offset %02x while locked\n", vga.crtc.index);
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LOGLOCKED("Attempt to read ext. CRTC register offset %02x while locked\n", vga.crtc.index);
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return 0xff;
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return 0xff;
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@ -359,7 +370,7 @@ u8 wd90c00_vga_device::crtc_data_r(offs_t offset)
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void wd90c00_vga_device::crtc_data_w(offs_t offset, u8 data)
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void wd90c00_vga_device::crtc_data_w(offs_t offset, u8 data)
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{
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{
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if (!m_ext_crtc_write_unlock && vga.crtc.index >= 0x2a && !machine().side_effects_disabled())
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if (!m_ext_crtc_write_unlock && vga.crtc.index >= 0x2a && vga.crtc.index <= 0x30 && !machine().side_effects_disabled())
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{
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{
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LOGLOCKED("Attempt to write ext. CRTC register offset [%02x] <- %02x while locked\n", vga.crtc.index, data);
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LOGLOCKED("Attempt to write ext. CRTC register offset [%02x] <- %02x while locked\n", vga.crtc.index, data);
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return;
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return;
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@ -426,7 +437,7 @@ void wd90c00_vga_device::ext_crtc_unlock_w(offs_t offset, u8 data)
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{
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{
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m_ext_crtc_read_unlock = (data & 0x88) == 0x80;
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m_ext_crtc_read_unlock = (data & 0x88) == 0x80;
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m_ext_crtc_write_unlock = (data & 0x7) == 5;
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m_ext_crtc_write_unlock = (data & 0x7) == 5;
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LOGLOCKED("PR10 read %s write %s state (%02x)\n"
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LOGLOCKED("PR10 CRTC read %s write %s state (%02x)\n"
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, m_ext_crtc_read_unlock ? "unlock" : "lock"
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, m_ext_crtc_read_unlock ? "unlock" : "lock"
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, m_ext_crtc_write_unlock ? "unlock" : "lock"
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, m_ext_crtc_write_unlock ? "unlock" : "lock"
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, data
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, data
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@ -78,6 +78,8 @@ protected:
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virtual ioport_constructor device_input_ports() const override ATTR_COLD;
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virtual ioport_constructor device_input_ports() const override ATTR_COLD;
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virtual void enter_setup_mode() override;
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private:
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private:
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virtual u8 crtc_data_r(offs_t offset) override;
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virtual u8 crtc_data_r(offs_t offset) override;
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virtual void crtc_data_w(offs_t offset, u8 data) override;
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virtual void crtc_data_w(offs_t offset, u8 data) override;
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@ -14,6 +14,11 @@ TODO:
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#include "emu.h"
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#include "emu.h"
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#include "wd90c26.h"
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#include "wd90c26.h"
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#define VERBOSE (LOG_GENERAL)
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//#define LOG_OUTPUT_FUNC osd_printf_info
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(WD90C26, wd90c26_vga_device, "wd90c26_vga", "Western Digital WD90C26 VGA Controller")
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DEFINE_DEVICE_TYPE(WD90C26, wd90c26_vga_device, "wd90c26_vga", "Western Digital WD90C26 VGA Controller")
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wd90c26_vga_device::wd90c26_vga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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wd90c26_vga_device::wd90c26_vga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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@ -33,15 +38,64 @@ wd90c26_vga_device::wd90c26_vga_device(const machine_config &mconfig, const char
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void wd90c26_vga_device::crtc_map(address_map &map)
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void wd90c26_vga_device::crtc_map(address_map &map)
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{
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{
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wd90c11a_vga_device::crtc_map(map);
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wd90c11a_vga_device::crtc_map(map);
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// map(0x31, 0x31) PR18 Flat Panel Status
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// PR18 Flat Panel Status
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// map(0x32, 0x33) PR19/PR1A Flat Panel Control
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map(0x31, 0x31).lrw8(
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// map(0x34, 0x34) PR1B Flat Panel Unlock
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NAME([this] (offs_t offset) {
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LOG("PR18 Flat Panel Status R\n");
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return m_pr18_fp_status;
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}),
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NAME([this] (offs_t offset, u8 data) {
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m_pr18_fp_status = data;
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LOG("PR18 Flat Panel Status W %02x\n", data);
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})
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);
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// PR19 Flat Panel Control I / PR1A Flat Panel Control II
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map(0x32, 0x33).lrw8(
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NAME([this] (offs_t offset) {
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LOG("PR%02X Flat Panel Control %s R\n", offset + 0x19, offset ? "II" : "I");
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return m_fp_control[offset];
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}),
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NAME([this] (offs_t offset, u8 data) {
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m_fp_control[offset] = data;
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LOG("PR%02X Flat Panel Control %s W %02x\n", offset + 0x19, offset ? "II" : "I", data);
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})
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);
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// PR1B Flat Panel Unlock
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map(0x34, 0x34).lrw8(
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NAME([this] (offs_t offset) {
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LOG("PR1B Flat Panel Unlock R\n");
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return m_pr1b_fp_unlock;
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}),
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NAME([this] (offs_t offset, u8 data) {
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m_pr1b_fp_unlock = data;
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LOG("PR1B Flat Panel Unlock W %02x\n", data);
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})
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);
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// map(0x35, 0x35) PR30 Mapping RAM Unlock
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// map(0x35, 0x35) PR30 Mapping RAM Unlock
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// map(0x37, 0x37) PR41 Vertical Expansion Initial Value
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// map(0x37, 0x37) PR41 Vertical Expansion Initial Value
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// map(0x38, 0x38) PR33 Mapping RAM Address Counter
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// map(0x38, 0x38) PR33 Mapping RAM Address Counter
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// map(0x39, 0x39) PR34 Mapping RAM Data
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// map(0x39, 0x39) PR34 Mapping RAM Data
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// map(0x3a, 0x3a) PR35 Mapping RAM Control and Power-Down
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// PR35 Mapping RAM Control and Power-Down
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// map(0x3b, 0x3b) PR36 LCD Panel Height Select
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map(0x3a, 0x3a).lrw8(
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NAME([this] (offs_t offset) {
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LOG("PR35 Mapping RAM Control and Power-Down R\n");
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return m_pr35_powerdown;
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}),
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NAME([this] (offs_t offset, u8 data) {
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m_pr35_powerdown = data;
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LOG("PR35 Mapping RAM Control and Power-Down W %02x\n", data);
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})
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);
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// PR36 LCD Panel Height Select
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map(0x3b, 0x3b).lrw8(
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NAME([this] (offs_t offset) {
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return m_pr36_lcd_height;
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}),
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NAME([this] (offs_t offset, u8 data) {
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m_pr36_lcd_height = data;
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LOG("PR36 LCD Panel Height W %02x\n", data);
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})
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);
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// map(0x3c, 0x3c) PR37 Flat Panel Blinking Control
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// map(0x3c, 0x3c) PR37 Flat Panel Blinking Control
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// map(0x3e, 0x3e) PR39 Color LCD Control
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// map(0x3e, 0x3e) PR39 Color LCD Control
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// map(0x3f, 0x3f) PR44 Power-Down Memory Refresh Control
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// map(0x3f, 0x3f) PR44 Power-Down Memory Refresh Control
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@ -17,6 +17,12 @@ protected:
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virtual void crtc_map(address_map &map) override ATTR_COLD;
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virtual void crtc_map(address_map &map) override ATTR_COLD;
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virtual void gc_map(address_map &map) override ATTR_COLD;
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virtual void gc_map(address_map &map) override ATTR_COLD;
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virtual void sequencer_map(address_map &map) override ATTR_COLD;
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virtual void sequencer_map(address_map &map) override ATTR_COLD;
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private:
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u8 m_pr18_fp_status;
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u8 m_fp_control[2];
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u8 m_pr1b_fp_unlock;
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u8 m_pr35_powerdown;
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u8 m_pr36_lcd_height;
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};
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};
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DECLARE_DEVICE_TYPE(WD90C26, wd90c26_vga_device)
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DECLARE_DEVICE_TYPE(WD90C26, wd90c26_vga_device)
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@ -595,6 +595,7 @@ u16 macpb030_state::pangola_r()
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void macpb030_state::pangola_w(u16 data)
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void macpb030_state::pangola_w(u16 data)
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{
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{
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m_pangola_data = data;
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m_pangola_data = data;
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// TODO: trace pins, 0x13 -> 0x17 -> 0x16 sequence written before waking up VGA core
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}
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}
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u8 macpb030_state::pangola_vram_r(offs_t offset)
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u8 macpb030_state::pangola_vram_r(offs_t offset)
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@ -1257,9 +1258,13 @@ void macpb030_state::macpb165c_map(address_map &map)
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map(0x50f24000, 0x50f27fff).r(FUNC(macpb030_state::buserror_r)); // bus error here to make sure we aren't mistaken for another decoder
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map(0x50f24000, 0x50f27fff).r(FUNC(macpb030_state::buserror_r)); // bus error here to make sure we aren't mistaken for another decoder
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map(0x50f80000, 0x50fbffff).rw(FUNC(macpb030_state::niagra_r), FUNC(macpb030_state::niagra_w));
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map(0x50f80000, 0x50fbffff).rw(FUNC(macpb030_state::niagra_r), FUNC(macpb030_state::niagra_w));
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// on-board color video on 165c/180c
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// on-board color video on 165c/180c, presumably under ISA bus
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map(0xfc000000, 0xfc07ffff).rw(FUNC(macpb030_state::pangola_vram_r), FUNC(macpb030_state::pangola_vram_w)).mirror(0x00380000);
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map(0xfc000000, 0xfc07ffff).rw(FUNC(macpb030_state::pangola_vram_r), FUNC(macpb030_state::pangola_vram_w)).mirror(0x00380000);
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// map(0xfc400102, 0xfc400102).w(wd90c26_vga_device::wakeup_w));
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map(0xfc4003b0, 0xfc4003df).m(m_vga, FUNC(wd90c26_vga_device::io_map));
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map(0xfc4003b0, 0xfc4003df).m(m_vga, FUNC(wd90c26_vga_device::io_map));
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// TODO: trace $3d0 writes (doesn't belong to WD90C26 core, RAMDAC overlay?)
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map(0xfc4046e8, 0xfc4046e8).mirror(0x3000).w(m_vga, FUNC(wd90c26_vga_device::mode_setup_w));
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|
|
||||||
map(0xfc800000, 0xfc800003).rw(FUNC(macpb030_state::pangola_r), FUNC(macpb030_state::pangola_w));
|
map(0xfc800000, 0xfc800003).rw(FUNC(macpb030_state::pangola_r), FUNC(macpb030_state::pangola_w));
|
||||||
map(0xfcff8000, 0xfcffffff).rom().region("vrom", 0x0000);
|
map(0xfcff8000, 0xfcffffff).rom().region("vrom", 0x0000);
|
||||||
|
|
||||||
@ -1521,6 +1526,7 @@ void macpb030_state::macpb165c(machine_config &config)
|
|||||||
m_screen->set_raw(25.175_MHz_XTAL, 800, 0, 640, 524, 0, 480);
|
m_screen->set_raw(25.175_MHz_XTAL, 800, 0, 640, 524, 0, 480);
|
||||||
m_screen->set_screen_update(FUNC(macpb030_state::screen_update_vga));
|
m_screen->set_screen_update(FUNC(macpb030_state::screen_update_vga));
|
||||||
m_screen->set_no_palette();
|
m_screen->set_no_palette();
|
||||||
|
m_screen->set_type(SCREEN_TYPE_LCD);
|
||||||
|
|
||||||
WD90C26(config, m_vga, 0);
|
WD90C26(config, m_vga, 0);
|
||||||
m_vga->set_screen(m_screen);
|
m_vga->set_screen(m_screen);
|
||||||
|
Loading…
Reference in New Issue
Block a user