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Cleanups and version bump

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This commit is contained in:
Miodrag Milanovic 2015-09-30 08:29:01 +02:00
parent 9fd990dea8
commit 8e4ced4b53
117 changed files with 2730 additions and 2747 deletions
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2
hash/pico.xml
View File

@ -3434,7 +3434,7 @@ But how do later protos fit with this theory? Maybe the later protos were from t
<info name="serial" value="HPC-6214"/>
<info name="release" value="200306xx"/>
<!-- * ピーターパン ネバーランドへ いこう!<10th> - Peter Pan - Neverland e Ikou! ~10th Anniversary Edition~ (Sega Toys - 200306xx - HPC-6124) [reprint HPC-6047]
malformed token? Used normal Peter Pan alt_title for now -->
malformed token? Used normal Peter Pan alt_title for now -->
<info name="alt_title" value="ピーターパン ネバーランドへ いこう!"/>
<part name="cart" interface="pico_cart">
<feature name="pcb" value="171-7090A" />

6
hash/tutor.xml
View File

@ -218,7 +218,7 @@ Battlefighter (Original) (Unreleased - Prototype Stage)
</dataarea>
</part>
</software>
<software name="mazeptrl">
<description>Maze Patrol (Jpn)</description>
<year>1983</year>
@ -270,7 +270,7 @@ Battlefighter (Original) (Unreleased - Prototype Stage)
</dataarea>
</part>
</software>
<software name="mysteryg">
<description>Mystery Gold (Jpn)</description>
<year>1983</year>
@ -283,7 +283,7 @@ Battlefighter (Original) (Unreleased - Prototype Stage)
</dataarea>
</part>
</software>
<software name="mrdo">
<description>Mr. Do! (Jpn)</description>
<year>1983</year>

6
hash/x1_cass.xml
View File

@ -25,7 +25,7 @@ Titles, publishers and release dates taken from:
</dataarea>
</part>
</software>
<software name="blckonyx" supported="no">
<description>The Black Onyx</description>
<year>1985</year>
@ -90,7 +90,7 @@ Titles, publishers and release dates taken from:
</dataarea>
</part>
</software>
<software name="cball">
<description>Cannon Ball</description>
<year>1983</year>
@ -322,7 +322,7 @@ Titles, publishers and release dates taken from:
</dataarea>
</part>
</software>
<software name="machgjoe">
<description>Ginkou Goutou - Machinegun Joe vs. the Mafia</description>
<year>1983</year>

8
src/devices/bus/centronics/nec_p72.h
View File

@ -17,15 +17,15 @@
// ======================> nec_p72_t
class nec_p72_t : public device_t,
public device_centronics_peripheral_interface
public device_centronics_peripheral_interface
{
public:
// construction/destruction
nec_p72_t(const machine_config &mconfig, const char *tag,
device_t *owner, UINT32 clock);
device_t *owner, UINT32 clock);
nec_p72_t(const machine_config &mconfig, device_type type,
const char *name, const char *tag, device_t *owner,
UINT32 clock, const char *shortname, const char *source);
const char *name, const char *tag, device_t *owner,
UINT32 clock, const char *shortname, const char *source);
// optional information overrides
virtual const rom_entry *device_rom_region() const;

2
src/devices/bus/cpc/cpcexp.h
View File

@ -33,7 +33,7 @@
* GND 49 50 CLOCK
*
* Aleste 520EX expansion port is 62-pin. Same as the CPC above, except that pin 40 is not connected, plus the following:
*
*
* MAP14 A26 B26 MAP15
* MAP16 A27 B27 MAP17
* MAP18 A28 B28 MAPBLK

13
src/devices/bus/cpc/magicsound.c
View File

@ -6,7 +6,7 @@
* Magic Sound Board for the Aleste 520EX
*
*/
#include "emu.h"
#include "magicsound.h"
#include "includes/amstrad.h"
@ -22,7 +22,7 @@ const device_type AL_MAGICSOUND = &device_creator<al_magicsound_device>;
static MACHINE_CONFIG_FRAGMENT( al_magicsound )
MCFG_DEVICE_ADD( "dmac", AM9517A, XTAL_4MHz ) // CLK from expansion port
// According to the schematics, the TC pin (EOP on western chips) is connected to NMI on the expansion port.
// NMIs seem to occur too quickly when this is active, so either EOP is not triggered at the correct time, or
// NMIs seem to occur too quickly when this is active, so either EOP is not triggered at the correct time, or
// the K1810WT37 is different to the i8237/AM9517A
//MCFG_I8237_OUT_EOP_CB(DEVWRITELINE("^", cpc_expansion_slot_device, nmi_w)) // MCFG_DEVCB_INVERT
MCFG_I8237_OUT_HREQ_CB(DEVWRITELINE("dmac", am9517a_device, hack_w))
@ -56,7 +56,7 @@ static MACHINE_CONFIG_FRAGMENT( al_magicsound )
MCFG_PIT8253_CLK2(XTAL_4MHz)
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_DAC_ADD("dac1")
MCFG_DAC_ADD("dac1")
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
// no pass-through(?)
MACHINE_CONFIG_END
@ -94,9 +94,9 @@ void al_magicsound_device::device_start()
space.install_write_handler(0xf9d0,0xf9df,0,0,write8_delegate(FUNC(al_magicsound_device::timer_w),this));
space.install_write_handler(0xfad0,0xfadf,0,0,write8_delegate(FUNC(al_magicsound_device::volume_w),this));
space.install_write_handler(0xfbd0,0xfbdf,0,0,write8_delegate(FUNC(al_magicsound_device::mapper_w),this));
m_ramptr = machine().device<ram_device>(":" RAM_TAG);
for(int x=0;x<4;x++)
{
save_item(NAME(m_output[x]),x);
@ -167,7 +167,7 @@ READ8_MEMBER(al_magicsound_device::dma_read_byte)
{
UINT8 ret = 0xff;
UINT8 page = (offset & 0xc000) >> 14;
if(m_current_channel != -1)
ret = m_ramptr->read(m_page[m_current_channel][page] + (offset & 0x3fff));
return ret;
@ -187,4 +187,3 @@ void al_magicsound_device::set_timer_gate(bool state)
m_timer2->write_gate1(state);
m_timer2->write_gate2(state);
}

6
src/devices/bus/cpc/magicsound.h
View File

@ -6,7 +6,7 @@
* Magic Sound Board for the Aleste 520EX
*
* DMA-based 4-channel sound board
*
*
* 1x K1810WT37 DMA controller (i8237/AM9517A)
* 2x K1810WT54 programmable timers (i8254)
* 1x K1118PA1 DAC (MC10318)
@ -72,9 +72,9 @@ private:
required_device<am9517a_device> m_dmac;
required_device<pit8254_device> m_timer1;
required_device<pit8254_device> m_timer2;
void set_timer_gate(bool state);
UINT8 m_volume[4];
UINT32 m_page[4][4];
UINT8 m_output[4];

38
src/devices/bus/isa/pgc.c
View File

@ -77,9 +77,9 @@ ROM_END
static INPUT_PORTS_START( pgc )
PORT_START("DSW")
/*
PORT_DIPNAME( 0x01, 0x00, "CGA emulator")
PORT_DIPSETTING( 0x00, DEF_STR(No) )
PORT_DIPSETTING( 0x01, DEF_STR(Yes) )
PORT_DIPNAME( 0x01, 0x00, "CGA emulator")
PORT_DIPSETTING( 0x00, DEF_STR(No) )
PORT_DIPSETTING( 0x01, DEF_STR(Yes) )
*/
PORT_DIPNAME( 0x02, 0x00, "Communication area")
PORT_DIPSETTING( 0x00, "C6000" )
@ -88,19 +88,19 @@ INPUT_PORTS_END
/*
write only
30000 LUT WR O L
30001 LUT WR I L
32000 MODE WT L
32001 NIBBLE WT L
3200A ??
34000 FUNCTION WT L
34001 STARTADD WT L
36001 CURSOR WT L
30000 LUT WR O L
30001 LUT WR I L
32000 MODE WT L
32001 NIBBLE WT L
3200A ??
34000 FUNCTION WT L
34001 STARTADD WT L
36001 CURSOR WT L
read only
38000 LUT RD O L
38001 LUT RD I L
3C001 INIT L/INIT H
38000 LUT RD O L
38001 LUT RD I L
3C001 INIT L/INIT H
*/
static ADDRESS_MAP_START( pgc_map, AS_PROGRAM, 8, isa8_pgc_device )
@ -108,10 +108,10 @@ static ADDRESS_MAP_START( pgc_map, AS_PROGRAM, 8, isa8_pgc_device )
AM_RANGE(0x00000, 0x07fff) AM_ROM
AM_RANGE(0x08000, 0x0ffff) AM_ROM AM_REGION("maincpu", 0x8000)
AM_RANGE(0x10000, 0x1001f) AM_READWRITE(stateparam_r, stateparam_w)
// AM_RANGE(0x18000, 0x18fff) AM_RAM // ??
// AM_RANGE(0x18000, 0x18fff) AM_RAM // ??
AM_RANGE(0x28000, 0x287ff) AM_RAM AM_REGION("commarea", 0) AM_MIRROR(0x800)
AM_RANGE(0x3c000, 0x3c001) AM_READ(init_r)
// AM_RANGE(0x3e000, 0x3efff) AM_RAM // ??
// AM_RANGE(0x3e000, 0x3efff) AM_RAM // ??
AM_RANGE(0xf8000, 0xfffff) AM_ROM AM_REGION("maincpu", 0x8000)
ADDRESS_MAP_END
@ -311,7 +311,7 @@ WRITE8_MEMBER( isa8_pgc_device::lut_w ) {
if (offset & 1) {
m_lut[o + 2] = (data & 15) << 4;
m_palette->set_pen_color( offset >> 1, m_lut[o], m_lut[o + 1], m_lut[o + 2] );
DBG_LOG(1,"lut",("W @ %02X <- %d %d %d\n",
DBG_LOG(1,"lut",("W @ %02X <- %d %d %d\n",
offset >> 1, m_lut[o], m_lut[o + 1], m_lut[o + 2] ));
} else {
m_lut[o ] = data & 0xf0;
@ -330,7 +330,7 @@ READ8_MEMBER( isa8_pgc_device::init_r ) {
DBG_LOG(1,"INIT",("mapping LUT\n"));
space.install_write_handler(0xf8400, 0xf85ff,
write8_delegate(FUNC(isa8_pgc_device::lut_w), this));
return 0; // XXX ignored
}
@ -341,7 +341,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(isa8_pgc_device::scanline_callback)
UINT8 *v;
// XXX hpos shifts every frame -- fix
if (y == 0) DBG_LOG(2,"scanline_cb",
if (y == 0) DBG_LOG(2,"scanline_cb",
("frame %d x %.4d y %.3d\n",
(int) m_screen->frame_number(), m_screen->hpos(), y));

5
src/devices/bus/lpci/vt82c505.c
View File

@ -2,7 +2,7 @@
// copyright-holders:Barry Rodewald
/*
VIA VT82C505 ISA/VL PCI bridge
VIA VT82C505 ISA/VL PCI bridge
*/
@ -27,7 +27,7 @@ vt82c505_device::vt82c505_device(const machine_config &mconfig, const char *tag,
UINT32 vt82c505_device::pci_read(pci_bus_device *pcibus, int function, int offset, UINT32 mem_mask)
{
UINT32 result = 0;
if (function != 0)
return result;
@ -94,4 +94,3 @@ void vt82c505_device::device_start()
void vt82c505_device::device_reset()
{
}

2
src/devices/bus/lpci/vt82c505.h
View File

@ -2,7 +2,7 @@
// copyright-holders:Barry Rodewald
/*
VIA VT82C505 PCI bridge
VIA VT82C505 PCI bridge
*/

2
src/devices/bus/pc_kbd/iskr1030.c
View File

@ -416,7 +416,7 @@ WRITE8_MEMBER( iskr_1030_keyboard_device::ram_w )
READ8_MEMBER( iskr_1030_keyboard_device::ram_r )
{
DBG_LOG(2,0,( "%s: ram_r[%02x] = %02x\n", tag(), offset, m_ram[offset]));
return m_ram[offset];
}

2
src/devices/cpu/m68000/m68kops.c
View File

@ -34872,5 +34872,3 @@ void m68ki_build_opcode_table(void)
/* ======================================================================== */
/* ============================== END OF FILE ============================= */
/* ======================================================================== */

6
src/devices/cpu/mips/mips3.c
View File

@ -2845,7 +2845,7 @@ void mips3_device::execute_run()
case 0x2e: /* SWR */ (this->*m_swr)(op); break;
case 0x2f: /* CACHE */ /* effective no-op */ break;
case 0x30: /* LL */ if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) RTVAL64 = (UINT32)temp; m_ll_value = RTVAL32; break;
case 0x31: /* LWC1 */
case 0x31: /* LWC1 */
if (!(SR & SR_COP1))
{
m_badcop_value = 1;
@ -2855,7 +2855,7 @@ void mips3_device::execute_run()
case 0x32: /* LWC2 */ if (RWORD(SIMMVAL+RSVAL32, &temp)) set_cop2_reg(RTREG, temp); break;
case 0x33: /* PREF */ /* effective no-op */ break;
case 0x34: /* LLD */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64; m_lld_value = temp64; break;
case 0x35: /* LDC1 */
case 0x35: /* LDC1 */
if (!(SR & SR_COP1))
{
m_badcop_value = 1;
@ -2877,7 +2877,7 @@ void mips3_device::execute_run()
}
}
break;
case 0x39: /* SWC1 */
case 0x39: /* SWC1 */
if (!(SR & SR_COP1))
{
m_badcop_value = 1;

8
src/devices/cpu/rsp/rsp_dasm.c
View File

@ -10,10 +10,10 @@
/*static const char *const reg[32] =
{
"0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
"0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
};
*/

2
src/devices/cpu/t11/t11.c
View File

@ -365,7 +365,7 @@ void t11_device::device_reset()
void k1801vm2_device::device_reset()
{
t11_device::device_reset();
PC = RWORD(c_initial_mode);
PSW = RWORD(c_initial_mode+2);
}

308
src/devices/machine/68230pit.c
View File

@ -27,21 +27,21 @@ const device_type PIT68230 = &device_creator<pit68230_device>;
// pit68230_device - constructors
//-------------------------------------------------
pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source)
: device_t (mconfig, type, name, tag, owner, clock, shortname, source),
device_execute_interface (mconfig, *this)
, m_icount (0)
, m_write_pa (*this)
, m_write_h2 (*this)
: device_t (mconfig, type, name, tag, owner, clock, shortname, source),
device_execute_interface (mconfig, *this)
, m_icount (0)
, m_write_pa (*this)
, m_write_h2 (*this)
{
}
pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
device_execute_interface (mconfig, *this)
, m_icount (0)
, m_write_pa (*this)
, m_write_h2 (*this)
: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
device_execute_interface (mconfig, *this)
, m_icount (0)
, m_write_pa (*this)
, m_write_h2 (*this)
{
}
@ -50,12 +50,12 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag,
//-------------------------------------------------
void pit68230_device::device_start ()
{
LOG (logerror ("PIT68230 device started\n"));
m_icountptr = &m_icount;
LOG (logerror ("PIT68230 device started\n"));
m_icountptr = &m_icount;
// resolve callbacks
m_write_pa.resolve_safe ();
m_write_h2.resolve_safe ();
// resolve callbacks
m_write_pa.resolve_safe ();
m_write_h2.resolve_safe ();
}
//-------------------------------------------------
@ -63,17 +63,17 @@ void pit68230_device::device_start ()
//-------------------------------------------------
void pit68230_device::device_reset ()
{
LOG (logerror ("PIT68230 device reseted\n"));
m_pgcr = 0;
m_psrr = 0;
m_paddr = 0;
m_pbddr = 0;
m_pcddr = 0;
m_pacr = 0; m_write_h2 (m_pacr);
m_pbcr = 0;
m_padr = 0; m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR
m_pbdr = 0;
m_psr = 0;
LOG (logerror ("PIT68230 device reseted\n"));
m_pgcr = 0;
m_psrr = 0;
m_paddr = 0;
m_pbddr = 0;
m_pcddr = 0;
m_pacr = 0; m_write_h2 (m_pacr);
m_pbcr = 0;
m_padr = 0; m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR
m_pbdr = 0;
m_psr = 0;
}
//-------------------------------------------------
@ -85,16 +85,16 @@ void pit68230_device::device_timer (emu_timer &timer, device_timer_id id, INT32
void pit68230_device::h1_set (UINT8 state)
{
LOG (logerror ("h1_set %d @ m_psr %2x => ", state, m_psr));
if (state) m_psr |= 1; else m_psr &= ~1;
LOG (logerror ("%02x %lld\n", m_psr, machine ().firstcpu->total_cycles ()));
LOG (logerror ("h1_set %d @ m_psr %2x => ", state, m_psr));
if (state) m_psr |= 1; else m_psr &= ~1;
LOG (logerror ("%02x %lld\n", m_psr, machine ().firstcpu->total_cycles ()));
}
void pit68230_device::portb_setbit (UINT8 bit, UINT8 state)
{
LOG (logerror ("portb_setbit %d/%d @ m_pbdr %2x => ", bit, state, m_pbdr));
if (state) m_pbdr |= (1 << bit); else m_pbdr &= ~(1 << bit);
LOG (logerror ("%02x %lld\n", m_pbdr, machine ().firstcpu->total_cycles ()));
LOG (logerror ("portb_setbit %d/%d @ m_pbdr %2x => ", bit, state, m_pbdr));
if (state) m_pbdr |= (1 << bit); else m_pbdr &= ~(1 << bit);
LOG (logerror ("%02x %lld\n", m_pbdr, machine ().firstcpu->total_cycles ()));
}
//-------------------------------------------------
@ -102,11 +102,11 @@ void pit68230_device::portb_setbit (UINT8 bit, UINT8 state)
//-------------------------------------------------
void pit68230_device::execute_run ()
{
do {
synchronize ();
do {
synchronize ();
m_icount--;
} while (m_icount > 0);
m_icount--;
} while (m_icount > 0);
}
LOG (static INT32 ow_cnt = 0);
@ -114,75 +114,75 @@ LOG (static INT32 ow_data = 0);
LOG (static INT32 ow_ofs = 0);
WRITE8_MEMBER (pit68230_device::write){
switch (offset) {
case PIT_68230_PGCR:
m_pgcr = data;
break;
switch (offset) {
case PIT_68230_PGCR:
m_pgcr = data;
break;
case PIT_68230_PSRR:
m_psrr = data;
break;
case PIT_68230_PSRR:
m_psrr = data;
break;
case PIT_68230_PADDR:
m_paddr = data;
break;
case PIT_68230_PADDR:
m_paddr = data;
break;
case PIT_68230_PBDDR:
m_pbddr = data;
break;
case PIT_68230_PBDDR:
m_pbddr = data;
break;
case PIT_68230_PCDDR:
m_pcddr = data;
break;
case PIT_68230_PCDDR:
m_pcddr = data;
break;
case PIT_68230_PACR:
m_pacr = data;
// callbacks
/*PACR in Mode 0
* 5 43 H2 Control in Submode 00 && 01
* ------------------------------------
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
* 1 00 Output pin - negated, H2S is always clear.
* 1 01 Output pin - asserted, H2S is always clear.
* 1 10 Output pin - interlocked input handshake protocol, H2S is always clear.
* 1 11 Output pin - pulsed input handshake protocol, H2S is always clear.
*
* 5 43 H2 Control in Submode 1x
* ------------------------------------
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
* 1 X0 Output pin - negated, H2S is always cleared.
* 1 X1 Output pin - asserted, H2S is always cleared.
*/
m_write_h2 (m_pacr & 0x08 ? 1 : 0); // TODO: Check mode and submodes
break;
case PIT_68230_PACR:
m_pacr = data;
// callbacks
/*PACR in Mode 0
* 5 43 H2 Control in Submode 00 && 01
* ------------------------------------
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
* 1 00 Output pin - negated, H2S is always clear.
* 1 01 Output pin - asserted, H2S is always clear.
* 1 10 Output pin - interlocked input handshake protocol, H2S is always clear.
* 1 11 Output pin - pulsed input handshake protocol, H2S is always clear.
*
* 5 43 H2 Control in Submode 1x
* ------------------------------------
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
* 1 X0 Output pin - negated, H2S is always cleared.
* 1 X1 Output pin - asserted, H2S is always cleared.
*/
m_write_h2 (m_pacr & 0x08 ? 1 : 0); // TODO: Check mode and submodes
break;
case PIT_68230_PBCR:
m_pbcr = data;
break;
case PIT_68230_PBCR:
m_pbcr = data;
break;
case PIT_68230_PADR:
m_padr = data;
// callbacks
m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR
break;
case PIT_68230_PADR:
m_padr = data;
// callbacks
m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR
break;
case PIT_68230_PSR:
m_psr = data;
break;
case PIT_68230_PSR:
m_psr = data;
break;
default:
LOG (logerror ("unhandled register %02x", offset));
}
default:
LOG (logerror ("unhandled register %02x", offset));
}
LOG (if (offset != ow_ofs || data != ow_data || ow_cnt >= 1000) {
logerror ("\npit68230_device::write: previous identical operation performed %02x times\n", ow_cnt);
ow_cnt = 0;
ow_data = data;
ow_ofs = offset;
logerror ("pit68230_device::write: offset=%02x data=%02x %lld\n", ow_ofs, ow_data, machine ().firstcpu->total_cycles ());
}
else
ow_cnt++; )
LOG (if (offset != ow_ofs || data != ow_data || ow_cnt >= 1000) {
logerror ("\npit68230_device::write: previous identical operation performed %02x times\n", ow_cnt);
ow_cnt = 0;
ow_data = data;
ow_ofs = offset;
logerror ("pit68230_device::write: offset=%02x data=%02x %lld\n", ow_ofs, ow_data, machine ().firstcpu->total_cycles ());
}
else
ow_cnt++; )
}
LOG (static INT32 or_cnt = 0);
@ -190,76 +190,76 @@ LOG (static INT32 or_data = 0);
LOG (static INT32 or_ofs = 0);
READ8_MEMBER (pit68230_device::read){
UINT8 data = 0;
UINT8 data = 0;
switch (offset) {
case PIT_68230_PGCR:
data = m_pgcr;
break;
switch (offset) {
case PIT_68230_PGCR:
data = m_pgcr;
break;
case PIT_68230_PSRR:
data = m_psrr;
break;
case PIT_68230_PSRR:
data = m_psrr;
break;
case PIT_68230_PADDR:
data = m_paddr;
break;
case PIT_68230_PADDR:
data = m_paddr;
break;
case PIT_68230_PBDDR:
data = m_pbddr;
break;
case PIT_68230_PBDDR:
data = m_pbddr;
break;
case PIT_68230_PCDDR:
data = m_pcddr;
break;
case PIT_68230_PCDDR:
data = m_pcddr;
break;
case PIT_68230_PACR:
data = m_pacr;
break;
case PIT_68230_PACR:
data = m_pacr;
break;
case PIT_68230_PBCR:
data = m_pbcr;
break;
case PIT_68230_PBCR:
data = m_pbcr;
break;
case PIT_68230_PADR:
data = m_padr;
break;
case PIT_68230_PADR:
data = m_padr;
break;
case PIT_68230_PBDR:
/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding
* register for moving data to and from port B pins. The port B data direction
* register determines whether each pin is an input (zero) or an output (one).
* This register is readable and writable at all times. Depending on the chosen
* mode/submode, reading or writing may affect the double-buffered handshake
* mechanism. The port B data register is not affected by the assertion of the
* RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
data = m_pbdr;
break;
case PIT_68230_PBDR:
/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding
* register for moving data to and from port B pins. The port B data direction
* register determines whether each pin is an input (zero) or an output (one).
* This register is readable and writable at all times. Depending on the chosen
* mode/submode, reading or writing may affect the double-buffered handshake
* mechanism. The port B data register is not affected by the assertion of the
* RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
data = m_pbdr;
break;
case PIT_68230_PSR:
/* 4.8. PORT STATUS REGISTER (PSR) The port status register contains information about
* handshake pin activity. Bits 7-4 show the instantaneous level of the respective handshake
* pin, and are independent of the handshake pin sense bits in the port general control
* register. Bits 3-0 are the respective status bits referred to throughout this document.
* Their interpretation depends on the programmed mode/submode of the PI/T. For bits
* 3-0 a one is the active or asserted state. */
data = m_psr;
break;
case PIT_68230_PSR:
/* 4.8. PORT STATUS REGISTER (PSR) The port status register contains information about
* handshake pin activity. Bits 7-4 show the instantaneous level of the respective handshake
* pin, and are independent of the handshake pin sense bits in the port general control
* register. Bits 3-0 are the respective status bits referred to throughout this document.
* Their interpretation depends on the programmed mode/submode of the PI/T. For bits
* 3-0 a one is the active or asserted state. */
data = m_psr;
break;
default:
LOG (logerror ("unhandled register %02x", offset));
data = 0;
}
default:
LOG (logerror ("unhandled register %02x", offset));
data = 0;
}
LOG (if (offset != or_ofs || data != or_data || or_cnt >= 1000) {
logerror ("\npit68230_device::read: previous identical operation performed %02x times\n", or_cnt);
or_cnt = 0;
or_data = data;
or_ofs = offset;
logerror ("pit68230_device::read: offset=%02x data=%02x %lld\n", or_ofs, or_data, machine ().firstcpu->total_cycles ());
}
else
or_cnt++; )
LOG (if (offset != or_ofs || data != or_data || or_cnt >= 1000) {
logerror ("\npit68230_device::read: previous identical operation performed %02x times\n", or_cnt);
or_cnt = 0;
or_data = data;
or_ofs = offset;
logerror ("pit68230_device::read: offset=%02x data=%02x %lld\n", or_ofs, or_data, machine ().firstcpu->total_cycles ());
}
else
or_cnt++; )
return data;
return data;
}

10
src/devices/machine/68230pit.h
View File

@ -44,13 +44,13 @@
//**************************************************************************
#define MCFG_PIT68230_PA_OUTPUT_CALLBACK(_write) \
devcb = &pit68230_device::set_pa_wr_callback (*device, DEVCB_ ## _write);
devcb = &pit68230_device::set_pa_wr_callback (*device, DEVCB_ ## _write);
#define MCFG_PIT68230_PB_OUTPUT_CALLBACK(_write) \
devcb = &pit68230_device::set_pb_wr_callback (*device, DEVCB_ ## _write);
devcb = &pit68230_device::set_pb_wr_callback (*device, DEVCB_ ## _write);
#define MCFG_PIT68230_H2_CALLBACK(_write) \
devcb = &pit68230_device::set_h2_wr_callback (*device, DEVCB_ ## _write);
devcb = &pit68230_device::set_h2_wr_callback (*device, DEVCB_ ## _write);
/*-----------------------------------------------------------------------
* Registers RS1-RS5 R/W Description
@ -90,11 +90,11 @@ pit68230_device(const machine_config &mconfig, device_type type, const char *nam
pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
template<class _Object> static devcb_base &set_pa_wr_callback (device_t &device, _Object object)
{
return downcast<pit68230_device &>(device).m_write_pa.set_callback (object);
return downcast<pit68230_device &>(device).m_write_pa.set_callback (object);
}
template<class _Object> static devcb_base &set_h2_wr_callback (device_t &device, _Object object)
{
return downcast<pit68230_device &>(device).m_write_h2.set_callback (object);
return downcast<pit68230_device &>(device).m_write_h2.set_callback (object);
}
DECLARE_WRITE8_MEMBER (write);

6
src/devices/machine/i8271.c
View File

@ -501,7 +501,7 @@ void i8271_device::live_run(attotime limit)
scan_cnt[1] = slot >> 9;
scan_done = true;
rr = command[4] & 0xc0 ? ERR_SMNE : ERR_SMEQ;
}
}
else
{
scan_match = true;
@ -753,7 +753,7 @@ void i8271_device::start_command(int cmd)
{
floppy_info &fi = flopi[BIT(command[0], 7)];
rr = (get_ready(1) ? 0x40 : 0) | (fi.dev->idx_r() ? 0x10 : 0) | (fi.dev->wpt_r() ? 0 : 8) |
(get_ready(0) ? 4 : 0) | (fi.dev->trk00_r() ? 1 : 0);
(get_ready(0) ? 4 : 0) | (fi.dev->trk00_r() ? 1 : 0);
flopi[0].ready = true;
flopi[1].ready = true;
main_phase = PHASE_IDLE;
@ -819,7 +819,7 @@ void i8271_device::start_command(int cmd)
case 0x22: {
floppy_info &fi = flopi[BIT(command[0], 7)];
rr = (get_ready(1) ? 0x40 : 0) | (fi.dev->idx_r() ? 0x10 : 0) | (fi.dev->wpt_r() ? 0 : 8) |
(get_ready(0) ? 4 : 0) | (fi.dev->trk00_r() ? 1 : 0);
(get_ready(0) ? 4 : 0) | (fi.dev->trk00_r() ? 1 : 0);
break;
}
case 0x23:

21
src/devices/machine/vt82c496.c
View File

@ -2,7 +2,7 @@
// copyright-holders:Barry Rodewald
/*
VIA VT82C496G "Green PC" system chipset
VIA VT82C496G "Green PC" system chipset
*/
@ -30,9 +30,9 @@ void vt82c496_device::device_start()
/* get rom region */
m_rom = machine().root_device().memregion(m_region_tag)->base();
save_pointer(m_reg,"Registers",0x100);
m_ram = machine().device<ram_device>(RAM_TAG);
}
@ -106,7 +106,7 @@ void vt82c496_device::update_mem_c0(UINT8 data)
}
else
m_space->nop_write(0xcc000,0xcffff,0,0);
if(data & 0x20)
machine().root_device().membank("bios_c8_r")->set_base(m_ram->pointer()+0xc8000);
else
@ -118,7 +118,7 @@ void vt82c496_device::update_mem_c0(UINT8 data)
}
else
m_space->nop_write(0xc8000,0xcbfff,0,0);
if(data & 0x08)
machine().root_device().membank("bios_c4_r")->set_base(m_ram->pointer()+0xc4000);
else
@ -130,7 +130,7 @@ void vt82c496_device::update_mem_c0(UINT8 data)
}
else
m_space->nop_write(0xc4000,0xc7fff,0,0);
if(data & 0x02)
machine().root_device().membank("bios_c0_r")->set_base(m_ram->pointer()+0xc0000);
else
@ -157,7 +157,7 @@ void vt82c496_device::update_mem_d0(UINT8 data)
}
else
m_space->nop_write(0xdc000,0xdffff,0,0);
if(data & 0x20)
machine().root_device().membank("bios_d8_r")->set_base(m_ram->pointer()+0xd8000);
else
@ -169,7 +169,7 @@ void vt82c496_device::update_mem_d0(UINT8 data)
}
else
m_space->nop_write(0xd8000,0xdbfff,0,0);
if(data & 0x08)
machine().root_device().membank("bios_d4_r")->set_base(m_ram->pointer()+0xd4000);
else
@ -181,7 +181,7 @@ void vt82c496_device::update_mem_d0(UINT8 data)
}
else
m_space->nop_write(0xd4000,0xd7fff,0,0);
if(data & 0x02)
machine().root_device().membank("bios_d0_r")->set_base(m_ram->pointer()+0xd0000);
else
@ -214,7 +214,7 @@ void vt82c496_device::update_mem_e0(UINT8 data)
machine().root_device().membank("bios_f0_r")->set_base(m_ram->pointer()+0xf0000);
else
machine().root_device().membank("bios_f0_r")->set_base(m_rom+0x30000);
if(data & 0x10)
{
m_space->install_write_bank(0xf0000,0xfffff,0,0,"bios_f0_w");
@ -223,4 +223,3 @@ void vt82c496_device::update_mem_e0(UINT8 data)
else
m_space->nop_write(0xf0000,0xfffff,0,0);
}

9
src/devices/machine/vt82c496.h
View File

@ -2,7 +2,7 @@
// copyright-holders:Barry Rodewald
/*
VIA VT82C496G "Green PC" system chipset
VIA VT82C496G "Green PC" system chipset
*/
@ -40,14 +40,14 @@ protected:
private:
const char* m_cpu_tag;
const char* m_region_tag;
// cpu_device* m_maincpu;
// cpu_device* m_maincpu;
address_space* m_space;
ram_device* m_ram;
UINT8* m_rom;
UINT8 m_reg[0x100];
UINT8 m_reg_select;
void update_mem_c0(UINT8 data);
void update_mem_d0(UINT8 data);
void update_mem_e0(UINT8 data);
@ -58,4 +58,3 @@ extern const device_type VT82C496;
#endif /* __VT82C496_H__ */

1401
src/devices/machine/z80scc.c
View File

File diff suppressed because it is too large Load Diff

334
src/devices/machine/z80scc.h
View File

@ -126,41 +126,41 @@ public:
virtual void rcv_callback();
virtual void rcv_complete();
// read register handlers
UINT8 do_sccreg_rr0();
UINT8 do_sccreg_rr1();
UINT8 do_sccreg_rr2();
UINT8 do_sccreg_rr3();
UINT8 do_sccreg_rr4();
UINT8 do_sccreg_rr5();
UINT8 do_sccreg_rr6();
UINT8 do_sccreg_rr7();
UINT8 do_sccreg_rr8();
UINT8 do_sccreg_rr9();
UINT8 do_sccreg_rr10();
UINT8 do_sccreg_rr11();
UINT8 do_sccreg_rr12();
UINT8 do_sccreg_rr13();
UINT8 do_sccreg_rr14();
UINT8 do_sccreg_rr15();
// read register handlers
UINT8 do_sccreg_rr0();
UINT8 do_sccreg_rr1();
UINT8 do_sccreg_rr2();
UINT8 do_sccreg_rr3();
UINT8 do_sccreg_rr4();
UINT8 do_sccreg_rr5();
UINT8 do_sccreg_rr6();
UINT8 do_sccreg_rr7();
UINT8 do_sccreg_rr8();
UINT8 do_sccreg_rr9();
UINT8 do_sccreg_rr10();
UINT8 do_sccreg_rr11();
UINT8 do_sccreg_rr12();
UINT8 do_sccreg_rr13();
UINT8 do_sccreg_rr14();
UINT8 do_sccreg_rr15();
// write register handlers
void do_sccreg_wr0(UINT8 data);
void do_sccreg_wr1(UINT8 data);
void do_sccreg_wr2(UINT8 data);
void do_sccreg_wr3(UINT8 data);
void do_sccreg_wr4(UINT8 data);
void do_sccreg_wr5(UINT8 data);
void do_sccreg_wr6(UINT8 data);
void do_sccreg_wr7(UINT8 data);
void do_sccreg_wr8(UINT8 data);
void do_sccreg_wr9(UINT8 data);
void do_sccreg_wr10(UINT8 data);
void do_sccreg_wr11(UINT8 data);
void do_sccreg_wr12(UINT8 data);
void do_sccreg_wr13(UINT8 data);
void do_sccreg_wr14(UINT8 data);
void do_sccreg_wr15(UINT8 data);
// write register handlers
void do_sccreg_wr0(UINT8 data);
void do_sccreg_wr1(UINT8 data);
void do_sccreg_wr2(UINT8 data);
void do_sccreg_wr3(UINT8 data);
void do_sccreg_wr4(UINT8 data);
void do_sccreg_wr5(UINT8 data);
void do_sccreg_wr6(UINT8 data);
void do_sccreg_wr7(UINT8 data);
void do_sccreg_wr8(UINT8 data);
void do_sccreg_wr9(UINT8 data);
void do_sccreg_wr10(UINT8 data);
void do_sccreg_wr11(UINT8 data);
void do_sccreg_wr12(UINT8 data);
void do_sccreg_wr13(UINT8 data);
void do_sccreg_wr14(UINT8 data);
void do_sccreg_wr15(UINT8 data);
UINT8 control_read();
void control_write(UINT8 data);
@ -170,7 +170,7 @@ public:
void receive_data(UINT8 data);
void m_rx_fifo_rp_step();
UINT8 m_rx_fifo_rp_data();
UINT8 m_rx_fifo_rp_data();
DECLARE_WRITE_LINE_MEMBER( write_rx );
DECLARE_WRITE_LINE_MEMBER( cts_w );
@ -184,9 +184,9 @@ public:
int m_txc;
// Register state
// read registers enum
// read registers enum
#if 0 //defined by z80sio.h
UINT8 m_rr0; // REG_RR0_STATUS
UINT8 m_rr0; // REG_RR0_STATUS
UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND
UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT
#endif
@ -204,18 +204,18 @@ public:
UINT8 m_rr14; // REG_RR14_WR7_OR_R10
UINT8 m_rr15; // REG_RR15_WR15_EXT_STAT
// write registers enum
// write registers enum
#if 0 //defined by z80sio.h
UINT8 m_wr0; // REG_WR0_COMMAND_REGPT
UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
UINT8 m_wr2; // REG_WR2_INT_VECTOR
UINT8 m_wr3; // REG_WR3_RX_CONTROL
UINT8 m_wr4; // REG_WR4_RX_TX_MODES
UINT8 m_wr5; // REG_WR5_TX_CONTROL
UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A
UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F
UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
UINT8 m_wr2; // REG_WR2_INT_VECTOR
UINT8 m_wr3; // REG_WR3_RX_CONTROL
UINT8 m_wr4; // REG_WR4_RX_TX_MODES
UINT8 m_wr5; // REG_WR5_TX_CONTROL
UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A
UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F
#endif
UINT8 m_wr8; // REG_WR8_TRANSMIT_DATA
UINT8 m_wr8; // REG_WR8_TRANSMIT_DATA
UINT8 m_wr9; // REG_WR9_MASTER_INT_CTRL
UINT8 m_wr10; // REG_WR10_MSC_RX_TX_CTRL
UINT8 m_wr11; // REG_WR11_CLOCK_MODES
@ -223,7 +223,7 @@ public:
UINT8 m_wr13; // REG_WR13_HI_BAUD_GEN
UINT8 m_wr14; // REG_WR14_MISC_CTRL
UINT8 m_wr15; // REG_WR15_EXT_ST_INT_CTRL
protected:
enum
@ -231,50 +231,50 @@ protected:
INT_TRANSMIT = 0,
INT_EXTERNAL = 1,
INT_RECEIVE = 2,
INT_SPECIAL = 3
INT_SPECIAL = 3
};
// Read registers
enum
{
REG_RR0_STATUS = 0, // SIO
REG_RR1_SPEC_RCV_COND = 1, // SIO
REG_RR2_INTERRUPT_VECT = 2, // SIO
REG_RR3_INTERUPPT_PEND = 3,
REG_RR4_WR4_OR_RR0 = 4,
REG_RR5_WR5_OR_RR0 = 5,
REG_RR6_LSB_OR_RR2 = 6,
REG_RR7_MSB_OR_RR3 = 7,
REG_RR8_RECEIVE_DATA = 8,
REG_RR9_WR3_OR_RR13 = 9,
REG_RR10_MISC_STATUS = 10,
REG_RR11_WR10_OR_RR15 = 11,
REG_RR12_LO_TIME_CONST = 12,
REG_RR13_HI_TIME_CONST = 13,
REG_RR14_WR7_OR_R10 = 14,
REG_RR15_WR15_EXT_STAT = 15
};
// Read registers
enum
{
REG_RR0_STATUS = 0, // SIO
REG_RR1_SPEC_RCV_COND = 1, // SIO
REG_RR2_INTERRUPT_VECT = 2, // SIO
REG_RR3_INTERUPPT_PEND = 3,
REG_RR4_WR4_OR_RR0 = 4,
REG_RR5_WR5_OR_RR0 = 5,
REG_RR6_LSB_OR_RR2 = 6,
REG_RR7_MSB_OR_RR3 = 7,
REG_RR8_RECEIVE_DATA = 8,
REG_RR9_WR3_OR_RR13 = 9,
REG_RR10_MISC_STATUS = 10,
REG_RR11_WR10_OR_RR15 = 11,
REG_RR12_LO_TIME_CONST = 12,
REG_RR13_HI_TIME_CONST = 13,
REG_RR14_WR7_OR_R10 = 14,
REG_RR15_WR15_EXT_STAT = 15
};
// Write registers
enum
{
REG_WR0_COMMAND_REGPT = 0, // SIO
REG_WR1_INT_DMA_ENABLE = 1, // SIO
REG_WR2_INT_VECTOR = 2, // SIO
REG_WR3_RX_CONTROL = 3, // SIO
REG_WR4_RX_TX_MODES = 4, // SIO
REG_WR5_TX_CONTROL = 5, // SIO
REG_WR6_SYNC_OR_SDLC_A = 6, // SIO
REG_WR7_SYNC_OR_SDLC_F = 7, // SIO
REG_WR8_TRANSMIT_DATA = 8,
REG_WR9_MASTER_INT_CTRL = 9,
REG_WR10_MSC_RX_TX_CTRL = 10,
REG_WR11_CLOCK_MODES = 11,
REG_WR12_LO_BAUD_GEN = 12,
REG_WR13_HI_BAUD_GEN = 13,
REG_WR14_MISC_CTRL = 14,
REG_WR15_EXT_ST_INT_CTRL= 15
};
// Write registers
enum
{
REG_WR0_COMMAND_REGPT = 0, // SIO
REG_WR1_INT_DMA_ENABLE = 1, // SIO
REG_WR2_INT_VECTOR = 2, // SIO
REG_WR3_RX_CONTROL = 3, // SIO
REG_WR4_RX_TX_MODES = 4, // SIO
REG_WR5_TX_CONTROL = 5, // SIO
REG_WR6_SYNC_OR_SDLC_A = 6, // SIO
REG_WR7_SYNC_OR_SDLC_F = 7, // SIO
REG_WR8_TRANSMIT_DATA = 8,
REG_WR9_MASTER_INT_CTRL = 9,
REG_WR10_MSC_RX_TX_CTRL = 10,
REG_WR11_CLOCK_MODES = 11,
REG_WR12_LO_BAUD_GEN = 12,
REG_WR13_HI_BAUD_GEN = 13,
REG_WR14_MISC_CTRL = 14,
REG_WR15_EXT_ST_INT_CTRL= 15
};
enum
{
@ -282,7 +282,7 @@ protected:
RR0_ZC = 0x02, // SCC bit
RR0_TX_BUFFER_EMPTY = 0x04, // SIO
RR0_DCD = 0x08, // SIO
RR0_RI = 0x10, // DART bit? TODO: investigate function and remove
RR0_RI = 0x10, // DART bit? TODO: investigate function and remove
RR0_SYNC_HUNT = 0x10, // SIO bit, not supported
RR0_CTS = 0x20, // SIO bit
RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported
@ -299,30 +299,30 @@ protected:
RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported
};
enum
{ // TODO: overload SIO functionality
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
};
enum
{ // TODO: overload SIO functionality
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
};
enum
{
RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers
RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels)
RR3_CHANB_RX_IP = 0x04, // channel B return all zero
RR3_CHANA_EXT_IP = 0x08,
RR3_CHANA_TX_IP = 0x10,
RR3_CHANA_RX_IP = 0x20
};
enum
{
RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers
RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels)
RR3_CHANB_RX_IP = 0x04, // channel B return all zero
RR3_CHANA_EXT_IP = 0x08,
RR3_CHANA_TX_IP = 0x10,
RR3_CHANA_RX_IP = 0x20
};
enum // Universal Bus WR0 commands for 85X30
{
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38, // COMMANDS
WR0_NULL = 0x00, // 0 0 0
WR0_POINT_HIGH = 0x08, // 0 0 1
WR0_POINT_HIGH = 0x08, // 0 0 1
WR0_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_SEND_ABORT = 0x18, // 0 1 1
WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
@ -340,17 +340,17 @@ protected:
{
WR0_Z_COMMAND_MASK = 0x38, // COMMANDS
WR0_Z_NULL_1 = 0x00, // 0 0 0
WR0_Z_NULL_2 = 0x08, // 0 0 1
WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_Z_NULL_2 = 0x08, // 0 0 1
WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_Z_SEND_ABORT = 0x18, // 0 1 1
WR0_Z_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
WR0_Z_RESET_TX_INT = 0x28, // 1 0 1
WR0_Z_ERROR_RESET = 0x30, // 1 1 0
WR0_Z_RESET_HIGHEST_IUS = 0x38, // 1 1 1
WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B
WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0
WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1
};
WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B
WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0
WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1
};
enum
{
@ -417,62 +417,62 @@ protected:
WR5_DTR = 0x80
};
/* SCC specifics */
enum
{
WR9_CMD_MASK = 0xC0,
WR9_CMD_NORESET = 0x00,
WR9_CMD_CHNB_RESET = 0x40,
WR9_CMD_CHNA_RESET = 0x80,
WR9_CMD_HW_RESET = 0xC0,
WR9_BIT_VIS = 0x01,
WR9_BIT_NV = 0x02,
WR9_BIT_DLC = 0x04,
WR9_BIT_MIE = 0x08,
WR9_BIT_SHSL = 0x10,
WR9_BIT_IACK = 0x20
};
/* SCC specifics */
enum
{
WR9_CMD_MASK = 0xC0,
WR9_CMD_NORESET = 0x00,
WR9_CMD_CHNB_RESET = 0x40,
WR9_CMD_CHNA_RESET = 0x80,
WR9_CMD_HW_RESET = 0xC0,
WR9_BIT_VIS = 0x01,
WR9_BIT_NV = 0x02,
WR9_BIT_DLC = 0x04,
WR9_BIT_MIE = 0x08,
WR9_BIT_SHSL = 0x10,
WR9_BIT_IACK = 0x20
};
enum
{
WR11_RCVCLK_TYPE = 0x80,
WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK
WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0
WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1
WR11_RCVCLK_SRC_BR = 0x40, // 1 0
WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1
WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK
WR11_TRACLK_SRC_RTXC = 0x00, // 0 0
WR11_TRACLK_SRC_TRXC = 0x08, // 0 1
WR11_TRACLK_SRC_BR = 0x10, // 1 0
WR11_TRACLK_SRC_DPLL = 0x18, // 1 1
WR11_TRXC_DIRECTION = 0x04,
WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK
WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0
WR11_TRXSRC_SRC_TRA = 0x01, // 0 1
WR11_TRXSRC_SRC_BR = 0x02, // 1 0
WR11_TRXSRC_SRC_DPLL = 0x03, // 1 1
};
enum
{
WR11_RCVCLK_TYPE = 0x80,
WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK
WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0
WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1
WR11_RCVCLK_SRC_BR = 0x40, // 1 0
WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1
WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK
WR11_TRACLK_SRC_RTXC = 0x00, // 0 0
WR11_TRACLK_SRC_TRXC = 0x08, // 0 1
WR11_TRACLK_SRC_BR = 0x10, // 1 0
WR11_TRACLK_SRC_DPLL = 0x18, // 1 1
WR11_TRXC_DIRECTION = 0x04,
WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK
WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0
WR11_TRXSRC_SRC_TRA = 0x01, // 0 1
WR11_TRXSRC_SRC_BR = 0x02, // 1 0
WR11_TRXSRC_SRC_DPLL = 0x03, // 1 1
};
enum
{
WR14_DPLL_CMD_MASK = 0xe0, // Command
WR14_CMD_NULL = 0x00, // 0 0 0
WR14_CMD_ESM = 0x20, // 0 0 1
WR14_CMD_RMC = 0x40, // 0 1 0
WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1
WR14_CMD_SS_BGR = 0x80, // 1 0 0
WR14_CMD_SS_RTXC = 0xa0, // 1 0 1
WR14_CMD_SET_FM = 0xc0, // 1 1 0
WR14_CMD_SET_NRZI = 0xe0 // 1 1 1
};
enum
{
WR14_DPLL_CMD_MASK = 0xe0, // Command
WR14_CMD_NULL = 0x00, // 0 0 0
WR14_CMD_ESM = 0x20, // 0 0 1
WR14_CMD_RMC = 0x40, // 0 1 0
WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1
WR14_CMD_SS_BGR = 0x80, // 1 0 0
WR14_CMD_SS_RTXC = 0xa0, // 1 0 1
WR14_CMD_SET_FM = 0xc0, // 1 1 0
WR14_CMD_SET_NRZI = 0xe0 // 1 1 1
};
void update_serial();
void set_dtr(int state);
void set_rts(int state);
int get_clock_mode();
void update_rts();
void update_rts();
stop_bits_t get_stop_bits();
int get_rx_word_length();
int get_tx_word_length();
@ -482,7 +482,7 @@ protected:
UINT8 m_rx_error_fifo[8]; // receive error FIFO
UINT8 m_rx_error; // current receive error
//int m_rx_fifo // receive FIFO pointer
int m_rx_fifo_rp; // receive FIFO read pointer
int m_rx_fifo_rp; // receive FIFO read pointer
int m_rx_fifo_wp; // receive FIFO write pointer
int m_rx_fifo_sz; // receive FIFO size
@ -506,19 +506,19 @@ protected:
// synchronous state
UINT16 m_sync; // sync character
// int m_index;
// int m_index;
z80scc_device *m_uart;
// SCC specifics
int m_ph; // Point high command to access regs 08-0f
UINT8 m_zc;
UINT8 m_zc;
};
// ======================> z80scc_device
class z80scc_device : public device_t
,public device_z80daisy_interface
,public device_z80daisy_interface
{
friend class z80scc_channel;
@ -604,7 +604,7 @@ protected:
void trigger_interrupt(int index, int state);
int get_channel_index(z80scc_channel *ch) { return (ch == m_chanA) ? 0 : 1; }
// Variants in the SCC family
// Variants in the SCC family
enum
{
TYPE_Z80SCC = 0x001,
@ -615,7 +615,7 @@ protected:
TYPE_SCC85C30 = 0x020,
TYPE_SCC85230 = 0x040,
TYPE_SCC85233 = 0x080,
TYPE_SCC8523L = 0x100
TYPE_SCC8523L = 0x100
};
#define SET_NMOS ( z80scc_device::TYPE_SCC8030 | z80scc_device::TYPE_SCC8530 )
@ -624,7 +624,7 @@ protected:
#define SET_EMSCC z80scc_device::TYPE_SCC85233
#define SET_Z80X30 ( z80scc_device::TYPE_SCC8030 | z80scc_device::TYPE_SCC80C30 | z80scc_device::TYPE_SCC80230 )
#define SET_Z85X3X ( z80scc_device::TYPE_SCC8530 | z80scc_device::TYPE_SCC85C30 | z80scc_device::TYPE_SCC85230 \
| z80scc_device::TYPE_SCC8523L | z80scc_device::TYPE_SCC85233 )
| z80scc_device::TYPE_SCC8523L | z80scc_device::TYPE_SCC85233 )
enum
{

398
src/devices/machine/z80sio.c
View File

@ -5,13 +5,13 @@
Z80-SIO Serial Input/Output emulation
The variants in the SIO family are only different in the packaging
but has the same register features. However, since some signals are
but has the same register features. However, since some signals are
not connected to the pins on the package or share a pin with another
signal the functionality is limited. However, this driver does not
check that an operation is invalid because of package type but relies
on the software to be adapated for the particular version.
Package: DIP40 SIO/0, SIO/1, SIO/2,
Package: DIP40 SIO/0, SIO/1, SIO/2,
QFP44 SIO/3
PLCC44 SIO/4
-------------------------------------------------------------------
@ -21,25 +21,25 @@
6MHz 1200Kbps
10MHz 2500Kbps
-- Asynchrounous features -------------------------------------------
5-8 bit per char Y
1,1.5,2 stop bits Y
odd/even parity Y
x1,x16,x32,x64 Y
break det/gen Y
parity, framing & Y
overrun error det Y
5-8 bit per char Y
1,1.5,2 stop bits Y
odd/even parity Y
x1,x16,x32,x64 Y
break det/gen Y
parity, framing & Y
overrun error det Y
-- Byte oriented synchrounous features -------------------------------
Int/ext char sync Y
1/2 synch chars Y
Aut synch char insertion Y
Aut CRC gen/det Y
Int/ext char sync Y
1/2 synch chars Y
Aut synch char insertion Y
Aut CRC gen/det Y
-- SDLC/HDLC capabilities --------------------------------------------
Abort seq gen/chk Y
Aut zero ins/det Y
Aut flag insert Y
Addr field rec Y
1-fld resid hand Y
Valid rec msg protection Y
Abort seq gen/chk Y
Aut zero ins/det Y
Aut flag insert Y
Addr field rec Y
1-fld resid hand Y
Valid rec msg protection Y
--
Receiver FIFO 3
Transmitter FIFO 1
@ -135,29 +135,29 @@ z80sio_device::z80sio_device(const machine_config &mconfig, device_type type, co
z80sio_device::z80sio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, Z80SIO, "Z80 SIO", tag, owner, clock, "z80sio", __FILE__),
device_z80daisy_interface(mconfig, *this),
m_chanA(*this, CHANA_TAG),
m_chanB(*this, CHANB_TAG),
m_rxca(0),
m_txca(0),
m_rxcb(0),
m_txcb(0),
m_out_txda_cb(*this),
m_out_dtra_cb(*this),
m_out_rtsa_cb(*this),
m_out_wrdya_cb(*this),
m_out_synca_cb(*this),
m_out_txdb_cb(*this),
m_out_dtrb_cb(*this),
m_out_rtsb_cb(*this),
m_out_wrdyb_cb(*this),
m_out_syncb_cb(*this),
m_out_int_cb(*this),
m_out_rxdrqa_cb(*this),
m_out_txdrqa_cb(*this),
m_out_rxdrqb_cb(*this),
m_out_txdrqb_cb(*this),
m_variant(TYPE_Z80SIO)
device_z80daisy_interface(mconfig, *this),
m_chanA(*this, CHANA_TAG),
m_chanB(*this, CHANB_TAG),
m_rxca(0),
m_txca(0),
m_rxcb(0),
m_txcb(0),
m_out_txda_cb(*this),
m_out_dtra_cb(*this),
m_out_rtsa_cb(*this),
m_out_wrdya_cb(*this),
m_out_synca_cb(*this),
m_out_txdb_cb(*this),
m_out_dtrb_cb(*this),
m_out_rtsb_cb(*this),
m_out_wrdyb_cb(*this),
m_out_syncb_cb(*this),
m_out_int_cb(*this),
m_out_rxdrqa_cb(*this),
m_out_txdrqa_cb(*this),
m_out_rxdrqb_cb(*this),
m_out_txdrqb_cb(*this),
m_variant(TYPE_Z80SIO)
{
for (int i = 0; i < 8; i++)
m_int_state[i] = 0;
@ -169,7 +169,7 @@ z80sio_device::z80sio_device(const machine_config &mconfig, const char *tag, dev
void z80sio_device::device_start()
{
LOG(("%s\n", FUNCNAME));
LOG(("%s\n", FUNCNAME));
// resolve callbacks
m_out_txda_cb.resolve_safe();
m_out_dtra_cb.resolve_safe();
@ -222,8 +222,8 @@ int z80sio_device::z80daisy_irq_state()
int i;
LOG(("Z80SIO \"%s\" : Interrupt State A:%d%d%d%d B:%d%d%d%d\n", tag(),
m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3],
m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7]));
m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3],
m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7]));
// loop over all interrupt sources
for (i = 0; i < 8; i++)
@ -386,7 +386,7 @@ void z80sio_device::trigger_interrupt(int index, int state)
// status affects vector
vector = (m_chanB->m_wr2 & 0xf1) | (!index << 3) | (state << 1);
}
// }
// }
LOG(("Z80SIO \"%s\" Channel %c : Interrupt Request %u\n", tag(), 'A' + index, state));
@ -422,7 +422,7 @@ READ8_MEMBER( z80sio_device::cd_ba_r )
int cd = BIT(offset, 1);
z80sio_channel *channel = ba ? m_chanB : m_chanA;
// LOG(("z80sio_device::cd_ba_r ba:%02x cd:%02x\n", ba, cd));
// LOG(("z80sio_device::cd_ba_r ba:%02x cd:%02x\n", ba, cd));
return cd ? channel->control_read() : channel->data_read();
}
@ -438,7 +438,7 @@ WRITE8_MEMBER( z80sio_device::cd_ba_w )
int cd = BIT(offset, 1);
z80sio_channel *channel = ba ? m_chanB : m_chanA;
LOG(("z80sio_device::cd_ba_w ba:%02x cd:%02x\n", ba, cd));
LOG(("z80sio_device::cd_ba_w ba:%02x cd:%02x\n", ba, cd));
if (cd)
channel->control_write(data);
@ -457,7 +457,7 @@ READ8_MEMBER( z80sio_device::ba_cd_r )
int cd = BIT(offset, 0);
z80sio_channel *channel = ba ? m_chanB : m_chanA;
// LOG(("z80sio_device::ba_cd_r ba:%02x cd:%02x\n", ba, cd));
// LOG(("z80sio_device::ba_cd_r ba:%02x cd:%02x\n", ba, cd));
return cd ? channel->control_read() : channel->data_read();
}
@ -473,7 +473,7 @@ WRITE8_MEMBER( z80sio_device::ba_cd_w )
int cd = BIT(offset, 0);
z80sio_channel *channel = ba ? m_chanB : m_chanA;
LOG(("z80sio_device::ba_cd_w ba:%02x cd:%02x\n", ba, cd));
LOG(("z80sio_device::ba_cd_w ba:%02x cd:%02x\n", ba, cd));
if (cd)
channel->control_write(data);
@ -508,9 +508,9 @@ z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, d
m_rts(0),
m_sync(0)
{
// Reset all registers
m_rr0 = m_rr1 = m_rr2 = 0;
m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = 0;
// Reset all registers
m_rr0 = m_rr1 = m_rr2 = 0;
m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = 0;
for (int i = 0; i < 3; i++)
{
@ -526,7 +526,7 @@ z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, d
void z80sio_channel::device_start()
{
LOG(("%s\n",FUNCNAME));
LOG(("%s\n",FUNCNAME));
m_uart = downcast<z80sio_device *>(owner());
m_index = m_uart->get_channel_index(this);
@ -568,7 +568,7 @@ void z80sio_channel::device_start()
void z80sio_channel::device_reset()
{
LOG(("%s\n", FUNCNAME));
LOG(("%s\n", FUNCNAME));
receive_register_reset();
transmit_register_reset();
@ -722,11 +722,11 @@ int z80sio_channel::get_clock_mode()
}
/* From "uPD7201/7201A MULTI PROTOCOL SERIAL COMMUNICATION CONTROLLER" by NEC:
"RTSA (Request to Send A): The state of the RTS bit (01 of the CR5 register) controls this pin. If
the RTS bit is reset in the asynchronous mode, a high level will not be output on the RTS pin until
all transmit characters are written and the all sent bit (D0 of the SR1 register) is set. In the
synchronous mode, the state of the RTS bit is used as is. That is, when the RTS bit is 0, the RTS
pin is 1. When the RTS bit is 1, the RTS pin is O."
"RTSA (Request to Send A): The state of the RTS bit (01 of the CR5 register) controls this pin. If
the RTS bit is reset in the asynchronous mode, a high level will not be output on the RTS pin until
all transmit characters are written and the all sent bit (D0 of the SR1 register) is set. In the
synchronous mode, the state of the RTS bit is used as is. That is, when the RTS bit is 0, the RTS
pin is 1. When the RTS bit is 1, the RTS pin is O."
CR5 = m_wr5 and SR1 = m_rr1
@ -742,20 +742,20 @@ void z80sio_channel::set_rts(int state)
void z80sio_channel::update_rts()
{
if (m_wr5 & WR5_RTS)
{
// when the RTS bit is set, the _RTS output goes low
set_rts(0);
m_rts = 1;
}
else
{
// when the RTS bit is reset, the _RTS output goes high after the transmitter empties
m_rts = 0;
}
if (m_wr5 & WR5_RTS)
{
// when the RTS bit is set, the _RTS output goes low
set_rts(0);
m_rts = 1;
}
else
{
// when the RTS bit is reset, the _RTS output goes high after the transmitter empties
m_rts = 0;
}
// data terminal ready output follows the state programmed into the DTR bit*/
set_dtr((m_wr5 & WR5_DTR) ? 0 : 1);
// data terminal ready output follows the state programmed into the DTR bit*/
set_dtr((m_wr5 & WR5_DTR) ? 0 : 1);
}
//-------------------------------------------------
@ -820,14 +820,14 @@ int z80sio_channel::get_tx_word_length()
* Break/Abort latch. */
UINT8 z80sio_channel::do_sioreg_rr0()
{
return m_rr0;
return m_rr0;
}
/*
* This register contains the Special Receive condition status bits and Residue
* codes for the I-Field in the SDLC Receive Mode. */
UINT8 z80sio_channel::do_sioreg_rr1()
{
return m_rr1;
return m_rr1;
}
/*
* This register contains the interrupt vector written into WR2 if the Status
@ -839,8 +839,8 @@ no interrupts are pending, the vector is modified with V3 = 0, V2 = 1, and
V1 = 1. This register is read only through Channel B. */
UINT8 z80sio_channel::do_sioreg_rr2()
{
// channel B only
return m_index == z80sio_device::CHANNEL_B ? m_rr2 : 0;
// channel B only
return m_index == z80sio_device::CHANNEL_B ? m_rr2 : 0;
}
@ -851,7 +851,7 @@ UINT8 z80sio_channel::do_sioreg_rr2()
UINT8 z80sio_channel::control_read()
{
UINT8 data = 0;
UINT8 reg = m_wr0 & WR0_REGISTER_MASK;
UINT8 reg = m_wr0 & WR0_REGISTER_MASK;
if (reg != 0)
{
@ -865,7 +865,7 @@ UINT8 z80sio_channel::control_read()
case REG_RR1_SPEC_RCV_COND: data = do_sioreg_rr1(); break;
case REG_RR2_INTERRUPT_VECT: data = do_sioreg_rr2(); break;
default:
logerror("Z80SIO \"%s\" Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
logerror("Z80SIO \"%s\" Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
}
//LOG(("Z80SIO \"%s\" Channel %c : Register R%d read '%02x'\n", m_owner->tag(), 'A' + m_index, reg, data));
@ -876,158 +876,158 @@ UINT8 z80sio_channel::control_read()
Handle the WR0 CRC Reset/Init bits separatelly, needed by derived devices separatelly from the commands */
void z80sio_channel::do_sioreg_wr0_resets(UINT8 data)
{
switch (data & WR0_CRC_RESET_CODE_MASK)
{
case WR0_CRC_RESET_NULL:
LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_NULL\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_CRC_RESET_RX: /* In Synchronous mode: all Os (zeros) (CCITT-O CRC-16) */
LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_RX - not implemented\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_CRC_RESET_TX: /* In HDLC mode: all 1s (ones) (CCITT-1) */
LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_TX - not implemented\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the SRO register) */
LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_TX_UNDERRUN - not implemented\n", m_owner->tag(), 'A' + m_index));
break;
default: /* Will not happen unless someone messes with the mask */
logerror("Z80SIO \"%s\" Channel %c : %s Wrong CRC reset/init command:%02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data & WR0_CRC_RESET_CODE_MASK);
}
switch (data & WR0_CRC_RESET_CODE_MASK)
{
case WR0_CRC_RESET_NULL:
LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_NULL\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_CRC_RESET_RX: /* In Synchronous mode: all Os (zeros) (CCITT-O CRC-16) */
LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_RX - not implemented\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_CRC_RESET_TX: /* In HDLC mode: all 1s (ones) (CCITT-1) */
LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_TX - not implemented\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_CRC_RESET_TX_UNDERRUN: /* Resets Tx underrun/EOM bit (D6 of the SRO register) */
LOG(("Z80SIO \"%s\" Channel %c : CRC_RESET_TX_UNDERRUN - not implemented\n", m_owner->tag(), 'A' + m_index));
break;
default: /* Will not happen unless someone messes with the mask */
logerror("Z80SIO \"%s\" Channel %c : %s Wrong CRC reset/init command:%02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data & WR0_CRC_RESET_CODE_MASK);
}
}
void z80sio_channel::do_sioreg_wr0(UINT8 data)
{
m_wr0 = data;
switch (data & WR0_COMMAND_MASK)
m_wr0 = data;
switch (data & WR0_COMMAND_MASK)
{
case WR0_NULL:
LOG(("Z80SIO \"%s\" Channel %c : Null\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_RESET_EXT_STATUS:
// reset external/status interrupt
m_rr0 &= ~(RR0_DCD | RR0_SYNC_HUNT | RR0_CTS | RR0_BREAK_ABORT);
// release the latch
m_rx_rr0_latch = 0;
// update register to reflect wire values TODO: Check if this will fire new interrupts
if (!m_dcd) m_rr0 |= RR0_DCD;
if (m_sync) m_rr0 |= RR0_SYNC_HUNT;
if (m_cts) m_rr0 |= RR0_CTS;
LOG(("Z80SIO \"%s\" Channel %c : Reset External/Status Interrupt\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_CHANNEL_RESET:
// channel reset
LOG(("Z80SIO \"%s\" Channel %c : Channel Reset\n", m_owner->tag(), 'A' + m_index));
device_reset();
break;
case WR0_ENABLE_INT_NEXT_RX:
// enable interrupt on next receive character
LOG(("Z80SIO \"%s\" Channel %c : Enable Interrupt on Next Received Character\n", m_owner->tag(), 'A' + m_index));
m_rx_first = 1;
break;
case WR0_RESET_TX_INT:
// reset transmitter interrupt pending
LOG(("Z80SIO \"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index));
logerror("Z80SIO \"%s\" Channel %c : unsupported command: Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index);
break;
case WR0_ERROR_RESET:
// error reset
LOG(("Z80SIO \"%s\" Channel %c : Error Reset\n", m_owner->tag(), 'A' + m_index));
m_rr1 &= ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR);
break;
case WR0_RETURN_FROM_INT:
// return from interrupt
LOG(("Z80SIO \"%s\" Channel %c : Return from Interrupt\n", m_owner->tag(), 'A' + m_index));
m_uart->z80daisy_irq_reti();
break;
default:
LOG(("Z80SIO \"%s\" Channel %c : Unsupported WR0 command %02x mask %02x\n", m_owner->tag(), 'A' + m_index, data, WR0_REGISTER_MASK));
case WR0_NULL:
LOG(("Z80SIO \"%s\" Channel %c : Null\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_RESET_EXT_STATUS:
// reset external/status interrupt
m_rr0 &= ~(RR0_DCD | RR0_SYNC_HUNT | RR0_CTS | RR0_BREAK_ABORT);
// release the latch
m_rx_rr0_latch = 0;
// update register to reflect wire values TODO: Check if this will fire new interrupts
if (!m_dcd) m_rr0 |= RR0_DCD;
if (m_sync) m_rr0 |= RR0_SYNC_HUNT;
if (m_cts) m_rr0 |= RR0_CTS;
}
do_sioreg_wr0_resets(data);
LOG(("Z80SIO \"%s\" Channel %c : Reset External/Status Interrupt\n", m_owner->tag(), 'A' + m_index));
break;
case WR0_CHANNEL_RESET:
// channel reset
LOG(("Z80SIO \"%s\" Channel %c : Channel Reset\n", m_owner->tag(), 'A' + m_index));
device_reset();
break;
case WR0_ENABLE_INT_NEXT_RX:
// enable interrupt on next receive character
LOG(("Z80SIO \"%s\" Channel %c : Enable Interrupt on Next Received Character\n", m_owner->tag(), 'A' + m_index));
m_rx_first = 1;
break;
case WR0_RESET_TX_INT:
// reset transmitter interrupt pending
LOG(("Z80SIO \"%s\" Channel %c : Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index));
logerror("Z80SIO \"%s\" Channel %c : unsupported command: Reset Transmitter Interrupt Pending\n", m_owner->tag(), 'A' + m_index);
break;
case WR0_ERROR_RESET:
// error reset
LOG(("Z80SIO \"%s\" Channel %c : Error Reset\n", m_owner->tag(), 'A' + m_index));
m_rr1 &= ~(RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR);
break;
case WR0_RETURN_FROM_INT:
// return from interrupt
LOG(("Z80SIO \"%s\" Channel %c : Return from Interrupt\n", m_owner->tag(), 'A' + m_index));
m_uart->z80daisy_irq_reti();
break;
default:
LOG(("Z80SIO \"%s\" Channel %c : Unsupported WR0 command %02x mask %02x\n", m_owner->tag(), 'A' + m_index, data, WR0_REGISTER_MASK));
}
do_sioreg_wr0_resets(data);
}
void z80sio_channel::do_sioreg_wr1(UINT8 data)
{
/* TODO: implement vector modifications when WR1 bit D2 is changed */
m_wr1 = data;
LOG(("Z80SIO \"%s\" Channel %c : External Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Transmit Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Status Affects Vector %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Function %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait"));
LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready on %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit"));
m_wr1 = data;
LOG(("Z80SIO \"%s\" Channel %c : External Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_EXT_INT_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Transmit Interrupt Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_TX_INT_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Status Affects Vector %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_STATUS_VECTOR) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready Function %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_FUNCTION) ? "Ready" : "Wait"));
LOG(("Z80SIO \"%s\" Channel %c : Wait/Ready on %s\n", m_owner->tag(), 'A' + m_index, (data & WR1_WRDY_ON_RX_TX) ? "Receive" : "Transmit"));
switch (data & WR1_RX_INT_MODE_MASK)
{
case WR1_RX_INT_DISABLE:
LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt Disabled\n", m_owner->tag(), 'A' + m_index));
break;
switch (data & WR1_RX_INT_MODE_MASK)
{
case WR1_RX_INT_DISABLE:
LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt Disabled\n", m_owner->tag(), 'A' + m_index));
break;
case WR1_RX_INT_FIRST:
LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on First Character\n", m_owner->tag(), 'A' + m_index));
break;
case WR1_RX_INT_FIRST:
LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on First Character\n", m_owner->tag(), 'A' + m_index));
break;
case WR1_RX_INT_ALL_PARITY:
LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", m_owner->tag(), 'A' + m_index));
break;
case WR1_RX_INT_ALL_PARITY:
LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters, Parity Affects Vector\n", m_owner->tag(), 'A' + m_index));
break;
case WR1_RX_INT_ALL:
LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters\n", m_owner->tag(), 'A' + m_index));
break;
}
case WR1_RX_INT_ALL:
LOG(("Z80SIO \"%s\" Channel %c : Receiver Interrupt on All Characters\n", m_owner->tag(), 'A' + m_index));
break;
}
}
void z80sio_channel::do_sioreg_wr2(UINT8 data)
{
m_wr2 = data;
if (m_index == z80sio_device::CHANNEL_B)
{
if (m_wr1 & z80sio_channel::WR1_STATUS_VECTOR)
m_rr2 = ( m_rr2 & 0x0e ) | ( m_wr2 & 0xF1);
else
m_rr2 = m_wr2;
}
m_uart->check_interrupts();
LOG(("Z80SIO \"%s\" Channel %c : Interrupt Vector %02x\n", m_owner->tag(), 'A' + m_index, data));
m_wr2 = data;
if (m_index == z80sio_device::CHANNEL_B)
{
if (m_wr1 & z80sio_channel::WR1_STATUS_VECTOR)
m_rr2 = ( m_rr2 & 0x0e ) | ( m_wr2 & 0xF1);
else
m_rr2 = m_wr2;
}
m_uart->check_interrupts();
LOG(("Z80SIO \"%s\" Channel %c : Interrupt Vector %02x\n", m_owner->tag(), 'A' + m_index, data));
}
void z80sio_channel::do_sioreg_wr3(UINT8 data)
{
m_wr3 = data;
LOG(("Z80SIO \"%s\" Channel %c : Receiver Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Auto Enables %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Receiver Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_rx_word_length()));
m_wr3 = data;
LOG(("Z80SIO \"%s\" Channel %c : Receiver Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_RX_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Auto Enables %u\n", m_owner->tag(), 'A' + m_index, (data & WR3_AUTO_ENABLES) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Receiver Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_rx_word_length()));
}
void z80sio_channel::do_sioreg_wr4(UINT8 data)
{
m_wr4 = data;
LOG(("Z80SIO \"%s\" Channel %c : Parity Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Parity %s\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd"));
LOG(("Z80SIO \"%s\" Channel %c : Stop Bits %s\n", m_owner->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits())));
LOG(("Z80SIO \"%s\" Channel %c : Clock Mode %uX\n", m_owner->tag(), 'A' + m_index, get_clock_mode()));
m_wr4 = data;
LOG(("Z80SIO \"%s\" Channel %c : Parity Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Parity %s\n", m_owner->tag(), 'A' + m_index, (data & WR4_PARITY_EVEN) ? "Even" : "Odd"));
LOG(("Z80SIO \"%s\" Channel %c : Stop Bits %s\n", m_owner->tag(), 'A' + m_index, stop_bits_tostring(get_stop_bits())));
LOG(("Z80SIO \"%s\" Channel %c : Clock Mode %uX\n", m_owner->tag(), 'A' + m_index, get_clock_mode()));
}
void z80sio_channel::do_sioreg_wr5(UINT8 data)
{
m_wr5 = data;
LOG(("Z80SIO \"%s\" Channel %c : Transmitter Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Transmitter Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_tx_word_length()));
LOG(("Z80SIO \"%s\" Channel %c : Send Break %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Request to Send %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Data Terminal Ready %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0));
m_wr5 = data;
LOG(("Z80SIO \"%s\" Channel %c : Transmitter Enable %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_TX_ENABLE) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Transmitter Bits/Character %u\n", m_owner->tag(), 'A' + m_index, get_tx_word_length()));
LOG(("Z80SIO \"%s\" Channel %c : Send Break %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_SEND_BREAK) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Request to Send %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_RTS) ? 1 : 0));
LOG(("Z80SIO \"%s\" Channel %c : Data Terminal Ready %u\n", m_owner->tag(), 'A' + m_index, (data & WR5_DTR) ? 1 : 0));
}
void z80sio_channel::do_sioreg_wr6(UINT8 data)
{
LOG(("Z80SIO \"%s\" Channel %c : Transmit Sync %02x\n", m_owner->tag(), 'A' + m_index, data));
m_sync = (m_sync & 0xff00) | data;
LOG(("Z80SIO \"%s\" Channel %c : Transmit Sync %02x\n", m_owner->tag(), 'A' + m_index, data));
m_sync = (m_sync & 0xff00) | data;
}
void z80sio_channel::do_sioreg_wr7(UINT8 data)
{
LOG(("Z80SIO \"%s\" Channel %c : Receive Sync %02x\n", m_owner->tag(), 'A' + m_index, data));
m_sync = (data << 8) | (m_sync & 0xff);
LOG(("Z80SIO \"%s\" Channel %c : Receive Sync %02x\n", m_owner->tag(), 'A' + m_index, data));
m_sync = (data << 8) | (m_sync & 0xff);
}
//-------------------------------------------------
@ -1036,7 +1036,7 @@ void z80sio_channel::do_sioreg_wr7(UINT8 data)
void z80sio_channel::control_write(UINT8 data)
{
UINT8 reg = m_wr0 & WR0_REGISTER_MASK;
UINT8 reg = m_wr0 & WR0_REGISTER_MASK;
if (reg != 0)
{
@ -1057,7 +1057,7 @@ void z80sio_channel::control_write(UINT8 data)
case REG_WR6_SYNC_OR_SDLC_A: do_sioreg_wr6(data); break;
case REG_WR7_SYNC_OR_SDLC_F: do_sioreg_wr7(data); break;
default:
logerror("Z80SIO \"%s\" Channel %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
logerror("Z80SIO \"%s\" Channel %c : Unsupported WRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
}
}
@ -1142,9 +1142,9 @@ void z80sio_channel::receive_data(UINT8 data)
{
case WR1_RX_INT_FIRST:
if (!m_rx_first)
{
m_uart->trigger_interrupt(m_index, INT_SPECIAL);
}
{
m_uart->trigger_interrupt(m_index, INT_SPECIAL);
}
break;
case WR1_RX_INT_ALL_PARITY:
@ -1347,7 +1347,7 @@ void z80sio_channel::update_serial()
stop_bits_t stop_bits = get_stop_bits();
parity_t parity;
LOG(("Z80SIO update_serial\n"));
LOG(("Z80SIO update_serial\n"));
if (m_wr4 & WR4_PARITY_ENABLE)
{

152
src/devices/machine/z80sio.h
View File

@ -10,44 +10,44 @@
D3 2| |39 D2 : |39 D2 : |39 D2
D5 3| |38 D4 : |38 D4 : |38 D4
D7 4| |37 D6 : |37 D6 : |37 D6
_INT 5| |36 _IORQ : |36 _IORQ : |36 _IORQ
IEO 6| |35 _CE : |35 _CE : |35 _CE
_INT 5| |36 _IORQ : |36 _IORQ : |36 _IORQ
IEO 6| |35 _CE : |35 _CE : |35 _CE
IEI 7| |34 B/_A : |34 B/_A : |34 B/_A
_M1 8| |33 C/_D : |33 C/_D : |33 C/_D
VDD 9| DIP40 |32 _RD : DIP40 |32 _RD : DIP40 |32 _RD
_W//RDYA 10| Z80 |31 GND : Z80 |31 GND : Z80 |31 GND
VDD 9| DIP40 |32 _RD : DIP40 |32 _RD : DIP40 |32 _RD
_W//RDYA 10| Z80 |31 GND : Z80 |31 GND : Z80 |31 GND
_SYNCA 11| SIO/0 |30 _W/_RDYB: SIO/1 |30 _W/_RDYB: SIO/2 |30 _W/_RDYB
RxDA 12| |29 _SYNCB : |29 _SYNCB : |29 _SYNCB
_RxCA 13| |28 RxDB : |28 RxDB : |28 _RxCB
_TxCA 14| |27 _RxTxCB : |27 _RxCB : |27 _TxCB
_RxCA 13| |28 RxDB : |28 RxDB : |28 _RxCB
_TxCA 14| |27 _RxTxCB : |27 _RxCB : |27 _TxCB
TxDA 15| |26 TxDB : |26 _TxCB : |26 TxDB
_DTRA 16| |25 _DTRB : |25 TxD_B : |25 _DTRB
_RTSA 17| |24 _RTSB : |24 _RTSB : |24 _RTSB
_CTSA 18| |23 _CTSB : |23 _CTSB : |23 _CTSB
_DCDA 19| |22 _DCDB : |22 _DCDB : |22 _DCDB
_DTRA 16| |25 _DTRB : |25 TxD_B : |25 _DTRB
_RTSA 17| |24 _RTSB : |24 _RTSB : |24 _RTSB
_CTSA 18| |23 _CTSB : |23 _CTSB : |23 _CTSB
_DCDA 19| |22 _DCDB : |22 _DCDB : |22 _DCDB
CLK 20|_____________|21 _RESET :_______|21 _RESET :_______|21 _RESET
*I *I
*I N O *I O
N D D D D / D D D D R N D D D D D D D D R*C
T 7 5 3 1 C 0 2 4 6 Q T 7 5 3 1 0 2 4 6 Q E
+----------------------+ +----------------------+
*I N O *I O
N D D D D / D D D D R N D D D D D D D D R*C
T 7 5 3 1 C 0 2 4 6 Q T 7 5 3 1 0 2 4 6 Q E
+----------------------+ +----------------------+
IEI|34 22| *CE IEI|6 5 4 3 2 1 44 42 40|B/ *A
IEO|35 21| B/ *A IEO|8 43 41 |C/ *D
IEO|35 21| B/ *A IEO|8 43 41 |C/ *D
*M1| | C/ *D *M1|9 37|*RD
+5v| | *RD +5V|10 36|GND
+5v| | *RD +5V|10 36|GND
*W/ *RDYA| QFP44 | GND *W/ *RDYA|11 PLCC44 35|*W/ *RDYB
N/C| Z80 SIO/3 | N/C *SYNCA|12 Z80 SIO/4 34|*SYNCB
*SYNCA| Z804C43 | *W/ *RDYB RxDA|13 33|RxDB
N/C| Z80 SIO/3 | N/C *SYNCA|12 Z80 SIO/4 34|*SYNCB
*SYNCA| Z804C43 | *W/ *RDYB RxDA|13 33|RxDB
RxDA| | *SYNCB *RxCA|14 32|*RxCB
*RxCA|42 | RxDB *TxCA|15 31|*TxCB
*TxCA|43 1 1 | *RxCB TxDA| 19 21 23 25 30|TxDB
TxDA`. 2 3 4 5 6 7 8 9 0 1 | *TxCB N/C|18 20 22 24 26 29|N/C
`--------------------+ +----------------------+
*D*R*C*D C*R*D*C*R*D*T *D*R*C*D C*R*D*C*R*D N
T T T C L E C*T T T x T T T C L E C T T T /
TxDA`. 2 3 4 5 6 7 8 9 0 1 | *TxCB N/C|18 20 22 24 26 29|N/C
`--------------------+ +----------------------+
*D*R*C*D C*R*D*C*R*D*T *D*R*C*D C*R*D*C*R*D N
T T T C L E C*T T T x T T T C L E C T T T /
R S S D K S D S S R D R S S D K S D S S R C
A A A A E B B B B B A A A A E B B B B
A A A A E B B B B B A A A A E B B B B
T T
***************************************************************************/
@ -124,7 +124,7 @@
class z80sio_device;
class z80sio_channel : public device_t,
public device_serial_interface
public device_serial_interface
{
friend class z80sio_device;
@ -142,21 +142,21 @@ public:
virtual void rcv_callback();
virtual void rcv_complete();
// read register handlers
UINT8 do_sioreg_rr0();
UINT8 do_sioreg_rr1();
UINT8 do_sioreg_rr2();
// read register handlers
UINT8 do_sioreg_rr0();
UINT8 do_sioreg_rr1();
UINT8 do_sioreg_rr2();
// write register handlers
void do_sioreg_wr0(UINT8 data);
void do_sioreg_wr0_resets(UINT8 data);
void do_sioreg_wr1(UINT8 data);
void do_sioreg_wr2(UINT8 data);
void do_sioreg_wr3(UINT8 data);
void do_sioreg_wr4(UINT8 data);
void do_sioreg_wr5(UINT8 data);
void do_sioreg_wr6(UINT8 data);
void do_sioreg_wr7(UINT8 data);
// write register handlers
void do_sioreg_wr0(UINT8 data);
void do_sioreg_wr0_resets(UINT8 data);
void do_sioreg_wr1(UINT8 data);
void do_sioreg_wr2(UINT8 data);
void do_sioreg_wr3(UINT8 data);
void do_sioreg_wr4(UINT8 data);
void do_sioreg_wr5(UINT8 data);
void do_sioreg_wr6(UINT8 data);
void do_sioreg_wr7(UINT8 data);
UINT8 control_read();
void control_write(UINT8 data);
@ -178,19 +178,19 @@ public:
int m_txc;
// Register state
// read registers enum
UINT8 m_rr0; // REG_RR0_STATUS
// read registers enum
UINT8 m_rr0; // REG_RR0_STATUS
UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND
UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT
// write registers enum
// write registers enum
UINT8 m_wr0; // REG_WR0_COMMAND_REGPT
UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
UINT8 m_wr2; // REG_WR2_INT_VECTOR
UINT8 m_wr3; // REG_WR3_RX_CONTROL
UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
UINT8 m_wr2; // REG_WR2_INT_VECTOR
UINT8 m_wr3; // REG_WR3_RX_CONTROL
UINT8 m_wr4; // REG_WR4_RX_TX_MODES
UINT8 m_wr5; // REG_WR5_TX_CONTROL
UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A
UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F
UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A
UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F
int m_variant; // Set in device
@ -203,26 +203,26 @@ protected:
INT_SPECIAL
};
// Read registers
enum
{
REG_RR0_STATUS = 0,
REG_RR1_SPEC_RCV_COND = 1,
REG_RR2_INTERRUPT_VECT = 2,
};
// Read registers
enum
{
REG_RR0_STATUS = 0,
REG_RR1_SPEC_RCV_COND = 1,
REG_RR2_INTERRUPT_VECT = 2,
};
// Write registers
enum
{
REG_WR0_COMMAND_REGPT = 0,
REG_WR1_INT_DMA_ENABLE = 1,
REG_WR2_INT_VECTOR = 2,
REG_WR3_RX_CONTROL = 3,
REG_WR4_RX_TX_MODES = 4,
REG_WR5_TX_CONTROL = 5,
REG_WR6_SYNC_OR_SDLC_A = 6,
REG_WR7_SYNC_OR_SDLC_F = 7,
};
// Write registers
enum
{
REG_WR0_COMMAND_REGPT = 0,
REG_WR1_INT_DMA_ENABLE = 1,
REG_WR2_INT_VECTOR = 2,
REG_WR3_RX_CONTROL = 3,
REG_WR4_RX_TX_MODES = 4,
REG_WR5_TX_CONTROL = 5,
REG_WR6_SYNC_OR_SDLC_A = 6,
REG_WR7_SYNC_OR_SDLC_F = 7,
};
enum
{
@ -233,7 +233,7 @@ protected:
RR0_SYNC_HUNT = 0x10,
RR0_CTS = 0x20,
RR0_TX_UNDERRUN = 0x40,
RR0_BREAK_ABORT = 0x80
RR0_BREAK_ABORT = 0x80
};
enum
@ -243,16 +243,16 @@ protected:
RR1_PARITY_ERROR = 0x10,
RR1_RX_OVERRUN_ERROR = 0x20,
RR1_CRC_FRAMING_ERROR = 0x40,
RR1_END_OF_FRAME = 0x80
RR1_END_OF_FRAME = 0x80
};
enum
{ // TODO: overload SIO functionality
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
};
enum
{ // TODO: overload SIO functionality
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
};
enum
{
@ -356,7 +356,7 @@ protected:
};
void update_serial();
void update_rts();
void update_rts();
void set_dtr(int state);
void set_rts(int state);
@ -399,7 +399,7 @@ protected:
// ======================> z80sio_device
class z80sio_device : public device_t,
public device_z80daisy_interface
public device_z80daisy_interface
{
friend class z80sio_channel;

2
src/devices/sound/315-5641.c
View File

@ -67,4 +67,4 @@ void sega_315_5641_pcm_device::device_reset()
m_fifo_write = 0x00;
upd775x_device::device_reset();
}
}

8
src/devices/sound/315-5641.h
View File

@ -16,9 +16,9 @@ public:
DECLARE_WRITE8_MEMBER(port_w);
UINT8 m_fifo_data[0x40];
UINT8 m_fifo_read; // last read offset (will read in m_fifo_read+1)
UINT8 m_fifo_write; // write offset
UINT8 m_fifo_read; // last read offset (will read in m_fifo_read+1)
UINT8 m_fifo_write; // write offset
protected:
// device-level overrides
virtual void device_start();
@ -27,4 +27,4 @@ protected:
};
extern const device_type SEGA_315_5641_PCM;
extern const device_type SEGA_315_5641_PCM;

4
src/devices/sound/c352.c
View File

@ -13,10 +13,10 @@
Supports 8-bit linear and 8-bit muLaw samples
Output: digital, 16 bit, 4 channels
Output sample rate is the input clock / (288 * 2).
superctr: The clock divider appears to be configurable for each system.
Below is a list of the divider values followed by the systems that use it.
* 228: System 11.
* 288: System 22, Super 22, NB-1/2, ND-1, FL.
* 296: System 23, Super 23.

2
src/devices/sound/sn76496.c
View File

@ -109,7 +109,7 @@
27/06/2012: Michael Zapf
Converted to modern device, legacy devices were gradually removed afterwards.
16/09/2015: Lord Nightmare
Fix PSG chips to have volume reg inited on reset to 0x0 based on tests by
ValleyBell. Made Sega PSG chips start up with register 0x3 selected (volume

4
src/devices/sound/tms5110.c
View File

@ -525,9 +525,9 @@ void tms5110_device::process(INT16 *buffer, unsigned int size)
fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]);
fprintf(stderr,"Out:%06d ", this_sample);
//#ifdef PERFECT_INTERPOLATION_HACK
// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar);
// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar);
//#else
// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar);
// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar);
//#endif
fprintf(stderr,"\n");
#endif

2
src/devices/sound/tms5110r.inc
View File

@ -568,7 +568,7 @@ NOTE FROM DECAP: immediately to the left of each of the K1,2,3,4,5,and 6
patent 4,335,277. They are likely related to the multiplicative interpolator
described in us patent 4,419,540; whether the 5200/2501E and the 5220 or 5220C
actually implement this interpolator or not is unclear. This interpolator
seems intended for chips with variable frame rate, so if it exists at all,
seems intended for chips with variable frame rate, so if it exists at all,
it may only exist on the TMS/TSP5220C and CD2501ECD.
*/

4
src/devices/sound/tms5220.c
View File

@ -919,9 +919,9 @@ void tms5220_device::process(INT16 *buffer, unsigned int size)
fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]);
fprintf(stderr,"Out:%06d ", this_sample);
//#ifdef PERFECT_INTERPOLATION_HACK
// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar);
// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar);
//#else
// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar);
// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar);
//#endif
fprintf(stderr,"\n");
#endif

4
src/lib/util/coreutil.c
View File

@ -86,8 +86,8 @@ int gregorian_days_in_month(int month, int year)
assert(month >= 1 && month <= 12);
int days[] = { 31,28,31,30,31,30,31,31,30,31,30,31 };
days[1] += gregorian_is_leap_year(year) ? 1 : 0;
return days[month-1];
days[1] += gregorian_is_leap_year(year) ? 1 : 0;
return days[month-1];
}

33
src/mame/arcade.lst
View File

@ -361,9 +361,9 @@ anteateruk // (c) 1983 Free Enterprise Games
rescue // (c) 1982 Stern
rescueb // (c) Videl Games (Rescue bootleg)
aponow // bootleg
rescuefe // bootleg
rescuefe // bootleg
minefld // (c) 1983 Stern
minefldfe // bootleg
minefldfe // bootleg
losttomb // (c) 1982 Stern
losttombh // (c) 1982 Stern
superbon // bootleg
@ -846,7 +846,7 @@ genpeitd // (c) 1986
rthunder // (c) 1986
rthunder2 // (c) 1986
rthunder1 // (c) 1986
rthunder0 // (c) 1986
rthunder0 // (c) 1986
wndrmomo // (c) 1987
// Thunder Ceptor HW
@ -4570,8 +4570,8 @@ enduror // (c) 1985 (FD1089B)
enduror1 // (c) 1985 (FD1089B)
endurob2 // (c) 1985 (Beta bootleg)
endurobl // (c) 1985 (Herb bootleg)
endurord // bootleg
enduror1d // bootleg
endurord // bootleg
enduror1d // bootleg
hangon // (c) 1985 (Rev A)
hangon1 // (c) 1985
hangon2 // (c) 1985
@ -4863,11 +4863,11 @@ toutrun3 // 1987 (FD1094)
toutrun2 // 1987 (FD1094)
toutrun1 // 1987 (FD1094)
toutrunj1 // 1987 (FD1094)
toutrund // bootleg
toutrunjd // bootleg
toutrun3d // bootleg
toutrunj1d // bootleg
shangon3d // bootleg
toutrund // bootleg
toutrunjd // bootleg
toutrun3d // bootleg
toutrunj1d // bootleg
shangon3d // bootleg
// X Board
aburner // 1987.07 After Burner (Japan)
@ -4892,11 +4892,11 @@ rachero // 1990.?? Racing Hero (World, FD1094)
abcop // 1990.?? A.B.Cop (World, FD1094)
abcopj // 1991.01 A.B.Cop (Japan, FD1094)
gpriderjs // 1990.10 GP Rider (Japan, FD1094)
gpriderj // as above
gpriderj // as above
gpriders // 1990.?? GP Rider (World, FD1094)
gprider // as above
gprider // as above
gpriderus // 1990.12 GP Rider (US, FD1094)
gprideru // as above
gprideru // as above
rascot // 1991.?? Royal Ascot (Japan)
// decrypted X-Board bootlegs
@ -6396,7 +6396,7 @@ wc90t // (c) 1989 Tecmo
wc90b1 // bootleg
wc90b2 // bootleg
wc90ba // bootleg
pac90 // bootleg
pac90 // bootleg
spbactn // 9002 - (c) 1991 Tecmo
spbactnj // 9002 - (c) 1991 Tecmo
spbactnp // prototype
@ -6441,7 +6441,7 @@ trackfldc // GX361 (c) 1983 + Centuri license
trackfldnz // (c) 1982 Goldberg Enterprizes Inc.
hyprolym // GX361 (c) 1983
hyprolymb // bootleg
hyprolymba // bootleg
hyprolymba // bootleg
atlantol // bootleg
wizzquiz // (c) 1985 Konami
wizzquiza // (c) 1985 Zilec-Zenitone
@ -10033,7 +10033,7 @@ amazonia // (c) 1999
fruitpar // (c) 200?
zhongguo // (c) 2000
sdwx // (c) 2002
amazoni2 // (c) 2002
amazoni2 // (c) 2002
sddz // (c) 200?
lhzb3 // (c) 200?
lhzb4 // (c) 200?
@ -32323,4 +32323,3 @@ dumpump
3lilpigs
wackygtr // Wacky Gator

6
src/mame/drivers/cntsteer.c
View File

@ -68,7 +68,7 @@ public:
/* misc */
int m_nmimask; // zerotrgt only
bool m_sub_nmimask; // counter steer only
bool m_sub_nmimask; // counter steer only
/* devices */
required_device<cpu_device> m_maincpu;
@ -619,8 +619,8 @@ WRITE8_MEMBER(cntsteer_state::nmimask_w)
INTERRUPT_GEN_MEMBER(cntsteer_state::subcpu_vblank_irq)
{
// TODO: hack for bus request: DP is enabled with 0xff only during POST, and disabled once that critical operations are performed.
// That's my best guess so far about how Slave is supposed to stop execution on Master CPU, the lack of any realistic write
// TODO: hack for bus request: DP is enabled with 0xff only during POST, and disabled once that critical operations are performed.
// That's my best guess so far about how Slave is supposed to stop execution on Master CPU, the lack of any realistic write
// between these operations brings us to this.
// Game currently returns error on MIX CPU RAM because halt-ing BACK CPU doesn't happen when it should of course ...
UINT8 dp_r = (UINT8)device.state().state_int(M6809_DP);

2
src/mame/drivers/coolridr.c
View File

@ -8,7 +8,7 @@
special thanks to Guru for references and HW advices
Games on this system include Cool Riders and Aqua Stage.
This system is interesting in that it makes use of an RLE compression scheme, which
is not something common for Sega hardware, there is a patent for it ( 6,141,122 )
http://www.google.com/patents/US6141122

2
src/mame/drivers/deco32.c
View File

@ -225,7 +225,7 @@ Notes:
Night Slashers
Data East, 1993
DE-0395-1 DEC-22VO
|-----------------------------------------------------|
| TA8205AH 6164 |-----| 2M-16M* MBH-07|

2
src/mame/drivers/galastrm.c
View File

@ -252,7 +252,7 @@ static const gfx_layout tile16x16_layout =
{ 0, 8, 16, 24 },
{ 32, 33, 34, 35, 36, 37, 38, 39, 0, 1, 2, 3, 4, 5, 6, 7 },
{ 0*64, 1*64, 2*64, 3*64, 4*64, 5*64, 6*64, 7*64,
8*64, 9*64, 10*64, 11*64, 12*64, 13*64, 14*64, 15*64 },
8*64, 9*64, 10*64, 11*64, 12*64, 13*64, 14*64, 15*64 },
64*16 /* every sprite takes 128 consecutive bytes */
};

6
src/mame/drivers/gunsmoke.c
View File

@ -421,9 +421,9 @@ ROM_START( gunsmokeb )
ROM_REGION( 0x8000, "gfx4", 0 ) /* background tilemaps */
ROM_LOAD( "14.ic25", 0x00000, 0x8000, CRC(0af4f7eb) SHA1(24a98fdeedeeaf1035b4af52d5a8dd5e47a5e62d) )
/* The names of the proms starting with "g-" do not yet reflect their position in the pcb layout of this bootleg.
As the ICs are not socketed, but directly soldered to the pcb, it is harder to identify which is which.
But it would be good to figure this out at some point, for the sake of documenting this specific board layout. */
/* The names of the proms starting with "g-" do not yet reflect their position in the pcb layout of this bootleg.
As the ICs are not socketed, but directly soldered to the pcb, it is harder to identify which is which.
But it would be good to figure this out at some point, for the sake of documenting this specific board layout. */
ROM_REGION( 0x0a00, "proms", 0 )
ROM_LOAD( "prom.ic3", 0x0000, 0x0100, CRC(02f55589) SHA1(8a3f98304aedf3aba1c08b615bf457752a480edc) ) /* red component */
ROM_LOAD( "prom.ic4", 0x0100, 0x0100, CRC(e1e36dd9) SHA1(5bd88a35898a2d973045bdde8311aac3a12826de) ) /* green component */

2
src/mame/drivers/igs017.c
View File

@ -221,7 +221,7 @@ UINT16 igs017_state::mgcs_palette_bitswap(UINT16 bgr)
UINT16 igs017_state::lhzb2a_palette_bitswap(UINT16 bgr)
{
// bgr = ((bgr & 0xff00) >> 8) | ((bgr & 0x00ff) << 8);
// bgr = ((bgr & 0xff00) >> 8) | ((bgr & 0x00ff) << 8);
return BITSWAP16(bgr, 15,9,13,12,11,5,4,8,7,6,0,14,3,2,1,10);
}

6
src/mame/drivers/igs_fear.c
View File

@ -49,7 +49,7 @@ ADDRESS_MAP_END
// debugging only, not tile based
static const gfx_layout fearlayout =
{
16,16,
16,16,
RGN_FRAC(1,1),
7, /* 7 bits per pixel - bit 0 unused in the roms we have*/
{ 1,2,3,4,5,6,7 },
@ -77,7 +77,7 @@ static MACHINE_CONFIG_START( igs_fear, igs_fear_state )
MCFG_CPU_ADD("maincpu",ARM7, 50000000/2)
MCFG_CPU_PROGRAM_MAP(igs_igs_fear_map)
// MCFG_CPU_VBLANK_INT_DRIVER("screen", igs_fear_state, igs_majhong_interrupt)
// MCFG_CPU_VBLANK_INT_DRIVER("screen", igs_fear_state, igs_majhong_interrupt)
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -114,7 +114,7 @@ ROM_START( fearless )
ROM_LOAD( "fearlessp_07.u33", 0x000000, 0x10000, CRC(7dae4900) SHA1(bbf7ba7c9e95ff2ffeb1dc0fc7ccedd4da274d01) ) // MX10EXAQC (80C51 XA based MCU) marked 07, not read protected?
// these all report FIXED BITS (0xxxxxxx), hopefully just 7-bit colour data, non-tile based sprites
ROM_REGION( 0x1000000, "gfx3", 0 )
ROM_REGION( 0x1000000, "gfx3", 0 )
ROM_LOAD16_BYTE( "fearlessp_u6_cg-0h.u6", 0x000001, 0x800000, CRC(02d8bbbf) SHA1(7cf36c909a5d76096a725ffe0a697bcbafbcf985) )
ROM_LOAD16_BYTE( "fearlessp_u7_cg-0l.u7", 0x000000, 0x800000, CRC(ca254db4) SHA1(f5670c2ff0720c84c9aff3cea95b118b6044e469) )
ROM_REGION( 0x1000000, "gfx2", 0 )

8
src/mame/drivers/igs_m027.c
View File

@ -36,7 +36,7 @@ public:
m_igs_mainram(*this, "igs_mainram"),
m_maincpu(*this, "maincpu"),
m_igs017_igs031(*this, "igs017_igs031")
{ }
{ }
optional_shared_ptr<UINT32> m_igs_mainram;
required_device<cpu_device> m_maincpu;
@ -350,7 +350,7 @@ static MACHINE_CONFIG_START( igs_majhong, igs_m027_state )
MCFG_SCREEN_PALETTE("palette")
MCFG_PALETTE_ADD("palette", 0x200)
// MCFG_PALETTE_FORMAT(xGGGGGRRRRRBBBBB)
// MCFG_PALETTE_FORMAT(xGGGGGRRRRRBBBBB)
MCFG_DEVICE_ADD("igs017_igs031", IGS017_IGS031, 0)
MCFG_GFX_PALETTE("palette")
@ -385,8 +385,8 @@ static MACHINE_CONFIG_START( amazonia, igs_m027_state )
MCFG_SCREEN_PALETTE("palette")
MCFG_PALETTE_ADD("palette", 0x200)
// MCFG_PALETTE_FORMAT(xGGGGGRRRRRBBBBB)
// MCFG_PALETTE_FORMAT(xGGGGGRRRRRBBBBB)
MCFG_DEVICE_ADD("igs017_igs031", IGS017_IGS031, 0)
MCFG_GFX_PALETTE("palette")
MCFG_REVERSE_TEXT_BITS

26
src/mame/drivers/igspoker.c
View File

@ -2465,24 +2465,24 @@ DRIVER_INIT_MEMBER(igspoker_state,pktet346)
Cherry master looking board
Big chip with no markings at U80 stickered KUNG FU
Big chip with no markings at U80 stickered KUNG FU
V1.0
1992
Board silkscreend on top PCB NO.0013-B
.45 27010 stickered 6
.44 27010 stickered 5
.43 27010 stickered 4
.42 27128 stickered 3
.41 27128 stickered 2
.40 27128 stickered 1
.98 27256 stickered 7 couldn't read chip, but board was silkscreened 27c256
.97 27512 stickered ? looked like japanese writing
.38 74s287
.46 18cv8 <--- same checksum as .48
.47 pal16l8a <--- checksum was 0
.48 18cv8 <--- same checksum as .46
.45 27010 stickered 6
.44 27010 stickered 5
.43 27010 stickered 4
.42 27128 stickered 3
.41 27128 stickered 2
.40 27128 stickered 1
.98 27256 stickered 7 couldn't read chip, but board was silkscreened 27c256
.97 27512 stickered ? looked like japanese writing
.38 74s287
.46 18cv8 <--- same checksum as .48
.47 pal16l8a <--- checksum was 0
.48 18cv8 <--- same checksum as .46
unknown 24 pin chip @ u29
open 24 pin socket @ u54

82
src/mame/drivers/konendev.c
View File

@ -101,16 +101,16 @@ READ32_MEMBER(konendev_state::mcu2_r)
{
r &= ~0x4000; // MCU2 presence
r &= ~0x2000; // IFU2 presence
r &= ~0x1000; // FMU2 presence
r &= ~0x1000; // FMU2 presence
}
if (ACCESSING_BITS_0_7)
{
r |= ioport("DSW")->read() & 0xff;
//r |= 0x80; // 0 = ram clear?
//r |= 0x40; // logic door
r |= 0x04; // battery 1 status
r |= 0x10; // battery 2 status
//r |= 0x80; // 0 = ram clear?
//r |= 0x40; // logic door
r |= 0x04; // battery 1 status
r |= 0x10; // battery 2 status
}
return r;
@ -133,19 +133,19 @@ UINT8 konendev_state::rtc_dev_r(UINT32 reg)
{
switch (reg)
{
case 0x0: return 9;
case 0x1: return 5;
case 0x2: return 3;
case 0x3: return 2;
case 0x4: return 1;
case 0x5: return 0;
case 0x6: return 7;
case 0x7: return 2;
case 0x8: return 2;
case 0x9: return 1;
case 0xa: return 5;
case 0xb: return 1;
case 0xc: return 3;
case 0x0: return 9;
case 0x1: return 5;
case 0x2: return 3;
case 0x3: return 2;
case 0x4: return 1;
case 0x5: return 0;
case 0x6: return 7;
case 0x7: return 2;
case 0x8: return 2;
case 0x9: return 1;
case 0xa: return 5;
case 0xb: return 1;
case 0xc: return 3;
}
return 0;
@ -154,7 +154,7 @@ UINT8 konendev_state::rtc_dev_r(UINT32 reg)
READ32_MEMBER(konendev_state::rtc_r)
{
UINT32 r = 0;
if (ACCESSING_BITS_24_31)
r |= (UINT32)(rtc_dev_r(offset * 4)) << 24;
if (ACCESSING_BITS_16_23)
@ -229,34 +229,34 @@ ADDRESS_MAP_END
static INPUT_PORTS_START( konendev )
PORT_START("IN0")
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE ) // "Take Win" button
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_GAMBLE_BET ) // "Gamble" button
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON1 ) // "25 Lines" button
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON2 ) // "20 Lines" button
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON3 ) // "15 Lines" button
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON4 ) // "10 Lines" button
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON5 ) // "5 Lines" button
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON6 ) // "1 Line" button
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON7 ) // "Reserve" button
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON8 ) // "Collect" button
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON9 ) // "Bet 20" button
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON10 ) // "Bet 10" button
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON11 ) // "Bet 5" button
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON12 ) // "Bet 3" button
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON13 ) // "Bet 2" button
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON14 ) // "Bet 1" button
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE ) // "Take Win" button
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_GAMBLE_BET ) // "Gamble" button
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON1 ) // "25 Lines" button
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON2 ) // "20 Lines" button
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON3 ) // "15 Lines" button
PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON4 ) // "10 Lines" button
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON5 ) // "5 Lines" button
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON6 ) // "1 Line" button
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON7 ) // "Reserve" button
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON8 ) // "Collect" button
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON9 ) // "Bet 20" button
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON10 ) // "Bet 10" button
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON11 ) // "Bet 5" button
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON12 ) // "Bet 3" button
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON13 ) // "Bet 2" button
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON14 ) // "Bet 1" button
PORT_START("IN1")
PORT_BIT( 0xc000, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_SERVICE( 0x2000, IP_ACTIVE_LOW ) // Audit key
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON16 ) // Reset key
PORT_SERVICE( 0x2000, IP_ACTIVE_LOW ) // Audit key
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON16 ) // Reset key
PORT_DIPNAME( 0x0800, 0x0800, "Main door switch" )
PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPNAME( 0x0400, 0x0400, "Cashbox door" )
PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_BIT( 0x0300, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x0300, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_DIPNAME( 0x0040, 0x0040, "BNA Door" )
PORT_DIPSETTING( 0x0040, DEF_STR( Off ) )
@ -482,15 +482,15 @@ DRIVER_INIT_MEMBER(konendev_state,konendev)
DRIVER_INIT_MEMBER(konendev_state,enchlamp)
{
UINT32 *rom = (UINT32*)memregion("program")->base();
rom[0x24/4] = 0x00002743; // patch flash checksum for now
rom[0x24/4] = 0x00002743; // patch flash checksum for now
// patch sound data checksums
rom[0x2d924/4] = 0x00000000;
rom[0x2d928/4] = 0x00000000;
rom[0x2d934/4] = 0x00000000;
rom[0x2d938/4] = 0x00000000;
rom[0] = 0x5782b930; // new checksum for program rom
rom[0] = 0x5782b930; // new checksum for program rom
}
// has a flash dump?

2
src/mame/drivers/midxunit.c
View File

@ -400,7 +400,7 @@ ROM_START( revxp5 )
ROM_LOAD32_BYTE( "revx.64", 0x0c00001, 0x80000, CRC(c33f5309) SHA1(6bb333f563ea66c4c862ffd5fb91fb5e1b919fe8) )
ROM_LOAD32_BYTE( "revx.65", 0x0c00002, 0x80000, CRC(6eee3e71) SHA1(0ef22732e0e2bb5207559decd43f90d1e338ad7b) )
ROM_LOAD32_BYTE( "revx.66", 0x0c00003, 0x80000, CRC(b43d6fff) SHA1(87584e7aeea9d52a43023d40c359591ff6342e84) )
ROM_LOAD32_BYTE( "revx_p5.51", 0xe00000, 0x80000, CRC(f3877eee) SHA1(7a4fdce36edddd35308c107c992ce626a2c9eb8c) )
ROM_LOAD32_BYTE( "revx_p5.52", 0xe00001, 0x80000, CRC(199a54d8) SHA1(45319437e11176d4926c00c95c372098203a32a3) )
ROM_LOAD32_BYTE( "revx_p5.53", 0xe00002, 0x80000, CRC(fcfcf72a) SHA1(b471afb416e3d348b046b0b40f497d27b0afa470) )

62
src/mame/drivers/namcops2.c
View File

@ -125,18 +125,18 @@ This is a general guideline flag showing compatibility between the different rev
1-7: Tested Working
X : Tested Not Working
- : Not Tested
% : 1 and 2; For testing purposes these games need a DVD drive. Using this hardware to play the actual game is
% : 1 and 2; For testing purposes these games need a DVD drive. Using this hardware to play the actual game is
normally impossible due to requiring controls/IO boards that can't be connected to this hardware version.
# : 5 and 6; Working only in S246+ mode.
@ : Multiple different DVD's and/or dongles are available and are compatible in any combination.
For 'Tested Working', working is defined as "boots to the attract mode".
Some games need specific controls and are unplayable even though the game loads (eg. most games on earliest rev 246
or the driving or gun games on non-factory-provided hardware). Some games will start to boot but either get stuck
Some games need specific controls and are unplayable even though the game loads (eg. most games on earliest rev 246
or the driving or gun games on non-factory-provided hardware). Some games will start to boot but either get stuck
somewhere in the boot process or nothing loads after the initial booting.
The DVD drive used for these tests was a Toshiba/Samsung SD-M1802. In the case where the original drive didn't work
The DVD drive used for these tests was a Toshiba/Samsung SD-M1802. In the case where the original drive didn't work
(i.e. factory drive was a CDROM and the disc was a DVD), this drive was substituted.
Finally, all games were tested with the SD-M1802 and worked, therefore no game requires a specific make and model of
Finally, all games were tested with the SD-M1802 and worked, therefore no game requires a specific make and model of
optical drive to BOOT. But of course not all drive models will work or work for extended periods. YMMV.
These makes and models have been tested and worked.....
H-L Data Storage LG GSA-4164B Super Multi DVD Drive (September 2005)
@ -150,21 +150,21 @@ Toshiba/Samsung SD-M1612 DVD-ROM Drive (January 2003) (Factory Supplied)
Toshiba/Samsung SD-M1712 DVD-ROM Drive (November 2003) (Factory Supplied)
Toshiba/Samsung SD-M1802 (Factory Supplied)
Different security cart revisions of the same game are filled in with the same status even if they are not dumped as
Different security cart revisions of the same game are filled in with the same status even if they are not dumped as
long as at least one revision is tested.
1 = 246 1st generation using COH-H30000 or COH-H31000 Playstation 2 main board (GH-004/GH-006 with PS2 power supply)
1 = 246 1st generation using COH-H30000 or COH-H31000 Playstation 2 main board (GH-004/GH-006 with PS2 power supply)
and custom Namco interface board 'System 246 MOTHER PCB' and Teac CD-540E CD drive
2 = 246A 2nd generation using COH-H30000 or COH-H31000 Playstation 2 main board (GH-004/GH-006 with PS2 power supply)
2 = 246A 2nd generation using COH-H30000 or COH-H31000 Playstation 2 main board (GH-004/GH-006 with PS2 power supply)
and custom Namco interface board 'System 246 MOTHER(A) PCB' and Teac CD-540E CD drive
3 = 246B 3rd generation using COH-H31000 Playstation 2 main board (GH-006 without PS2 power supply) and custom Namco
3 = 246B 3rd generation using COH-H31000 Playstation 2 main board (GH-006 without PS2 power supply) and custom Namco
interface board 'System 246 PMOTHER PCB'
4 = 246C 4th generation using integrated single main board 'System 246 Main PCB'
5 = 256 5th generation using integrated single main board 'System 256 Main PCB'. Note some games requiring S246 will
5 = 256 5th generation using integrated single main board 'System 256 Main PCB'. Note some games requiring S246 will
work in S246+ mode.
6 = 256B 6th generation using integrated single main board 'System 256 Main(B) PCB'. Note some games requiring S246
6 = 256B 6th generation using integrated single main board 'System 256 Main(B) PCB'. Note some games requiring S246
will work in S246+ mode.
7 = S256 7th generation using integrated single main board 'Super System 256 Main PCB'. All other games are X because
7 = S256 7th generation using integrated single main board 'Super System 256 Main PCB'. All other games are X because
this system only runs Time Crisis 4.
@ -381,7 +381,7 @@ System246 PAC PCB
|J1 J2 SW1 |
|-----------------------------------------------------|
Notes:
J1/J2 - RCA jacks for stereo audio output (mono audio is also output from the JAMMA connector on the I/O board
J1/J2 - RCA jacks for stereo audio output (mono audio is also output from the JAMMA connector on the I/O board
for Bloody Roar 3)
J3 - Multi-pin connector (located on other side of PCB, plugs into J3 on MOTHER(A) PCB)
J4 - 4-pin connector (not used)
@ -419,7 +419,7 @@ Notes:
TSSIOPROG - Atmel AT29C020 EEPROM stamped 'TSSIOP8' (PLCC32)
C78 - Namco Custom C78, actually a rebadged Hitachi HD643334 MCU, clock input 14.746MHz (PLCC84)
TSSIOPLD - Altera MAX EPM7128ELC84 CPLD with label 'TSSIOPLD' (PLCC84)
SLA4060 - Sanken Electric SLA4060 NPN general purpose darlington transistor (used to drive the kick-back
SLA4060 - Sanken Electric SLA4060 NPN general purpose darlington transistor (used to drive the kick-back
solenoid in the gun)
PST592 - System Reset IC (SOIC4)
J1 - 12 pin connector for power and I/O communication joined to main board
@ -429,7 +429,7 @@ Notes:
J601 - not used?
JP1 - jumper set to 1-2 (lower position), labelled 'WR'
DSW - 4 position dipswitch block, all off
This board is used with Time Crisis 3 (System 246B/C twin CRT-screen version)
It's also used with Time Crisis II (on System 23)
Note this board requires a standard light gun.
@ -514,10 +514,10 @@ Notes:
MCU - Fujitsu MB90F574 Microcontroller with sticker 'FCAF11' (QFP120)
ADM485 - Analog Devices ADM485 +5V Low Power EIA RS-485 Transceiver (SOIC8)
This PCB is used with Ridge Racer V and Wangan Midnight and will also work with most of the
This PCB is used with Ridge Racer V and Wangan Midnight and will also work with most of the
System 246 games when wired to suit those games.
FCA2 PCB
FCA2 PCB
--------
[to-do]
@ -556,17 +556,17 @@ Connector J3 pinout Connector J2 pinout
2 - P2 Button 6 2 - Left - / Also wired to JAMMA audio output pins
3 - P2 Button 5 3 - Right +
4 - P2 Button 4 4 - Right -
5 -
6 - P1 Button 6
5 -
6 - P1 Button 6
7 - P1 Button 5
8 - P1 Button 4
9 -
9 -
10- GND
This I/O board works with all the games that require regular joysticks and buttons which run on System 246B/C and
This I/O board works with all the games that require regular joysticks and buttons which run on System 246B/C and
System 256.
Drive/Feedback Board
--------------------
@ -611,7 +611,7 @@ Notes:
MB3773 - Fujitsu MB3773 Power Supply Monitor with Watch Dog Timer and Reset (SOIC8)
MB3771 - Fujitsu MB3771 System Reset IC (SOIC8)
DIP42 - Unpopulated DIP42 socket for 27C4096 EPROM
MB90242A - Fujitsu MB90242A 16-Bit CISC ROM-less F2MC-16F Family Microcontroller optimized for mechatronics
MB90242A - Fujitsu MB90242A 16-Bit CISC ROM-less F2MC-16F Family Microcontroller optimized for mechatronics
control applications (TQFP80)
7815 - LM7815 15V voltage regulator
J101 - 8 pin connector (purpose unknown)
@ -624,12 +624,12 @@ Notes:
This PCB is used with Ridge Racer V and Wangan Midnight and controls the steering feed-back motor.
When the driving games boot they test the feed-back motor by monitoring a potentiometer
connected to the steering wheel mechanism. On Ridge Racer V, if the pot is faulty or not connected
connected to the steering wheel mechanism. On Ridge Racer V, if the pot is faulty or not connected
or if the drive/feedback board isn't connected (including the 110VAC input voltage), the
steering check will fail after a time-out period and the game will not continue further.
Wangan Midnight doesn't test the potentiometer and will boot without it connected, but it does
test for the presence of the feedback PCB.
Note this same PCB (with a different ROM) is also used with Mario Kart on Triforce hardware and all of the Wangan
Note this same PCB (with a different ROM) is also used with Mario Kart on Triforce hardware and all of the Wangan
Midnight Maximum Tune series up to Maximum Tune 3 DX.
@ -1099,8 +1099,8 @@ ROM_START( tekken51b )
// this key should work with Tekken 5 or 5.1 discs, according to Guru
ROM_REGION(0x840000, "key", ROMREGION_ERASE00)
ROM_LOAD( "te53verb.ic002", 0x000000, 0x800000, CRC(4d605636) SHA1(417b02d6c69f883920cd43a7278d0af183583c55) )
ROM_LOAD( "te53verb_spr.ic002", 0x800000, 0x040000, CRC(b7094978) SHA1(1e4903cd5f594c13dad2fd74666ba35c62550044) )
ROM_LOAD( "te53verb.ic002", 0x000000, 0x800000, CRC(4d605636) SHA1(417b02d6c69f883920cd43a7278d0af183583c55) )
ROM_LOAD( "te53verb_spr.ic002", 0x800000, 0x040000, CRC(b7094978) SHA1(1e4903cd5f594c13dad2fd74666ba35c62550044) )
DISK_REGION("dvd")
DISK_IMAGE_READONLY( "te51-dvd0", 0, SHA1(2a0ac3723725572c1810b0ef4bcfa7aa114062f8) )
@ -1195,8 +1195,8 @@ ROM_START( cobrata )
SYSTEM246_BIOS
ROM_REGION(0x840000, "key", ROMREGION_ERASE00)
ROM_LOAD( "cbr1verb.ic002", 0x000000, 0x800000, CRC(aecda462) SHA1(97c8e98c44d66231ee3f2527756d92dbc947b76d) )
ROM_LOAD( "cbr1verb_spr.ic002", 0x800000, 0x040000, CRC(65aaadcf) SHA1(5cc642f71bef3b5e44db5e999e8abccca7fdaa4c) )
ROM_LOAD( "cbr1verb.ic002", 0x000000, 0x800000, CRC(aecda462) SHA1(97c8e98c44d66231ee3f2527756d92dbc947b76d) )
ROM_LOAD( "cbr1verb_spr.ic002", 0x800000, 0x040000, CRC(65aaadcf) SHA1(5cc642f71bef3b5e44db5e999e8abccca7fdaa4c) )
DISK_REGION("dvd")
DISK_IMAGE_READONLY( "cbr1-ha", 0, SHA1(a20d4ace91a2f2caab0804ebdf62c87ab267239b) )
@ -1244,8 +1244,8 @@ ROM_START( rrvac1 )
SYSTEM246_BIOS
ROM_REGION(0x840000, "key", ROMREGION_ERASE00)
ROM_LOAD( "rrv1vera.ic002", 0x000000, 0x800000, CRC(e28bb0be) SHA1(9683ddc228e9aedd338cf2eb4d4373faeaea5b75) )
ROM_LOAD( "rrv1vera_spr.ic002", 0x800000, 0x040000, CRC(81c370b7) SHA1(7693c03b544c79fa3b6e536abb32ad34cf14dfbf) )
ROM_LOAD( "rrv1vera.ic002", 0x000000, 0x800000, CRC(e28bb0be) SHA1(9683ddc228e9aedd338cf2eb4d4373faeaea5b75) )
ROM_LOAD( "rrv1vera_spr.ic002", 0x800000, 0x040000, CRC(81c370b7) SHA1(7693c03b544c79fa3b6e536abb32ad34cf14dfbf) )
ROM_REGION(0x4010, "jvsio", 0) // Namco "FCA" JVS I/O board PIC16F84 code (see namcos23.c for FCA details)
ROM_LOAD( "fcap11.ic2", 0x000000, 0x004010, CRC(1b2592ce) SHA1(a1a487361053af564f6ec67e545413e370a3b38c) )

50
src/mame/drivers/namcos23.c
View File

@ -1248,7 +1248,7 @@ Notes:
#define H8CLOCK (16737350) /* from 2061 */
#define BUSCLOCK (16737350*2) /* 33MHz CPU bus clock / input */
#define C352CLOCK (25992000) /* measured at 25.992MHz from 2061 pin 9 */
#define C352DIV (296)
#define C352DIV (296)
#define VSYNC1 (59.8824)
#define VSYNC2 (59.915)
#define HSYNC (16666150)
@ -1294,14 +1294,14 @@ class namcos23_state;
class namcos23_renderer : public poly_manager<float, namcos23_render_data, 4, POLY_MAX_ENTRIES>
{
public:
namcos23_renderer(namcos23_state &state);
void render_flush(bitmap_rgb32& bitmap);
void render_scanline(INT32 scanline, const extent_t& extent, const namcos23_render_data& object, int threadid);
namcos23_renderer(namcos23_state &state);
void render_flush(bitmap_rgb32& bitmap);
void render_scanline(INT32 scanline, const extent_t& extent, const namcos23_render_data& object, int threadid);
private:
namcos23_state& m_state;
bitmap_rgb32 m_bitmap;
namcos23_state& m_state;
bitmap_rgb32 m_bitmap;
};
typedef namcos23_renderer::vertex_t poly_vertex;
@ -1361,7 +1361,7 @@ struct c404_t
struct render_t
{
namcos23_renderer *polymgr;
namcos23_renderer *polymgr;
int cur;
int poly_count;
int count[2];
@ -1584,9 +1584,9 @@ UINT16 namcos23_state::nthword(const UINT32 *pSource, int offs)
***************************************************************************/
namcos23_renderer::namcos23_renderer(namcos23_state &state)
: poly_manager<float, namcos23_render_data, 4, POLY_MAX_ENTRIES>(state.machine()),
m_state(state),
m_bitmap(state.m_screen->width(), state.m_screen->height())
: poly_manager<float, namcos23_render_data, 4, POLY_MAX_ENTRIES>(state.machine()),
m_state(state),
m_bitmap(state.m_screen->width(), state.m_screen->height())
{}
// 3D hardware, to throw at least in part in video/namcos23.c
@ -2084,19 +2084,19 @@ void namcos23_renderer::render_flush(bitmap_rgb32& bitmap)
for(int i=0; i<render.poly_count; i++) {
const namcos23_poly_entry *p = render.poly_order[i];
namcos23_render_data& extra = render.polymgr->object_data_alloc();
extra = p->rd;
if (p->vertex_count == 3)
render_triangle(scissor, render_delegate(FUNC(namcos23_renderer::render_scanline), this), 4, p->pv[0], p->pv[1], p->pv[2]);
else if (p->vertex_count == 4)
render_polygon<4>(scissor, render_delegate(FUNC(namcos23_renderer::render_scanline), this), 4, p->pv);
else if (p->vertex_count == 5)
render_polygon<5>(scissor, render_delegate(FUNC(namcos23_renderer::render_scanline), this), 4, p->pv);
namcos23_render_data& extra = render.polymgr->object_data_alloc();
extra = p->rd;
if (p->vertex_count == 3)
render_triangle(scissor, render_delegate(FUNC(namcos23_renderer::render_scanline), this), 4, p->pv[0], p->pv[1], p->pv[2]);
else if (p->vertex_count == 4)
render_polygon<4>(scissor, render_delegate(FUNC(namcos23_renderer::render_scanline), this), 4, p->pv);
else if (p->vertex_count == 5)
render_polygon<5>(scissor, render_delegate(FUNC(namcos23_renderer::render_scanline), this), 4, p->pv);
}
render.poly_count = 0;
copybitmap(bitmap, m_bitmap, 0, 0, 0, 0, scissor);
copybitmap(bitmap, m_bitmap, 0, 0, 0, 0, scissor);
}
void namcos23_state::render_run(bitmap_rgb32 &bitmap)
@ -2117,7 +2117,7 @@ void namcos23_state::render_run(bitmap_rgb32 &bitmap)
re++;
}
render.polymgr->render_flush(bitmap);
render.polymgr->wait();
render.polymgr->wait();
}
@ -2189,7 +2189,7 @@ VIDEO_START_MEMBER(namcos23_state,s23)
m_bgtilemap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcos23_state::TextTilemapGetInfo),this), TILEMAP_SCAN_ROWS, 16, 16, 64, 64);
m_bgtilemap->set_transparent_pen(0xf);
m_bgtilemap->set_scrolldx(860, 860);
m_render.polymgr = auto_alloc(machine(), namcos23_renderer(*this));
m_render.polymgr = auto_alloc(machine(), namcos23_renderer(*this));
}

4
src/mame/drivers/naomi.c
View File

@ -9080,8 +9080,8 @@ ROM_END
/* 0043 */ GAME( 2000, crackndj, naomi, naomim2, crackndj,naomi_state, naomi, ROT0, "Sega", "Crackin' DJ", GAME_FLAGS )
/* 0044 */ GAME( 2000, csmasho, csmash, naomim2, naomi, naomi_state, naomi, ROT0, "Sega", "Cosmic Smash (JPN, USA, EXP, KOR, AUS)", GAME_FLAGS )
/* 0044 */ GAME( 2000, csmash, naomi, naomim2, naomi, naomi_state, naomi, ROT0, "Sega", "Cosmic Smash (JPN, USA, EXP, KOR, AUS) (Rev A)", GAME_FLAGS )
// 0045 1999, "FortyFive / Sega", "Tokio Bus Guide"
// 0045 1999, "FortyFive / Sega", "Tokio Bus Guide (Rev A)"
// 0045 1999, "FortyFive / Sega", "Tokio Bus Guide"
// 0045 1999, "FortyFive / Sega", "Tokio Bus Guide (Rev A)"
/* 0047 */ GAME( 2000, samba2k, naomi, naomim2, naomi, naomi_state, naomi, ROT0, "Sega", "Samba de Amigo ver. 2000", GAME_FLAGS )
/* 0048 */ GAME( 2001, alienfnt, naomi, naomim2, naomi, naomi_state, naomi, ROT0, "Sega", "Alien Front (Rev T)", GAME_FLAGS )
/* 0048 */ GAME( 2001, alienfnta,alienfnt, naomim2, naomi, naomi_state, naomi, ROT0, "Sega", "Alien Front (Rev A)", GAME_FLAGS )

2
src/mame/drivers/nmk16.c
View File

@ -6216,7 +6216,7 @@ Notes:
VSync - 56.205Hz
NMK CUSTOM IC'S
- NMK004 marked "NMK004 0840-1324". Actually a TLCS90-based Toshiba TMP90C840AF
- NMK004 marked "NMK004 0840-1324". Actually a TLCS90-based Toshiba TMP90C840AF
Microcontroller with 256 bytes RAM & 8Kb ROM, running at 8.000MHz [16/2] (QFP64)
- NMK005 (x1, Square QFP64)
- NMK008 (x1, Square QFP84)

6
src/mame/drivers/piggypas.c
View File

@ -76,7 +76,7 @@ static MACHINE_CONFIG_START( piggypas, piggypas_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", Z80,8000000) // wrong CPU? (not valid Z80 code)
MCFG_CPU_PROGRAM_MAP(piggypas_map)
// MCFG_CPU_VBLANK_INT_DRIVER("screen", piggypas_state, irq0_line_hold)
// MCFG_CPU_VBLANK_INT_DRIVER("screen", piggypas_state, irq0_line_hold)
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")
@ -157,9 +157,9 @@ ROM_END
GAME( 1992, piggypas, 0, piggypas, piggypas, driver_device, 0, ROT0, "Doyle & Assoc.", "Piggy Pass (version 04.40)", MACHINE_IS_SKELETON_MECHANICAL )
// COPYRIGHT (c) 1990, 1991, 1992, DOYLE & ASSOC., INC. VERSION 05.22
GAME( 1992, hoopshot, 0, piggypas, piggypas, driver_device, 0, ROT0, "Doyle & Assoc.", "Hoop Shot (version 05.22)", MACHINE_IS_SKELETON_MECHANICAL )
// Quick $ilver Development Co. 10/08/96 ROUND REV 6
// Quick $ilver Development Co. 10/08/96 ROUND REV 6
GAME( 1996, rndrndqs, 0, piggypas, piggypas, driver_device, 0, ROT0, "Quick $ilver Development Co.", "Round and Round (Rev 6) (Quick $ilver)", MACHINE_IS_SKELETON_MECHANICAL )
// Quick$ilver Development Co. 10/02/95 -FIDDLESTIX- REV 15T
// Quick$ilver Development Co. 10/02/95 -FIDDLESTIX- REV 15T
GAME( 1995, fidlstix, 0, piggypas, piggypas, driver_device, 0, ROT0, "Quick $ilver Development Co.", "Fiddle Stix (1st Rev)", MACHINE_IS_SKELETON_MECHANICAL )
// bad dump, so version unknown
GAME( 199?, jackbean, 0, piggypas, piggypas, driver_device, 0, ROT0, "Doyle & Assoc.", "Jack & The Beanstalk (Doyle & Assoc.?)", MACHINE_IS_SKELETON_MECHANICAL )

2
src/mame/drivers/quantum.c
View File

@ -13,7 +13,7 @@
* none at this time
NOTE: The Atari 136002-125 PROM in the sets below wasn't dumped from an actual
Quantum PCB. It is assumed all Atari 136002-125 PROMs are the same data.
Quantum PCB. It is assumed all Atari 136002-125 PROMs are the same data.
****************************************************************************

2
src/mame/drivers/route16.c
View File

@ -669,7 +669,7 @@ MACHINE_CONFIG_END
*
*************************************/
ROM_START( route16 )
ROM_START( route16 )
ROM_REGION( 0x10000, "cpu1", 0 )
ROM_LOAD( "tvg54.a0", 0x0000, 0x0800, CRC(aef9ffc1) SHA1(178d23e4963336ded93c13cb17940a4ae98270c5) )
ROM_LOAD( "tvg55.a1", 0x0800, 0x0800, CRC(389bc077) SHA1(b0606f6e647e81ceae7148bda96bd4673a51e823) )

40
src/mame/drivers/scobra.c
View File

@ -211,7 +211,7 @@ static ADDRESS_MAP_START( rescuefe_map, AS_PROGRAM, 8, scobra_state )
AM_RANGE(0x4400, 0x5dff) AM_ROM
AM_RANGE(0x5e00, 0x6bff) AM_ROM // some right?
AM_RANGE(0x8200, 0x93ff) AM_ROM // wrong? (maybe some correct?)
AM_RANGE(0xa600, 0xa6ff) AM_ROM // wrong (taunt string) jumps to around a600 so something must map in this area?
@ -226,13 +226,13 @@ static ADDRESS_MAP_START( rescuefe_map, AS_PROGRAM, 8, scobra_state )
AM_RANGE(0xC160, 0xC163) AM_DEVREAD("ppi8255_0", i8255_device, read) // ?
AM_RANGE(0xC4Ac, 0xC4AF) AM_DEVREAD("ppi8255_1", i8255_device, read) // ?
AM_RANGE(0xc180, 0xc183) AM_DEVWRITE("ppi8255_0", i8255_device, write) // correct based on main set?
AM_RANGE(0xc220, 0xc223) AM_DEVWRITE("ppi8255_1", i8255_device, write) // ^
AM_RANGE(0xc220, 0xc223) AM_DEVWRITE("ppi8255_1", i8255_device, write) // ^
// addresses below are WRONG, just moved to keep things out the way while the rom mapping is figured out
// AM_RANGE(0xf802, 0xf802) AM_WRITE(galaxold_coin_counter_w)
// AM_RANGE(0xf000, 0xf000) AM_READ(watchdog_reset_r)
// AM_RANGE(0xf802, 0xf802) AM_WRITE(galaxold_coin_counter_w)
// AM_RANGE(0xf000, 0xf000) AM_READ(watchdog_reset_r)
ADDRESS_MAP_END
static ADDRESS_MAP_START( minefldfe_map, AS_PROGRAM, 8, scobra_state )
@ -254,11 +254,11 @@ static ADDRESS_MAP_START( minefldfe_map, AS_PROGRAM, 8, scobra_state )
AM_RANGE(0x7616, 0x7616) AM_WRITE(galaxold_flip_screen_x_w) // a806
AM_RANGE(0x7617, 0x7617) AM_WRITE(galaxold_flip_screen_y_w) // a807
AM_RANGE(0x4C00, 0x4C03) AM_MIRROR(0x00fc) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
AM_RANGE(0x4B00, 0x4B03) AM_MIRROR(0x00fc) AM_DEVREADWRITE("ppi8255_0", i8255_device, read, write)
AM_RANGE(0x4C00, 0x4C03) AM_MIRROR(0x00fc) AM_DEVREADWRITE("ppi8255_1", i8255_device, read, write)
AM_RANGE(0x4B00, 0x4B03) AM_MIRROR(0x00fc) AM_DEVREADWRITE("ppi8255_0", i8255_device, read, write)
AM_RANGE(0x1D98, 0x1D98) AM_READ(watchdog_reset_r) // 0xb000
@ -836,8 +836,8 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( rescuefe, rescue )
/* basic machine hardware */
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(rescuefe_map)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(rescuefe_map)
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( rescueb, rescue )
@ -860,8 +860,8 @@ static MACHINE_CONFIG_DERIVED( minefld, type1 )
MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( minefldfe, minefld )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(minefldfe_map)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(minefldfe_map)
MACHINE_CONFIG_END
@ -1221,13 +1221,13 @@ Both are missing the top sound PCB.
/* the 'Minefield' shop shows a Logicshop copyright, and a phone number with a Great Yarmouth area code
which seems to indicate the following manufacturer / operator.
The Logicshop (Great Yarmouth)
Caesar's Arcade
Beach Rd
Hemsby
Great Yarmouth
Norfolk
NR29 4HS
The Logicshop (Great Yarmouth)
Caesar's Arcade
Beach Rd
Hemsby
Great Yarmouth
Norfolk
NR29 4HS
*/

12
src/mame/drivers/seattle.c
View File

@ -3028,12 +3028,12 @@ ROM_START( hyprdriv )
ROM_SYSTEM_BIOS( 1, "update", "Unknown Update" )
ROMX_LOAD( "hyperdrive1.2.u33", 0x000000, 0x100000, CRC(fcc922fb) SHA1(7bfa4f0614f561ba77ad2dc7d776af2c3e84b7e7), ROM_BIOS(2) )
/* it's either an update to 1.40, or an older version, either way we can't use it with the drive we have, it reports the following
'Valid Update Rom Detected'
'Processing Rom'
'Rom is Wrong Revision Level'
'Operation Failure'
'Valid Update Rom Detected'
'Processing Rom'
'Rom is Wrong Revision Level'
'Operation Failure'
*/
ROM_REGION32_LE( 0x80000, "user1", 0 )

2
src/mame/drivers/segac2.c
View File

@ -1630,7 +1630,7 @@ ROM_START( soniccar ) /* Waku Waku Sonic Patrol Car (c)1991 Sega - 834-8401 SON
ROM_REGION( 0x200000, "maincpu", 0 )
ROM_LOAD16_BYTE( "epr-14369.ic32", 0x000000, 0x040000, CRC(2ea4c9a3) SHA1(92ee27c93bd1cbb99c88af39f5f227a8cadfb13c) )
ROM_LOAD16_BYTE( "epr-14395.ic31", 0x000001, 0x040000, CRC(39622e18) SHA1(b7093c6d86e429e9721a0e1fd781231dc4342b31) )
ROM_REGION( 0x040000, "upd", 0 )
ROM_LOAD( "epr-14394.ic4", 0x000000, 0x040000, CRC(476e30dd) SHA1(c9d381160c58b05763ea286a53c7ca6de074fda2) )
ROM_END

2
src/mame/drivers/segas16b.c
View File

@ -8214,7 +8214,7 @@ GAME( 1989, fpoint1d, fpoint, system16b, fpoint, segas16b_state,generic
GAME( 1988, tetris2d, tetris, system16b, tetris, segas16b_state,generic_5704, ROT0, "bootleg", "Tetris (set 2, Japan, System 16B) (bootleg of FD1094 317-0092 set)", 0 )
GAME( 1988, tetris1d, tetris, system16b, tetris, segas16b_state,generic_5358_small, ROT0, "bootleg", "Tetris (set 1, Japan, System 16B) (bootleg of FD1094 317-0091 set)", 0 )
GAME( 1988, dduxd, ddux, system16b, ddux, segas16b_state,generic_5521, ROT0, "bootleg", "Dynamite Dux (set 3, World) (bootleg of FD1094 317-0096 set)", 0 )
GAME( 1988, dduxd, ddux, system16b, ddux, segas16b_state,generic_5521, ROT0, "bootleg", "Dynamite Dux (set 3, World) (bootleg of FD1094 317-0096 set)", 0 )
GAME( 1988, dduxjd, ddux, system16b, ddux, segas16b_state,generic_5521, ROT0, "bootleg", "Dynamite Dux (set 2, Japan) (bootleg of FD1094 317-0094 set)", 0 )
GAME( 1988, altbeast5d, altbeast, system16b, altbeast, segas16b_state,generic_5521, ROT0, "bootleg", "Altered Beast (set 5) (bootleg of FD1094 317-0069 set)", 0 )

2
src/mame/drivers/segaxbd.c
View File

@ -330,7 +330,6 @@ void segaxbd_state::device_start()
void segaxbd_state::device_reset()
{
m_segaic16vid->tilemap_reset(*m_screen);
// hook the RESET line, which resets CPU #1
@ -348,7 +347,6 @@ public:
: driver_device(mconfig, type, tag),
m_mainpcb(*this, "mainpcb")
{
}
required_device<segaxbd_state> m_mainpcb;

2
src/mame/drivers/taito_f3.c
View File

@ -62,7 +62,7 @@ READ32_MEMBER(taito_f3_state::f3_control_r)
if (offset<6)
return m_input[offset]->read();
else logerror("CPU #0 PC %06x: warning - read unmapped control address %06x\n", space.device().safe_pc(), offset);
return 0xffffffff;
}

28
src/mame/drivers/toratora.c
View File

@ -440,34 +440,34 @@ ROM_START( toratora )
ROM_END
/* Tora Tora? Game Plan?
Etched in copper on top of board 20-00047C
20-10051A
Etched in copper on top of board 20-00047C
20-10051A
Etched in copper on back of daughter board 20-00048C
20-10052A
Etched in copper on back of daughter board 20-00048C
20-10052A
ROM text showed TORA TOR* * was A with bit 7 set
1980 GAME PLAN,INC
ROM text showed TORA TOR* * was A with bit 7 set
1980 GAME PLAN,INC
and war stuff (PLANE, BOMB, SQUAD, etc)
.u2 2716 handwritten sticker U-2
.u9 2716 handwritten sticker U-9
.u10 2716 handwritten sticker U-10
.u11 2716 handwritten sticker U-11
.u2 2716 handwritten sticker U-2
.u9 2716 handwritten sticker U-9
.u10 2716 handwritten sticker U-10
.u11 2716 handwritten sticker U-11
open 24 pin socket @ U1 and U3
open 40 pin socket @ U42
Main board
crystal with 5 185 on the top
5280 x8
socketed ds8833 x2
socketed ds8t28 x2
5280 x8
socketed ds8833 x2
socketed ds8t28 x2
Daughter board
open 40 pin socket @ U3 @ U2
76477 X2 */
76477 X2 */
ROM_START( toratorab )
ROM_REGION( 0x10000, "maincpu", 0 )

154
src/mame/drivers/wacky_gator.c
View File

@ -36,39 +36,39 @@
class wackygtr_state : public driver_device
{
public:
wackygtr_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_msm(*this, "msm"),
m_maincpu(*this, "maincpu")
{ }
wackygtr_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_msm(*this, "msm"),
m_maincpu(*this, "maincpu")
{ }
UINT8* m_samples;
int m_adpcm_data;
int m_adpcm_pos;
int m_adpcm_length;
UINT8* m_samples;
int m_adpcm_data;
int m_adpcm_pos;
int m_adpcm_length;
required_device<msm5205_device> m_msm;
required_device<cpu_device> m_maincpu;
DECLARE_DRIVER_INIT(wackygtr);
required_device<msm5205_device> m_msm;
required_device<cpu_device> m_maincpu;
DECLARE_DRIVER_INIT(wackygtr);
INTERRUPT_GEN_MEMBER(wackygtr_interrupt);
DECLARE_WRITE_LINE_MEMBER(adpcm_int);
DECLARE_READ8_MEMBER(_0x6000_r);
DECLARE_READ8_MEMBER(_0x6001_r);
DECLARE_READ8_MEMBER(_0x6002_r);
DECLARE_READ8_MEMBER(_0x71d0_r);
DECLARE_READ8_MEMBER(_0x71d5_r);
DECLARE_WRITE8_MEMBER(sample_pos_w);
DECLARE_WRITE8_MEMBER(sample_length_w);
INTERRUPT_GEN_MEMBER(wackygtr_interrupt);
DECLARE_WRITE_LINE_MEMBER(adpcm_int);
DECLARE_READ8_MEMBER(_0x6000_r);
DECLARE_READ8_MEMBER(_0x6001_r);
DECLARE_READ8_MEMBER(_0x6002_r);
DECLARE_READ8_MEMBER(_0x71d0_r);
DECLARE_READ8_MEMBER(_0x71d5_r);
DECLARE_WRITE8_MEMBER(sample_pos_w);
DECLARE_WRITE8_MEMBER(sample_length_w);
};
DRIVER_INIT_MEMBER(wackygtr_state, wackygtr)
{
m_adpcm_data = -1;
m_adpcm_pos = 0;
m_adpcm_length = 0;
m_samples = memregion("oki")->base();
m_adpcm_data = -1;
m_adpcm_pos = 0;
m_adpcm_length = 0;
m_samples = memregion("oki")->base();
}
/*
@ -76,23 +76,23 @@ DRIVER_INIT_MEMBER(wackygtr_state, wackygtr)
* and may be completely wrong, so should not yet be understood as hardware documentation.
*/
READ8_MEMBER(wackygtr_state::_0x6000_r){
return 0x00;
return 0x00;
}
READ8_MEMBER(wackygtr_state::_0x6001_r){
return 0x00;
return 0x00;
}
READ8_MEMBER(wackygtr_state::_0x6002_r){
return 0x00;
return 0x00;
}
READ8_MEMBER(wackygtr_state::_0x71d0_r){
return 0;
return 0;
}
READ8_MEMBER(wackygtr_state::_0x71d5_r){
return 0xFF;
return 0xFF;
}
/* The handling of sample playback is also guessed.
@ -100,79 +100,79 @@ READ8_MEMBER(wackygtr_state::_0x71d5_r){
* better understand how this is actually hooked up on the original boards;
*/
WRITE8_MEMBER(wackygtr_state::sample_pos_w){
m_adpcm_pos = (m_adpcm_pos & 0xFF) << 8 | (data & 0xFF);
m_adpcm_pos = (m_adpcm_pos & 0xFF) << 8 | (data & 0xFF);
}
WRITE8_MEMBER(wackygtr_state::sample_length_w){
m_adpcm_length = (m_adpcm_length & 0xFF) << 8 | (data & 0xFF);
m_adpcm_length = (m_adpcm_length & 0xFF) << 8 | (data & 0xFF);
}
static INPUT_PORTS_START( wackygtr )
PORT_START("INP0")
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("INP0")
PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
INPUT_PORTS_END
WRITE_LINE_MEMBER(wackygtr_state::adpcm_int)
{
{
/* This looks almost correct, but I am not yet completely sure. */
if (m_adpcm_length > 0)
{
m_adpcm_length--;
if (m_adpcm_data == -1)
{
/* transferring 1st nibble */
m_adpcm_data = m_samples[m_adpcm_pos];
m_adpcm_pos = (m_adpcm_pos + 1) & 0xffff;
m_msm->data_w((m_adpcm_data >> 4) & 0xf);
}
else
{
/* transferring 2nd nibble */
m_msm->data_w(m_adpcm_data & 0x0f);
m_adpcm_data = -1;
}
}
if (m_adpcm_length > 0)
{
m_adpcm_length--;
if (m_adpcm_data == -1)
{
/* transferring 1st nibble */
m_adpcm_data = m_samples[m_adpcm_pos];
m_adpcm_pos = (m_adpcm_pos + 1) & 0xffff;
m_msm->data_w((m_adpcm_data >> 4) & 0xf);
}
else
{
/* transferring 2nd nibble */
m_msm->data_w(m_adpcm_data & 0x0f);
m_adpcm_data = -1;
}
}
}
static ADDRESS_MAP_START( program_map, AS_PROGRAM, 8, wackygtr_state )
AM_RANGE(0x3000, 0x3000) AM_WRITE(sample_length_w)
AM_RANGE(0x3001, 0x3001) AM_WRITE(sample_pos_w)
AM_RANGE(0x6000, 0x6000) AM_READ(_0x6000_r) /* guessed hw peripheral address */
AM_RANGE(0x6001, 0x6001) AM_READ(_0x6001_r) /* guessed hw peripheral address */
AM_RANGE(0x6002, 0x6002) AM_READ(_0x6002_r) /* guessed hw peripheral address */
AM_RANGE(0x71d0, 0x71d0) AM_READ(_0x71d0_r) /* guessed hw peripheral address */
AM_RANGE(0x71d5, 0x71d5) AM_READ(_0x71d5_r) /* guessed hw peripheral address */
AM_RANGE(0x7000, 0x7fff) AM_RAM
AM_RANGE(0x8000, 0xffff) AM_ROM
AM_RANGE(0x3000, 0x3000) AM_WRITE(sample_length_w)
AM_RANGE(0x3001, 0x3001) AM_WRITE(sample_pos_w)
AM_RANGE(0x6000, 0x6000) AM_READ(_0x6000_r) /* guessed hw peripheral address */
AM_RANGE(0x6001, 0x6001) AM_READ(_0x6001_r) /* guessed hw peripheral address */
AM_RANGE(0x6002, 0x6002) AM_READ(_0x6002_r) /* guessed hw peripheral address */
AM_RANGE(0x71d0, 0x71d0) AM_READ(_0x71d0_r) /* guessed hw peripheral address */
AM_RANGE(0x71d5, 0x71d5) AM_READ(_0x71d5_r) /* guessed hw peripheral address */
AM_RANGE(0x7000, 0x7fff) AM_RAM
AM_RANGE(0x8000, 0xffff) AM_ROM
ADDRESS_MAP_END
static MACHINE_CONFIG_START( wackygtr, wackygtr_state )
MCFG_CPU_ADD("maincpu", M6809E, XTAL_8MHz)
MCFG_CPU_PROGRAM_MAP(program_map)
MCFG_CPU_ADD("maincpu", M6809E, XTAL_8MHz)
MCFG_CPU_PROGRAM_MAP(program_map)
/* Video */
/* Video */
// MCFG_DEFAULT_LAYOUT(layout_wackygtr)
/* Sound */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("msm", MSM5205, XTAL_384kHz )
MCFG_MSM5205_VCLK_CB(WRITELINE(wackygtr_state, adpcm_int)) /* IRQ handler */
MCFG_MSM5205_PRESCALER_SELECTOR(MSM5205_S48_4B) /* 8 KHz, 4 Bits */
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
/* Sound */
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("msm", MSM5205, XTAL_384kHz )
MCFG_MSM5205_VCLK_CB(WRITELINE(wackygtr_state, adpcm_int)) /* IRQ handler */
MCFG_MSM5205_PRESCALER_SELECTOR(MSM5205_S48_4B) /* 8 KHz, 4 Bits */
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
/* I have a hunch that this board may also
* contain a YM2151 sound chip for background music...
*/
/* I have a hunch that this board may also
* contain a YM2151 sound chip for background music...
*/
MACHINE_CONFIG_END
ROM_START( wackygtr )
ROM_REGION(0x10000, "maincpu", 0)
ROM_LOAD("wp3-pr0.4d", 0x8000, 0x8000, CRC(71ca4437) SHA1(c7d948c5593e6053fd0a65601f6c06871f5861f0))
ROM_REGION(0x10000, "maincpu", 0)
ROM_LOAD("wp3-pr0.4d", 0x8000, 0x8000, CRC(71ca4437) SHA1(c7d948c5593e6053fd0a65601f6c06871f5861f0))
ROM_REGION(0x10000, "oki", 0)
ROM_LOAD("wp3-vo0.2h", 0x0000, 0x10000, CRC(91c7986f) SHA1(bc9fa0d41c1caa0f909a349f511d022b7e42c6cd))
ROM_REGION(0x10000, "oki", 0)
ROM_LOAD("wp3-vo0.2h", 0x0000, 0x10000, CRC(91c7986f) SHA1(bc9fa0d41c1caa0f909a349f511d022b7e42c6cd))
ROM_END
GAME(1990, wackygtr, 0, wackygtr, wackygtr, wackygtr_state, wackygtr, ROT0, "Data East", "Wacky Gator", MACHINE_IS_SKELETON_MECHANICAL)

6
src/mame/drivers/zaccaria.c
View File

@ -506,16 +506,16 @@ static MACHINE_CONFIG_START( zaccaria, zaccaria_state )
MCFG_CPU_ADD("maincpu", Z80,XTAL_18_432MHz/6) /* verified on pcb */
MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_CPU_VBLANK_INT_DRIVER("screen", zaccaria_state, vblank_irq)
// MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
// MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
MCFG_CPU_ADD("audiocpu", M6802,XTAL_3_579545MHz) /* verified on pcb */
MCFG_CPU_PROGRAM_MAP(sound_map_1)
MCFG_CPU_PERIODIC_INT_DRIVER(zaccaria_state, cb1_toggle, (double)XTAL_3_579545MHz/4096)
// MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
// MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
MCFG_CPU_ADD("audio2", M6802,XTAL_3_579545MHz) /* verified on pcb */
MCFG_CPU_PROGRAM_MAP(sound_map_2)
// MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
// MCFG_QUANTUM_TIME(attotime::from_hz(1000000))
MCFG_DEVICE_ADD("ppi8255", I8255A, 0)
MCFG_I8255_IN_PORTA_CB(IOPORT("P1"))

16
src/mame/includes/galastrm.h
View File

@ -19,14 +19,14 @@ class galastrm_renderer : public poly_manager<float, gs_poly_data, 2, 10000>
public:
galastrm_renderer(galastrm_state &state);
void tc0610_draw_scanline(INT32 scanline, const extent_t& extent, const gs_poly_data& object, int threadid);
void tc0610_rotate_draw(bitmap_ind16 &srcbitmap, const rectangle &clip);
bitmap_ind16 &screenbits() { return m_screenbits; }
void tc0610_draw_scanline(INT32 scanline, const extent_t& extent, const gs_poly_data& object, int threadid);
void tc0610_rotate_draw(bitmap_ind16 &srcbitmap, const rectangle &clip);
bitmap_ind16 &screenbits() { return m_screenbits; }
private:
galastrm_state& m_state;
bitmap_ind16 m_screenbits;
bitmap_ind16 m_screenbits;
};
@ -81,8 +81,8 @@ public:
struct gs_tempsprite *m_spritelist;
struct gs_tempsprite *m_sprite_ptr_pre;
bitmap_ind16 m_tmpbitmaps;
galastrm_renderer *m_poly;
galastrm_renderer *m_poly;
int m_rsxb;
int m_rsyb;
int m_rsxoffs;

34
src/mame/includes/hng64.h
View File

@ -109,21 +109,21 @@ class hng64_state;
class hng64_poly_renderer : public poly_manager<float, hng64_poly_data, 7, HNG64_MAX_POLYGONS>
{
public:
hng64_poly_renderer(hng64_state& state);
void drawShaded(struct polygon *p);
void render_scanline(INT32 scanline, const extent_t& extent, const hng64_poly_data& renderData, int threadid);
hng64_poly_renderer(hng64_state& state);
void drawShaded(struct polygon *p);
void render_scanline(INT32 scanline, const extent_t& extent, const hng64_poly_data& renderData, int threadid);
hng64_state& state() { return m_state; }
bitmap_rgb32& colorBuffer3d() { return m_colorBuffer3d; }
float* depthBuffer3d() { return m_depthBuffer3d; }
hng64_state& state() { return m_state; }
bitmap_rgb32& colorBuffer3d() { return m_colorBuffer3d; }
float* depthBuffer3d() { return m_depthBuffer3d; }
private:
hng64_state& m_state;
// (Temporarily class members - someday they will live in the memory map)
bitmap_rgb32 m_colorBuffer3d;
float* m_depthBuffer3d;
hng64_state& m_state;
// (Temporarily class members - someday they will live in the memory map)
bitmap_rgb32 m_colorBuffer3d;
float* m_depthBuffer3d;
};
@ -173,7 +173,7 @@ public:
required_shared_ptr<UINT32> m_videoregs;
required_shared_ptr<UINT32> m_tcram;
/* 3D stuff */
/* 3D stuff */
UINT16* m_dl;
required_shared_ptr<UINT32> m_3dregs;
@ -325,9 +325,9 @@ public:
DECLARE_CUSTOM_INPUT_MEMBER(acc_down_r);
DECLARE_CUSTOM_INPUT_MEMBER(brake_down_r);
hng64_poly_renderer* m_poly_renderer;
void clear3d();
hng64_poly_renderer* m_poly_renderer;
void clear3d();
TIMER_CALLBACK_MEMBER(hng64_3dfifo_processed);
void hng64_command3d(const UINT16* packet);

163
src/mame/includes/model2.h
View File

@ -280,91 +280,90 @@ struct triangle;
class model2_renderer : public poly_manager<float, m2_poly_extra_data, 4, 4000>
{
public:
typedef void (model2_renderer::*scanline_render_func)(INT32 scanline, const extent_t& extent, const m2_poly_extra_data& object, int threadid);
public:
model2_renderer(model2_state& state)
: poly_manager<float, m2_poly_extra_data, 4, 4000>(state.machine())
, m_state(state)
, m_destmap(state.m_screen->width(), state.m_screen->height())
{
m_renderfuncs[0] = &model2_renderer::model2_3d_render_0;
m_renderfuncs[1] = &model2_renderer::model2_3d_render_1;
m_renderfuncs[2] = &model2_renderer::model2_3d_render_2;
m_renderfuncs[3] = &model2_renderer::model2_3d_render_3;
m_renderfuncs[4] = &model2_renderer::model2_3d_render_4;
m_renderfuncs[5] = &model2_renderer::model2_3d_render_5;
m_renderfuncs[6] = &model2_renderer::model2_3d_render_6;
m_renderfuncs[7] = &model2_renderer::model2_3d_render_7;
}
bitmap_rgb32& destmap() { return m_destmap; }
void model2_3d_render(triangle *tri, const rectangle &cliprect);
/* checker = 0, textured = 0, transparent = 0 */
#define MODEL2_FUNC 0
#define MODEL2_FUNC_NAME model2_3d_render_0
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 0, textured = 0, translucent = 1 */
#define MODEL2_FUNC 1
#define MODEL2_FUNC_NAME model2_3d_render_1
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 0, textured = 1, translucent = 0 */
#define MODEL2_FUNC 2
#define MODEL2_FUNC_NAME model2_3d_render_2
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 0, textured = 1, translucent = 1 */
#define MODEL2_FUNC 3
#define MODEL2_FUNC_NAME model2_3d_render_3
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 1, textured = 0, translucent = 0 */
#define MODEL2_FUNC 4
#define MODEL2_FUNC_NAME model2_3d_render_4
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 1, textured = 0, translucent = 1 */
#define MODEL2_FUNC 5
#define MODEL2_FUNC_NAME model2_3d_render_5
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 1, textured = 1, translucent = 0 */
#define MODEL2_FUNC 6
#define MODEL2_FUNC_NAME model2_3d_render_6
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 1, textured = 1, translucent = 1 */
#define MODEL2_FUNC 7
#define MODEL2_FUNC_NAME model2_3d_render_7
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
typedef void (model2_renderer::*scanline_render_func)(INT32 scanline, const extent_t& extent, const m2_poly_extra_data& object, int threadid);
public:
model2_renderer(model2_state& state)
: poly_manager<float, m2_poly_extra_data, 4, 4000>(state.machine())
, m_state(state)
, m_destmap(state.m_screen->width(), state.m_screen->height())
{
m_renderfuncs[0] = &model2_renderer::model2_3d_render_0;
m_renderfuncs[1] = &model2_renderer::model2_3d_render_1;
m_renderfuncs[2] = &model2_renderer::model2_3d_render_2;
m_renderfuncs[3] = &model2_renderer::model2_3d_render_3;
m_renderfuncs[4] = &model2_renderer::model2_3d_render_4;
m_renderfuncs[5] = &model2_renderer::model2_3d_render_5;
m_renderfuncs[6] = &model2_renderer::model2_3d_render_6;
m_renderfuncs[7] = &model2_renderer::model2_3d_render_7;
}
bitmap_rgb32& destmap() { return m_destmap; }
void model2_3d_render(triangle *tri, const rectangle &cliprect);
/* checker = 0, textured = 0, transparent = 0 */
#define MODEL2_FUNC 0
#define MODEL2_FUNC_NAME model2_3d_render_0
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 0, textured = 0, translucent = 1 */
#define MODEL2_FUNC 1
#define MODEL2_FUNC_NAME model2_3d_render_1
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 0, textured = 1, translucent = 0 */
#define MODEL2_FUNC 2
#define MODEL2_FUNC_NAME model2_3d_render_2
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 0, textured = 1, translucent = 1 */
#define MODEL2_FUNC 3
#define MODEL2_FUNC_NAME model2_3d_render_3
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 1, textured = 0, translucent = 0 */
#define MODEL2_FUNC 4
#define MODEL2_FUNC_NAME model2_3d_render_4
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 1, textured = 0, translucent = 1 */
#define MODEL2_FUNC 5
#define MODEL2_FUNC_NAME model2_3d_render_5
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 1, textured = 1, translucent = 0 */
#define MODEL2_FUNC 6
#define MODEL2_FUNC_NAME model2_3d_render_6
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
/* checker = 1, textured = 1, translucent = 1 */
#define MODEL2_FUNC 7
#define MODEL2_FUNC_NAME model2_3d_render_7
#include "video/model2rd.inc"
#undef MODEL2_FUNC
#undef MODEL2_FUNC_NAME
scanline_render_func m_renderfuncs[8];
scanline_render_func m_renderfuncs[8];
private:
model2_state& m_state;
bitmap_rgb32 m_destmap;
model2_state& m_state;
bitmap_rgb32 m_destmap;
};
typedef model2_renderer::vertex_t poly_vertex;

2
src/mame/includes/n64.h
View File

@ -311,7 +311,7 @@ extern const device_type N64PERIPH;
#define DP_STATUS_XBUS_DMA 0x01
#define DP_STATUS_FREEZE 0x02
#define DP_STATUS_FLUSH 0x04
#define DP_STATUS_START_VALID 0x400
#define DP_STATUS_START_VALID 0x400
#define DD_ASIC_STATUS_DISK_CHANGE 0x00010000
#define DD_ASIC_STATUS_MECHA_ERR 0x00020000

6
src/mame/includes/segaxbd.h
View File

@ -54,7 +54,7 @@ public:
// video updates
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
// palette helpers
DECLARE_WRITE16_MEMBER( paletteram_w );
@ -78,7 +78,7 @@ protected:
};
// device overrides
// virtual void machine_reset();
// virtual void machine_reset();
virtual void video_start();
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
@ -239,5 +239,3 @@ protected:
// virtual void device_start();
// virtual void device_reset();
};

6
src/mame/machine/atari_vg.c
View File

@ -14,7 +14,7 @@
x x x x | | \---- /EAROM C1 (note this is inverted! the value written here is inverted, then connected to EAROM C1 AND to the /OE of the 'input latch' which drive the EAROM bus when writing)
x x x x | \------ EAROM C2 (directly connected)
x x x x \-------- EAROM CS1 (positive enable, directly connected)
Gravitar, Red Baron, Black Widow, Tempest, Liberator, Asteroids Deluxe, Runaway CTRL port wiring:
7 6 5 4 3 2 1 0
x x x x | | | \-- EAROM CLK (directly connected)
@ -165,8 +165,8 @@ void atari_vg_earom_device::device_start()
void atari_vg_earom_device::device_reset()
{
m_state = ER2055_READ_WAITING_FOR_CLOCK; // start in read mode
m_old_ctrl = 0;
m_old_ctrl = 0;
m_in_offset = 0;
m_in_data = 0;
m_out_data = 0xFF; // the value driven to the bus by the resistors if EAROM is open bus
m_out_data = 0xFF; // the value driven to the bus by the resistors if EAROM is open bus
}

2
src/mame/machine/fd1094.c
View File

@ -566,7 +566,7 @@ fd1094_device::fd1094_device(const machine_config &mconfig, const char *tag, dev
m_name.assign("FD1094");
// add the decrypted opcodes map
// m_address_map[AS_DECRYPTED_OPCODES] = ADDRESS_MAP_NAME(decrypted_opcodes_map);
// m_address_map[AS_DECRYPTED_OPCODES] = ADDRESS_MAP_NAME(decrypted_opcodes_map);
// create the initial masked opcode table
memset(m_masked_opcodes_lookup, 0, sizeof(m_masked_opcodes_lookup));

144
src/mame/machine/m2comm.c
View File

@ -24,21 +24,21 @@ Sega MODEL2 COMMUNICATION BOARD 837-10537
| |-------------------| |-------------------| |-------------------| |
|-----------------------------------------------------------------------------|
Setup:
Z80 Zilog Z0840008PSC Z80 CPU (DIP40)
LH5268A SHARP LH5268AD-10LL 8k x8 SRAM (DIP28)
uPD72103 NEC uPD72103 HDLC/Frame Relay Controller (QFP80)
16726.7 M27C1001 128k x8 EPROM (DIP32, labelled 'EPR-16726')
315-5751 Lattice GAL16V8B-25LP PAL (DIP20)
315-5752 Lattice GAL16V8B-25LP PAL (DIP20)
315-5753A AMI 18CV8PC-15 PAL (DIP20)
315-5547 AMI 18CV8PC-25 PAL (DIP20)
Setup:
Z80 Zilog Z0840008PSC Z80 CPU (DIP40)
LH5268A SHARP LH5268AD-10LL 8k x8 SRAM (DIP28)
uPD72103 NEC uPD72103 HDLC/Frame Relay Controller (QFP80)
16726.7 M27C1001 128k x8 EPROM (DIP32, labelled 'EPR-16726')
315-5751 Lattice GAL16V8B-25LP PAL (DIP20)
315-5752 Lattice GAL16V8B-25LP PAL (DIP20)
315-5753A AMI 18CV8PC-15 PAL (DIP20)
315-5547 AMI 18CV8PC-25 PAL (DIP20)
Board:
837-10537 Daytona USA
Board:
837-10537 Daytona USA
EEPROM:
16726.7 Daytona USA
EEPROM:
16726.7 Daytona USA
Sega PC BD MODEL2 A-CRX COMMUNICATION 837-11525
@ -63,23 +63,23 @@ Sega PC BD MODEL2 A-CRX COMMUNICATION 837-11525
| |-------------------| |-------------------| |-------------------| |
|-------------------------------------------------------------------------------------------|
Setup:
Z80 Zilog Z0840008PSC Z80 CPU (DIP40)
LH5268A SHARP LH5268AD-10LL 8k x8 SRAM (DIP28)
uPD72103 NEC uPD72103 HDLC/Frame Relay Controller (QFP80)
16726.7 M27C1001 128k x8 EPROM (DIP32, labelled 'EPR-16726')
315-5751 Lattice GAL16V8B-25LP PAL (DIP20)
315-5752 Lattice GAL16V8B-25LP PAL (DIP20)
315-5753A AMI 18CV8PC-15 PAL (DIP20)
315-5547 AMI 18CV8PC-25 PAL (DIP20)
Setup:
Z80 Zilog Z0840008PSC Z80 CPU (DIP40)
LH5268A SHARP LH5268AD-10LL 8k x8 SRAM (DIP28)
uPD72103 NEC uPD72103 HDLC/Frame Relay Controller (QFP80)
16726.7 M27C1001 128k x8 EPROM (DIP32, labelled 'EPR-16726')
315-5751 Lattice GAL16V8B-25LP PAL (DIP20)
315-5752 Lattice GAL16V8B-25LP PAL (DIP20)
315-5753A AMI 18CV8PC-15 PAL (DIP20)
315-5547 AMI 18CV8PC-25 PAL (DIP20)
Board:
837-11525
837-11572 Sega Rally Championship
Board:
837-11525
837-11572 Sega Rally Championship
EEPROM:
16726.7 Sega Rally Championship
18643A.7 ManxTT
EEPROM:
16726.7 Sega Rally Championship
18643A.7 ManxTT
Sega PC BD MODEL2 B-CRX COMMUNICATION 837-11615
@ -104,23 +104,23 @@ Sega PC BD MODEL2 B-CRX COMMUNICATION 837-11615
| CN3 |-------------------| |
|-------------------------------------------------------------------------------------------|
Setup:
Z80 Zilog Z0840008PSC Z80 CPU (DIP40)
MB84256A Fujitsu MB84256A-70LL 32k x8 SRAM (SDIP28)
uPD72103A NEC uPD72103 HDLC/Frame Relay Controller (QFP80)
18643A.7 M27C1001 128k x8 EPROM (DIP32, labelled 'EPR-18643A')
315-5751 Lattice GAL16V8B-25LP PAL (DIP20)
315-5752 Lattice GAL16V8B-25LP PAL (DIP20)
315-5753A ICT PEEL18CV8P-15 PAL (DIP20)
315-5547A AMI 18CV8PC-25 PAL (DIP20)
Setup:
Z80 Zilog Z0840008PSC Z80 CPU (DIP40)
MB84256A Fujitsu MB84256A-70LL 32k x8 SRAM (SDIP28)
uPD72103A NEC uPD72103 HDLC/Frame Relay Controller (QFP80)
18643A.7 M27C1001 128k x8 EPROM (DIP32, labelled 'EPR-18643A')
315-5751 Lattice GAL16V8B-25LP PAL (DIP20)
315-5752 Lattice GAL16V8B-25LP PAL (DIP20)
315-5753A ICT PEEL18CV8P-15 PAL (DIP20)
315-5547A AMI 18CV8PC-25 PAL (DIP20)
Board:
837-11615 Virtua On
837-11615-02 Virtua On
Board:
837-11615 Virtua On
837-11615-02 Virtua On
EEPROM:
18643.7 Virtua On
18643A.7 Virtua On
EEPROM:
18643.7 Virtua On
18643A.7 Virtua On
@ -146,21 +146,21 @@ Sega PC BD MODEL2 C-CRX COMMUNICATION 837-12839
| CN3 |-------------------| |
|-------------------------------------------------------------------------------------------|
Setup:
Z80 Zilog Z0840008PSC Z80 CPU (DIP40)
MB84256A Fujitsu MB84256A-70LL 32k x8 SRAM (SDIP28)
uPD72103A NEC uPD72103 HDLC/Frame Relay Controller (QFP80)
18643A.7 M27C1001 128k x8 EPROM (DIP32, labelled 'EPR-18643A')
315-5751 Lattice GAL16V8B-25LP PAL (DIP20)
315-5752 Lattice GAL16V8B-25LP PAL (DIP20)
315-5753A ICT PEEL18CV8P-15 PAL (DIP20)
315-5547A AMI 18CV8PC-25 PAL (DIP20)
Setup:
Z80 Zilog Z0840008PSC Z80 CPU (DIP40)
MB84256A Fujitsu MB84256A-70LL 32k x8 SRAM (SDIP28)
uPD72103A NEC uPD72103 HDLC/Frame Relay Controller (QFP80)
18643A.7 M27C1001 128k x8 EPROM (DIP32, labelled 'EPR-18643A')
315-5751 Lattice GAL16V8B-25LP PAL (DIP20)
315-5752 Lattice GAL16V8B-25LP PAL (DIP20)
315-5753A ICT PEEL18CV8P-15 PAL (DIP20)
315-5547A AMI 18CV8PC-25 PAL (DIP20)
Board:
837-12839 Sega Touring Car Championship
Board:
837-12839 Sega Touring Car Championship
EEPROM:
18643A.7 Sega Touring Car Championship
EEPROM:
18643A.7 Sega Touring Car Championship
*/
#include "machine/m2comm.h"
@ -296,7 +296,7 @@ WRITE8_MEMBER(m2comm_device::cn_w)
m_linkalive = 0x00;
m_linkcount = 0x00;
m_linktimer = 0x04; //0x00E8; // 58 fps * 4s
comm_tick();
}
#endif
@ -324,7 +324,7 @@ void m2comm_device::check_vint_irq()
void m2comm_device::set_linktype(UINT16 linktype)
{
m_linktype = linktype;
switch (m_linktype)
{
case 16726:
@ -347,7 +347,7 @@ void m2comm_device::comm_tick()
void m2comm_device::comm_tick_16726()
{
if (m_linkenable == 0x01)
if (m_linkenable == 0x01)
{
m_zfg ^= 1;
@ -369,21 +369,21 @@ void m2comm_device::comm_tick_16726()
m_shared[0] = 0x00;
m_shared[2] = 0xff;
m_shared[3] = 0xff;
// check rx socket
if (!m_line_rx.is_open())
{
printf("M2COMM: listen on %s\n", m_localhost);
m_line_rx.open(m_localhost);
}
// check tx socket
if (!m_line_tx.is_open())
{
printf("M2COMM: connect to %s\n", m_remotehost);
m_line_tx.open(m_remotehost);
}
// if both sockets are there check ring
if ((m_line_rx.is_open()) && (m_line_tx.is_open()))
{
@ -416,7 +416,7 @@ void m2comm_device::comm_tick_16726()
m_line_tx.write(m_buffer, dataSize);
}
}
// 0xFE - link size
else if (idx == 0xfe)
{
@ -427,11 +427,11 @@ void m2comm_device::comm_tick_16726()
// forward message
m_line_tx.write(m_buffer, dataSize);
}
// consider it done
printf("M2COMM: link established - id %02x of %02x\n", m_linkid, m_linkcount);
m_linkalive = 0x01;
// write to shared mem
m_shared[0] = 0x01;
m_shared[2] = m_linkid;
@ -449,13 +449,13 @@ void m2comm_device::comm_tick_16726()
}
printf("M2COMM: droped a message...\n");
}
if (m_linkalive == 0x00)
recv = m_line_rx.read(m_buffer, dataSize);
else
recv = 0;
}
// if we are master and link is not yet established
if (isMaster && (m_linkalive == 0x00))
{
@ -493,7 +493,7 @@ void m2comm_device::comm_tick_16726()
}
}
}
}
}
// update "ring buffer" if link established
if (m_linkalive == 0x01)
@ -522,7 +522,7 @@ void m2comm_device::comm_tick_16726()
for (int j = 0x00 ; j < frameSize ; j++)
{
m_shared[frameOffset2 + j] = m_shared[frameOffset1 + j];
}
}
}
slotDest -= m_linkcount;
}
@ -574,7 +574,7 @@ void m2comm_device::comm_tick_16726()
}
m_line_tx.write(m_buffer, dataSize);
// master sends some additional status bytes
// master sends some additional status bytes
if (isMaster){
m_buffer[0] = 0xF0;
for (int j = 0x00 ; j < frameSize ; j++)
@ -589,9 +589,9 @@ void m2comm_device::comm_tick_16726()
m_line_tx.write(m_buffer, dataSize);
}
}
// clear 03
//TODO:m_shared[3] = 0x00;
}
}
}
#endif

18
src/mame/machine/m2comm.h
View File

@ -11,7 +11,7 @@
#define MCFG_M2COMM_ADD(_tag ) \
MCFG_DEVICE_ADD(_tag, M2COMM, 0)
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
@ -45,7 +45,7 @@ public:
DECLARE_READ8_MEMBER(fg_r);
DECLARE_WRITE8_MEMBER(fg_w);
// IRQ logic - 5 = VINT, 7 = DLC
// IRQ logic - 5 = VINT, 7 = DLC
void check_vint_irq();
#ifdef __M2COMM_SIMULATION__
void set_linktype(UINT16 linktype);
@ -58,16 +58,16 @@ protected:
private:
UINT8 m_shared[0x4000]; // 16k shared memory
UINT8 m_zfg; // z80 flip gate? purpose unknown, bit0 is stored
UINT8 m_cn; // bit0 is used to enable/disable the comm board
UINT8 m_fg; // flip gate? purpose unknown, bit0 is stored, bit7 is connected to ZFG bit 0
UINT8 m_zfg; // z80 flip gate? purpose unknown, bit0 is stored
UINT8 m_cn; // bit0 is used to enable/disable the comm board
UINT8 m_fg; // flip gate? purpose unknown, bit0 is stored, bit7 is connected to ZFG bit 0
emu_file m_line_rx; // rx line - can be either differential, simple serial or toslink
emu_file m_line_tx; // tx line - is differential, simple serial and toslink
char m_localhost[256];
char m_remotehost[256];
UINT8 m_buffer[0x4000];
#ifdef __M2COMM_SIMULATION__
UINT8 m_linkenable;
UINT16 m_linktimer;
@ -76,9 +76,9 @@ private:
UINT8 m_linkcount;
UINT16 m_linktype;
void comm_tick();
void comm_tick_16726();
#endif
};

6
src/mame/machine/n64.c
View File

@ -27,7 +27,7 @@ n64_periphs::n64_periphs(const machine_config &mconfig, const char *tag, device_
, dd_present(false)
, disk_present(false)
, cart_present(false)
{
{
for (INT32 i = 0; i < 256; i++)
{
m_gamma_table[i] = sqrt((float)(i << 6));
@ -976,7 +976,7 @@ WRITE32_MEMBER( n64_periphs::dp_reg_w )
if(status & DP_STATUS_START_VALID)
{
state->m_rdp->set_status(status & ~DP_STATUS_START_VALID);
state->m_rdp->set_current(state->m_rdp->get_start());
state->m_rdp->set_current(state->m_rdp->get_start());
state->m_rdp->set_end(data & ~ 7);
g_profiler.start(PROFILER_USER1);
state->m_rdp->process_command_list();
@ -989,7 +989,7 @@ WRITE32_MEMBER( n64_periphs::dp_reg_w )
g_profiler.start(PROFILER_USER1);
state->m_rdp->process_command_list();
g_profiler.stop();
break;
break;
}
case 0x0c/4: // DP_STATUS_REG

132
src/mame/machine/pgmcrypt.c
View File

@ -1573,93 +1573,93 @@ void fruitpar_decrypt(running_machine &machine)
}
static UINT8 amazonia_tab[0x100] = {
0x86, 0x00, 0xd2, 0x6b, 0x78, 0x79, 0xbc, 0x80, 0xc6, 0x8e, 0x9b, 0xd8, 0x3a, 0x52, 0x09, 0x15,
0x05, 0x57, 0x7a, 0x1f, 0x2f, 0x08, 0x47, 0xa0, 0x44, 0x4c, 0xf7, 0xbe, 0x3d, 0x59, 0xd1, 0x18,
0xac, 0xd5, 0xa0, 0x03, 0x2c, 0x34, 0xc6, 0x06, 0x08, 0x4e, 0x84, 0x94, 0x2b, 0x3f, 0x88, 0x08,
0x48, 0x84, 0xb8, 0xe6, 0x4a, 0x53, 0x3e, 0x51, 0xfe, 0x3b, 0xd4, 0xc8, 0xff, 0xfd, 0x52, 0x25,
0xe2, 0xa9, 0x75, 0xd7, 0xa3, 0xfc, 0xf1, 0x5f, 0x50, 0xfa, 0xba, 0x09, 0xf4, 0xc8, 0x90, 0xed,
0xc6, 0xcc, 0xc9, 0x25, 0x93, 0x07, 0x63, 0x50, 0x69, 0xb2, 0x4a, 0x47, 0x85, 0x18, 0xe6, 0x1f,
0x7f, 0xb3, 0xe8, 0x5f, 0xb4, 0x8a, 0x56, 0x83, 0xf4, 0xca, 0xd5, 0xb1, 0x6d, 0xa3, 0x37, 0xba,
0xd7, 0x66, 0x45, 0x54, 0xe2, 0xdc, 0xce, 0x96, 0xdc, 0xe9, 0xf0, 0xb5, 0xa7, 0x62, 0xa5, 0xfd,
0xdb, 0x2b, 0x92, 0x13, 0x37, 0x95, 0x0c, 0x69, 0x4d, 0xf7, 0x6c, 0x02, 0x6e, 0x8a, 0x95, 0x68,
0xd4, 0x8a, 0xc3, 0xea, 0x0f, 0x8b, 0x96, 0x1b, 0xb1, 0x19, 0x5e, 0x88, 0x3d, 0x94, 0xa9, 0xb9,
0x4e, 0x4a, 0x0a, 0x6a, 0x04, 0xd5, 0x2c, 0x0b, 0xb4, 0xb7, 0x18, 0x75, 0xcf, 0x35, 0xc3, 0xef,
0x13, 0x71, 0xdb, 0x61, 0xf2, 0xcb, 0xd3, 0xd7, 0x3f, 0x79, 0x2d, 0x39, 0x20, 0x65, 0x07, 0x49,
0x30, 0x47, 0xe9, 0xdd, 0xf3, 0x03, 0xce, 0x5f, 0x7f, 0x45, 0x70, 0x82, 0x69, 0x5a, 0xd9, 0x46,
0xee, 0x52, 0x27, 0x2f, 0x63, 0x54, 0x9f, 0xc1, 0xde, 0x41, 0xf5, 0x40, 0x26, 0x8d, 0xda, 0xa6,
0xd9, 0x5a, 0xc7, 0xe4, 0xdc, 0xd6, 0x09, 0x5e, 0x08, 0xd6, 0x0d, 0xa1, 0x12, 0xb3, 0xee, 0x67,
0xbb, 0x65, 0x3c, 0xcd, 0x3a, 0xdf, 0x0f, 0xd3, 0xe6, 0xaa, 0x4d, 0x14, 0x28, 0xc5, 0x38, 0xc8
0x86, 0x00, 0xd2, 0x6b, 0x78, 0x79, 0xbc, 0x80, 0xc6, 0x8e, 0x9b, 0xd8, 0x3a, 0x52, 0x09, 0x15,
0x05, 0x57, 0x7a, 0x1f, 0x2f, 0x08, 0x47, 0xa0, 0x44, 0x4c, 0xf7, 0xbe, 0x3d, 0x59, 0xd1, 0x18,
0xac, 0xd5, 0xa0, 0x03, 0x2c, 0x34, 0xc6, 0x06, 0x08, 0x4e, 0x84, 0x94, 0x2b, 0x3f, 0x88, 0x08,
0x48, 0x84, 0xb8, 0xe6, 0x4a, 0x53, 0x3e, 0x51, 0xfe, 0x3b, 0xd4, 0xc8, 0xff, 0xfd, 0x52, 0x25,
0xe2, 0xa9, 0x75, 0xd7, 0xa3, 0xfc, 0xf1, 0x5f, 0x50, 0xfa, 0xba, 0x09, 0xf4, 0xc8, 0x90, 0xed,
0xc6, 0xcc, 0xc9, 0x25, 0x93, 0x07, 0x63, 0x50, 0x69, 0xb2, 0x4a, 0x47, 0x85, 0x18, 0xe6, 0x1f,
0x7f, 0xb3, 0xe8, 0x5f, 0xb4, 0x8a, 0x56, 0x83, 0xf4, 0xca, 0xd5, 0xb1, 0x6d, 0xa3, 0x37, 0xba,
0xd7, 0x66, 0x45, 0x54, 0xe2, 0xdc, 0xce, 0x96, 0xdc, 0xe9, 0xf0, 0xb5, 0xa7, 0x62, 0xa5, 0xfd,
0xdb, 0x2b, 0x92, 0x13, 0x37, 0x95, 0x0c, 0x69, 0x4d, 0xf7, 0x6c, 0x02, 0x6e, 0x8a, 0x95, 0x68,
0xd4, 0x8a, 0xc3, 0xea, 0x0f, 0x8b, 0x96, 0x1b, 0xb1, 0x19, 0x5e, 0x88, 0x3d, 0x94, 0xa9, 0xb9,
0x4e, 0x4a, 0x0a, 0x6a, 0x04, 0xd5, 0x2c, 0x0b, 0xb4, 0xb7, 0x18, 0x75, 0xcf, 0x35, 0xc3, 0xef,
0x13, 0x71, 0xdb, 0x61, 0xf2, 0xcb, 0xd3, 0xd7, 0x3f, 0x79, 0x2d, 0x39, 0x20, 0x65, 0x07, 0x49,
0x30, 0x47, 0xe9, 0xdd, 0xf3, 0x03, 0xce, 0x5f, 0x7f, 0x45, 0x70, 0x82, 0x69, 0x5a, 0xd9, 0x46,
0xee, 0x52, 0x27, 0x2f, 0x63, 0x54, 0x9f, 0xc1, 0xde, 0x41, 0xf5, 0x40, 0x26, 0x8d, 0xda, 0xa6,
0xd9, 0x5a, 0xc7, 0xe4, 0xdc, 0xd6, 0x09, 0x5e, 0x08, 0xd6, 0x0d, 0xa1, 0x12, 0xb3, 0xee, 0x67,
0xbb, 0x65, 0x3c, 0xcd, 0x3a, 0xdf, 0x0f, 0xd3, 0xe6, 0xaa, 0x4d, 0x14, 0x28, 0xc5, 0x38, 0xc8
};
void amazonia_decrypt(running_machine &machine)
{
int i;
UINT16 *src = (UINT16 *) machine.root_device().memregion("user1")->base();
int i;
UINT16 *src = (UINT16 *) machine.root_device().memregion("user1")->base();
int rom_size = 0x80000;
int rom_size = 0x80000;
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
for(i=0; i<rom_size/2; i++) {
UINT16 x = src[i];
IGS27_CRYPT1
IGS27_CRYPT2_ALT
IGS27_CRYPT3
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8
IGS27_CRYPT1
IGS27_CRYPT2_ALT
IGS27_CRYPT3
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT
IGS27_CRYPT7
IGS27_CRYPT8
x ^= amazonia_tab[(i >> 1) & 0xff] << 8;
x ^= amazonia_tab[(i >> 1) & 0xff] << 8;
src[i] = x;
}
src[i] = x;
}
}
// not 100% verified
static const UINT8 amazoni2_tab[0x100] = {
0x49, 0x47, 0x53, 0x30, 0x30, 0x37, 0x37, 0x52, 0x44, 0x34, 0x30, 0x32, 0x31, 0x30, 0x31, 0x36,
0xed, 0x3f, 0x77, 0xd0, 0xc4, 0x72, 0x77, 0xe1, 0x35, 0x15, 0x10, 0xc6, 0x1b, 0xee, 0x25, 0x4a,
0x0d, 0x06, 0x37, 0x19, 0xfa, 0xf9, 0x29, 0xb0, 0x03, 0x7e, 0x32, 0x83, 0x99, 0x32, 0x23, 0x6e,
0xd8, 0xa9, 0xdb, 0x5f, 0x23, 0xb7, 0x08, 0x41, 0x00, 0xfb, 0x20, 0x2b, 0x36, 0xae, 0x9f, 0xc9,
0x24, 0xaa, 0x82, 0x0b, 0x64, 0xbe, 0x03, 0x0d, 0xa2, 0x31, 0x97, 0x47, 0xb6, 0x94, 0x26, 0xf6,
0x09, 0xcd, 0x8a, 0xca, 0x26, 0x61, 0x4a, 0xd1, 0x9f, 0x01, 0x98, 0xa3, 0x23, 0x58, 0x88, 0xcf,
0xdd, 0x14, 0x93, 0x86, 0x0f, 0x33, 0x4c, 0x86, 0xef, 0x8f, 0x61, 0x4a, 0xc2, 0xad, 0xd5, 0x70,
0x37, 0xc2, 0x7b, 0x6a, 0x06, 0x07, 0xb7, 0x69, 0xc9, 0x3f, 0x71, 0x87, 0x1a, 0x85, 0x5a, 0x33,
0xee, 0x5b, 0x63, 0xe2, 0x32, 0xf0, 0x7a, 0xf4, 0xa4, 0xb2, 0x87, 0xe4, 0xf3, 0x14, 0xa7, 0xb4,
0x1a, 0xa1, 0xa8, 0x98, 0xf9, 0x42, 0xc5, 0xe1, 0x36, 0xcc, 0xa3, 0x2d, 0x54, 0xcd, 0x8b, 0xcd,
0x11, 0x98, 0xe9, 0x77, 0x05, 0x8e, 0x06, 0x2d, 0x78, 0xb0, 0x02, 0x6d, 0x83, 0x62, 0x15, 0x9a,
0x6b, 0x82, 0x07, 0xaa, 0x3a, 0xa9, 0xed, 0x12, 0x9f, 0xc0, 0x25, 0xee, 0x08, 0xc7, 0x94, 0x75,
0xfd, 0xe2, 0x1f, 0x9d, 0xc0, 0xa5, 0x68, 0x0a, 0x23, 0xa1, 0xca, 0x3d, 0xa9, 0x2f, 0x97, 0xfa,
0xe0, 0x7c, 0x91, 0xfa, 0xfe, 0xd5, 0xa6, 0xd2, 0xbb, 0x34, 0xf1, 0x23, 0x6e, 0x0c, 0xed, 0x03,
0x6b, 0x52, 0xfb, 0xac, 0x9c, 0xcc, 0x17, 0x64, 0x5d, 0x9e, 0xd7, 0xac, 0x9e, 0x12, 0xa5, 0xac,
0x34, 0xa7, 0x3e, 0xde, 0x7f, 0x5d, 0x6a, 0xfa, 0x42, 0x40, 0xfd, 0x23, 0xbf, 0x33, 0x0e, 0x50
0x49, 0x47, 0x53, 0x30, 0x30, 0x37, 0x37, 0x52, 0x44, 0x34, 0x30, 0x32, 0x31, 0x30, 0x31, 0x36,
0xed, 0x3f, 0x77, 0xd0, 0xc4, 0x72, 0x77, 0xe1, 0x35, 0x15, 0x10, 0xc6, 0x1b, 0xee, 0x25, 0x4a,
0x0d, 0x06, 0x37, 0x19, 0xfa, 0xf9, 0x29, 0xb0, 0x03, 0x7e, 0x32, 0x83, 0x99, 0x32, 0x23, 0x6e,
0xd8, 0xa9, 0xdb, 0x5f, 0x23, 0xb7, 0x08, 0x41, 0x00, 0xfb, 0x20, 0x2b, 0x36, 0xae, 0x9f, 0xc9,
0x24, 0xaa, 0x82, 0x0b, 0x64, 0xbe, 0x03, 0x0d, 0xa2, 0x31, 0x97, 0x47, 0xb6, 0x94, 0x26, 0xf6,
0x09, 0xcd, 0x8a, 0xca, 0x26, 0x61, 0x4a, 0xd1, 0x9f, 0x01, 0x98, 0xa3, 0x23, 0x58, 0x88, 0xcf,
0xdd, 0x14, 0x93, 0x86, 0x0f, 0x33, 0x4c, 0x86, 0xef, 0x8f, 0x61, 0x4a, 0xc2, 0xad, 0xd5, 0x70,
0x37, 0xc2, 0x7b, 0x6a, 0x06, 0x07, 0xb7, 0x69, 0xc9, 0x3f, 0x71, 0x87, 0x1a, 0x85, 0x5a, 0x33,
0xee, 0x5b, 0x63, 0xe2, 0x32, 0xf0, 0x7a, 0xf4, 0xa4, 0xb2, 0x87, 0xe4, 0xf3, 0x14, 0xa7, 0xb4,
0x1a, 0xa1, 0xa8, 0x98, 0xf9, 0x42, 0xc5, 0xe1, 0x36, 0xcc, 0xa3, 0x2d, 0x54, 0xcd, 0x8b, 0xcd,
0x11, 0x98, 0xe9, 0x77, 0x05, 0x8e, 0x06, 0x2d, 0x78, 0xb0, 0x02, 0x6d, 0x83, 0x62, 0x15, 0x9a,
0x6b, 0x82, 0x07, 0xaa, 0x3a, 0xa9, 0xed, 0x12, 0x9f, 0xc0, 0x25, 0xee, 0x08, 0xc7, 0x94, 0x75,
0xfd, 0xe2, 0x1f, 0x9d, 0xc0, 0xa5, 0x68, 0x0a, 0x23, 0xa1, 0xca, 0x3d, 0xa9, 0x2f, 0x97, 0xfa,
0xe0, 0x7c, 0x91, 0xfa, 0xfe, 0xd5, 0xa6, 0xd2, 0xbb, 0x34, 0xf1, 0x23, 0x6e, 0x0c, 0xed, 0x03,
0x6b, 0x52, 0xfb, 0xac, 0x9c, 0xcc, 0x17, 0x64, 0x5d, 0x9e, 0xd7, 0xac, 0x9e, 0x12, 0xa5, 0xac,
0x34, 0xa7, 0x3e, 0xde, 0x7f, 0x5d, 0x6a, 0xfa, 0x42, 0x40, 0xfd, 0x23, 0xbf, 0x33, 0x0e, 0x50
};
void amazoni2_decrypt(running_machine &machine)
{
int i;
UINT16 *src = (UINT16 *) machine.root_device().memregion("user1")->base();
int i;
UINT16 *src = (UINT16 *) machine.root_device().memregion("user1")->base();
int rom_size = 0x80000;
int rom_size = 0x80000;
for(i=0; i<rom_size/2; i++)
{
UINT16 x = src[i];
for(i=0; i<rom_size/2; i++)
{
UINT16 x = src[i];
// should be correct
IGS27_CRYPT1
IGS27_CRYPT2_ALT
// IGS27_CRYPT3
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT // second half is junk, not sure...
IGS27_CRYPT7
IGS27_CRYPT8
// should be correct
IGS27_CRYPT1
IGS27_CRYPT2_ALT
// IGS27_CRYPT3
IGS27_CRYPT4
IGS27_CRYPT5
IGS27_CRYPT6_ALT // second half is junk, not sure...
IGS27_CRYPT7
IGS27_CRYPT8
x ^= amazoni2_tab[(i >> 1) & 0xff] << 8;
x ^= amazoni2_tab[(i >> 1) & 0xff] << 8;
src[i] = x;
}
src[i] = x;
}
}

6
src/mame/machine/scramble.c
View File

@ -686,9 +686,9 @@ DRIVER_INIT_MEMBER(scramble_state,newsin7a)
{
DRIVER_INIT_CALL(devilfsh); // decrypt
// UINT8 *ROM = memregion("maincpu")->base();
// ROM[0x0067] ^= 0x22; /* rst $00 - should be push hl - the NMI routine is corrupt in this set, but the IRQ routine bypasses it? intentional? */
// UINT8 *ROM = memregion("maincpu")->base();
// ROM[0x0067] ^= 0x22; /* rst $00 - should be push hl - the NMI routine is corrupt in this set, but the IRQ routine bypasses it? intentional? */
// attempts to access port at c20x instead of 820x in one location, mirror or bitrot?
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc200, 0xc20f, read8_delegate(FUNC(scramble_state::mars_ppi8255_1_r),this), write8_delegate(FUNC(scramble_state::mars_ppi8255_1_w),this));

2
src/mame/mess.lst
View File

@ -729,7 +729,7 @@ a4000tn
c65 // 1991 C65 / C64DX (Prototype, NTSC)
c64dx // 1991 C65 / C64DX (Prototype, German PAL)
mps1230 // 1988 Commodore MPS-1230 near-letter-quality dot matrix printer
mps1230 // 1988 Commodore MPS-1230 near-letter-quality dot matrix printer
// Epson
px4 // 1985 Epson PX-4

35
src/mame/video/galastrm.c
View File

@ -15,11 +15,10 @@ struct polyVert
galastrm_renderer::galastrm_renderer(galastrm_state& state)
: poly_manager<float, gs_poly_data, 2, 10000>(state.machine())
, m_state(state)
, m_screenbits(state.m_screen->width(), state.m_screen->height())
: poly_manager<float, gs_poly_data, 2, 10000>(state.machine())
, m_state(state)
, m_screenbits(state.m_screen->width(), state.m_screen->height())
{
}
@ -29,10 +28,10 @@ void galastrm_state::video_start()
{
m_spritelist = auto_alloc_array(machine(), struct gs_tempsprite, 0x4000);
m_poly = auto_alloc(machine(), galastrm_renderer(*this));
m_poly = auto_alloc(machine(), galastrm_renderer(*this));
m_screen->register_screen_bitmap(m_tmpbitmaps);
m_screen->register_screen_bitmap(m_poly->screenbits());
m_screen->register_screen_bitmap(m_tmpbitmaps);
m_screen->register_screen_bitmap(m_poly->screenbits());
}
@ -184,7 +183,7 @@ void galastrm_state::draw_sprites_pre(int x_offs, int y_offs)
m_sprite_ptr_pre++;
}
if (bad_chunks)
logerror("Sprite number %04x had %02x invalid chunks\n",tilenum,bad_chunks);
logerror("Sprite number %04x had %02x invalid chunks\n",tilenum,bad_chunks);
}
}
@ -216,11 +215,11 @@ void galastrm_state::draw_sprites(screen_device &screen, bitmap_ind16 &bitmap, c
void galastrm_renderer::tc0610_draw_scanline(INT32 scanline, const extent_t& extent, const gs_poly_data& object, int threadid)
{
UINT16 *framebuffer = &m_screenbits.pix16(scanline);
UINT16 *framebuffer = &m_screenbits.pix16(scanline);
const INT32 dudx = extent.param[0].dpdx;
const INT32 dvdx = extent.param[1].dpdx;
INT32 u = extent.param[0].start;
INT32 u = extent.param[0].start;
INT32 v = extent.param[1].start;
for (int x = extent.startx; x < extent.stopx; x++)
{
@ -406,11 +405,11 @@ void galastrm_renderer::tc0610_rotate_draw(bitmap_ind16 &srcbitmap, const rectan
vert[3].p[0] = (float)(lx - 1) * 65536.0f;
vert[3].p[1] = 0.0;
gs_poly_data& extra = object_data_alloc();
extra.texbase = &srcbitmap;
render_polygon<4>(clip, render_delegate(FUNC(galastrm_renderer::tc0610_draw_scanline), this), 2, vert);
wait();
gs_poly_data& extra = object_data_alloc();
extra.texbase = &srcbitmap;
render_polygon<4>(clip, render_delegate(FUNC(galastrm_renderer::tc0610_draw_scanline), this), 2, vert);
wait();
}
/**************************************************************
@ -530,10 +529,10 @@ UINT32 galastrm_state::screen_update_galastrm(screen_device &screen, bitmap_ind1
draw_sprites_pre(42-X_OFFSET, -571+Y_OFFSET);
draw_sprites(screen,m_tmpbitmaps,clip,primasks,1);
copybitmap_trans(bitmap, m_poly->screenbits(), 0,0, 0,0, cliprect, 0);
copybitmap_trans(bitmap, m_poly->screenbits(), 0,0, 0,0, cliprect, 0);
m_poly->screenbits().fill(0, clip);
m_poly->tc0610_rotate_draw(m_tmpbitmaps, cliprect);
m_poly->tc0610_rotate_draw(m_tmpbitmaps, cliprect);
priority_bitmap.fill(0, cliprect);
draw_sprites(screen,bitmap,cliprect,primasks,0);

2
src/mame/video/galaxian.c
View File

@ -999,7 +999,7 @@ void galaxian_state::jumpbug_draw_background(bitmap_rgb32 &bitmap, const rectang
bitmap.fill(m_background_enable ? rgb_t(0,0,0x56) : rgb_t::black, cliprect);
/* render stars same as galaxian but nothing in the status area */
/* update the star origin to the current frame */
stars_update_origin();

14
src/mame/video/hng64.c
View File

@ -168,19 +168,19 @@ void hng64_state::hng64_mark_tile_dirty( int tilemap, int tile_index )
{ \
UINT16 tilemapinfo = (m_videoregs[reg]>>shift)&0xffff; \
int tileno,pal, flip; \
\
\
tileno = m_videoram[tile_index+(offset/4)]; \
\
\
pal = (tileno&0xff000000)>>24; \
flip =(tileno&0x00c00000)>>22; \
\
\
if (tileno&0x200000) \
{ \
tileno = (tileno & m_videoregs[0x0b]) | m_videoregs[0x0c]; \
} \
\
\
tileno &= 0x1fffff; \
\
\
if (size==0) \
{ \
if (tilemapinfo&0x400) \
@ -1269,9 +1269,9 @@ void hng64_state::video_start()
m_additive_tilemap_debug = 0;
// Rasterizer creation
m_poly_renderer = auto_alloc(machine(), hng64_poly_renderer(*this));
m_poly_renderer = auto_alloc(machine(), hng64_poly_renderer(*this));
// 3d information
// 3d information
m_dl = auto_alloc_array(machine(), UINT16, 0x200/2);
polys.resize(1024*5);

186
src/mame/video/hng64_3d.c
View File

@ -10,12 +10,12 @@
// Polygon rasterizer interface
hng64_poly_renderer::hng64_poly_renderer(hng64_state& state)
: poly_manager<float, hng64_poly_data, 7, HNG64_MAX_POLYGONS>(state.machine())
, m_state(state)
, m_colorBuffer3d(state.m_screen->visible_area().width(), state.m_screen->visible_area().height())
: poly_manager<float, hng64_poly_data, 7, HNG64_MAX_POLYGONS>(state.machine())
, m_state(state)
, m_colorBuffer3d(state.m_screen->visible_area().width(), state.m_screen->visible_area().height())
{
const INT32 bufferSize = state.m_screen->visible_area().width() * state.m_screen->visible_area().height();
m_depthBuffer3d = auto_alloc_array(state.machine(), float, bufferSize);
const INT32 bufferSize = state.m_screen->visible_area().width() * state.m_screen->visible_area().height();
m_depthBuffer3d = auto_alloc_array(state.machine(), float, bufferSize);
}
@ -964,7 +964,7 @@ void hng64_state::hng64_command3d(const UINT16* packet)
m_poly_renderer->drawShaded(&polys[i]);
}
}
m_poly_renderer->wait();
m_poly_renderer->wait();
}
void hng64_state::clear3d()
@ -976,11 +976,11 @@ void hng64_state::clear3d()
// Reset the buffers...
for (i = 0; i < (visarea.max_x)*(visarea.max_y); i++)
{
m_poly_renderer->depthBuffer3d()[i] = 100.0f;
m_poly_renderer->depthBuffer3d()[i] = 100.0f;
}
// Clear the 3d rasterizer buffer
m_poly_renderer->colorBuffer3d().fill(0x00000000, m_screen->visible_area());
// Clear the 3d rasterizer buffer
m_poly_renderer->colorBuffer3d().fill(0x00000000, m_screen->visible_area());
// Set some matrices to the identity...
setIdentity(m_projectionMatrix);
@ -1169,11 +1169,11 @@ void hng64_state::Intersect(struct polyVert *input0, struct polyVert *input1, st
void hng64_state::performFrustumClip(struct polygon *p)
{
polyVert *v0;
polyVert *v0;
polyVert *v1;
polyVert *tv;
polygon temp;
polygon temp;
temp.n = 0;
// Skip near and far clipping planes ?
@ -1219,42 +1219,42 @@ void hng64_state::performFrustumClip(struct polygon *p)
void hng64_poly_renderer::render_scanline(INT32 scanline, const extent_t& extent, const hng64_poly_data& renderData, int threadid)
{
// Pull the parameters out of the extent structure
float z = extent.param[0].start;
float w = extent.param[1].start;
// Pull the parameters out of the extent structure
float z = extent.param[0].start;
float w = extent.param[1].start;
float lightR = extent.param[2].start;
float lightG = extent.param[3].start;
float lightB = extent.param[4].start;
float s = extent.param[5].start;
float t = extent.param[6].start;
const float dz = extent.param[0].dpdx;
const float dw = extent.param[1].dpdx;
float t = extent.param[6].start;
const float dz = extent.param[0].dpdx;
const float dw = extent.param[1].dpdx;
const float dlightR = extent.param[2].dpdx;
const float dlightG = extent.param[3].dpdx;
const float dlightB = extent.param[4].dpdx;
const float ds = extent.param[5].dpdx;
const float dt = extent.param[6].dpdx;
// Pointers to the pixel buffers
UINT32* colorBuffer = &m_colorBuffer3d.pix32(scanline, extent.startx);
float* depthBuffer = &m_depthBuffer3d[(scanline * m_state.m_screen->visible_area().width()) + extent.startx];
const float dt = extent.param[6].dpdx;
const UINT8 *textureOffset = &m_state.m_texturerom[renderData.texIndex * 1024 * 1024];
// Step over each pixel in the horizontal span
for(int x = extent.startx; x < extent.stopx; x++)
{
if (z < *depthBuffer)
{
// Multiply back through by w for everything that was interpolated perspective-correctly
const float sCorrect = s / w;
const float tCorrect = t / w;
const float rCorrect = lightR / w;
const float gCorrect = lightG / w;
const float bCorrect = lightB / w;
if ((renderData.debugColor & 0xff000000) == 0x01000000)
// Pointers to the pixel buffers
UINT32* colorBuffer = &m_colorBuffer3d.pix32(scanline, extent.startx);
float* depthBuffer = &m_depthBuffer3d[(scanline * m_state.m_screen->visible_area().width()) + extent.startx];
const UINT8 *textureOffset = &m_state.m_texturerom[renderData.texIndex * 1024 * 1024];
// Step over each pixel in the horizontal span
for(int x = extent.startx; x < extent.stopx; x++)
{
if (z < *depthBuffer)
{
// Multiply back through by w for everything that was interpolated perspective-correctly
const float sCorrect = s / w;
const float tCorrect = t / w;
const float rCorrect = lightR / w;
const float gCorrect = lightG / w;
const float bCorrect = lightB / w;
if ((renderData.debugColor & 0xff000000) == 0x01000000)
{
// ST color mode
*colorBuffer = rgb_t(255, (UINT8)(sCorrect*255.0f), (UINT8)(tCorrect*255.0f), (UINT8)(0));
@ -1333,29 +1333,29 @@ void hng64_poly_renderer::render_scanline(INT32 scanline, const extent_t& extent
color = rgb_t(255, (UINT8)red, (UINT8)green, (UINT8)blue);
*colorBuffer = color;
*depthBuffer = z;
*depthBuffer = z;
}
}
}
}
z += dz;
w += dw;
lightR += dlightR;
z += dz;
w += dw;
lightR += dlightR;
lightG += dlightG;
lightB += dlightB;
s += ds;
t += dt;
colorBuffer++;
depthBuffer++;
}
t += dt;
colorBuffer++;
depthBuffer++;
}
}
void hng64_poly_renderer::drawShaded(struct polygon *p)
{
// Polygon information for the rasterizer
hng64_poly_data rOptions;
rOptions.texType = p->texType;
// Polygon information for the rasterizer
hng64_poly_data rOptions;
rOptions.texType = p->texType;
rOptions.texIndex = p->texIndex;
rOptions.palOffset = p->palOffset;
rOptions.palPageSize = p->palPageSize;
@ -1363,7 +1363,7 @@ void hng64_poly_renderer::drawShaded(struct polygon *p)
rOptions.texPageSmall = p->texPageSmall;
rOptions.texPageHorizOffset = p->texPageHorizOffset;
rOptions.texPageVertOffset = p->texPageVertOffset;
// The perspective-correct texture divide...
// NOTE: There is a very good chance the HNG64 hardware does not do perspective-correct texture-mapping - explore
for (int j = 0; j < p->n; j++)
@ -1376,50 +1376,50 @@ void hng64_poly_renderer::drawShaded(struct polygon *p)
p->vert[j].texCoords[1] = p->vert[j].texCoords[1] * p->vert[j].clipCoords[3];
}
// Rasterize the triangles
// Rasterize the triangles
for (int j = 1; j < p->n-1; j++)
{
// Build some MAME rasterizer vertices from the hng64 vertices
vertex_t pVert[3];
// Build some MAME rasterizer vertices from the hng64 vertices
vertex_t pVert[3];
const polyVert& pv0 = p->vert[0];
pVert[0].x = pv0.clipCoords[0];
pVert[0].y = pv0.clipCoords[1];
pVert[0].p[0] = pv0.clipCoords[2];
pVert[0].p[1] = pv0.clipCoords[3];
pVert[0].p[2] = pv0.light[0];
pVert[0].p[3] = pv0.light[1];
pVert[0].p[4] = pv0.light[2];
pVert[0].p[5] = pv0.texCoords[0];
pVert[0].p[6] = pv0.texCoords[1];
const polyVert& pvj = p->vert[j];
pVert[1].x = pvj.clipCoords[0];
pVert[1].y = pvj.clipCoords[1];
pVert[1].p[0] = pvj.clipCoords[2];
pVert[1].p[1] = pvj.clipCoords[3];
pVert[1].p[2] = pvj.light[0];
pVert[1].p[3] = pvj.light[1];
pVert[1].p[4] = pvj.light[2];
pVert[1].p[5] = pvj.texCoords[0];
pVert[1].p[6] = pvj.texCoords[1];
const polyVert& pv0 = p->vert[0];
pVert[0].x = pv0.clipCoords[0];
pVert[0].y = pv0.clipCoords[1];
pVert[0].p[0] = pv0.clipCoords[2];
pVert[0].p[1] = pv0.clipCoords[3];
pVert[0].p[2] = pv0.light[0];
pVert[0].p[3] = pv0.light[1];
pVert[0].p[4] = pv0.light[2];
pVert[0].p[5] = pv0.texCoords[0];
pVert[0].p[6] = pv0.texCoords[1];
const polyVert& pvjp1 = p->vert[j+1];
pVert[2].x = pvjp1.clipCoords[0];
pVert[2].y = pvjp1.clipCoords[1];
pVert[2].p[0] = pvjp1.clipCoords[2];
pVert[2].p[1] = pvjp1.clipCoords[3];
pVert[2].p[2] = pvjp1.light[0];
pVert[2].p[3] = pvjp1.light[1];
pVert[2].p[4] = pvjp1.light[2];
pVert[2].p[5] = pvjp1.texCoords[0];
pVert[2].p[6] = pvjp1.texCoords[1];
const polyVert& pvj = p->vert[j];
pVert[1].x = pvj.clipCoords[0];
pVert[1].y = pvj.clipCoords[1];
pVert[1].p[0] = pvj.clipCoords[2];
pVert[1].p[1] = pvj.clipCoords[3];
pVert[1].p[2] = pvj.light[0];
pVert[1].p[3] = pvj.light[1];
pVert[1].p[4] = pvj.light[2];
pVert[1].p[5] = pvj.texCoords[0];
pVert[1].p[6] = pvj.texCoords[1];
// Pass the render data into the rasterizer
hng64_poly_data& renderData = object_data_alloc();
renderData = rOptions;
const rectangle& visibleArea = m_state.m_screen->visible_area();
render_triangle(visibleArea, render_delegate(FUNC(hng64_poly_renderer::render_scanline), this), 7, pVert[0], pVert[1], pVert[2]);
const polyVert& pvjp1 = p->vert[j+1];
pVert[2].x = pvjp1.clipCoords[0];
pVert[2].y = pvjp1.clipCoords[1];
pVert[2].p[0] = pvjp1.clipCoords[2];
pVert[2].p[1] = pvjp1.clipCoords[3];
pVert[2].p[2] = pvjp1.light[0];
pVert[2].p[3] = pvjp1.light[1];
pVert[2].p[4] = pvjp1.light[2];
pVert[2].p[5] = pvjp1.texCoords[0];
pVert[2].p[6] = pvjp1.texCoords[1];
// Pass the render data into the rasterizer
hng64_poly_data& renderData = object_data_alloc();
renderData = rOptions;
const rectangle& visibleArea = m_state.m_screen->visible_area();
render_triangle(visibleArea, render_delegate(FUNC(hng64_poly_renderer::render_scanline), this), 7, pVert[0], pVert[1], pVert[2]);
}
}

28
src/mame/video/igs017_igs031.c
View File

@ -9,15 +9,15 @@ what's the difference between IGS017 and IGS031? encryption?
all the known IGS017 / IGS031 games use the following memory map, is the IGS017 / IGS031 providing the interface to the 8255, or is it coincidence?
AM_RANGE( 0x1000, 0x17ff ) AM_RAM AM_SHARE("spriteram")
AM_RANGE( 0x1800, 0x1bff ) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
AM_RANGE( 0x1c00, 0x1fff ) AM_RAM
AM_RANGE( 0x2010, 0x2013 ) AM_DEVREAD("ppi8255", i8255_device, read)
AM_RANGE( 0x2012, 0x2012 ) AM_WRITE(video_disable_w )
AM_RANGE( 0x2014, 0x2014 ) AM_WRITE(nmi_enable_w )
AM_RANGE( 0x2015, 0x2015 ) AM_WRITE(irq_enable_w )
AM_RANGE( 0x4000, 0x5fff ) AM_RAM_WRITE(fg_w ) AM_SHARE("fg_videoram")
AM_RANGE( 0x6000, 0x7fff ) AM_RAM_WRITE(bg_w ) AM_SHARE("bg_videoram")
AM_RANGE( 0x1000, 0x17ff ) AM_RAM AM_SHARE("spriteram")
AM_RANGE( 0x1800, 0x1bff ) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
AM_RANGE( 0x1c00, 0x1fff ) AM_RAM
AM_RANGE( 0x2010, 0x2013 ) AM_DEVREAD("ppi8255", i8255_device, read)
AM_RANGE( 0x2012, 0x2012 ) AM_WRITE(video_disable_w )
AM_RANGE( 0x2014, 0x2014 ) AM_WRITE(nmi_enable_w )
AM_RANGE( 0x2015, 0x2015 ) AM_WRITE(irq_enable_w )
AM_RANGE( 0x4000, 0x5fff ) AM_RAM_WRITE(fg_w ) AM_SHARE("fg_videoram")
AM_RANGE( 0x6000, 0x7fff ) AM_RAM_WRITE(bg_w ) AM_SHARE("bg_videoram")
*/
@ -30,7 +30,7 @@ all the known IGS017 / IGS031 games use the following memory map, is the IGS017
DEVICE_ADDRESS_MAP_START( map, 8, igs017_igs031_device )
AM_RANGE( 0x1000, 0x17ff ) AM_RAM AM_SHARE("spriteram")
// AM_RANGE( 0x1800, 0x1bff ) AM_RAM //_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
// AM_RANGE( 0x1800, 0x1bff ) AM_RAM //_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
AM_RANGE( 0x1800, 0x1bff ) AM_RAM_WRITE(palram_w) AM_SHARE("palram")
AM_RANGE( 0x1c00, 0x1fff ) AM_RAM
@ -69,7 +69,7 @@ static const gfx_layout layout_8x8x4 =
GFXDECODE_MEMBER( igs017_igs031_device::gfxinfo )
GFXDECODE_DEVICE( "^tilemaps", 0, layout_8x8x4, 0, 16 )
// GFXDECODE_DEVICE( DEVICE_SELF, 0, spritelayout, 0, 0x1000 )
// GFXDECODE_DEVICE( DEVICE_SELF, 0, spritelayout, 0, 0x1000 )
GFXDECODE_END
@ -127,7 +127,7 @@ void igs017_igs031_device::device_start()
m_debug_addr = 0;
m_debug_width = 512;
}
void igs017_igs031_device::video_start()
@ -144,7 +144,7 @@ void igs017_igs031_device::video_start()
for (i = 0; i < size ; i++)
{
rom[i] = BITSWAP8(rom[i], 0, 1, 2, 3, 4, 5, 6, 7);
// rom[i^1] = BITSWAP8(rom[i], 0, 1, 2, 3, 4, 5, 6, 7);
// rom[i^1] = BITSWAP8(rom[i], 0, 1, 2, 3, 4, 5, 6, 7);
}
}
}
@ -446,5 +446,3 @@ WRITE8_MEMBER(igs017_igs031_device::irq_enable_w)
if (data & (~1))
logerror("%s: irq_enable = %02x\n", machine().describe_context(), data);
}

2
src/mame/video/igs017_igs031.h
View File

@ -59,7 +59,7 @@ public:
int m_nmi_enable;
int m_irq_enable;
DECLARE_WRITE8_MEMBER(palram_w);
DECLARE_READ8_MEMBER(i8255_r);

2
src/mame/video/k057714.c
View File

@ -343,7 +343,7 @@ int k057714_device::draw(screen_device &screen, bitmap_ind16 &bitmap, const rect
// UINT16 pix3 = vram16[fbaddr3 ^ NATIVE_ENDIAN_VALUE_LE_BE(1,0)];
d[i] = 0;
if (pix2 & 0x8000)
{
d[i] = pix2 & 0x7fff;

48
src/mame/video/midzeus.c
View File

@ -66,16 +66,16 @@ struct mz_poly_extra_data
class midzeus_renderer : public poly_manager<float, mz_poly_extra_data, 4, 10000>
{
public:
midzeus_renderer(midzeus_state &state);
void render_poly(INT32 scanline, const extent_t& extent, const mz_poly_extra_data& object, int threadid);
void render_poly_solid_fixedz(INT32 scanline, const extent_t& extent, const mz_poly_extra_data& object, int threadid);
void zeus_draw_quad(int long_fmt, const UINT32 *databuffer, UINT32 texdata, int logit);
void zeus_draw_debug_quad(const rectangle& rect, const vertex_t* vert);
midzeus_renderer(midzeus_state &state);
void render_poly(INT32 scanline, const extent_t& extent, const mz_poly_extra_data& object, int threadid);
void render_poly_solid_fixedz(INT32 scanline, const extent_t& extent, const mz_poly_extra_data& object, int threadid);
void zeus_draw_quad(int long_fmt, const UINT32 *databuffer, UINT32 texdata, int logit);
void zeus_draw_debug_quad(const rectangle& rect, const vertex_t* vert);
private:
midzeus_state& m_state;
midzeus_state& m_state;
};
typedef midzeus_renderer::vertex_t poly_vertex;
@ -272,8 +272,8 @@ INLINE UINT8 get_texel_alt_8bit(const void *base, int y, int x, int width)
*************************************/
midzeus_renderer::midzeus_renderer(midzeus_state &state)
: poly_manager<float, mz_poly_extra_data, 4, 10000>(state.machine()),
m_state(state)
: poly_manager<float, mz_poly_extra_data, 4, 10000>(state.machine()),
m_state(state)
{}
VIDEO_START_MEMBER(midzeus_state,midzeus)
@ -289,8 +289,8 @@ VIDEO_START_MEMBER(midzeus_state,midzeus)
m_palette->set_pen_color(i, pal5bit(i >> 10), pal5bit(i >> 5), pal5bit(i >> 0));
/* initialize polygon engine */
poly = auto_alloc(machine(), midzeus_renderer(*this));
poly = auto_alloc(machine(), midzeus_renderer(*this));
/* we need to cleanup on exit */
machine().add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(midzeus_state::exit_handler), this));
@ -656,7 +656,7 @@ void midzeus_state::zeus_register_update(offs_t offset)
// m_zeusbase[0x46] = ??? = 0x00000000
// m_zeusbase[0x4c] = ??? = 0x00808080 (brightness?)
// m_zeusbase[0x4e] = ??? = 0x00808080 (brightness?)
mz_poly_extra_data& extra = poly->object_data_alloc();
mz_poly_extra_data& extra = poly->object_data_alloc();
poly_vertex vert[4];
vert[0].x = (INT16)m_zeusbase[0x08];
@ -671,7 +671,7 @@ void midzeus_state::zeus_register_update(offs_t offset)
extra.solidcolor = m_zeusbase[0x00];
extra.zoffset = 0x7fff;
poly->zeus_draw_debug_quad(zeus_cliprect, vert);
poly->zeus_draw_debug_quad(zeus_cliprect, vert);
poly->wait("Normal");
}
else
@ -1230,7 +1230,7 @@ void midzeus_renderer::zeus_draw_quad(int long_fmt, const UINT32 *databuffer, UI
clipvert[i].y += 0.0005f;
}
mz_poly_extra_data& extra = poly->object_data_alloc();
mz_poly_extra_data& extra = poly->object_data_alloc();
if (ctrl_word & 0x01000000)
{
@ -1265,18 +1265,18 @@ void midzeus_renderer::zeus_draw_quad(int long_fmt, const UINT32 *databuffer, UI
extra.transcolor = ((ctrl_word >> 16) & 1) ? 0 : 0x100;
extra.palbase = waveram0_ptr_from_block_addr(zeus_palbase);
// Note: Before being upgraded to the new polygon rasterizing code, this function call was
// a poly_render_quad_fan. It appears as though the new code defaults to a fan if
// the template argument is 4, but keep an eye out for missing quads.
poly->render_polygon<4>(zeus_cliprect,
render_delegate(FUNC(midzeus_renderer::render_poly), this),
4,
clipvert);
// Note: Before being upgraded to the new polygon rasterizing code, this function call was
// a poly_render_quad_fan. It appears as though the new code defaults to a fan if
// the template argument is 4, but keep an eye out for missing quads.
poly->render_polygon<4>(zeus_cliprect,
render_delegate(FUNC(midzeus_renderer::render_poly), this),
4,
clipvert);
}
void midzeus_renderer::zeus_draw_debug_quad(const rectangle& rect, const vertex_t *vert)
{
poly->render_polygon<4>(rect, render_delegate(FUNC(midzeus_renderer::render_poly_solid_fixedz), this), 0, vert);
poly->render_polygon<4>(rect, render_delegate(FUNC(midzeus_renderer::render_poly_solid_fixedz), this), 0, vert);
}

43
src/mame/video/midzeus2.c
View File

@ -61,10 +61,10 @@ class midzeus2_renderer : public poly_manager<float, mz2_poly_extra_data, 4, 100
public:
midzeus2_renderer(midzeus2_state &state);
void render_poly_8bit(INT32 scanline, const extent_t& extent, const mz2_poly_extra_data& object, int threadid);
void zeus2_draw_quad(const UINT32 *databuffer, UINT32 texoffs, int logit);
void render_poly_8bit(INT32 scanline, const extent_t& extent, const mz2_poly_extra_data& object, int threadid);
void zeus2_draw_quad(const UINT32 *databuffer, UINT32 texoffs, int logit);
private:
midzeus2_state& m_state;
};
@ -73,10 +73,9 @@ typedef midzeus2_renderer::vertex_t poly_vertex;
typedef midzeus2_renderer::extent_t poly_extent;
midzeus2_renderer::midzeus2_renderer(midzeus2_state &state)
: poly_manager<float, mz2_poly_extra_data, 4, 10000>(state.machine())
, m_state(state)
: poly_manager<float, mz2_poly_extra_data, 4, 10000>(state.machine())
, m_state(state)
{
}
@ -279,8 +278,8 @@ VIDEO_START_MEMBER(midzeus2_state,midzeus2)
waveram[1] = auto_alloc_array(machine(), UINT32, WAVERAM1_WIDTH * WAVERAM1_HEIGHT * 12/4);
/* initialize polygon engine */
poly = auto_alloc(machine(), midzeus2_renderer(*this));
poly = auto_alloc(machine(), midzeus2_renderer(*this));
/* we need to cleanup on exit */
machine().add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(midzeus2_state::exit_handler2), this));
@ -370,8 +369,8 @@ UINT32 midzeus2_state::screen_update_midzeus2(screen_device &screen, bitmap_rgb3
{
int x, y;
poly->wait();
poly->wait();
if (machine().input().code_pressed(KEYCODE_UP)) { zbase += 1.0f; popmessage("Zbase = %f", (double) zbase); }
if (machine().input().code_pressed(KEYCODE_DOWN)) { zbase -= 1.0f; popmessage("Zbase = %f", (double) zbase); }
@ -1226,7 +1225,7 @@ In memory:
clipvert[i].y += 0.0005f;
}
mz2_poly_extra_data& extra = poly->object_data_alloc();
mz2_poly_extra_data& extra = poly->object_data_alloc();
switch (texmode)
{
case 0x01d: /* crusnexo: RHS of score bar */
@ -1272,16 +1271,16 @@ In memory:
extra.texbase = WAVERAM_BLOCK0(zeus_texbase);
extra.palbase = waveram0_ptr_from_expanded_addr(m_state.m_zeusbase[0x41]);
// Note: Before being converted to the "poly.h" interface, this used to call the polylgcy function
// poly_render_quad_fan. The behavior seems to be the same as it once was after a few short
// tests, but the (numverts == 5) statement below may actually be a quad fan instead of a 5-sided
// polygon.
if (numverts == 3)
render_triangle(zeus_cliprect, render_delegate(FUNC(midzeus2_renderer::render_poly_8bit), this), 4, clipvert[0], clipvert[1], clipvert[2]);
else if (numverts == 4)
render_polygon<4>(zeus_cliprect, render_delegate(FUNC(midzeus2_renderer::render_poly_8bit), this), 4, clipvert);
else if (numverts == 5)
render_polygon<5>(zeus_cliprect, render_delegate(FUNC(midzeus2_renderer::render_poly_8bit), this), 4, clipvert);
// Note: Before being converted to the "poly.h" interface, this used to call the polylgcy function
// poly_render_quad_fan. The behavior seems to be the same as it once was after a few short
// tests, but the (numverts == 5) statement below may actually be a quad fan instead of a 5-sided
// polygon.
if (numverts == 3)
render_triangle(zeus_cliprect, render_delegate(FUNC(midzeus2_renderer::render_poly_8bit), this), 4, clipvert[0], clipvert[1], clipvert[2]);
else if (numverts == 4)
render_polygon<4>(zeus_cliprect, render_delegate(FUNC(midzeus2_renderer::render_poly_8bit), this), 4, clipvert);
else if (numverts == 5)
render_polygon<5>(zeus_cliprect, render_delegate(FUNC(midzeus2_renderer::render_poly_8bit), this), 4, clipvert);
}

68
src/mame/video/model2.c
View File

@ -780,13 +780,13 @@ static void model2_3d_process_triangle( raster_state *raster, UINT32 attr )
}
/***********************************************************************************************/
/***********************************************************************************************/
void model2_renderer::model2_3d_render(triangle *tri, const rectangle &cliprect)
{
model2_renderer *poly = m_state.m_poly;
m2_poly_extra_data& extra = poly->object_data_alloc();
m2_poly_extra_data& extra = poly->object_data_alloc();
UINT8 renderer;
/* select renderer based on attributes (bit15 = checker, bit14 = textured, bit13 = transparent */
@ -821,35 +821,35 @@ void model2_renderer::model2_3d_render(triangle *tri, const rectangle &cliprect)
tri->v[2].pu = tri->v[2].pu * tri->v[2].pz * (1.0f / 8.0f);
tri->v[2].pv = tri->v[2].pv * tri->v[2].pz * (1.0f / 8.0f);
// Note : The class model2_renderer has an array of function pointers in it named m_renderfuncs, in theory this simply
// needs to be passed into the render_triangle function as such model2_renderer::m_renderfuncs[renderer], but
// I was unable to make it work when converting to the new polygon rasterizer interface.
switch (renderer)
{
case 0: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_0), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 1: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_1), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 2: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_2), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 3: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_3), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 4: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_4), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 5: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_5), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 6: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_6), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 7: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_7), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
}
// Note : The class model2_renderer has an array of function pointers in it named m_renderfuncs, in theory this simply
// needs to be passed into the render_triangle function as such model2_renderer::m_renderfuncs[renderer], but
// I was unable to make it work when converting to the new polygon rasterizer interface.
switch (renderer)
{
case 0: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_0), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 1: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_1), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 2: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_2), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 3: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_3), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 4: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_4), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 5: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_5), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 6: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_6), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
case 7: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_7), this), 3, tri->v[0], tri->v[1], tri->v[2]); break;
}
}
else
{
switch (renderer)
{
case 0: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_0), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 1: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_1), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 2: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_2), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 3: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_3), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 4: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_4), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 5: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_5), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 6: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_6), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 7: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_7), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
}
}
{
switch (renderer)
{
case 0: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_0), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 1: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_1), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 2: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_2), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 3: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_3), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 4: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_4), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 5: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_5), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 6: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_6), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
case 7: render_triangle(vp, render_delegate(FUNC(model2_renderer::model2_3d_render_7), this), 0, tri->v[0], tri->v[1], tri->v[2]); break;
}
}
}
/*
@ -947,8 +947,8 @@ void model2_state::model2_3d_frame_end( bitmap_rgb32 &bitmap, const rectangle &c
}
#endif
m_poly->destmap().fill(0x00000000, cliprect);
m_poly->destmap().fill(0x00000000, cliprect);
/* go through the Z levels, and render each bucket */
for( z = raster->max_z; z >= raster->min_z; z-- )
{
@ -970,8 +970,8 @@ void model2_state::model2_3d_frame_end( bitmap_rgb32 &bitmap, const rectangle &c
}
}
m_poly->wait("End of frame");
copybitmap_trans(bitmap, m_poly->destmap(), 0, 0, 0, 0, cliprect, 0x00000000);
copybitmap_trans(bitmap, m_poly->destmap(), 0, 0, 0, 0, cliprect, 0x00000000);
}
/* 3D Rasterizer main data input port */
@ -2590,7 +2590,7 @@ VIDEO_START_MEMBER(model2_state,model2)
m_sys24_bitmap.allocate(width, height+4);
m_poly = auto_alloc(machine(), model2_renderer(*this));
m_poly = auto_alloc(machine(), model2_renderer(*this));
/* initialize the hardware rasterizer */
model2_3d_init( machine(), (UINT16*)memregion("user3")->base() );

8
src/mame/video/n64.c
View File

@ -214,8 +214,8 @@ void n64_periphs::video_update16(bitmap_rgb32 &bitmap)
//if (hres > 640) // Needed by Top Gear Overdrive (E)
//{
// invisiblewidth += (hres - 640);
// hres = 640;
// invisiblewidth += (hres - 640);
// hres = 640;
//}
if (vres > bitmap.height()) // makes Perfect Dark boot w/o crashing
@ -270,8 +270,8 @@ void n64_periphs::video_update32(bitmap_rgb32 &bitmap)
//if (hres > 640) // Needed by Top Gear Overdrive (E)
//{
// invisiblewidth += (hres - 640);
// hres = 640;
// invisiblewidth += (hres - 640);
// hres = 640;
//}
if (frame_buffer32)

2
src/mame/video/n64.h
View File

@ -302,7 +302,7 @@ public:
UINT16 m_dzpix_normalize[0x10000];
rectangle_t m_scissor;
rectangle_t m_scissor;
span_base_t m_span_base;
void draw_triangle(bool shade, bool texture, bool zbuffer, bool rect);

2
src/mame/video/segaxbd.c
View File

@ -18,7 +18,7 @@ void segaxbd_state::video_start()
{
if(!m_segaic16vid->started())
throw device_missing_dependencies();
if(!m_segaic16road->started())
throw device_missing_dependencies();

4
src/mame/video/suna8.c
View File

@ -288,7 +288,7 @@ void suna8_state::draw_sprites(screen_device &screen, bitmap_ind16 &bitmap, cons
// note: fireballs in level 5 (fe20/40) should go above flames and score (text sprites)
int text_list = (i - start) & 0x20;
int text_start = text_list ? 0x19c0 : 0x1980;
bool write_mask = (text_list == 0); // hack?
bool write_mask = (text_list == 0); // hack?
draw_text_sprites(screen, bitmap, cliprect, text_start, text_start + 0x80, y, write_mask);
continue;
}
@ -459,7 +459,7 @@ void suna8_state::draw_sprites(screen_device &screen, bitmap_ind16 &bitmap, cons
2.b X
3.b 7--- ---- 0 = Last Sprite
3.b 7--- ---- 0 = Last Sprite
-6-- ---- X (Sign Bit)
--54 3210 Tiles Bank ($400 tiles each)

2
src/mess/drivers/asst128.c
View File

@ -108,7 +108,7 @@ static MACHINE_CONFIG_START( asst128, asst128_state )
asst128_mb_device::static_set_cputag(*device, "maincpu");
MCFG_DEVICE_INPUT_DEFAULTS(asst128)
// MCFG_DEVICE_REMOVE("mb:dma8237")
// MCFG_DEVICE_REMOVE("mb:dma8237")
MCFG_DEVICE_REMOVE("mb:cassette")
MCFG_CASSETTE_ADD("mb:cassette")

128
src/mess/drivers/bbc.c
View File

@ -143,7 +143,7 @@ static ADDRESS_MAP_START( bbca_mem, AS_PROGRAM, 8, bbc_state )
AM_RANGE(0x8000, 0xbfff) AM_READ_BANK("bank4") AM_WRITE(bbc_memoryb4_w) /* 8000-bfff Paged ROM */
AM_RANGE(0xc000, 0xfbff) AM_READ_BANK("bank7") /* c000-fbff OS ROM */
AM_RANGE(0xfc00, 0xfdff) AM_NOP /* fc00-fdff FRED & JIM Pages */
/* fe00-feff SHEILA Address Page */
/* fe00-feff SHEILA Address Page */
AM_RANGE(0xfe00, 0xfe00) AM_MIRROR(0x06) AM_DEVREADWRITE("mc6845", mc6845_device, status_r, address_w) /* fe00-fe07 6845 CRTC Video controller */
AM_RANGE(0xfe01, 0xfe01) AM_MIRROR(0x06) AM_DEVREADWRITE("mc6845", mc6845_device, register_r, register_w)
AM_RANGE(0xfe08, 0xfe08) AM_MIRROR(0x06) AM_DEVREADWRITE("acia6850", acia6850_device, status_r, control_w) /* fe08-fe0F 6850 ACIA Serial controller */
@ -151,9 +151,9 @@ static ADDRESS_MAP_START( bbca_mem, AS_PROGRAM, 8, bbc_state )
AM_RANGE(0xfe10, 0xfe17) AM_READWRITE(bbc_fe_r, bbc_SerialULA_w) /* fe10-fe17 Serial ULA Serial system chip */
AM_RANGE(0xfe18, 0xfe1f) AM_NOP /* fe18-fe1f INTOFF/STATID # ECONET Interrupt Off / ID No. */
AM_RANGE(0xfe20, 0xfe2f) AM_WRITE(bbc_videoULA_w) /* R: fe20-fe2f INTON # ECONET Interrupt On */
/* W: fe20-fe2f Video ULA Video system chip */
/* W: fe20-fe2f Video ULA Video system chip */
AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE(bbc_fe_r, bbc_page_selecta_w) /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
AM_RANGE(0xfe40, 0xfe5f) AM_DEVREADWRITE("via6522_0", via6522_device, read, write) /* fe40-fe5f 6522 VIA SYSTEM VIA */
AM_RANGE(0xfe60, 0xfe7f) AM_NOP /* fe60-fe7f 6522 VIA # USER VIA */
AM_RANGE(0xfe80, 0xfe9f) AM_NOP /* fe80-fe9f 8271/1770 FDC # Floppy disc controller */
@ -169,7 +169,7 @@ static ADDRESS_MAP_START( bbc_base, AS_PROGRAM, 8, bbc_state )
AM_RANGE(0xc000, 0xfbff) AM_READ_BANK("bank7") /* c000-fbff OS ROM */
AM_RANGE(0xfc00, 0xfdff) AM_NOP /* fc00-fdff FRED & JIM Pages */
/* fe00-feff SHEILA Address Page */
/* fe00-feff SHEILA Address Page */
AM_RANGE(0xfe00, 0xfe00) AM_MIRROR(0x06) AM_DEVREADWRITE("mc6845", mc6845_device, status_r, address_w) /* fe00-fe07 6845 CRTC Video controller */
AM_RANGE(0xfe01, 0xfe01) AM_MIRROR(0x06) AM_DEVREADWRITE("mc6845", mc6845_device, register_r, register_w)
AM_RANGE(0xfe08, 0xfe08) AM_MIRROR(0x06) AM_DEVREADWRITE("acia6850", acia6850_device, status_r, control_w) /* fe08-fe0F 6850 ACIA Serial controller */
@ -177,10 +177,10 @@ static ADDRESS_MAP_START( bbc_base, AS_PROGRAM, 8, bbc_state )
AM_RANGE(0xfe10, 0xfe17) AM_READWRITE(bbc_fe_r, bbc_SerialULA_w) /* fe10-fe17 Serial ULA Serial system chip */
AM_RANGE(0xfe18, 0xfe1f) AM_READ_PORT("S11") /* fe18-fe1f INTOFF/STATID ECONET Interrupt Off / ID No. */
AM_RANGE(0xfe20, 0xfe2f) AM_WRITE(bbc_videoULA_w) /* R: fe20-fe2f INTON ECONET Interrupt On */
/* W: fe20-fe2f Video ULA Video system chip */
/* W: fe20-fe2f Video ULA Video system chip */
AM_RANGE(0xfe40, 0xfe5f) AM_DEVREADWRITE("via6522_0", via6522_device, read, write) /* fe40-fe5f 6522 VIA SYSTEM VIA */
AM_RANGE(0xfe60, 0xfe7f) AM_DEVREADWRITE("via6522_1", via6522_device, read, write) /* fe60-fe7f 6522 VIA USER VIA */
/* fe80-fe9f FDC Floppy disc controller */
/* fe80-fe9f FDC Floppy disc controller */
AM_RANGE(0xfea0, 0xfebf) AM_READ(bbc_fe_r) /* fea0-febf 68B54 ADLC ECONET controller */
AM_RANGE(0xfec0, 0xfedf) AM_DEVREADWRITE("upd7002", upd7002_device, read, write) /* fec0-fedf uPD7002 Analogue to digital converter */
AM_RANGE(0xfee0, 0xfeff) AM_READ(bbc_fe_r) /* fee0-feff Tube ULA Tube system interface */
@ -193,7 +193,7 @@ static ADDRESS_MAP_START( bbcb_mem, AS_PROGRAM, 8, bbc_state )
AM_RANGE(0x4000, 0x7fff) AM_READ_BANK("bank3") AM_WRITE(bbc_memoryb3_w) /* 4000-7fff Regular Ram */
AM_RANGE(0x8000, 0xbfff) AM_READ_BANK("bank4") AM_WRITE(bbc_memoryb4_w) /* 8000-bfff Paged ROM */
AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE(bbc_fe_r, bbc_page_selectb_w) /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
AM_RANGE(0xfe80, 0xfe83) AM_DEVICE("i8271" , i8271_device, map) /* fe80-fe9f 8271 FDC Floppy disc controller */
AM_RANGE(0xfe84, 0xfe9f) AM_DEVREADWRITE("i8271", i8271_device, data_r, data_w) /* fe80-fe9f 8271 FDC Floppy disc controller */
AM_IMPORT_FROM(bbc_base)
@ -205,7 +205,7 @@ static ADDRESS_MAP_START(bbcb1770_mem, AS_PROGRAM, 8, bbc_state)
AM_RANGE(0x4000, 0x7fff) AM_READ_BANK("bank3") AM_WRITE(bbc_memoryb3_w) /* 4000-7fff Regular Ram */
AM_RANGE(0x8000, 0xbfff) AM_READ_BANK("bank4") AM_WRITE(bbc_memoryb4_w) /* 8000-bfff Paged ROM */
AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE(bbc_fe_r, bbc_page_selectb_w) /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
AM_RANGE(0xfe80, 0xfe83) AM_WRITE(bbc_wd1770_status_w) /* fe80-fe83 1770 FDC Drive control register */
AM_RANGE(0xfe84, 0xfe9f) AM_DEVREADWRITE("wd1770", wd1770_t, read, write) /* fe84-fe9f 1770 FDC Floppy disc controller */
AM_IMPORT_FROM(bbc_base)
@ -218,7 +218,7 @@ static ADDRESS_MAP_START( bbcbp_mem, AS_PROGRAM, 8, bbc_state )
AM_RANGE(0x8000, 0xafff) AM_READ_BANK("bank4") AM_WRITE(bbc_memorybp4_w) /* 8000-afff Paged ROM or 12K of SWRAM */
AM_RANGE(0xb000, 0xbfff) AM_READ_BANK("bank6") /* b000-bfff Rest of paged ROM area */
AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE(bbc_fe_r, bbc_page_selectbp_w) /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
AM_RANGE(0xfe80, 0xfe83) AM_WRITE(bbc_wd1770_status_w) /* fe80-fe83 1770 FDC Drive control register */
AM_RANGE(0xfe84, 0xfe9f) AM_DEVREADWRITE("wd1770", wd1770_t, read, write) /* fe84-fe9f 1770 FDC Floppy disc controller */
AM_IMPORT_FROM(bbc_base)
@ -231,7 +231,7 @@ static ADDRESS_MAP_START( bbcbp128_mem, AS_PROGRAM, 8, bbc_state )
AM_RANGE(0x8000, 0xafff) AM_READ_BANK("bank4") AM_WRITE(bbc_memorybp4_128_w) /* 8000-afff Paged ROM or 12K of SWRAM */
AM_RANGE(0xb000, 0xbfff) AM_READ_BANK("bank6") AM_WRITE(bbc_memorybp6_128_w) /* b000-bfff Rest of paged ROM area */
AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE(bbc_fe_r, bbc_page_selectbp_w) /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
AM_RANGE(0xfe80, 0xfe83) AM_WRITE(bbc_wd1770_status_w) /* fe80-fe83 1770 FDC Drive control register */
AM_RANGE(0xfe84, 0xfe9f) AM_DEVREADWRITE("wd1770", wd1770_t, read, write) /* fe84-fe9f 1770 FDC Floppy disc controller */
AM_IMPORT_FROM(bbc_base)
@ -244,7 +244,7 @@ static ADDRESS_MAP_START( reutapm_mem, AS_PROGRAM, 8, bbc_state )
AM_RANGE(0x8000, 0xafff) AM_READ_BANK("bank4") AM_WRITE(bbc_memorybp4_w) /* 8000-afff Paged ROM or 12K of SWRAM */
AM_RANGE(0xb000, 0xbfff) AM_READ_BANK("bank6") /* b000-bfff Rest of paged ROM area */
AM_RANGE(0xfe30, 0xfe3f) AM_READWRITE(bbc_fe_r, bbc_page_selectbp_w) /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
AM_RANGE(0xfe80, 0xfe83) AM_NOP /* fe80-fe83 1770 FDC Drive control register */
AM_RANGE(0xfe84, 0xfe9f) AM_NOP /* fe84-fe9f 1770 FDC Floppy disc controller */
AM_IMPORT_FROM(bbc_base)
@ -490,7 +490,7 @@ static INPUT_PORTS_START(bbc_dipswitch)
PORT_DIPNAME(0x01, 0x01, "Screen Mode") PORT_DIPLOCATION("KBD:6")
PORT_DIPSETTING( 0x00, "+0" )
PORT_DIPSETTING( 0x01, "+4" )
PORT_MODIFY("COL8")
PORT_DIPNAME(0x01, 0x01, "Screen Mode") PORT_DIPLOCATION("KBD:7")
PORT_DIPSETTING( 0x00, "+0" )
@ -506,57 +506,57 @@ INPUT_PORTS_END
static INPUT_PORTS_START(bbc_links)
PORT_START("S11")
PORT_DIPNAME(0xff, 0xfe, "Econet ID") PORT_DIPLOCATION("S11:1,2,3,4,5,6,7,8")
PORT_DIPSETTING( 0x00, "0" ) PORT_DIPSETTING( 0x01, "1" ) PORT_DIPSETTING( 0x02, "2" ) PORT_DIPSETTING( 0x03, "3" ) PORT_DIPSETTING( 0x04, "4" )
PORT_DIPSETTING( 0x05, "5" ) PORT_DIPSETTING( 0x06, "6" ) PORT_DIPSETTING( 0x07, "7" ) PORT_DIPSETTING( 0x08, "8" ) PORT_DIPSETTING( 0x09, "9" )
PORT_DIPSETTING( 0x0a, "10" ) PORT_DIPSETTING( 0x0b, "11" ) PORT_DIPSETTING( 0x0c, "12" ) PORT_DIPSETTING( 0x0d, "13" ) PORT_DIPSETTING( 0x0e, "14" )
PORT_DIPSETTING( 0x0f, "15" ) PORT_DIPSETTING( 0x10, "16" ) PORT_DIPSETTING( 0x11, "17" ) PORT_DIPSETTING( 0x12, "18" ) PORT_DIPSETTING( 0x13, "19" )
PORT_DIPSETTING( 0x14, "20" ) PORT_DIPSETTING( 0x15, "21" ) PORT_DIPSETTING( 0x16, "22" ) PORT_DIPSETTING( 0x17, "23" ) PORT_DIPSETTING( 0x18, "24" )
PORT_DIPSETTING( 0x19, "25" ) PORT_DIPSETTING( 0x1a, "26" ) PORT_DIPSETTING( 0x1b, "27" ) PORT_DIPSETTING( 0x1c, "28" ) PORT_DIPSETTING( 0x1d, "29" )
PORT_DIPSETTING( 0x1e, "30" ) PORT_DIPSETTING( 0x1f, "31" ) PORT_DIPSETTING( 0x20, "32" ) PORT_DIPSETTING( 0x21, "33" ) PORT_DIPSETTING( 0x22, "34" )
PORT_DIPSETTING( 0x23, "35" ) PORT_DIPSETTING( 0x24, "36" ) PORT_DIPSETTING( 0x25, "37" ) PORT_DIPSETTING( 0x26, "38" ) PORT_DIPSETTING( 0x27, "39" )
PORT_DIPSETTING( 0x28, "40" ) PORT_DIPSETTING( 0x29, "41" ) PORT_DIPSETTING( 0x2a, "42" ) PORT_DIPSETTING( 0x2b, "43" ) PORT_DIPSETTING( 0x2c, "44" )
PORT_DIPSETTING( 0x2d, "45" ) PORT_DIPSETTING( 0x2e, "46" ) PORT_DIPSETTING( 0x2f, "47" ) PORT_DIPSETTING( 0x30, "48" ) PORT_DIPSETTING( 0x31, "49" )
PORT_DIPSETTING( 0x32, "50" ) PORT_DIPSETTING( 0x33, "51" ) PORT_DIPSETTING( 0x34, "52" ) PORT_DIPSETTING( 0x35, "53" ) PORT_DIPSETTING( 0x36, "54" )
PORT_DIPSETTING( 0x37, "15" ) PORT_DIPSETTING( 0x38, "56" ) PORT_DIPSETTING( 0x39, "57" ) PORT_DIPSETTING( 0x3a, "58" ) PORT_DIPSETTING( 0x3b, "59" )
PORT_DIPSETTING( 0x3c, "60" ) PORT_DIPSETTING( 0x3d, "61" ) PORT_DIPSETTING( 0x3e, "62" ) PORT_DIPSETTING( 0x3f, "63" ) PORT_DIPSETTING( 0x40, "64" )
PORT_DIPSETTING( 0x41, "65" ) PORT_DIPSETTING( 0x42, "66" ) PORT_DIPSETTING( 0x43, "67" ) PORT_DIPSETTING( 0x44, "68" ) PORT_DIPSETTING( 0x45, "69" )
PORT_DIPSETTING( 0x46, "70" ) PORT_DIPSETTING( 0x47, "71" ) PORT_DIPSETTING( 0x48, "72" ) PORT_DIPSETTING( 0x49, "73" ) PORT_DIPSETTING( 0x4a, "74" )
PORT_DIPSETTING( 0x4b, "75" ) PORT_DIPSETTING( 0x4c, "76" ) PORT_DIPSETTING( 0x4d, "77" ) PORT_DIPSETTING( 0x4e, "78" ) PORT_DIPSETTING( 0x4f, "79" )
PORT_DIPSETTING( 0x50, "80" ) PORT_DIPSETTING( 0x51, "81" ) PORT_DIPSETTING( 0x52, "82" ) PORT_DIPSETTING( 0x53, "83" ) PORT_DIPSETTING( 0x54, "84" )
PORT_DIPSETTING( 0x55, "85" ) PORT_DIPSETTING( 0x56, "86" ) PORT_DIPSETTING( 0x57, "87" ) PORT_DIPSETTING( 0x58, "88" ) PORT_DIPSETTING( 0x59, "89" )
PORT_DIPSETTING( 0x5a, "90" ) PORT_DIPSETTING( 0x5b, "91" ) PORT_DIPSETTING( 0x5c, "92" ) PORT_DIPSETTING( 0x5d, "93" ) PORT_DIPSETTING( 0x5e, "94" )
PORT_DIPSETTING( 0x5f, "95" ) PORT_DIPSETTING( 0x60, "96" ) PORT_DIPSETTING( 0x61, "97" ) PORT_DIPSETTING( 0x62, "98" ) PORT_DIPSETTING( 0x63, "99" )
PORT_DIPSETTING( 0x64, "100" ) PORT_DIPSETTING( 0x65, "101" ) PORT_DIPSETTING( 0x66, "102" ) PORT_DIPSETTING( 0x67, "103" ) PORT_DIPSETTING( 0x68, "104" )
PORT_DIPSETTING( 0x69, "105" ) PORT_DIPSETTING( 0x6a, "106" ) PORT_DIPSETTING( 0x6b, "107" ) PORT_DIPSETTING( 0x6c, "108" ) PORT_DIPSETTING( 0x6d, "109" )
PORT_DIPSETTING( 0x6e, "110" ) PORT_DIPSETTING( 0x6f, "111" ) PORT_DIPSETTING( 0x70, "112" ) PORT_DIPSETTING( 0x71, "113" ) PORT_DIPSETTING( 0x72, "114" )
PORT_DIPSETTING( 0x73, "115" ) PORT_DIPSETTING( 0x74, "116" ) PORT_DIPSETTING( 0x75, "117" ) PORT_DIPSETTING( 0x76, "118" ) PORT_DIPSETTING( 0x77, "119" )
PORT_DIPSETTING( 0x78, "120" ) PORT_DIPSETTING( 0x79, "121" ) PORT_DIPSETTING( 0x7a, "122" ) PORT_DIPSETTING( 0x7b, "123" ) PORT_DIPSETTING( 0x7c, "124" )
PORT_DIPSETTING( 0x7d, "125" ) PORT_DIPSETTING( 0x7e, "126" ) PORT_DIPSETTING( 0x7f, "127" ) PORT_DIPSETTING( 0x80, "128" ) PORT_DIPSETTING( 0x81, "129" )
PORT_DIPSETTING( 0x82, "130" ) PORT_DIPSETTING( 0x83, "131" ) PORT_DIPSETTING( 0x84, "132" ) PORT_DIPSETTING( 0x85, "133" ) PORT_DIPSETTING( 0x86, "134" )
PORT_DIPSETTING( 0x87, "135" ) PORT_DIPSETTING( 0x88, "136" ) PORT_DIPSETTING( 0x89, "137" ) PORT_DIPSETTING( 0x8a, "138" ) PORT_DIPSETTING( 0x8b, "139" )
PORT_DIPSETTING( 0x8c, "140" ) PORT_DIPSETTING( 0x8d, "141" ) PORT_DIPSETTING( 0x8e, "142" ) PORT_DIPSETTING( 0x8f, "143" ) PORT_DIPSETTING( 0x90, "144" )
PORT_DIPSETTING( 0x91, "145" ) PORT_DIPSETTING( 0x92, "146" ) PORT_DIPSETTING( 0x93, "147" ) PORT_DIPSETTING( 0x94, "148" ) PORT_DIPSETTING( 0x95, "149" )
PORT_DIPSETTING( 0x96, "150" ) PORT_DIPSETTING( 0x97, "151" ) PORT_DIPSETTING( 0x98, "152" ) PORT_DIPSETTING( 0x99, "153" ) PORT_DIPSETTING( 0x9a, "154" )
PORT_DIPSETTING( 0x9b, "155" ) PORT_DIPSETTING( 0x9c, "156" ) PORT_DIPSETTING( 0x9d, "157" ) PORT_DIPSETTING( 0x9e, "158" ) PORT_DIPSETTING( 0x9f, "159" )
PORT_DIPSETTING( 0xa0, "160" ) PORT_DIPSETTING( 0xa1, "161" ) PORT_DIPSETTING( 0xa2, "162" ) PORT_DIPSETTING( 0xa3, "163" ) PORT_DIPSETTING( 0xa4, "164" )
PORT_DIPSETTING( 0xa5, "165" ) PORT_DIPSETTING( 0xa6, "166" ) PORT_DIPSETTING( 0xa7, "167" ) PORT_DIPSETTING( 0xa8, "168" ) PORT_DIPSETTING( 0xa9, "169" )
PORT_DIPSETTING( 0xaa, "170" ) PORT_DIPSETTING( 0xab, "171" ) PORT_DIPSETTING( 0xac, "172" ) PORT_DIPSETTING( 0xad, "173" ) PORT_DIPSETTING( 0xae, "174" )
PORT_DIPSETTING( 0xaf, "175" ) PORT_DIPSETTING( 0xb0, "176" ) PORT_DIPSETTING( 0xb1, "177" ) PORT_DIPSETTING( 0xb2, "178" ) PORT_DIPSETTING( 0xb3, "179" )
PORT_DIPSETTING( 0xb4, "180" ) PORT_DIPSETTING( 0xb5, "181" ) PORT_DIPSETTING( 0xb6, "182" ) PORT_DIPSETTING( 0xb7, "183" ) PORT_DIPSETTING( 0xb8, "184" )
PORT_DIPSETTING( 0xb9, "185" ) PORT_DIPSETTING( 0xba, "186" ) PORT_DIPSETTING( 0xbb, "187" ) PORT_DIPSETTING( 0xbc, "188" ) PORT_DIPSETTING( 0xbd, "189" )
PORT_DIPSETTING( 0xbe, "190" ) PORT_DIPSETTING( 0xbf, "191" ) PORT_DIPSETTING( 0xc0, "192" ) PORT_DIPSETTING( 0xc1, "193" ) PORT_DIPSETTING( 0xc2, "194" )
PORT_DIPSETTING( 0xc3, "195" ) PORT_DIPSETTING( 0xc4, "196" ) PORT_DIPSETTING( 0xc5, "197" ) PORT_DIPSETTING( 0xc6, "198" ) PORT_DIPSETTING( 0xc7, "199" )
PORT_DIPSETTING( 0xc8, "200" ) PORT_DIPSETTING( 0xc9, "201" ) PORT_DIPSETTING( 0xca, "202" ) PORT_DIPSETTING( 0xcb, "203" ) PORT_DIPSETTING( 0xcc, "204" )
PORT_DIPSETTING( 0xcd, "205" ) PORT_DIPSETTING( 0xce, "206" ) PORT_DIPSETTING( 0xcf, "207" ) PORT_DIPSETTING( 0xd0, "208" ) PORT_DIPSETTING( 0xd1, "209" )
PORT_DIPSETTING( 0xd2, "210" ) PORT_DIPSETTING( 0xd3, "211" ) PORT_DIPSETTING( 0xd4, "212" ) PORT_DIPSETTING( 0xd5, "213" ) PORT_DIPSETTING( 0xd6, "214" )
PORT_DIPSETTING( 0xd7, "215" ) PORT_DIPSETTING( 0xd8, "216" ) PORT_DIPSETTING( 0xd9, "217" ) PORT_DIPSETTING( 0xda, "218" ) PORT_DIPSETTING( 0xdb, "219" )
PORT_DIPSETTING( 0xdc, "220" ) PORT_DIPSETTING( 0xdd, "221" ) PORT_DIPSETTING( 0xde, "222" ) PORT_DIPSETTING( 0xdf, "223" ) PORT_DIPSETTING( 0xe0, "224" )
PORT_DIPSETTING( 0xe1, "225" ) PORT_DIPSETTING( 0xe2, "226" ) PORT_DIPSETTING( 0xe3, "227" ) PORT_DIPSETTING( 0xe4, "228" ) PORT_DIPSETTING( 0xe5, "229" )
PORT_DIPSETTING( 0xe6, "230" ) PORT_DIPSETTING( 0xe7, "231" ) PORT_DIPSETTING( 0xe8, "232" ) PORT_DIPSETTING( 0xe9, "233" ) PORT_DIPSETTING( 0xea, "234" )
PORT_DIPSETTING( 0xeb, "235" ) PORT_DIPSETTING( 0xec, "236" ) PORT_DIPSETTING( 0xed, "237" ) PORT_DIPSETTING( 0xee, "238" ) PORT_DIPSETTING( 0xef, "239" )
PORT_DIPSETTING( 0xf0, "240" ) PORT_DIPSETTING( 0xf1, "241" ) PORT_DIPSETTING( 0xf2, "242" ) PORT_DIPSETTING( 0xf3, "243" ) PORT_DIPSETTING( 0xf4, "244" )
PORT_DIPSETTING( 0xf5, "245" ) PORT_DIPSETTING( 0xf6, "246" ) PORT_DIPSETTING( 0xf7, "247" ) PORT_DIPSETTING( 0xf8, "248" ) PORT_DIPSETTING( 0xf9, "249" )
PORT_DIPSETTING( 0xfa, "250" ) PORT_DIPSETTING( 0xfb, "251" ) PORT_DIPSETTING( 0xfc, "252" ) PORT_DIPSETTING( 0xfd, "253" ) PORT_DIPSETTING( 0xfe, "254" )
PORT_DIPSETTING( 0x00, "0" ) PORT_DIPSETTING( 0x01, "1" ) PORT_DIPSETTING( 0x02, "2" ) PORT_DIPSETTING( 0x03, "3" ) PORT_DIPSETTING( 0x04, "4" )
PORT_DIPSETTING( 0x05, "5" ) PORT_DIPSETTING( 0x06, "6" ) PORT_DIPSETTING( 0x07, "7" ) PORT_DIPSETTING( 0x08, "8" ) PORT_DIPSETTING( 0x09, "9" )
PORT_DIPSETTING( 0x0a, "10" ) PORT_DIPSETTING( 0x0b, "11" ) PORT_DIPSETTING( 0x0c, "12" ) PORT_DIPSETTING( 0x0d, "13" ) PORT_DIPSETTING( 0x0e, "14" )
PORT_DIPSETTING( 0x0f, "15" ) PORT_DIPSETTING( 0x10, "16" ) PORT_DIPSETTING( 0x11, "17" ) PORT_DIPSETTING( 0x12, "18" ) PORT_DIPSETTING( 0x13, "19" )
PORT_DIPSETTING( 0x14, "20" ) PORT_DIPSETTING( 0x15, "21" ) PORT_DIPSETTING( 0x16, "22" ) PORT_DIPSETTING( 0x17, "23" ) PORT_DIPSETTING( 0x18, "24" )
PORT_DIPSETTING( 0x19, "25" ) PORT_DIPSETTING( 0x1a, "26" ) PORT_DIPSETTING( 0x1b, "27" ) PORT_DIPSETTING( 0x1c, "28" ) PORT_DIPSETTING( 0x1d, "29" )
PORT_DIPSETTING( 0x1e, "30" ) PORT_DIPSETTING( 0x1f, "31" ) PORT_DIPSETTING( 0x20, "32" ) PORT_DIPSETTING( 0x21, "33" ) PORT_DIPSETTING( 0x22, "34" )
PORT_DIPSETTING( 0x23, "35" ) PORT_DIPSETTING( 0x24, "36" ) PORT_DIPSETTING( 0x25, "37" ) PORT_DIPSETTING( 0x26, "38" ) PORT_DIPSETTING( 0x27, "39" )
PORT_DIPSETTING( 0x28, "40" ) PORT_DIPSETTING( 0x29, "41" ) PORT_DIPSETTING( 0x2a, "42" ) PORT_DIPSETTING( 0x2b, "43" ) PORT_DIPSETTING( 0x2c, "44" )
PORT_DIPSETTING( 0x2d, "45" ) PORT_DIPSETTING( 0x2e, "46" ) PORT_DIPSETTING( 0x2f, "47" ) PORT_DIPSETTING( 0x30, "48" ) PORT_DIPSETTING( 0x31, "49" )
PORT_DIPSETTING( 0x32, "50" ) PORT_DIPSETTING( 0x33, "51" ) PORT_DIPSETTING( 0x34, "52" ) PORT_DIPSETTING( 0x35, "53" ) PORT_DIPSETTING( 0x36, "54" )
PORT_DIPSETTING( 0x37, "15" ) PORT_DIPSETTING( 0x38, "56" ) PORT_DIPSETTING( 0x39, "57" ) PORT_DIPSETTING( 0x3a, "58" ) PORT_DIPSETTING( 0x3b, "59" )
PORT_DIPSETTING( 0x3c, "60" ) PORT_DIPSETTING( 0x3d, "61" ) PORT_DIPSETTING( 0x3e, "62" ) PORT_DIPSETTING( 0x3f, "63" ) PORT_DIPSETTING( 0x40, "64" )
PORT_DIPSETTING( 0x41, "65" ) PORT_DIPSETTING( 0x42, "66" ) PORT_DIPSETTING( 0x43, "67" ) PORT_DIPSETTING( 0x44, "68" ) PORT_DIPSETTING( 0x45, "69" )
PORT_DIPSETTING( 0x46, "70" ) PORT_DIPSETTING( 0x47, "71" ) PORT_DIPSETTING( 0x48, "72" ) PORT_DIPSETTING( 0x49, "73" ) PORT_DIPSETTING( 0x4a, "74" )
PORT_DIPSETTING( 0x4b, "75" ) PORT_DIPSETTING( 0x4c, "76" ) PORT_DIPSETTING( 0x4d, "77" ) PORT_DIPSETTING( 0x4e, "78" ) PORT_DIPSETTING( 0x4f, "79" )
PORT_DIPSETTING( 0x50, "80" ) PORT_DIPSETTING( 0x51, "81" ) PORT_DIPSETTING( 0x52, "82" ) PORT_DIPSETTING( 0x53, "83" ) PORT_DIPSETTING( 0x54, "84" )
PORT_DIPSETTING( 0x55, "85" ) PORT_DIPSETTING( 0x56, "86" ) PORT_DIPSETTING( 0x57, "87" ) PORT_DIPSETTING( 0x58, "88" ) PORT_DIPSETTING( 0x59, "89" )
PORT_DIPSETTING( 0x5a, "90" ) PORT_DIPSETTING( 0x5b, "91" ) PORT_DIPSETTING( 0x5c, "92" ) PORT_DIPSETTING( 0x5d, "93" ) PORT_DIPSETTING( 0x5e, "94" )
PORT_DIPSETTING( 0x5f, "95" ) PORT_DIPSETTING( 0x60, "96" ) PORT_DIPSETTING( 0x61, "97" ) PORT_DIPSETTING( 0x62, "98" ) PORT_DIPSETTING( 0x63, "99" )
PORT_DIPSETTING( 0x64, "100" ) PORT_DIPSETTING( 0x65, "101" ) PORT_DIPSETTING( 0x66, "102" ) PORT_DIPSETTING( 0x67, "103" ) PORT_DIPSETTING( 0x68, "104" )
PORT_DIPSETTING( 0x69, "105" ) PORT_DIPSETTING( 0x6a, "106" ) PORT_DIPSETTING( 0x6b, "107" ) PORT_DIPSETTING( 0x6c, "108" ) PORT_DIPSETTING( 0x6d, "109" )
PORT_DIPSETTING( 0x6e, "110" ) PORT_DIPSETTING( 0x6f, "111" ) PORT_DIPSETTING( 0x70, "112" ) PORT_DIPSETTING( 0x71, "113" ) PORT_DIPSETTING( 0x72, "114" )
PORT_DIPSETTING( 0x73, "115" ) PORT_DIPSETTING( 0x74, "116" ) PORT_DIPSETTING( 0x75, "117" ) PORT_DIPSETTING( 0x76, "118" ) PORT_DIPSETTING( 0x77, "119" )
PORT_DIPSETTING( 0x78, "120" ) PORT_DIPSETTING( 0x79, "121" ) PORT_DIPSETTING( 0x7a, "122" ) PORT_DIPSETTING( 0x7b, "123" ) PORT_DIPSETTING( 0x7c, "124" )
PORT_DIPSETTING( 0x7d, "125" ) PORT_DIPSETTING( 0x7e, "126" ) PORT_DIPSETTING( 0x7f, "127" ) PORT_DIPSETTING( 0x80, "128" ) PORT_DIPSETTING( 0x81, "129" )
PORT_DIPSETTING( 0x82, "130" ) PORT_DIPSETTING( 0x83, "131" ) PORT_DIPSETTING( 0x84, "132" ) PORT_DIPSETTING( 0x85, "133" ) PORT_DIPSETTING( 0x86, "134" )
PORT_DIPSETTING( 0x87, "135" ) PORT_DIPSETTING( 0x88, "136" ) PORT_DIPSETTING( 0x89, "137" ) PORT_DIPSETTING( 0x8a, "138" ) PORT_DIPSETTING( 0x8b, "139" )
PORT_DIPSETTING( 0x8c, "140" ) PORT_DIPSETTING( 0x8d, "141" ) PORT_DIPSETTING( 0x8e, "142" ) PORT_DIPSETTING( 0x8f, "143" ) PORT_DIPSETTING( 0x90, "144" )
PORT_DIPSETTING( 0x91, "145" ) PORT_DIPSETTING( 0x92, "146" ) PORT_DIPSETTING( 0x93, "147" ) PORT_DIPSETTING( 0x94, "148" ) PORT_DIPSETTING( 0x95, "149" )
PORT_DIPSETTING( 0x96, "150" ) PORT_DIPSETTING( 0x97, "151" ) PORT_DIPSETTING( 0x98, "152" ) PORT_DIPSETTING( 0x99, "153" ) PORT_DIPSETTING( 0x9a, "154" )
PORT_DIPSETTING( 0x9b, "155" ) PORT_DIPSETTING( 0x9c, "156" ) PORT_DIPSETTING( 0x9d, "157" ) PORT_DIPSETTING( 0x9e, "158" ) PORT_DIPSETTING( 0x9f, "159" )
PORT_DIPSETTING( 0xa0, "160" ) PORT_DIPSETTING( 0xa1, "161" ) PORT_DIPSETTING( 0xa2, "162" ) PORT_DIPSETTING( 0xa3, "163" ) PORT_DIPSETTING( 0xa4, "164" )
PORT_DIPSETTING( 0xa5, "165" ) PORT_DIPSETTING( 0xa6, "166" ) PORT_DIPSETTING( 0xa7, "167" ) PORT_DIPSETTING( 0xa8, "168" ) PORT_DIPSETTING( 0xa9, "169" )
PORT_DIPSETTING( 0xaa, "170" ) PORT_DIPSETTING( 0xab, "171" ) PORT_DIPSETTING( 0xac, "172" ) PORT_DIPSETTING( 0xad, "173" ) PORT_DIPSETTING( 0xae, "174" )
PORT_DIPSETTING( 0xaf, "175" ) PORT_DIPSETTING( 0xb0, "176" ) PORT_DIPSETTING( 0xb1, "177" ) PORT_DIPSETTING( 0xb2, "178" ) PORT_DIPSETTING( 0xb3, "179" )
PORT_DIPSETTING( 0xb4, "180" ) PORT_DIPSETTING( 0xb5, "181" ) PORT_DIPSETTING( 0xb6, "182" ) PORT_DIPSETTING( 0xb7, "183" ) PORT_DIPSETTING( 0xb8, "184" )
PORT_DIPSETTING( 0xb9, "185" ) PORT_DIPSETTING( 0xba, "186" ) PORT_DIPSETTING( 0xbb, "187" ) PORT_DIPSETTING( 0xbc, "188" ) PORT_DIPSETTING( 0xbd, "189" )
PORT_DIPSETTING( 0xbe, "190" ) PORT_DIPSETTING( 0xbf, "191" ) PORT_DIPSETTING( 0xc0, "192" ) PORT_DIPSETTING( 0xc1, "193" ) PORT_DIPSETTING( 0xc2, "194" )
PORT_DIPSETTING( 0xc3, "195" ) PORT_DIPSETTING( 0xc4, "196" ) PORT_DIPSETTING( 0xc5, "197" ) PORT_DIPSETTING( 0xc6, "198" ) PORT_DIPSETTING( 0xc7, "199" )
PORT_DIPSETTING( 0xc8, "200" ) PORT_DIPSETTING( 0xc9, "201" ) PORT_DIPSETTING( 0xca, "202" ) PORT_DIPSETTING( 0xcb, "203" ) PORT_DIPSETTING( 0xcc, "204" )
PORT_DIPSETTING( 0xcd, "205" ) PORT_DIPSETTING( 0xce, "206" ) PORT_DIPSETTING( 0xcf, "207" ) PORT_DIPSETTING( 0xd0, "208" ) PORT_DIPSETTING( 0xd1, "209" )
PORT_DIPSETTING( 0xd2, "210" ) PORT_DIPSETTING( 0xd3, "211" ) PORT_DIPSETTING( 0xd4, "212" ) PORT_DIPSETTING( 0xd5, "213" ) PORT_DIPSETTING( 0xd6, "214" )
PORT_DIPSETTING( 0xd7, "215" ) PORT_DIPSETTING( 0xd8, "216" ) PORT_DIPSETTING( 0xd9, "217" ) PORT_DIPSETTING( 0xda, "218" ) PORT_DIPSETTING( 0xdb, "219" )
PORT_DIPSETTING( 0xdc, "220" ) PORT_DIPSETTING( 0xdd, "221" ) PORT_DIPSETTING( 0xde, "222" ) PORT_DIPSETTING( 0xdf, "223" ) PORT_DIPSETTING( 0xe0, "224" )
PORT_DIPSETTING( 0xe1, "225" ) PORT_DIPSETTING( 0xe2, "226" ) PORT_DIPSETTING( 0xe3, "227" ) PORT_DIPSETTING( 0xe4, "228" ) PORT_DIPSETTING( 0xe5, "229" )
PORT_DIPSETTING( 0xe6, "230" ) PORT_DIPSETTING( 0xe7, "231" ) PORT_DIPSETTING( 0xe8, "232" ) PORT_DIPSETTING( 0xe9, "233" ) PORT_DIPSETTING( 0xea, "234" )
PORT_DIPSETTING( 0xeb, "235" ) PORT_DIPSETTING( 0xec, "236" ) PORT_DIPSETTING( 0xed, "237" ) PORT_DIPSETTING( 0xee, "238" ) PORT_DIPSETTING( 0xef, "239" )
PORT_DIPSETTING( 0xf0, "240" ) PORT_DIPSETTING( 0xf1, "241" ) PORT_DIPSETTING( 0xf2, "242" ) PORT_DIPSETTING( 0xf3, "243" ) PORT_DIPSETTING( 0xf4, "244" )
PORT_DIPSETTING( 0xf5, "245" ) PORT_DIPSETTING( 0xf6, "246" ) PORT_DIPSETTING( 0xf7, "247" ) PORT_DIPSETTING( 0xf8, "248" ) PORT_DIPSETTING( 0xf9, "249" )
PORT_DIPSETTING( 0xfa, "250" ) PORT_DIPSETTING( 0xfb, "251" ) PORT_DIPSETTING( 0xfc, "252" ) PORT_DIPSETTING( 0xfd, "253" ) PORT_DIPSETTING( 0xfe, "254" )
PORT_DIPSETTING( 0xff, "255" )
INPUT_PORTS_END
@ -965,7 +965,7 @@ static MACHINE_CONFIG_DERIVED( reutapm, bbcbp )
/* sound hardware */
MCFG_DEVICE_REMOVE("mono")
MCFG_DEVICE_REMOVE("sn76489")
MCFG_DEVICE_REMOVE("sn76489")
MCFG_DEVICE_REMOVE("vsm")
MCFG_DEVICE_REMOVE("tms5220")

18
src/mess/drivers/besta.c
View File

@ -101,18 +101,18 @@ WRITE8_MEMBER( besta_state::kbd_put )
static ADDRESS_MAP_START(besta_mem, AS_PROGRAM, 32, besta_state)
AM_RANGE(0x00000000, 0x001fffff) AM_RAM AM_SHARE("p_ram") // local bus DRAM, 4MB
// AM_RANGE(0x08010000, 0x08011fff) AM_RAM // unknown -- accessed by cp31dssp
// AM_RANGE(0xfca03500, 0xfca0350f) AM_READWRITE8(iscsi_reg_r, iscsi_reg_w, 0xffffffff)
// AM_RANGE(0x08010000, 0x08011fff) AM_RAM // unknown -- accessed by cp31dssp
// AM_RANGE(0xfca03500, 0xfca0350f) AM_READWRITE8(iscsi_reg_r, iscsi_reg_w, 0xffffffff)
AM_RANGE(0xff000000, 0xff00ffff) AM_ROM AM_REGION("user1", 0) // actual mapping is up to 0xff03ffff
AM_RANGE(0xff040000, 0xff07ffff) AM_RAM // onboard SRAM
// AM_RANGE(0xff800000, 0xff80001f) AM_DEVREADWRITE8("mpcc", mpcc68561_t, reg_r, reg_w, 0xffffffff)
// AM_RANGE(0xff800000, 0xff80001f) AM_DEVREADWRITE8("mpcc", mpcc68561_t, reg_r, reg_w, 0xffffffff)
AM_RANGE(0xff800000, 0xff80001f) AM_READWRITE8(mpcc_reg_r, mpcc_reg_w, 0xffffffff) // console
AM_RANGE(0xff800200, 0xff800237) AM_DEVREADWRITE8 ("pit2", pit68230_device, read, write, 0xffffffff)
// AM_RANGE(0xff800400, 0xff800xxx) // ??? -- shows up in cp31dssp log
// AM_RANGE(0xff800800, 0xff800xxx) // 68153 BIM
// AM_RANGE(0xff800a00, 0xff800xxx) // 62421 RTC
// AM_RANGE(0xff800400, 0xff800xxx) // ??? -- shows up in cp31dssp log
// AM_RANGE(0xff800800, 0xff800xxx) // 68153 BIM
// AM_RANGE(0xff800a00, 0xff800xxx) // 62421 RTC
AM_RANGE(0xff800c00, 0xff800c37) AM_DEVREADWRITE8 ("pit1", pit68230_device, read, write, 0xffffffff)
// AM_RANGE(0xff800e00, 0xff800xxx) // PIT3?
// AM_RANGE(0xff800e00, 0xff800xxx) // PIT3?
ADDRESS_MAP_END
/* Input ports */
@ -137,9 +137,9 @@ static MACHINE_CONFIG_START( besta, besta_state )
MCFG_CPU_ADD("maincpu", M68030, 2*16670000)
MCFG_CPU_PROGRAM_MAP(besta_mem)
MCFG_DEVICE_ADD ("pit1", PIT68230, 16670000 / 2) // XXX verify clock
MCFG_DEVICE_ADD ("pit1", PIT68230, 16670000 / 2) // XXX verify clock
MCFG_DEVICE_ADD ("pit2", PIT68230, 16670000 / 2) // XXX verify clock
MCFG_DEVICE_ADD ("pit2", PIT68230, 16670000 / 2) // XXX verify clock
MCFG_DEVICE_ADD(TERMINAL_TAG, GENERIC_TERMINAL, 0)
MCFG_GENERIC_TERMINAL_KEYBOARD_CB(WRITE8(besta_state, kbd_put))

4
src/mess/drivers/canon_s80.c
View File

@ -32,8 +32,8 @@ public:
static ADDRESS_MAP_START(canons80_map, AS_PROGRAM, 8, canons80_state )
AM_RANGE(0x0000, 0x7fff) AM_RAM
AM_RANGE(0x8000, 0xffff) AM_ROM
AM_RANGE(0x0000, 0x7fff) AM_RAM
AM_RANGE(0x8000, 0xffff) AM_ROM
ADDRESS_MAP_END
static MACHINE_CONFIG_START( canons80, canons80_state )

2
src/mess/drivers/decwritr.c
View File

@ -202,7 +202,7 @@ static INPUT_PORTS_START( la120 )
PORT_BIT(0x60, IP_ACTIVE_HIGH, IPT_UNUSED)
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
PORT_START("COL4")
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Num -") PORT_CODE(KEYCODE_MINUS_PAD)
PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Num -") PORT_CODE(KEYCODE_MINUS_PAD)
PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Num ,") PORT_CODE(KEYCODE_PLUS_PAD)
PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("' \"") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('\'') PORT_CHAR('"')
PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("[ {") PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[') PORT_CHAR('{')

68
src/mess/drivers/dvk_kcgd.c
View File

@ -4,7 +4,7 @@
Display Controller), a replacement for KSM (dvk_ksm.c) in later
models of DVK desktops.
MPI (Q-Bus clone) board. Interfaces with MS7004 (DEC LK201 workalike)
MPI (Q-Bus clone) board. Interfaces with MS7004 (DEC LK201 workalike)
keyboard, mouse, and monochrome or color CRT.
To do:
@ -20,23 +20,23 @@
#include "machine/clock.h"
#include "machine/ms7004.h"
#define KCGD_TOTAL_HORZ 1000 // XXX verify
#define KCGD_TOTAL_HORZ 1000 // XXX verify
#define KCGD_DISP_HORZ 800
#define KCGD_HORZ_START 200 // XXX verify
#define KCGD_HORZ_START 200 // XXX verify
#define KCGD_TOTAL_VERT 600 // XXX verify
#define KCGD_TOTAL_VERT 600 // XXX verify
#define KCGD_DISP_VERT 480
#define KCGD_VERT_START 100 // XXX verify
#define KCGD_VERT_START 100 // XXX verify
#define KCGD_STATUS_PAGE 0
#define KCGD_STATUS_INTERLACE 1
#define KCGD_STATUS_TIMER_INT 5
#define KCGD_STATUS_MODE_INT 6
#define KCGD_STATUS_MODE_LAST 7
#define KCGD_STATUS_TIMER_VAL 15
#define KCGD_STATUS_PAGE 0
#define KCGD_STATUS_INTERLACE 1
#define KCGD_STATUS_TIMER_INT 5
#define KCGD_STATUS_MODE_INT 6
#define KCGD_STATUS_MODE_LAST 7
#define KCGD_STATUS_TIMER_VAL 15
#define KCGD_PAGE_0 015574
#define KCGD_PAGE_1 005574
#define KCGD_PAGE_0 015574
#define KCGD_PAGE_1 005574
#define VERBOSE_DBG 1 /* general debug messages */
@ -57,7 +57,7 @@ public:
kcgd_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
// m_ms7004(*this, "ms7004"),
// m_ms7004(*this, "ms7004"),
m_palette(*this, "palette"),
m_screen(*this, "screen")
{ }
@ -102,8 +102,8 @@ private:
bitmap_ind16 m_tmpbmp;
struct {
UINT16 status; // 167770
UINT8 control; // 167772
UINT16 status; // 167770
UINT8 control; // 167772
int palette_index, vram_addr;
UINT8 palette[16];
} m_video;
@ -111,7 +111,7 @@ private:
protected:
required_device<cpu_device> m_maincpu;
// required_device<ms7004_device> m_ms7004;
// required_device<ms7004_device> m_ms7004;
required_device<palette_device> m_palette;
required_device<screen_device> m_screen;
};
@ -123,10 +123,10 @@ static ADDRESS_MAP_START( kcgd_mem, AS_PROGRAM, 16, kcgd_state )
AM_RANGE (0160000, 0160001) AM_MIRROR(03774) AM_READWRITE(vram_addr_r, vram_addr_w)
AM_RANGE (0160002, 0160003) AM_MIRROR(03774) AM_READWRITE(vram_data_r, vram_data_w)
AM_RANGE (0167770, 0167771) AM_READWRITE(status_r, status_w)
AM_RANGE (0167772, 0167773) AM_READWRITE8(palette_index_r, palette_index_w, 0x00ff) // reads always return 0
AM_RANGE (0167772, 0167773) AM_READWRITE8(palette_index_r, palette_index_w, 0x00ff) // reads always return 0
AM_RANGE (0167772, 0167773) AM_READWRITE8(palette_data_r, palette_data_w, 0xff00)
// AM_RANGE (0176560, 0176567) AM_RAM // USART2 -- host
// AM_RANGE (0177560, 0177567) AM_RAM // USART3 -- keyboard
// AM_RANGE (0176560, 0176567) AM_RAM // USART2 -- host
// AM_RANGE (0177560, 0177567) AM_RAM // USART3 -- keyboard
ADDRESS_MAP_END
void kcgd_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
@ -134,13 +134,13 @@ void kcgd_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
switch (id)
{
/*
case TIMER_ID_VSYNC_ON:
m_maincpu->set_input_line(INPUT_LINE_EVNT, ASSERT_LINE);
break;
case TIMER_ID_VSYNC_ON:
m_maincpu->set_input_line(INPUT_LINE_EVNT, ASSERT_LINE);
break;
case TIMER_ID_VSYNC_OFF:
m_maincpu->set_input_line(INPUT_LINE_EVNT, CLEAR_LINE);
break;
case TIMER_ID_VSYNC_OFF:
m_maincpu->set_input_line(INPUT_LINE_EVNT, CLEAR_LINE);
break;
*/
case TIMER_ID_500HZ:
m_video.status ^= (1 << KCGD_STATUS_TIMER_VAL);
@ -155,7 +155,7 @@ void kcgd_state::machine_reset()
void kcgd_state::video_start()
{
// screen_device *screen = machine().device<screen_device>("screen");
// screen_device *screen = machine().device<screen_device>("screen");
// 64 kwords, word size is 17 bits
m_videoram = auto_alloc_array(machine(), UINT32, 65536);
@ -163,11 +163,11 @@ void kcgd_state::video_start()
m_tmpclip = rectangle(0, KCGD_DISP_HORZ-1, 0, KCGD_DISP_VERT-1);
m_tmpbmp.allocate(KCGD_DISP_HORZ, KCGD_DISP_VERT);
/*
m_vsync_on_timer = timer_alloc(TIMER_ID_VSYNC_ON);
m_vsync_on_timer->adjust(screen->time_until_pos(0, 0), 0, screen->frame_period());
m_vsync_on_timer = timer_alloc(TIMER_ID_VSYNC_ON);
m_vsync_on_timer->adjust(screen->time_until_pos(0, 0), 0, screen->frame_period());
m_vsync_off_timer = timer_alloc(TIMER_ID_VSYNC_OFF);
m_vsync_off_timer->adjust(screen->time_until_pos(16, 0), 0, screen->frame_period());
m_vsync_off_timer = timer_alloc(TIMER_ID_VSYNC_OFF);
m_vsync_off_timer->adjust(screen->time_until_pos(16, 0), 0, screen->frame_period());
*/
m_500hz_timer = timer_alloc(TIMER_ID_500HZ);
m_500hz_timer->adjust(attotime::from_hz(500), 0, attotime::from_hz(500));
@ -182,8 +182,8 @@ PALETTE_INIT_MEMBER(kcgd_state, kcgd)
}
/*
VRAM is 128K and is word-addressable, so address fits into 16 bits.
Low 32K of VRAM are not used to store pixel data -- XXX.
VRAM is 128K and is word-addressable, so address fits into 16 bits.
Low 32K of VRAM are not used to store pixel data -- XXX.
*/
WRITE16_MEMBER(kcgd_state::vram_addr_w)
{
@ -247,7 +247,7 @@ WRITE8_MEMBER(kcgd_state::palette_data_w)
{
DBG_LOG(1,"Palette data W", ("data %02XH index %d\n", data, m_video.palette_index));
m_video.palette[m_video.palette_index] = data;
m_palette->set_pen_color(m_video.palette_index,
m_palette->set_pen_color(m_video.palette_index,
85*(data & 3), 85*((data >> 2) & 3), 85*((data >> 4) & 3));
}

142
src/mess/drivers/force68k.c
View File

@ -1,5 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstr??m
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstrom
/***************************************************************************
*
* Force SYS68K CPU-1/CPU-6 VME SBC drivers, initially based on the 68ksbc.c
@ -125,19 +125,19 @@ class force68k_state : public driver_device
{
public:
force68k_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device (mconfig, type, tag),
m_maincpu (*this, "maincpu"),
m_rtc (*this, "rtc"),
m_pit (*this, "pit"),
m_aciahost (*this, "aciahost"),
m_aciaterm (*this, "aciaterm"),
m_aciaremt (*this, "aciaremt"),
m_centronics (*this, "centronics")
, m_centronics_ack (0)
, m_centronics_busy (0)
, m_centronics_perror (0)
, m_centronics_select (0)
,m_cart(*this, "exp_rom1")
driver_device (mconfig, type, tag),
m_maincpu (*this, "maincpu"),
m_rtc (*this, "rtc"),
m_pit (*this, "pit"),
m_aciahost (*this, "aciahost"),
m_aciaterm (*this, "aciaterm"),
m_aciaremt (*this, "aciaremt"),
m_centronics (*this, "centronics")
, m_centronics_ack (0)
, m_centronics_busy (0)
, m_centronics_perror (0)
, m_centronics_select (0)
,m_cart(*this, "exp_rom1")
{
}
@ -253,8 +253,8 @@ INPUT_PORTS_END
WRITE_LINE_MEMBER (force68k_state::centronics_ack_w)
{
// LOG (logerror ("centronics_ack_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
m_centronics_ack = state;
m_pit->h1_set (state);
m_centronics_ack = state;
m_pit->h1_set (state);
}
/* Centronics BUSY handler
@ -262,7 +262,7 @@ WRITE_LINE_MEMBER (force68k_state::centronics_ack_w)
*/
WRITE_LINE_MEMBER (force68k_state::centronics_busy_w){
// LOG (logerror ("centronics_busy_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
m_centronics_busy = state;
m_centronics_busy = state;
}
/* Centronics PERROR handler
@ -270,7 +270,7 @@ WRITE_LINE_MEMBER (force68k_state::centronics_busy_w){
*/
WRITE_LINE_MEMBER (force68k_state::centronics_perror_w){
// LOG (logerror ("centronics_perror_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
m_centronics_perror = state;
m_centronics_perror = state;
}
/* Centronics SELECT handler
@ -278,44 +278,44 @@ WRITE_LINE_MEMBER (force68k_state::centronics_perror_w){
*/
WRITE_LINE_MEMBER (force68k_state::centronics_select_w){
// LOG (logerror ("centronics_select_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
m_centronics_select = state;
m_pit->portb_setbit (0, state);
m_centronics_select = state;
m_pit->portb_setbit (0, state);
}
/* Start it up */
void force68k_state::machine_start ()
{
LOG (logerror ("machine_start\n"));
LOG (logerror ("machine_start\n"));
save_item (NAME (m_centronics_busy));
save_item (NAME (m_centronics_ack));
save_item (NAME (m_centronics_select));
save_item (NAME (m_centronics_perror));
save_item (NAME (m_centronics_busy));
save_item (NAME (m_centronics_ack));
save_item (NAME (m_centronics_select));
save_item (NAME (m_centronics_perror));
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0x080000);
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0x080000);
/* Map user ROM/RAM socket(s) */
if (m_cart->exists())
{
m_usrrom = (UINT16*)m_cart->get_rom_base();
/* Map user ROM/RAM socket(s) */
if (m_cart->exists())
{
m_usrrom = (UINT16*)m_cart->get_rom_base();
#if 0 // This should be the correct way but produces odd and even bytes swapped
m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16_delegate(FUNC(generic_slot_device::read16_rom), (generic_slot_device*)m_cart));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16_delegate(FUNC(generic_slot_device::read16_rom), (generic_slot_device*)m_cart));
#else // So we installs a custom very ineffecient handler for now until we understand hwp to solve the problem better
m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16_delegate(FUNC(force68k_state::read16_rom), this));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16_delegate(FUNC(force68k_state::read16_rom), this));
#endif
}
}
}
/* A very ineffecient User cart emulation of two 8 bit sockets (odd and even) */
READ16_MEMBER (force68k_state::read16_rom){
offset = offset % m_cart->common_get_size("rom"); // Don't read outside buffer...
return ((m_usrrom [offset] << 8) & 0xff00) | ((m_usrrom [offset] >> 8) & 0x00ff);
offset = offset % m_cart->common_get_size("rom"); // Don't read outside buffer...
return ((m_usrrom [offset] << 8) & 0xff00) | ((m_usrrom [offset] >> 8) & 0x00ff);
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
READ16_MEMBER (force68k_state::bootvect_r){
return m_sysrom [offset];
return m_sysrom [offset];
}
/* 10. The VMEbus (text from board documentation)
@ -326,7 +326,7 @@ READ16_MEMBER (force68k_state::bootvect_r){
* systems. In addition to the bus arbiter, a separate slave bus
* arbitration allows selection of the arbitration level (0-3).
*
* The address modifier range .,Short 110 Access« can be selected
* The address modifier range .,Short 110 Access can be selected
* via a jumper for variable system generation. The 7 interrupt
* request levels of the VMEbus are fully supported from the
* SYS68K1CPU-1 B/D. For multi-processing, each IRQ signal can be
@ -338,44 +338,44 @@ READ16_MEMBER (force68k_state::bootvect_r){
/* Dummy VME access methods until the VME bus device is ready for use */
READ16_MEMBER (force68k_state::vme_a24_r){
LOG (logerror ("vme_a24_r\n"));
return (UINT16) 0;
LOG (logerror ("vme_a24_r\n"));
return (UINT16) 0;
}
WRITE16_MEMBER (force68k_state::vme_a24_w){
LOG (logerror ("vme_a24_w\n"));
LOG (logerror ("vme_a24_w\n"));
}
READ16_MEMBER (force68k_state::vme_a16_r){
LOG (logerror ("vme_16_r\n"));
return (UINT16) 0;
LOG (logerror ("vme_16_r\n"));
return (UINT16) 0;
}
WRITE16_MEMBER (force68k_state::vme_a16_w){
LOG (logerror ("vme_a16_w\n"));
LOG (logerror ("vme_a16_w\n"));
}
/*
* Serial port clock sources can all be driven by different outputs of the 14411
*/
WRITE_LINE_MEMBER (force68k_state::write_aciahost_clock){
m_aciahost->write_txc (state);
m_aciahost->write_rxc (state);
m_aciahost->write_txc (state);
m_aciahost->write_rxc (state);
}
WRITE_LINE_MEMBER (force68k_state::write_aciaterm_clock){
m_aciaterm->write_txc (state);
m_aciaterm->write_rxc (state);
m_aciaterm->write_txc (state);
m_aciaterm->write_rxc (state);
}
WRITE_LINE_MEMBER (force68k_state::write_aciaremt_clock){
m_aciaremt->write_txc (state);
m_aciaremt->write_rxc (state);
m_aciaremt->write_txc (state);
m_aciaremt->write_rxc (state);
}
/*
* 4. The USER Area (Text from the board manual)
The USER area contains two 28 pin sockets with JEDEC compatible pin out.
The USER area contains two 28 pin sockets with JEDEC compatible pin out.
To allow the usage of static RAM's, the access to the USER area is byte
oriented. Table 3. lists the usable device types.
@ -388,14 +388,14 @@ WRITE_LINE_MEMBER (force68k_state::write_aciaremt_clock){
32Kx16 64 Kbyte 27256
--------------------------
*/
// Implementation of static 2 x 64K EPROM in sockets J10/J11 as 16 bit wide cartridge for easier
// Implementation of static 2 x 64K EPROM in sockets J10/J11 as 16 bit wide cartridge for easier
// software handling. TODO: make configurable according to table above.
static MACHINE_CONFIG_FRAGMENT( fccpu1_eprom_sockets )
MCFG_GENERIC_CARTSLOT_ADD("exp_rom1", generic_plain_slot, "fccpu1_cart")
MCFG_GENERIC_EXTENSIONS("bin,rom")
MCFG_GENERIC_WIDTH(GENERIC_ROM16_WIDTH)
MCFG_GENERIC_ENDIAN(ENDIANNESS_BIG)
MCFG_GENERIC_LOAD(force68k_state, exp1_load)
MCFG_GENERIC_CARTSLOT_ADD("exp_rom1", generic_plain_slot, "fccpu1_cart")
MCFG_GENERIC_EXTENSIONS("bin,rom")
MCFG_GENERIC_WIDTH(GENERIC_ROM16_WIDTH)
MCFG_GENERIC_ENDIAN(ENDIANNESS_BIG)
MCFG_GENERIC_LOAD(force68k_state, exp1_load)
// MCFG_SOFTWARE_LIST_ADD("cart_list", "fccpu1_cart")
MACHINE_CONFIG_END
@ -404,19 +404,19 @@ MACHINE_CONFIG_END
****************************/
int force68k_state::force68k_load_cart(device_image_interface &image, generic_slot_device *slot)
{
UINT32 size = slot->common_get_size("rom");
UINT32 size = slot->common_get_size("rom");
if (size > 0x20000) // Max 128Kb
{
LOG( printf("Cartridge size exceeding max size (128Kb): %d\n", size) );
image.seterror(IMAGE_ERROR_UNSPECIFIED, "Cartridge size exceeding max size (128Kb)");
return IMAGE_INIT_FAIL;
}
if (size > 0x20000) // Max 128Kb
{
LOG( printf("Cartridge size exceeding max size (128Kb): %d\n", size) );
image.seterror(IMAGE_ERROR_UNSPECIFIED, "Cartridge size exceeding max size (128Kb)");
return IMAGE_INIT_FAIL;
}
slot->rom_alloc(size, GENERIC_ROM16_WIDTH, ENDIANNESS_BIG);
slot->common_load_rom(slot->get_rom_base(), size, "rom");
return IMAGE_INIT_PASS;
slot->rom_alloc(size, GENERIC_ROM16_WIDTH, ENDIANNESS_BIG);
slot->common_load_rom(slot->get_rom_base(), size, "rom");
return IMAGE_INIT_PASS;
}
/*
@ -427,7 +427,7 @@ static MACHINE_CONFIG_START (fccpu1, force68k_state)
MCFG_CPU_ADD ("maincpu", M68000, XTAL_16MHz / 2)
MCFG_CPU_PROGRAM_MAP (force68k_mem)
/* P3/Host Port config
/* P3/Host Port config
* LO command causes ROM monitor to expect S-records on HOST port by default
* Implementation through nullmodem currently does not support handshakes so
* the ROM momitor is over-run while checking for checksums etc if used with
@ -535,7 +535,7 @@ ROM_LOAD16_BYTE ("fccpu1V1.0L.j9.bin", 0x080000, 0x2000, CRC (035315fb) SHA1 (90
* DC <expression> <CR> Data Conversion
* DF <CR> Display Formatted registers
* DU [n] <address1> <address2>[<string>] <CR> Dump memory to object file
* GO or G [<address] <CR> Execute program.
* GO or G [<address] <CR> Execute program.
* GD [<address] <CR> Go Direct
* GT <address> <CR> Exec prog: temporary breakpoint
* HE<CR> Help; display monitor commands

110
src/mess/drivers/hk68v10.c
View File

@ -8,18 +8,18 @@
*
* I baught this board from http://www.retrotechnology.com without documentation.
* It has a Motorola 68010 CPU @ 10MHz and two 2764 EPROMS with HBUG firmware
* The board is very populated and suitable to run a real server OS supported by
* FPU,MMU and DMA controller chips. The firmware supports SCSI, Centronics/FPI
* and a serial port. I have not found so much on the FPI interface yet and it is
* The board is very populated and suitable to run a real server OS supported by
* FPU,MMU and DMA controller chips. The firmware supports SCSI, Centronics/FPI
* and a serial port. I have not found so much on the FPI interface yet and it is
* possibly Heurikon specific. There is also a Heurikon Multibus board called
* HK68/M10 for which I might add support from specs, however would need a ROM
* to verify.
*
* ||
* || ||
* ||||--||
* ||||--||
* || ||____________________________________________________________ ___
*
* ||
* || ||
* ||||--||
* ||||--||
* || ||____________________________________________________________ ___
* || | | | 12 PALs 68/V-... | | | | | |_| |
* || | | 2 x | |74 |74 |74 |74 | | | |
* || | | 74273 | VS4-01 VM4-00 | 244 573 645 645 | | |
@ -37,14 +37,14 @@
* || |paral| | FPU || | | | | | | |
* || |Z8536| |_________||_________________|_ _| | | |_| |
* ||| | | | | | | ------------ |___|
* /==||| | | | | | | | 3 PALs | |
* FSM || | | | MC68010 | MC68451 | MC68450 | | MP1-00 | |
* 1234 || | | | CPU | MMU | DMA | | MX2-00 | |
* LEDs || |-----| |_________|__________|_________|__| MX1-01 |---|
* || | | ____ ____ ---| |__________|74 |
* \==||| | | | | | | |74| 4 x | 3 PALs |145|
* ||| |SCC | | | | | |804 74245 | CS3-00 |___|
* FPI || |seria| |U12 | |U23 | | | | CS2-00 | |
* /==||| | | | | | | | 3 PALs | |
* FSM || | | | MC68010 | MC68451 | MC68450 | | MP1-00 | |
* 1234 || | | | CPU | MMU | DMA | | MX2-00 | |
* LEDs || |-----| |_________|__________|_________|__| MX1-01 |---|
* || | | ____ ____ ---| |__________|74 |
* \==||| | | | | | | |74| 4 x | 3 PALs |145|
* ||| |SCC | | | | | |804 74245 | CS3-00 |___|
* FPI || |seria| |U12 | |U23 | | | | CS2-00 | |
* paralell |Z8530A |HBUG| |HBUG| | | | CS1-00 | |___
* port || | | | | | | ---_---------------|__________| _| |
* || | | | | | | |MTTLDL|MDLDM| 2 x |___________ | | |
@ -64,15 +64,15 @@
* || | each || RFS-01 |590|257 | | | |
* ||| | || RCT-01 | | | | |_| |
* /==||| +--------+|__________________________|___|__|__________| |___|
* || ||------------------------------------------------------------+-+
* ||||--||
* ||||--||
* || ||------------------------------------------------------------+-+
* ||||--||
* ||||--||
* ||
*
* History of Heurikon
*---------------------
* The company was founded 1972 as cellar company. Heurikon was aquired
* 1989 by Computer Products, 1990 by Artesyn and finally in 2005 by Emerson
* The company was founded 1972 as cellar company. Heurikon was aquired
* 1989 by Computer Products, 1990 by Artesyn and finally in 2005 by Emerson
* Electric who consilidated it fully by 2009 and closed the office.
*
* Misc links about Heurikon and this board:
@ -116,13 +116,13 @@
* (open)
* 0x*00000 (maxmeml)
* RAM (bus) (optional)
* 0x200000 (top of 2 meg RAM)
* 0x200000 (top of 2 meg RAM)
* RAM (bus) (optional)
* 0x100000 (top of 1 meg RAM)
* User RAM
* 0x001000 UNIX Kernel
* Exception Vectors
* 0x000000 (bottom of memory)
* 0x000000 (bottom of memory)
* --------------------------------------------------------------------------
*
* Interrupt sources M10/V10
@ -130,8 +130,8 @@
* Description Device Lvl IRQ VME board
* /Board Vector Address
* ----------------------------------------------------------
* On board Sources M10/V10
*
* On board Sources M10/V10
*
* Off board Sources (other VME boards)
* EXOS Ethernet 5 4
* TapeMaster Reel-to-Reel Tape 3
@ -198,9 +198,9 @@ class hk68v10_state : public driver_device
{
public:
hk68v10_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device (mconfig, type, tag),
m_maincpu (*this, "maincpu")
,m_sccterm(*this, "scc")
driver_device (mconfig, type, tag),
m_maincpu (*this, "maincpu")
,m_sccterm(*this, "scc")
// ,m_cart(*this, "exp_rom1")
{
}
@ -222,8 +222,8 @@ required_device<cpu_device> m_maincpu;
required_device<scc8530_device> m_sccterm;
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
UINT16 *m_sysrom;
UINT16 m_sysram[4];
UINT16 *m_sysrom;
UINT16 m_sysram[4];
};
static ADDRESS_MAP_START (hk68v10_mem, AS_PROGRAM, 16, hk68v10_state)
@ -233,7 +233,7 @@ AM_RANGE (0x000000, 0x000007) AM_RAM AM_WRITE (bootvect_w) /* After first
AM_RANGE (0x000008, 0x1fffff) AM_RAM /* 2 Mb RAM */
AM_RANGE (0xFC0000, 0xFC3fff) AM_ROM /* System EPROM Area 16Kb HBUG */
AM_RANGE (0xFC4000, 0xFDffff) AM_ROM /* System EPROM Area an additional 112Kb for System ROM */
AM_RANGE (0xFE9000, 0xFE9009) AM_RAM //AM_DEVREADWRITE8("scc", scc8530_device, ba_cd_r, ba_cd_w, 0xffff) /* Z80-PIO? */
AM_RANGE (0xFE9000, 0xFE9009) AM_RAM //AM_DEVREADWRITE8("scc", scc8530_device, ba_cd_r, ba_cd_w, 0xffff) /* Z80-PIO? */
AM_RANGE (0xFEA000, 0xFEA001) AM_DEVREADWRITE8("scc", scc8530_device, ca_r, ca_w, 0xff00) /* Dual serial port Z80-SCC */
AM_RANGE (0xFEA002, 0xFEA003) AM_DEVREADWRITE8("scc", scc8530_device, cb_r, cb_w, 0xff00) /* Dual serial port Z80-SCC */
AM_RANGE (0xFEA004, 0xFEA005) AM_DEVREADWRITE8("scc", scc8530_device, da_r, da_w, 0xff00) /* Dual serial port Z80-SCC */
@ -249,13 +249,13 @@ INPUT_PORTS_END
/* Start it up */
void hk68v10_state::machine_start ()
{
LOG (("%" I64FMT "d %s\n", m_maincpu->total_cycles(), FUNCNAME));
LOG (("%" I64FMT "d %s\n", m_maincpu->total_cycles(), FUNCNAME));
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0x0fc0000);
}
/* Support CPU resets
/* Support CPU resets
TODO: Investigate why the user need two 'softreset' commands for the below to work. Eg F3 + F11 + F3 + F11
If only one 'softreset' is given the reset PC gets the RAM content, not the intended ROM vector.
@ -263,50 +263,50 @@ void hk68v10_state::machine_start ()
*/
void hk68v10_state::machine_reset ()
{
LOG (("%" I64FMT "d %s\n", m_maincpu->total_cycles(), FUNCNAME));
LOG (("%" I64FMT "d %s\n", m_maincpu->total_cycles(), FUNCNAME));
/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0x0fc0000);
/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0x0fc0000);
}
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xfc0000 to 0x0 at reset*/
/*
Right after HBUG reset the bootvector is masked by RAM:
/*
Right after HBUG reset the bootvector is masked by RAM:
FC001C: move.w #$700, $fe4000.l
FC0024: move.l #$0, $0.l # <- zeroing the reset vector
FC002E: move.l #$0, $4.l # There is for sure some hardware mapping going in here
*/
READ16_MEMBER (hk68v10_state::bootvect_r){
//LOG (("bootvect_r %s\n", m_sysrom != &m_sysram[0] ? "as reset" : "as swapped"));
return m_sysrom[offset];
//LOG (("bootvect_r %s\n", m_sysrom != &m_sysram[0] ? "as reset" : "as swapped"));
return m_sysrom[offset];
}
WRITE16_MEMBER (hk68v10_state::bootvect_w){
LOG (("bootvect_w offset %08x, mask %08x, data %04x\n", offset, mem_mask, data));
m_sysram[offset % sizeof(m_sysram)] &= ~mem_mask;
m_sysram[offset % sizeof(m_sysram)] |= (data & mem_mask);
m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset.
LOG (("bootvect_w offset %08x, mask %08x, data %04x\n", offset, mem_mask, data));
m_sysram[offset % sizeof(m_sysram)] &= ~mem_mask;
m_sysram[offset % sizeof(m_sysram)] |= (data & mem_mask);
m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset.
}
#if 0
/* Dummy VME access methods until the VME bus device is ready for use */
READ16_MEMBER (hk68v10_state::vme_a24_r){
LOG (("vme_a24_r\n"));
return (UINT16) 0;
LOG (("vme_a24_r\n"));
return (UINT16) 0;
}
WRITE16_MEMBER (hk68v10_state::vme_a24_w){
LOG (("vme_a24_w\n"));
LOG (("vme_a24_w\n"));
}
READ16_MEMBER (hk68v10_state::vme_a16_r){
LOG (("vme_16_r\n"));
return (UINT16) 0;
LOG (("vme_16_r\n"));
return (UINT16) 0;
}
WRITE16_MEMBER (hk68v10_state::vme_a16_w){
LOG (("vme_a16_w\n"));
LOG (("vme_a16_w\n"));
}
#endif
@ -334,8 +334,8 @@ WRITE16_MEMBER (hk68v10_state::vme_a16_w){
*
*/
WRITE_LINE_MEMBER (hk68v10_state::write_sccterm_clock){
m_sccterm->txca_w (state);
m_sccterm->rxca_w (state);
m_sccterm->txca_w (state);
m_sccterm->rxca_w (state);
}
/*

4
src/mess/drivers/hp64k.c
View File

@ -406,7 +406,7 @@ void hp64k_state::machine_reset()
m_floppy0_wpt = false;
m_floppy1_wpt = false;
m_beeper->set_state(0);
m_baud_rate->str_w((m_s5_sw->read() >> 1) & 0xf);
m_baud_rate->str_w((m_s5_sw->read() >> 1) & 0xf);
m_16x_clk = (m_rs232_sw->read() & 0x02) != 0;
m_loopback = false;
m_txd_state = true;
@ -1389,7 +1389,7 @@ static MACHINE_CONFIG_START(hp64k , hp64k_state)
MCFG_TIMER_DRIVER_ADD("beep_timer" , hp64k_state , hp64k_beeper_off);
MCFG_DEVICE_ADD("baud_rate" , COM8116 , XTAL_5_0688MHz)
MCFG_COM8116_FR_HANDLER(WRITELINE(hp64k_state , hp64k_baud_clk_w));
MCFG_COM8116_FR_HANDLER(WRITELINE(hp64k_state , hp64k_baud_clk_w));
MCFG_DEVICE_ADD("uart" , I8251 , 0)
MCFG_I8251_RXRDY_HANDLER(WRITELINE(hp64k_state , hp64k_rxrdy_w));

2
src/mess/drivers/lg-dvd.c
View File

@ -12,7 +12,7 @@ class lg_dvd_state : public driver_device {
public:
lg_dvd_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
maincpu(*this, "maincpu")
maincpu(*this, "maincpu")
{ }
required_device<i80c52_device> maincpu;

10
src/mess/drivers/mps1230.c
View File

@ -5,9 +5,9 @@
mps1230.c - Commodore MPS-1230 dot-matrix printer
Skeleton made September, 2015 by R. Belmont
-------------------------------------
-------------------------------------
Commodore MPS-1230 Dot Matrix Printer
Commodore 1988/89
@ -74,7 +74,7 @@ Notes: (all IC's shown)
J899 - 15-pin connector for ribbon cable for console buttons and leds (feed, online etc)
J369 - 36-pin centronics parallel connector
J02G - 6-pin Commodore serial bus connector
************************************************************************/
#include "emu.h"
@ -121,7 +121,7 @@ void mps1230_state::machine_reset()
static ADDRESS_MAP_START( mps1230_map, AS_PROGRAM, 8, mps1230_state )
AM_RANGE(0x0000, 0x7fff) AM_ROM AM_REGION("mps1230", 0)
AM_RANGE(0xc000, 0xdfff) AM_RAM // as per the service manual
AM_RANGE(0xc000, 0xdfff) AM_RAM // as per the service manual
AM_RANGE(0xff00, 0xffff) AM_RAM // tested at PC=77, then used for the 7810's stack
ADDRESS_MAP_END

100
src/mess/drivers/mvme350.c
View File

@ -2,22 +2,22 @@
// copyright-holders:Joakim Larsson Edstrom
/***************************************************************************
*
* Motorola MVME-350 6U Intelligent Tape Controller driver, initially derived
* Motorola MVME-350 6U Intelligent Tape Controller driver, initially derived
* from hk68v10.c
*
* 31/08/2015
*
* I baught this board from http://www.retrotechnology.com without documentation.
* It has a Motorola 68010 CPU @ 10MHz, 128 Mb RAM and two 2764 EPROMS with
* It has a Motorola 68010 CPU @ 10MHz, 128 Mb RAM and two 2764 EPROMS with
* QIC-02 tape controller firmware. The board also populates a 68230 PIT and loads
* of descrete TTL components.
*
*
* ||
* || ||
* ||||--||
* ||||--||
* || ||__________________________________________________________ ___
*
* ||
* || ||
* ||||--||
* ||||--||
* || ||__________________________________________________________ ___
* ||_______________________________________________________ |_| |
* || |74F74 | xxxxx | xxxxx | 74LS245 | 74ALS645| | | |
* || |______|________|_________|___________| ________| | | |
@ -35,14 +35,14 @@
* ||| | |______| __|_______________________|---------| | | |
* ||| | |74LS74| |25LS251 | | RAM |74S244 | |_| |
* ||+---+ ---------- |---------- | HM6264P-12 |---------| |___|
* || | PAL | | 74245 | |______________|74S244 | |
* || +--------- |_________| | U40 27128 |---------| |
* || | 74F32 | | || System ROM |74LS682 | |
* Red || +-------- | CPU || |-+-------| |
* FAIL ||LED | 74F138| | MC68010 |+--------------+ |DIPSW__| |
* Red || +-------- | || RAM | |74S38 | |
* HALT ||LED | 74F32 | |__________|| HM6264P-12 | |______ | |
* Green || +-------+ |74245 |+--------------+ |74F08 | |
* || | PAL | | 74245 | |______________|74S244 | |
* || +--------- |_________| | U40 27128 |---------| |
* || | 74F32 | | || System ROM |74LS682 | |
* Red || +-------- | CPU || |-+-------| |
* FAIL ||LED | 74F138| | MC68010 |+--------------+ |DIPSW__| |
* Red || +-------- | || RAM | |74S38 | |
* HALT ||LED | 74F32 | |__________|| HM6264P-12 | |______ | |
* Green || +-------+ |74245 |+--------------+ |74F08 | |
* RUN ||LED |XTAL | |__________|| U47 27128 | |______ | |___
* ||+---+|20MHz | |74244 || System ROM | |74F00 | _| |
* |||CON|--------+___|__________|+--------------+_|_______| | | |
@ -62,24 +62,24 @@
* || +------------------------------------------+------| | | |
* || |DM2353 |74F10 |74F32 | 74LS32| 74F08 |DM2353| |_| |
* || +------------------------------------------+------+-+ |___|
* || ||------------------------------------------------------------+-+
* ||||--||
* ||||--||
* || ||------------------------------------------------------------+-+
* ||||--||
* ||||--||
* ||
*
* History of Motorola VME division (https://en.wikipedia.org/wiki/VMEbus)
*---------------------------------
* When Motorola released the 68000 processor 1979 the ambition of the deisgners
* was also to standardize a versatile CPU bus to be able to build computer
* was also to standardize a versatile CPU bus to be able to build computer
* systems without constructing PCB:s from scratch. This become VersaBus but the
* boards was really too big and the computer world already saw the systems shrink
* in size. Motorola's design center in Munich proposed to use the smaller and
* already used Euroboard form factor and call it Versabus-E. This later became
* VME which was standardized in the VITA organization 1981
* VME which was standardized in the VITA organization 1981
*
* Misc links about Motorola VME division and this board:
* Misc links about Motorola VME division and this board:
* http://bitsavers.trailing-edge.com/pdf/motorola/_dataBooks/1987_Microcomputer_Systems_and_Components.pdf
*
*
* Description
* ------------
* Streaming Tape Controller released 1984 with the following feature set
@ -100,7 +100,7 @@
* - High Level Command/Status Packets offer efficient Operating System Support
* - Permits Chaining of Host Command
*
* Address Map
* Address Map
* --------------------------------------------------------------------------
* Local to VME Decscription
* --------------------------------------------------------------------------
@ -117,8 +117,8 @@
* Description Device Lvl IRQ VME board
* /Board Vector Address
* ----------------------------------------------------------
* On board Sources
*
* On board Sources
*
* Off board Sources (other VME boards)
*
* ----------------------------------------------------------
@ -149,9 +149,9 @@ class mvme350_state : public driver_device
{
public:
mvme350_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device (mconfig, type, tag),
m_maincpu (*this, "maincpu"),
m_pit(*this, "pit")
driver_device (mconfig, type, tag),
m_maincpu (*this, "maincpu"),
m_pit(*this, "pit")
{
}
@ -164,19 +164,19 @@ virtual void machine_reset ();
protected:
private:
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_maincpu;
required_device<pit68230_device> m_pit;
};
static ADDRESS_MAP_START (mvme350_mem, AS_PROGRAM, 16, mvme350_state)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE (0x000000, 0x01ffff) AM_ROM /* 128 Mb ROM */
AM_RANGE (0x020000, 0x03ffff) AM_RAM /* 128 Mb RAM */
AM_RANGE (0x000000, 0x01ffff) AM_ROM /* 128 Mb ROM */
AM_RANGE (0x020000, 0x03ffff) AM_RAM /* 128 Mb RAM */
#if 1
AM_RANGE(0x040000, 0x040035) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0x00ff) /* PIT ?*/
AM_RANGE(0x060000, 0x06001f) AM_RAM /* Area is cleared on start */
AM_RANGE(0x080000, 0x080035) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0x00ff) /* PIT ?*/
AM_RANGE(0x040000, 0x040035) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0x00ff) /* PIT ?*/
AM_RANGE(0x060000, 0x06001f) AM_RAM /* Area is cleared on start */
AM_RANGE(0x080000, 0x080035) AM_DEVREADWRITE8("pit", pit68230_device, read, write, 0x00ff) /* PIT ?*/
#endif
//AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
//AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) - not verified */
@ -189,32 +189,32 @@ INPUT_PORTS_END
/* Start it up */
void mvme350_state::machine_start ()
{
LOG (logerror ("machine_start\n"));
LOG (logerror ("machine_start\n"));
}
void mvme350_state::machine_reset ()
{
LOG (logerror ("machine_reset\n"));
LOG (logerror ("machine_reset\n"));
}
#if 0
/* Dummy VME access methods until the VME bus device is ready for use */
READ16_MEMBER (mvme350_state::vme_a24_r){
LOG (logerror ("vme_a24_r\n"));
return (UINT16) 0;
LOG (logerror ("vme_a24_r\n"));
return (UINT16) 0;
}
WRITE16_MEMBER (mvme350_state::vme_a24_w){
LOG (logerror ("vme_a24_w\n"));
LOG (logerror ("vme_a24_w\n"));
}
READ16_MEMBER (mvme350_state::vme_a16_r){
LOG (logerror ("vme_16_r\n"));
return (UINT16) 0;
LOG (logerror ("vme_16_r\n"));
return (UINT16) 0;
}
WRITE16_MEMBER (mvme350_state::vme_a16_w){
LOG (logerror ("vme_a16_w\n"));
LOG (logerror ("vme_a16_w\n"));
}
#endif
@ -222,10 +222,10 @@ WRITE16_MEMBER (mvme350_state::vme_a16_w){
* Machine configuration
*/
static MACHINE_CONFIG_START (mvme350, mvme350_state)
/* basic machine hardware */
MCFG_CPU_ADD ("maincpu", M68010, XTAL_10MHz)
MCFG_CPU_PROGRAM_MAP (mvme350_mem)
/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
/* basic machine hardware */
MCFG_CPU_ADD ("maincpu", M68010, XTAL_10MHz)
MCFG_CPU_PROGRAM_MAP (mvme350_mem)
/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
MCFG_DEVICE_ADD("pit", PIT68230, XTAL_16MHz / 2)
MACHINE_CONFIG_END
@ -243,11 +243,11 @@ ROM_LOAD16_BYTE ("mvme350U47v2.3.bin", 0x0001, 0x4000, CRC (582ce095) SHA1 (d092
* The ROMs known commands from different sources:
*
* It communicates with the master through data buffers in shared memory and VME bus interrupts
* as desribed in
* as desribed in
* http://bitsavers.trailing-edge.com/pdf/motorola/_dataBooks/1987_Microcomputer_Systems_and_Components.pdf
*
*
* The board is pretty boring as stand alone, it initializes everything and then executes a STOP instruction
* awaiting a CPU on the VME bus to request its services. However, it enables boot from tape devices, we just
* awaiting a CPU on the VME bus to request its services. However, it enables boot from tape devices, we just
* need a MVME-131 and a dump of a VersaDOS or Motorola UNIX System V system tape and some work.
*/
ROM_END

184
src/mess/drivers/mzr8105.c
View File

@ -1,5 +1,5 @@
// license:BSD-3-Clause
// copyright-holders:Joakim Larsson Edstr??m
// copyright-holders:Joakim Larsson Edstrom
/***************************************************************************
*
* Mizar VME8105 rev D 3U SBC driver, initially derived from force68k.c
@ -10,13 +10,13 @@
* It has a Motorola 68000 CPU @ 10MHz and two 27128 EPROMS with OS9 DEBUG labels
* and not much more except 16 or so TTLs, 2 PALs and a VME P1 connector. It is a
* 2 sided design so it shold be possible to trace the schematics quite easily.
* There is a date on the P1 Connector: "Feb 20 1987"
*
* ||
* ||
* ||
* ||
* ||____________________________________________________________ ___
* There is a date on the P1 Connector: "Feb 20 1987"
*
* ||
* ||
* ||
* ||
* ||____________________________________________________________ ___
* || --------------K2|U6-7432|U7-7474|U14-7405|U21-74645 | |_| |
* || | 2764 - low |-+-------+-------+--------+-----------+ | | |
* || | OS9 DEBUG U4| +---------+ +--------+---------+ | | |
@ -34,40 +34,40 @@
* || | | | |XTAL |U9-7410+---------+| || | |
* ||K1 | U1| | |FOX100-------+---------+|K5||_| |
* || -------------- |_________|10MHz|U8-7404|U15-74148|| || |___|
* ||--||--------------------------------+----+-------+---------++--+
* ||--||
* ||
* ||--||--------------------------------+----+-------+---------++--+
* ||--||
* ||
*
* PAL:s
*------
* The board has two PAL:s, a PAL20L10 and a PAL14L4.
* The board has two PAL:s, a PAL20L10 and a PAL14L4.
*
* _____ _____
* OD/CLK 1 |* \_/ | 20 VCC
* OD/CLK 1 |* \_/ | 20 VCC
* CPU A13 I0 2 | | 19 O0/LR A23
* U9 7410p12 I1 3 | | 18 O1/A0 A22
* CPU *AS I2 4 | | 17 02/A1 U2/U4 2764p22 *OE
* GND I3 5 | | 16 03/A2 U11 PAL20L10p6 I4
* CPU A14 I4 6 | U10 | 15 A0/O0 U11 PAL20L10p7 I5
* CPU A15 I5 7 | PAL14L4 | 14 A1/O1 U19 74LS244p11 I0b
* CPU A16 I6 8 | | 13 A2/O2 A18
* CPU A16 I6 8 | | 13 A2/O2 A18
* CPU A17 I7 9 | | 12 LR/O3 A20
* GND 10 |_____________| 11 CLK/OD A21
*
*
* _____ _____
* OD/CLK 1 |* \_/ | 24 VCC
* I0 2 | | 23 O0/LR
* CPU *AS I1 3 | | 22 O1/A0
* U10 PAL14L4p3 I2 4 | | 21 02/A1
* I3 5 | | 20 03/A2
* U10 PAL14L4p16 I4 6 | U10 | 19 04/NC
* U10 PAL14L4p15 I5 7 | PAL20L10 | 18 NC/O0
* I6 8 | | 17 A2/O1
* I7 9 | | 16 A1/O2
* I8 10 | | 15 A0/O3
* I9 11 | | 14 LR/O4
* GND 12 |_____________| 13 CLK/OD
*
* OD/CLK 1 |* \_/ | 24 VCC
* I0 2 | | 23 O0/LR
* CPU *AS I1 3 | | 22 O1/A0
* U10 PAL14L4p3 I2 4 | | 21 02/A1
* I3 5 | | 20 03/A2
* U10 PAL14L4p16 I4 6 | U10 | 19 04/NC
* U10 PAL14L4p15 I5 7 | PAL20L10 | 18 NC/O0
* I6 8 | | 17 A2/O1
* I7 9 | | 16 A1/O2
* I8 10 | | 15 A0/O3
* I9 11 | | 14 LR/O4
* GND 12 |_____________| 13 CLK/OD
*
* Trace is not fully completed and validated.
*
* History of Mizar
@ -81,27 +81,27 @@
*
* From http://archive.org/stream/68micro-vol-11-num-02/V11N02_Feb1989_djvu.txt :
*--------------------------------------------------------------------------------
* " Mizar provides complete OS-9 solutions for the VMEbus. Mizar's VME CPUs
* offer (he functions and performance your application demands. Our single
* height (3U) VME processors are uniquely configurable computing engines,
* Through Mizar's unique MXbus™ expansion interface, standard and custom side
* modules can be added to basic processors to create double-height (6U) boards
* tor specific applications, 3U CPU options include 68010, 66020, and 63030
* microprocessors, up to one MB of DRAM, serial I/O, real-time clock, and
* mailbox interrupt support. Standard MXbus side modules include additional DRAM.
* SRAM, and I/O.
* " Mizar provides complete OS-9 solutions for the VMEbus. Mizar's VME CPUs
* offer (he functions and performance your application demands. Our single
* height (3U) VME processors are uniquely configurable computing engines,
* Through Mizar's unique MXbus expansion interface, standard and custom side
* modules can be added to basic processors to create double-height (6U) boards
* tor specific applications, 3U CPU options include 68010, 66020, and 63030
* microprocessors, up to one MB of DRAM, serial I/O, real-time clock, and
* mailbox interrupt support. Standard MXbus side modules include additional DRAM.
* SRAM, and I/O.
*
* Mizar's standard double- height (6U) processors provide additional features such
* as a high-speed cache to enhance 68030 performance, floating, point coprocessor
* support, up to four MB dual ported DRAM, VSB memory interface, Ethernet, and SCSI.
* Mizar's standard double- height (6U) processors provide additional features such
* as a high-speed cache to enhance 68030 performance, floating, point coprocessor
* support, up to four MB dual ported DRAM, VSB memory interface, Ethernet, and SCSI.
*
* Mizar also supports OS-9 with completely configured OS9 development systems and
* OS-9 application server systems. For more information, call Mizar today
* Mizar also supports OS-9 with completely configured OS9 development systems and
* OS-9 application server systems. For more information, call Mizar today
*
* 800-635-0200 MIZAR 1419 Dunn Drive • CarrolHon, TX 75006 • 214-446-2664"
* 800-635-0200 MIZAR 1419 Dunn Drive CarrolHon, TX 75006 214-446-2664"
*
* Known boards from Mizar:
*
*
*-Comp.Os.Vxworks diguest mailing list May 1992: VxWorks Drivers Available from Mizar:
* EMX 7320 Serial I/O Board
* EMX 7550 Ethernet Controller Board (AMD 7990 Lance) MAC: 00:80:F8 MIZAR, INC.
@ -121,9 +121,9 @@
*--------------------------------------------------------------------
* Aug 20 1984 a report by James Jones from the OS/9 conferance in Des Moines:
* "...
* Mizar: is selling VME bus 68010 boards, running OS-9/68000; they also make
* various memory and I/O boards, disk controller boards, and and a NEC 7220-based
* graphics controller board...."
* Mizar: is selling VME bus 68010 boards, running OS-9/68000; they also make
* various memory and I/O boards, disk controller boards, and and a NEC 7220-based
* graphics controller board...."
*
* Misc links about Mizar:
* http://www.vita.com/History
@ -134,10 +134,10 @@
* --------------------------------------------------------------------------
* Address Range Description/Assumption
* --------------------------------------------------------------------------
* 0x000000 0x01ffff ROM because of fixed vectors
* 0x020000 0x03ffff RAM because bootvector stack starts at 0x21000
* 0x000000 0x01ffff ROM because of fixed vectors
* 0x020000 0x03ffff RAM because bootvector stack starts at 0x21000
* -- VME adresses---
* 0xff0000 0xff0003 Bootstrap expects to find a UPD7201 serial device here
* 0xff0000 0xff0003 Bootstrap expects to find a UPD7201 serial device here
* --------------------------------------------------------------------------
*
* Interrupt sources
@ -164,7 +164,7 @@
#include "bus/rs232/rs232.h"
#include "machine/clock.h"
#define CARDSLOT 0
#define CARDSLOT 0
#if CARDSLOT // Awaiting info on how to boot the user eproms
#include "bus/generic/slot.h"
@ -173,7 +173,7 @@
#define LOG(x) x
/* These values are borrowed just to get the terminal going and should be replaced
* once a proper serial board hardware (ie MZ 8300) is found and emulated. */
#define BAUDGEN_CLOCK XTAL_19_6608MHz /* fake */
@ -183,9 +183,9 @@ class mzr8105_state : public driver_device
{
public:
mzr8105_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device (mconfig, type, tag),
m_maincpu (*this, "maincpu")
,m_updterm(*this, "upd")
driver_device (mconfig, type, tag),
m_maincpu (*this, "maincpu")
,m_updterm(*this, "upd")
// ,m_cart(*this, "exp_rom1")
{
}
@ -231,10 +231,10 @@ AM_RANGE (0x020000, 0x03ffff) AM_RAM /* Not verified */
AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
//AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) - not verified */
// Faking a Mizar 8300 SIO BOARD in VME A16 adress space
AM_RANGE (0xFF0000, 0xFF0001) AM_DEVREADWRITE8("upd", upd7201_device, da_r, da_w, 0x00ff) /* Dual serial port NEC uPD7201 */
AM_RANGE (0xFF0002, 0xFF0003) AM_DEVREADWRITE8("upd", upd7201_device, ca_r, ca_w, 0x00ff) /* Dual serial port NEC uPD7201 */
AM_RANGE (0xFF0004, 0xFF0005) AM_DEVREADWRITE8("upd", upd7201_device, db_r, db_w, 0x00ff) /* Dual serial port NEC uPD7201 */
AM_RANGE (0xFF0006, 0xFF0007) AM_DEVREADWRITE8("upd", upd7201_device, cb_r, cb_w, 0x00ff) /* Dual serial port NEC uPD7201 */
AM_RANGE (0xFF0000, 0xFF0001) AM_DEVREADWRITE8("upd", upd7201_device, da_r, da_w, 0x00ff) /* Dual serial port NEC uPD7201 */
AM_RANGE (0xFF0002, 0xFF0003) AM_DEVREADWRITE8("upd", upd7201_device, ca_r, ca_w, 0x00ff) /* Dual serial port NEC uPD7201 */
AM_RANGE (0xFF0004, 0xFF0005) AM_DEVREADWRITE8("upd", upd7201_device, db_r, db_w, 0x00ff) /* Dual serial port NEC uPD7201 */
AM_RANGE (0xFF0006, 0xFF0007) AM_DEVREADWRITE8("upd", upd7201_device, cb_r, cb_w, 0x00ff) /* Dual serial port NEC uPD7201 */
ADDRESS_MAP_END
@ -245,49 +245,49 @@ INPUT_PORTS_END
/* Start it up */
void mzr8105_state::machine_start ()
{
LOG (logerror ("machine_start\n"));
LOG (logerror ("machine_start\n"));
#if CARDSLOT
/* Map user ROM/RAM socket(s) */
if (m_cart->exists())
{
m_usrrom = (UINT16*)m_cart->get_rom_base();
m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16_delegate(FUNC(generic_slot_device::read16_rom), (generic_slot_device*)m_cart));
}
/* Map user ROM/RAM socket(s) */
if (m_cart->exists())
{
m_usrrom = (UINT16*)m_cart->get_rom_base();
m_maincpu->space(AS_PROGRAM).install_read_handler(0xa0000, 0xbffff, read16_delegate(FUNC(generic_slot_device::read16_rom), (generic_slot_device*)m_cart));
}
#endif
}
/* Dummy VME access methods until the VME bus device is ready for use */
READ16_MEMBER (mzr8105_state::vme_a24_r){
LOG (logerror ("vme_a24_r\n"));
return (UINT16) 0;
LOG (logerror ("vme_a24_r\n"));
return (UINT16) 0;
}
WRITE16_MEMBER (mzr8105_state::vme_a24_w){
LOG (logerror ("vme_a24_w\n"));
LOG (logerror ("vme_a24_w\n"));
}
READ16_MEMBER (mzr8105_state::vme_a16_r){
LOG (logerror ("vme_16_r\n"));
return (UINT16) 0;
LOG (logerror ("vme_16_r\n"));
return (UINT16) 0;
}
WRITE16_MEMBER (mzr8105_state::vme_a16_w){
LOG (logerror ("vme_a16_w\n"));
LOG (logerror ("vme_a16_w\n"));
}
#if CARDSLOT
/*
* 4. The USER EPROM Area
* 4. The USER EPROM Area
*/
// Implementation of static 2 x 64K EPROM in sockets U1/U3 as 16 bit wide cartridge for easier
// Implementation of static 2 x 64K EPROM in sockets U1/U3 as 16 bit wide cartridge for easier
// software handling. TODO: make configurable according to table above.
static MACHINE_CONFIG_FRAGMENT( mzr8105_eprom_sockets )
MCFG_GENERIC_CARTSLOT_ADD("exp_rom1", generic_plain_slot, "mzr8105_cart")
MCFG_GENERIC_EXTENSIONS("bin,rom")
MCFG_GENERIC_WIDTH(GENERIC_ROM16_WIDTH)
MCFG_GENERIC_ENDIAN(ENDIANNESS_BIG)
MCFG_GENERIC_LOAD(mzr8105_state, exp1_load)
MCFG_GENERIC_CARTSLOT_ADD("exp_rom1", generic_plain_slot, "mzr8105_cart")
MCFG_GENERIC_EXTENSIONS("bin,rom")
MCFG_GENERIC_WIDTH(GENERIC_ROM16_WIDTH)
MCFG_GENERIC_ENDIAN(ENDIANNESS_BIG)
MCFG_GENERIC_LOAD(mzr8105_state, exp1_load)
// MCFG_SOFTWARE_LIST_ADD("cart_list", "mzr8105_cart")
MACHINE_CONFIG_END
@ -296,25 +296,25 @@ MACHINE_CONFIG_END
****************************/
int mzr8105_state::mzr8105_load_cart(device_image_interface &image, generic_slot_device *slot)
{
UINT32 size = slot->common_get_size("rom");
UINT32 size = slot->common_get_size("rom");
if (size > 0x20000) // Max 128Kb - not verified
{
LOG( printf("Cartridge size exceeding max size (128Kb): %d\n", size) );
image.seterror(IMAGE_ERROR_UNSPECIFIED, "Cartridge size exceeding max size (128Kb)");
return IMAGE_INIT_FAIL;
}
if (size > 0x20000) // Max 128Kb - not verified
{
LOG( printf("Cartridge size exceeding max size (128Kb): %d\n", size) );
image.seterror(IMAGE_ERROR_UNSPECIFIED, "Cartridge size exceeding max size (128Kb)");
return IMAGE_INIT_FAIL;
}
slot->rom_alloc(size, GENERIC_ROM16_WIDTH, ENDIANNESS_BIG);
slot->common_load_rom(slot->get_rom_base(), size, "rom");
return IMAGE_INIT_PASS;
slot->rom_alloc(size, GENERIC_ROM16_WIDTH, ENDIANNESS_BIG);
slot->common_load_rom(slot->get_rom_base(), size, "rom");
return IMAGE_INIT_PASS;
}
#endif
WRITE_LINE_MEMBER (mzr8105_state::write_updterm_clock){
m_updterm->txca_w (state);
m_updterm->rxca_w (state);
m_updterm->txca_w (state);
m_updterm->rxca_w (state);
}
/*

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