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z80dart: Replace old device with new variant of modern SIO emulation

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z80sio: Make LOGBIT less spammy; booleanize a few members (nw)

machine/mtx.cpp: Remove unnecessary includes (nw)
This commit is contained in:
AJR 2020-02-29 22:45:20 -05:00
parent d502c5a880
commit 8e52be5c1e
37 changed files with 176 additions and 1788 deletions
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12
scripts/src/machine.lua
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@ -3335,18 +3335,6 @@ if (MACHINES["Z80CTC"]~=null) then
}
end
---------------------------------------------------
--
--@src/devices/machine/z80dart.h,MACHINES["Z80DART"] = true
---------------------------------------------------
if (MACHINES["Z80DART"]~=null) then
files {
MAME_DIR .. "src/devices/machine/z80dart.cpp",
MAME_DIR .. "src/devices/machine/z80dart.h",
}
end
---------------------------------------------------
--
--@src/devices/machine/z80sio.h,MACHINES["Z80SIO"] = true

1
scripts/target/mame/arcade.lua
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@ -650,7 +650,6 @@ MACHINES["X2212"] = true
MACHINES["X76F041"] = true
MACHINES["X76F100"] = true
MACHINES["Z80CTC"] = true
MACHINES["Z80DART"] = true
MACHINES["Z80SIO"] = true
MACHINES["Z80SCC"] = true
MACHINES["Z80DMA"] = true

1
scripts/target/mame/mess.lua
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@ -691,7 +691,6 @@ MACHINES["X76F100"] = true
MACHINES["YM2148"] = true
MACHINES["YM3802"] = true
MACHINES["Z80CTC"] = true
MACHINES["Z80DART"] = true
MACHINES["Z80SIO"] = true
MACHINES["Z80SCC"] = true
MACHINES["Z80DMA"] = true

2
src/devices/bus/abcbus/sio.h
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@ -7,7 +7,7 @@
#include "abcbus.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"

2
src/devices/bus/cpc/cpc_rs232.h
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@ -12,7 +12,7 @@
#pragma once
#include "cpcexp.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/pit8253.h"
#include "bus/rs232/rs232.h"

1
src/devices/bus/wangpc/mcc.h
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@ -12,7 +12,6 @@
#pragma once
#include "wangpc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"

1270
src/devices/machine/z80dart.cpp
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File diff suppressed because it is too large Load Diff

416
src/devices/machine/z80dart.h
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@ -1,416 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Curt Coder
/***************************************************************************
Z80-DART Dual Asynchronous Receiver/Transmitter emulation
****************************************************************************
_____ _____
D1 1 |* \_/ | 40 D0
D3 2 | | 39 D2
D5 3 | | 38 D4
D7 4 | | 37 D6
_INT 5 | | 36 _IORQ
IEI 6 | | 35 _CE
IEO 7 | | 34 B/_A
_M1 8 | | 33 C/_D
Vdd 9 | | 32 _RD
_W/RDYA 10 | Z80-DART | 31 GND
_RIA 11 | Z8470 | 30 _W/RDYB
RxDA 12 | | 29 _RIB
_RxCA 13 | | 28 RxDB
_TxCA 14 | | 27 _RxTxCB
TxDA 15 | | 26 TxDB
_DTRA 16 | | 25 _DTRB
_RTSA 17 | | 24 _RTSB
_CTSA 18 | | 23 _CTSB
_DCDA 19 | | 22 _DCDB
CLK 20 |_____________| 21 _RESET
***************************************************************************/
#ifndef MAME_MACHINE_Z80DART_H
#define MAME_MACHINE_Z80DART_H
#pragma once
#include "machine/z80daisy.h"
#include "diserial.h"
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
// ======================> z80dart_channel
class z80dart_device;
class z80dart_channel : public device_t,
public device_serial_interface
{
friend class z80dart_device; // FIXME: still accesses m_rr and m_wr directly in a couple of places
public:
enum
{
INT_TRANSMIT = 0,
INT_EXTERNAL,
INT_RECEIVE,
INT_SPECIAL
};
z80dart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
DECLARE_WRITE_LINE_MEMBER( write_rx );
DECLARE_WRITE_LINE_MEMBER( cts_w );
DECLARE_WRITE_LINE_MEMBER( dcd_w );
DECLARE_WRITE_LINE_MEMBER( ri_w );
DECLARE_WRITE_LINE_MEMBER( rxc_w );
DECLARE_WRITE_LINE_MEMBER( txc_w );
DECLARE_WRITE_LINE_MEMBER( sync_w );
uint8_t control_read();
void control_write(uint8_t data);
uint8_t data_read();
void data_write(uint8_t data);
void set_rxc(int rxc) { m_rxc = rxc; }
void set_txc(int txc) { m_txc = txc; }
void clr_interrupt_pending() { m_rr[0] &= ~RR0_INTERRUPT_PENDING; }
void set_interrupt_pending() { m_rr[0] |= RR0_INTERRUPT_PENDING; }
uint8_t get_vector() const { return m_rr[2]; }
void set_vector(uint8_t vector) { m_rr[2] = vector; }
bool get_status_vector() const { return m_wr[1] & WR1_STATUS_VECTOR; }
bool get_priority() const { return m_wr[2] & WR2_PRIORITY; }
protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
// device_serial_interface overrides
virtual void tra_callback() override;
virtual void tra_complete() override;
virtual void rcv_callback() override;
virtual void rcv_complete() override;
void receive_data(uint8_t data);
int m_rxc;
int m_txc;
// register state
uint8_t m_rr[3]; // read register
uint8_t m_wr[6]; // write register
enum
{
RR0_RX_CHAR_AVAILABLE = 0x01,
RR0_INTERRUPT_PENDING = 0x02,
RR0_TX_BUFFER_EMPTY = 0x04,
RR0_DCD = 0x08,
RR0_RI = 0x10,
RR0_SYNC_HUNT = 0x10, // not supported
RR0_CTS = 0x20,
RR0_TX_UNDERRUN = 0x40, // not supported
RR0_BREAK_ABORT = 0x80 // not supported
};
enum
{
RR1_ALL_SENT = 0x01,
RR1_RESIDUE_CODE_MASK = 0x0e, // not supported
RR1_PARITY_ERROR = 0x10,
RR1_RX_OVERRUN_ERROR = 0x20,
RR1_CRC_FRAMING_ERROR = 0x40,
RR1_END_OF_FRAME = 0x80 // not supported
};
enum
{
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38,
WR0_NULL = 0x00,
WR0_SEND_ABORT = 0x08, // not supported
WR0_RESET_EXT_STATUS = 0x10,
WR0_CHANNEL_RESET = 0x18,
WR0_ENABLE_INT_NEXT_RX = 0x20,
WR0_RESET_TX_INT = 0x28, // not supported
WR0_ERROR_RESET = 0x30,
WR0_RETURN_FROM_INT = 0x38, // not supported
WR0_CRC_RESET_CODE_MASK = 0xc0, // not supported
WR0_CRC_RESET_NULL = 0x00, // not supported
WR0_CRC_RESET_RX = 0x40, // not supported
WR0_CRC_RESET_TX = 0x80, // not supported
WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // not supported
};
enum
{
WR1_EXT_INT_ENABLE = 0x01,
WR1_TX_INT_ENABLE = 0x02,
WR1_STATUS_VECTOR = 0x04,
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
WR1_RX_INT_ALL = 0x18,
WR1_WRDY_ON_RX_TX = 0x20, // not supported
WR1_WRDY_FUNCTION = 0x40, // not supported
WR1_WRDY_ENABLE = 0x80 // not supported
};
enum
{
WR2_DATA_XFER_INT = 0x00, // not supported
WR2_DATA_XFER_DMA_INT = 0x01, // not supported
WR2_DATA_XFER_DMA = 0x02, // not supported
WR2_DATA_XFER_ILLEGAL = 0x03, // not supported
WR2_DATA_XFER_MASK = 0x03, // not supported
WR2_PRIORITY = 0x04, // not supported
WR2_MODE_8085_1 = 0x00, // not supported
WR2_MODE_8085_2 = 0x08, // not supported
WR2_MODE_8086_8088 = 0x10, // not supported
WR2_MODE_ILLEGAL = 0x18, // not supported
WR2_MODE_MASK = 0x18, // not supported
WR2_VECTORED_INT = 0x20, // not supported
WR2_PIN10_SYNDETB_RTSB = 0x80 // not supported
};
enum
{
WR3_RX_ENABLE = 0x01,
WR3_SYNC_CHAR_LOAD_INHIBIT= 0x02, // not supported
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
WR3_RX_CRC_ENABLE = 0x08, // not supported
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
WR3_AUTO_ENABLES = 0x20,
WR3_RX_WORD_LENGTH_MASK = 0xc0,
WR3_RX_WORD_LENGTH_5 = 0x00,
WR3_RX_WORD_LENGTH_7 = 0x40,
WR3_RX_WORD_LENGTH_6 = 0x80,
WR3_RX_WORD_LENGTH_8 = 0xc0
};
enum
{
WR4_PARITY_ENABLE = 0x01,
WR4_PARITY_EVEN = 0x02,
WR4_STOP_BITS_MASK = 0x0c,
WR4_STOP_BITS_1 = 0x04,
WR4_STOP_BITS_1_5 = 0x08, // not supported
WR4_STOP_BITS_2 = 0x0c,
WR4_SYNC_MODE_MASK = 0x30, // not supported
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
WR4_SYNC_MODE_SDLC = 0x20, // not supported
WR4_SYNC_MODE_EXT = 0x30, // not supported
WR4_CLOCK_RATE_MASK = 0xc0,
WR4_CLOCK_RATE_X1 = 0x00,
WR4_CLOCK_RATE_X16 = 0x40,
WR4_CLOCK_RATE_X32 = 0x80,
WR4_CLOCK_RATE_X64 = 0xc0
};
enum
{
WR5_TX_CRC_ENABLE = 0x01, // not supported
WR5_RTS = 0x02,
WR5_CRC16 = 0x04, // not supported
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_WORD_LENGTH_MASK = 0x60,
WR5_TX_WORD_LENGTH_5 = 0x00,
WR5_TX_WORD_LENGTH_6 = 0x40,
WR5_TX_WORD_LENGTH_7 = 0x20,
WR5_TX_WORD_LENGTH_8 = 0x60,
WR5_DTR = 0x80
};
void update_serial();
void set_dtr(int state);
void set_rts(int state);
int get_clock_mode();
stop_bits_t get_stop_bits();
int get_rx_word_length();
int get_tx_word_length();
// receiver state
util::fifo<uint8_t, 3> m_rx_data_fifo;
util::fifo<uint8_t, 3> m_rx_error_fifo;
uint8_t m_rx_error; // current receive error
int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received
int m_rx_break; // receive break condition
uint8_t m_rx_rr0_latch; // read register 0 latched
int m_rxd;
int m_ri; // ring indicator latch
int m_cts; // clear to send latch
int m_dcd; // data carrier detect latch
// transmitter state
uint8_t m_tx_data; // transmit data register
int m_tx_clock; // transmit clock pulse count
int m_dtr; // data terminal ready
int m_rts; // request to send
// synchronous state
uint16_t m_sync; // sync character
int m_index;
z80dart_device *m_uart;
};
// ======================> z80dart_device
class z80dart_device : public device_t,
public device_z80daisy_interface
{
friend class z80dart_channel;
public:
// construction/destruction
z80dart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
auto out_txda_callback() { return m_out_txda_cb.bind(); }
auto out_dtra_callback() { return m_out_dtra_cb.bind(); }
auto out_rtsa_callback() { return m_out_rtsa_cb.bind(); }
auto out_wrdya_callback() { return m_out_wrdya_cb.bind(); }
auto out_synca_callback() { return m_out_synca_cb.bind(); }
auto out_txdb_callback() { return m_out_txdb_cb.bind(); }
auto out_dtrb_callback() { return m_out_dtrb_cb.bind(); }
auto out_rtsb_callback() { return m_out_rtsb_cb.bind(); }
auto out_wrdyb_callback() { return m_out_wrdyb_cb.bind(); }
auto out_syncb_callback() { return m_out_syncb_cb.bind(); }
auto out_int_callback() { return m_out_int_cb.bind(); }
auto out_rxdrqa_callback() { return m_out_rxdrqa_cb.bind(); }
auto out_txdrqa_callback() { return m_out_txdrqa_cb.bind(); }
auto out_rxdrqb_callback() { return m_out_rxdrqb_cb.bind(); }
auto out_txdrqb_callback() { return m_out_txdrqb_cb.bind(); }
void configure_channels(int rxa, int txa, int rxb, int txb)
{
m_rxca = rxa;
m_txca = txa;
m_rxcb = rxb;
m_txcb = txb;
}
uint8_t cd_ba_r(offs_t offset);
void cd_ba_w(offs_t offset, uint8_t data);
uint8_t ba_cd_r(offs_t offset);
void ba_cd_w(offs_t offset, uint8_t data);
uint8_t da_r() { return m_chanA->data_read(); }
void da_w(uint8_t data) { m_chanA->data_write(data); }
uint8_t db_r() { return m_chanB->data_read(); }
void db_w(uint8_t data) { m_chanB->data_write(data); }
uint8_t ca_r() { return m_chanA->control_read(); }
void ca_w(uint8_t data) { m_chanA->control_write(data); }
uint8_t cb_r() { return m_chanB->control_read(); }
void cb_w(uint8_t data) { m_chanB->control_write(data); }
// interrupt acknowledge
int m1_r();
DECLARE_WRITE_LINE_MEMBER( rxa_w ) { m_chanA->write_rx(state); }
DECLARE_WRITE_LINE_MEMBER( rxb_w ) { m_chanB->write_rx(state); }
DECLARE_WRITE_LINE_MEMBER( ctsa_w ) { m_chanA->cts_w(state); }
DECLARE_WRITE_LINE_MEMBER( ctsb_w ) { m_chanB->cts_w(state); }
DECLARE_WRITE_LINE_MEMBER( dcda_w ) { m_chanA->dcd_w(state); }
DECLARE_WRITE_LINE_MEMBER( dcdb_w ) { m_chanB->dcd_w(state); }
DECLARE_WRITE_LINE_MEMBER( ria_w ) { m_chanA->ri_w(state); }
DECLARE_WRITE_LINE_MEMBER( rib_w ) { m_chanB->ri_w(state); }
DECLARE_WRITE_LINE_MEMBER( rxca_w ) { m_chanA->rxc_w(state); }
DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { m_chanB->rxc_w(state); }
DECLARE_WRITE_LINE_MEMBER( txca_w ) { m_chanA->txc_w(state); }
DECLARE_WRITE_LINE_MEMBER( txcb_w ) { m_chanB->txc_w(state); }
DECLARE_WRITE_LINE_MEMBER( rxtxcb_w ) { m_chanB->rxc_w(state); m_chanB->txc_w(state); }
DECLARE_WRITE_LINE_MEMBER( synca_w ) { m_chanA->sync_w(state); }
DECLARE_WRITE_LINE_MEMBER( syncb_w ) { m_chanB->sync_w(state); }
protected:
z80dart_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t variant);
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
virtual void device_add_mconfig(machine_config &config) override;
// device_z80daisy_interface overrides
virtual int z80daisy_irq_state() override;
virtual int z80daisy_irq_ack() override;
virtual void z80daisy_irq_reti() override;
// internal interrupt management
void check_interrupts();
void reset_interrupts();
void trigger_interrupt(int index, int state);
int get_channel_index(z80dart_channel *ch) { return (ch == m_chanA) ? 0 : 1; }
enum
{
TYPE_DART,
TYPE_SIO0,
TYPE_SIO1,
TYPE_SIO2,
TYPE_SIO3,
TYPE_SIO4,
TYPE_I8274,
TYPE_UPD7201
};
enum
{
CHANNEL_A = 0,
CHANNEL_B
};
required_device<z80dart_channel> m_chanA;
required_device<z80dart_channel> m_chanB;
// internal state
int m_rxca;
int m_txca;
int m_rxcb;
int m_txcb;
devcb_write_line m_out_txda_cb;
devcb_write_line m_out_dtra_cb;
devcb_write_line m_out_rtsa_cb;
devcb_write_line m_out_wrdya_cb;
devcb_write_line m_out_synca_cb;
devcb_write_line m_out_txdb_cb;
devcb_write_line m_out_dtrb_cb;
devcb_write_line m_out_rtsb_cb;
devcb_write_line m_out_wrdyb_cb;
devcb_write_line m_out_syncb_cb;
devcb_write_line m_out_int_cb;
devcb_write_line m_out_rxdrqa_cb;
devcb_write_line m_out_txdrqa_cb;
devcb_write_line m_out_rxdrqb_cb;
devcb_write_line m_out_txdrqb_cb;
int m_int_state[8]; // interrupt state
int const m_variant;
};
// device type definition
DECLARE_DEVICE_TYPE(Z80DART_CHANNEL, z80dart_channel)
DECLARE_DEVICE_TYPE(Z80DART, z80dart_device)
#endif // MAME_MACHINE_Z80DART_H

113
src/devices/machine/z80sio.cpp
View File

@ -3,6 +3,7 @@
/***************************************************************************
Z80-SIO Serial Input/Output emulation
Z80-DART Dual Asynchronous Receiver/Transmitter emulation
Intel 8274 Multi-Protocol Serial Controller emulation
NEC µPD7201 Multiprotocol Serial Communications Controller emulation
@ -119,7 +120,7 @@ enum : uint8_t
RR0_INTERRUPT_PENDING = 0x02,
RR0_TX_BUFFER_EMPTY = 0x04,
RR0_DCD = 0x08,
RR0_SYNC_HUNT = 0x10,
RR0_SYNC_HUNT = 0x10, // RI on DART
RR0_CTS = 0x20,
RR0_TX_UNDERRUN = 0x40,
RR0_BREAK_ABORT = 0x80
@ -254,9 +255,11 @@ constexpr uint16_t SDLC_RESIDUAL = 0x1d0f;
// device type definition
DEFINE_DEVICE_TYPE(Z80SIO_CHANNEL, z80sio_channel, "z80sio_channel", "Z80 SIO channel")
DEFINE_DEVICE_TYPE(Z80DART_CHANNEL, z80dart_channel, "z80dart_channel", "Z80 DART channel")
DEFINE_DEVICE_TYPE(I8274_CHANNEL, i8274_channel, "i8274_channel", "Intel 8274 MPSC channel")
DEFINE_DEVICE_TYPE(MK68564_CHANNEL, mk68564_channel, "mk68564_channel", "Mostek MK68564 SIO channel")
DEFINE_DEVICE_TYPE(Z80SIO, z80sio_device, "z80sio", "Z80 SIO")
DEFINE_DEVICE_TYPE(Z80DART, z80dart_device, "z80dart", "Z80 DART")
DEFINE_DEVICE_TYPE(I8274, i8274_device, "i8274", "Intel 8274 MPSC")
DEFINE_DEVICE_TYPE(UPD7201, upd7201_device, "upd7201", "NEC uPD7201 MPSC")
DEFINE_DEVICE_TYPE(MK68564, mk68564_device, "mk68564", "Mostek MK68564 SIO")
@ -270,6 +273,12 @@ void z80sio_device::device_add_mconfig(machine_config &config)
Z80SIO_CHANNEL(config, CHANB_TAG, 0);
}
void z80dart_device::device_add_mconfig(machine_config &config)
{
Z80DART_CHANNEL(config, CHANA_TAG, 0);
Z80DART_CHANNEL(config, CHANB_TAG, 0);
}
void i8274_device::device_add_mconfig(machine_config &config)
{
I8274_CHANNEL(config, CHANA_TAG, 0);
@ -358,7 +367,7 @@ inline void z80sio_channel::tx_setup(uint16_t data, int bits, bool framing, bool
LOGBIT("%.6f TX_SR %05x data %04x flags %x\n" , machine().time().as_double() , m_tx_sr & TX_SR_MASK , data , m_tx_flags);
}
inline void z80sio_channel::tx_setup_idle()
void z80sio_channel::tx_setup_idle()
{
switch (m_wr4 & WR4_SYNC_MODE_MASK)
{
@ -380,6 +389,11 @@ inline void z80sio_channel::tx_setup_idle()
m_tx_in_pkt = false;
}
void z80dart_channel::tx_setup_idle()
{
logerror("%s (sync mode not supported by DART)\n", FUNCNAME);
}
//-------------------------------------------------
// z80sio_device - constructor
//-------------------------------------------------
@ -407,6 +421,11 @@ z80sio_device::z80sio_device(const machine_config &mconfig, const char *tag, dev
{
}
z80dart_device::z80dart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
z80sio_device(mconfig, Z80DART, tag, owner, clock)
{
}
i8274_device::i8274_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
z80sio_device(mconfig, type, tag, owner, clock)
{
@ -943,12 +962,13 @@ z80sio_channel::z80sio_channel(
, m_rx_count(0)
, m_rx_bit(0)
, m_rx_sr(0)
, m_rx_first(0)
, m_rx_first(false)
, m_rxd(1)
, m_tx_data(0)
, m_tx_clock(0), m_tx_count(0), m_tx_parity(0), m_tx_sr(0), m_tx_crc(0), m_tx_hist(0), m_tx_flags(0)
, m_txd(1), m_dtr(0), m_rts(0)
, m_ext_latched(0), m_brk_latched(0), m_cts(0), m_dcd(0), m_sync(0)
, m_ext_latched(false), m_brk_latched(false)
, m_cts(0), m_dcd(0), m_sync(0)
, m_rr1_auto_reset(rr1_auto_reset)
{
LOG("%s\n",FUNCNAME);
@ -963,6 +983,11 @@ z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, d
{
}
z80dart_channel::z80dart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: z80sio_channel(mconfig, Z80DART_CHANNEL, tag, owner, clock, RR1_END_OF_FRAME | RR1_CRC_FRAMING_ERROR | RR1_RESIDUE_CODE_MASK)
{
}
i8274_channel::i8274_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: z80sio_channel(mconfig, I8274_CHANNEL, tag, owner, clock, RR1_RX_OVERRUN_ERROR)
{
@ -1005,23 +1030,13 @@ void z80sio_channel::device_start()
save_item(NAME(m_wr3));
save_item(NAME(m_wr4));
save_item(NAME(m_wr5));
save_item(NAME(m_wr6));
save_item(NAME(m_wr7));
save_item(NAME(m_rx_fifo_depth));
save_item(NAME(m_rx_data_fifo));
save_item(NAME(m_rx_error_fifo));
save_item(NAME(m_rx_clock));
save_item(NAME(m_rx_count));
save_item(NAME(m_dlyd_rxd));
save_item(NAME(m_rx_bit));
save_item(NAME(m_rx_bit_limit));
save_item(NAME(m_rx_sync_fsm));
save_item(NAME(m_rx_one_cnt));
save_item(NAME(m_rx_sr));
save_item(NAME(m_rx_sync_sr));
save_item(NAME(m_rx_crc_delay));
save_item(NAME(m_rx_crc));
save_item(NAME(m_rx_crc_en));
save_item(NAME(m_rx_parity));
save_item(NAME(m_rx_first));
save_item(NAME(m_tx_data));
@ -1029,10 +1044,8 @@ void z80sio_channel::device_start()
save_item(NAME(m_tx_count));
save_item(NAME(m_tx_phase));
save_item(NAME(m_tx_parity));
save_item(NAME(m_tx_in_pkt));
save_item(NAME(m_tx_forced_sync));
save_item(NAME(m_tx_in_pkt)); // TODO: does this actually function in async mode?
save_item(NAME(m_tx_sr));
save_item(NAME(m_tx_crc));
save_item(NAME(m_tx_hist));
save_item(NAME(m_tx_flags));
save_item(NAME(m_tx_delay));
@ -1045,6 +1058,29 @@ void z80sio_channel::device_start()
save_item(NAME(m_dcd));
save_item(NAME(m_sync));
save_item(NAME(m_cts));
sync_save_state();
}
void z80sio_channel::sync_save_state()
{
save_item(NAME(m_wr6));
save_item(NAME(m_wr7));
save_item(NAME(m_dlyd_rxd));
save_item(NAME(m_rx_bit_limit));
save_item(NAME(m_rx_sync_fsm));
save_item(NAME(m_rx_one_cnt));
save_item(NAME(m_rx_sync_sr));
save_item(NAME(m_rx_crc_delay));
save_item(NAME(m_rx_crc));
save_item(NAME(m_rx_crc_en));
//save_item(NAME(m_tx_in_pkt));
save_item(NAME(m_tx_forced_sync));
save_item(NAME(m_tx_crc));
}
void z80dart_channel::sync_save_state()
{
// no need to save the above members
}
void mk68564_channel::device_start()
@ -1104,7 +1140,7 @@ void z80sio_channel::device_reset()
m_uart->clear_interrupt(m_index, INT_TRANSMIT);
m_uart->clear_interrupt(m_index, INT_RECEIVE);
reset_ext_status();
// FIXME: should this actually reset all the interrtupts, or just the prioritisation (daisy chain) logic?
// FIXME: should this actually reset all the interrupts, or just the prioritisation (daisy chain) logic?
if (m_index == z80sio_device::CHANNEL_A)
m_uart->reset_interrupts();
}
@ -1258,6 +1294,11 @@ void z80sio_channel::sync_tx_sr_empty()
}
}
void z80dart_channel::sync_tx_sr_empty()
{
LOG("%s (sync mode not supported by DART)\n", FUNCNAME);
}
bool z80sio_channel::get_tx_empty() const
{
// During CRC transmission, tx buffer is shown as full
@ -1335,8 +1376,8 @@ void z80sio_channel::async_tx_setup()
void z80sio_channel::reset_ext_status()
{
// this will clear latched external pin state
m_ext_latched = 0;
m_brk_latched = 0;
m_ext_latched = false;
m_brk_latched = false;
read_ext();
// Clear any pending External interrupt
@ -1380,7 +1421,7 @@ void z80sio_channel::trigger_ext_int()
// update line
if (!m_ext_latched)
read_ext();
m_ext_latched = 1;
m_ext_latched = true;
// trigger interrupt if enabled
if (m_wr1 & WR1_EXT_INT_ENABLE)
@ -1625,7 +1666,7 @@ void z80sio_channel::do_sioreg_wr0(uint8_t data)
case WR0_ENABLE_INT_NEXT_RX:
// enable interrupt on next receive character
LOGINT("%s Ch:%c : Enable Interrupt on Next Received Character\n", FUNCNAME, 'A' + m_index);
m_rx_first = 1;
m_rx_first = true;
break;
case WR0_RESET_TX_INT:
LOGCMD("%s Ch:%c : Reset Transmitter Interrupt Pending\n", FUNCNAME, 'A' + m_index);
@ -1925,6 +1966,11 @@ void z80sio_channel::enter_hunt_mode()
}
}
void z80dart_channel::enter_hunt_mode()
{
LOG("%s (sync mode not supported by DART)\n", FUNCNAME);
}
//-------------------------------------------------
// sync_receive - synchronous reception handler
//-------------------------------------------------
@ -2042,6 +2088,11 @@ void z80sio_channel::sync_receive()
m_dlyd_rxd = m_rxd;
}
void z80dart_channel::sync_receive()
{
LOG("%s (sync mode not supported by DART)\n", FUNCNAME);
}
//-------------------------------------------------
// sdlc_receive - SDLC reception handler
//-------------------------------------------------
@ -2068,7 +2119,7 @@ void z80sio_channel::sdlc_receive()
LOGRCV("SDLC Abort detected\n");
m_rr0 |= RR0_BREAK_ABORT;
if (!m_brk_latched) {
m_brk_latched = 1;
m_brk_latched = true;
trigger_ext_int();
}
enter_hunt_mode();
@ -2088,7 +2139,7 @@ void z80sio_channel::sdlc_receive()
{
m_rr0 &= ~RR0_BREAK_ABORT;
if (!m_brk_latched) {
m_brk_latched = 1;
m_brk_latched = true;
trigger_ext_int();
}
}
@ -2189,6 +2240,11 @@ void z80sio_channel::sdlc_receive()
}
}
void z80dart_channel::sdlc_receive()
{
logerror("%s (sync mode not supported by DART)\n", FUNCNAME);
}
//-------------------------------------------------
// receive_data - receive data word
//-------------------------------------------------
@ -2234,7 +2290,7 @@ void z80sio_channel::queue_received(uint16_t data, uint32_t error)
case WR1_RX_INT_FIRST:
if (m_rx_first || (error & get_special_rx_mask()))
m_uart->trigger_interrupt(m_index, INT_RECEIVE);
m_rx_first = 0;
m_rx_first = false;
break;
case WR1_RX_INT_ALL_PARITY:
@ -2340,7 +2396,7 @@ WRITE_LINE_MEMBER( z80sio_channel::rxc_w )
LOGRCV("Break termination detected\n");
m_rr0 &= ~RR0_BREAK_ABORT;
if (!m_brk_latched) {
m_brk_latched = 1;
m_brk_latched = true;
trigger_ext_int();
}
}
@ -2407,7 +2463,7 @@ WRITE_LINE_MEMBER( z80sio_channel::rxc_w )
{
LOGRCV("Break detected\n");
m_rr0 |= RR0_BREAK_ABORT;
m_brk_latched = 1;
m_brk_latched = true;
trigger_ext_int();
}
}
@ -2454,7 +2510,8 @@ WRITE_LINE_MEMBER( z80sio_channel::txc_w )
m_tx_count = get_clock_mode() / 2;
// Send out a delayed half bit
bool new_txd = BIT(m_tx_delay , 3);
LOGBIT("%.6f TX %d DLY %x\n" , machine().time().as_double() , new_txd , m_tx_delay & 0xf);
if ((m_wr4 & WR4_STOP_BITS_MASK) == WR4_STOP_BITS_SYNC || !(m_rr1 & RR1_ALL_SENT))
LOGBIT("%.6f TX %d DLY %x\n" , machine().time().as_double() , new_txd , m_tx_delay & 0xf);
if (new_txd != m_txd && !(m_wr5 & WR5_SEND_BREAK))
{
out_txd_cb(new_txd);

72
src/devices/machine/z80sio.h
View File

@ -3,6 +3,7 @@
/***************************************************************************
Z80-SIO Serial Input/Output
Z80-DART Dual Asynchronous Receiver/Transmitter
Intel 8274 Multi-Protocol Serial Controller
NEC µPD7201 Multiprotocol Serial Communications Controller
@ -51,6 +52,28 @@
R S S D K S D S S R D R S S D K S D S S R C
A A A A E B B B B B A A A A E B B B B
T T
_____ _____
D1 1 |* \_/ | 40 D0
D3 2 | | 39 D2
D5 3 | | 38 D4
D7 4 | | 37 D6
_INT 5 | | 36 _IORQ
IEI 6 | | 35 _CE
IEO 7 | | 34 B/_A
_M1 8 | | 33 C/_D
Vdd 9 | | 32 _RD
_W/RDYA 10 | Z80-DART | 31 GND
_RIA 11 | Z8470 | 30 _W/RDYB
RxDA 12 | | 29 _RIB
_RxCA 13 | | 28 RxDB
_TxCA 14 | | 27 _RxTxCB
TxDA 15 | | 26 TxDB
_DTRA 16 | | 25 _DTRB
_RTSA 17 | | 24 _RTSB
_CTSA 18 | | 23 _CTSB
_DCDA 19 | | 22 _DCDB
CLK 20 |_____________| 21 _RESET
_____ _____
CLK 1 |* \_/ | 40 Vcc
_RESET 2 | | 39 _CTSA
@ -149,6 +172,7 @@ class z80sio_device;
class z80sio_channel : public device_t
{
friend class z80sio_device;
friend class z80dart_device;
friend class i8274_device;
friend class upd7201_device;
friend class mk68564_device;
@ -294,7 +318,7 @@ protected:
bool m_rx_crc_en; // rx CRC enabled
bool m_rx_parity; // accumulated parity
int m_rx_first; // first character received
bool m_rx_first; // first character received
int m_rxd;
@ -319,8 +343,8 @@ protected:
int m_rts; // request to send
// external/status monitoring
int m_ext_latched; // changed data lines
int m_brk_latched; // break status latched
bool m_ext_latched; // changed data lines
bool m_brk_latched; // break status latched
int m_cts; // clear to send line state
int m_dcd; // data carrier detect line state
int m_sync; // sync line state
@ -340,9 +364,9 @@ protected:
virtual bool transmit_allowed() const;
void receive_enabled();
void enter_hunt_mode();
void sync_receive();
void sdlc_receive();
virtual void enter_hunt_mode();
virtual void sync_receive();
virtual void sdlc_receive();
void receive_data();
void queue_received(uint16_t data, uint32_t error);
void advance_rx_fifo();
@ -352,13 +376,14 @@ protected:
void transmit_enable();
void transmit_complete();
void async_tx_setup();
void sync_tx_sr_empty();
virtual void sync_tx_sr_empty();
void tx_setup(uint16_t data, int bits, bool framing, bool crc_tx, bool abort_tx);
void tx_setup_idle();
virtual void tx_setup_idle();
bool get_tx_empty() const;
void set_tx_empty(bool prev_state, bool new_state);
void update_crc(uint16_t& crc , bool bit);
virtual void sync_save_state();
void reset_ext_status();
void read_ext();
void trigger_ext_int();
@ -367,6 +392,23 @@ protected:
};
// ======================> z80dart_channel
class z80dart_channel : public z80sio_channel
{
public:
z80dart_channel(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
virtual void enter_hunt_mode() override;
virtual void sync_receive() override;
virtual void sdlc_receive() override;
virtual void sync_tx_sr_empty() override;
virtual void tx_setup_idle() override;
virtual void sync_save_state() override;
};
// ======================> i8274_channel
class i8274_channel : public z80sio_channel
@ -534,6 +576,19 @@ protected:
int m_int_source[8]; // interrupt source
};
class z80dart_device : public z80sio_device
{
public:
z80dart_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
DECLARE_WRITE_LINE_MEMBER( ria_w ) { m_chanA->sync_w(state); }
DECLARE_WRITE_LINE_MEMBER( rib_w ) { m_chanB->sync_w(state); }
protected:
// device_t overrides
virtual void device_add_mconfig(machine_config &config) override;
};
class i8274_device : public z80sio_device
{
public:
@ -582,6 +637,7 @@ private:
// device type declaration
DECLARE_DEVICE_TYPE(Z80SIO, z80sio_device)
DECLARE_DEVICE_TYPE(Z80DART, z80dart_device)
DECLARE_DEVICE_TYPE(I8274, i8274_device)
DECLARE_DEVICE_TYPE(UPD7201, upd7201_device)
DECLARE_DEVICE_TYPE(MK68564, mk68564_device)

2
src/mame/drivers/alphatpc16.cpp
View File

@ -51,7 +51,7 @@ via the PC 16 Terminal, operates independently after programming), connects to t
#include "imagedev/floppy.h"
#include "machine/wd_fdc.h"
#include "video/ef9345.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/pic8259.h"
#include "machine/timer.h"
#include "machine/ram.h"

2
src/mame/drivers/altos2.cpp
View File

@ -18,7 +18,7 @@ Keyboard: P8035L CPU, undumped 2716 labelled "358_2758", XTAL marked "4608-300-1
#include "cpu/z80/z80.h"
#include "machine/z80daisy.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/x2212.h"
#include "sound/beep.h"
//#include "video/crt9006.h"

1
src/mame/drivers/altos5.cpp
View File

@ -17,7 +17,6 @@
#include "machine/z80ctc.h"
#include "machine/z80pio.h"
#include "machine/z80sio.h"
#include "machine/z80dart.h"
#include "machine/z80dma.h"
#include "machine/wd_fdc.h"
#include "machine/clock.h"

2
src/mame/drivers/ampex210.cpp
View File

@ -12,7 +12,7 @@
#include "machine/mos6551.h"
#include "machine/nvram.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "video/scn2674.h"
#include "screen.h"

2
src/mame/drivers/ampro.cpp
View File

@ -27,7 +27,7 @@ of a hard drive of up to 88MB.
#include "machine/output_latch.h"
#include "machine/z80daisy.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/wd_fdc.h"
#include "machine/timer.h"
#include "softlist.h"

2
src/mame/drivers/czk80.cpp
View File

@ -44,7 +44,7 @@ I/O ports: These ranges are what is guessed
#include "machine/upd765.h"
#include "machine/z80daisy.h"
#include "machine/z80pio.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/z80ctc.h"
#include "machine/terminal.h"

2
src/mame/drivers/dmax8000.cpp
View File

@ -29,7 +29,7 @@ What there is of the schematic shows no sign of a daisy chain or associated inte
#include "machine/wd_fdc.h"
#include "machine/z80daisy.h"
#include "machine/z80pio.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/z80ctc.h"
#include "machine/mm58274c.h"
#include "bus/rs232/rs232.h"

2
src/mame/drivers/facit4440.cpp
View File

@ -32,7 +32,7 @@
#include "machine/clock.h"
#include "machine/er1400.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "video/mc6845.h"
#include "screen.h"

2
src/mame/drivers/falcots.cpp
View File

@ -13,7 +13,7 @@
#include "machine/nvram.h"
#include "machine/rstbuf.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "video/mc6845.h"
#include "screen.h"

2
src/mame/drivers/fs3216.cpp
View File

@ -18,7 +18,7 @@
#include "machine/upd765.h"
#include "machine/x2212.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "video/mc6845.h"
#include "screen.h"

14
src/mame/drivers/isbc.cpp
View File

@ -25,7 +25,6 @@ able to deal with 256byte sectors so fails to load the irmx 512byte sector image
#include "machine/pit8253.h"
#include "machine/i8255.h"
#include "machine/i8251.h"
//#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "bus/centronics/ctronics.h"
#include "bus/isbx/isbx.h"
@ -449,7 +448,6 @@ void isbc_state::isbc286(machine_config &config)
pit.set_clk<0>(XTAL(22'118'400)/18);
pit.out_handler<0>().set(m_pic_0, FUNC(pic8259_device::ir0_w));
pit.set_clk<1>(XTAL(22'118'400)/18);
// pit.out_handler<1>().set(m_uart8274, FUNC(z80dart_device::rxtxcb_w));
pit.out_handler<1>().set(m_uart8274, FUNC(i8274_device::rxtxcb_w));
pit.set_clk<2>(XTAL(22'118'400)/18);
pit.out_handler<2>().set(FUNC(isbc_state::isbc286_tmr2_w));
@ -491,26 +489,14 @@ void isbc_state::isbc286(machine_config &config)
#endif
rs232_port_device &rs232a(RS232_PORT(config, "rs232a", default_rs232_devices, nullptr));
#if 0
rs232a.rxd_handler().set(m_uart8274, FUNC(z80dart_device::rxa_w));
rs232a.dcd_handler().set(m_uart8274, FUNC(z80dart_device::dcda_w));
rs232a.cts_handler().set(m_uart8274, FUNC(z80dart_device::ctsa_w));
#else
rs232a.rxd_handler().set(m_uart8274, FUNC(i8274_device::rxa_w));
rs232a.dcd_handler().set(m_uart8274, FUNC(i8274_device::dcda_w));
rs232a.cts_handler().set(m_uart8274, FUNC(i8274_device::ctsa_w));
#endif
rs232_port_device &rs232b(RS232_PORT(config, "rs232b", default_rs232_devices, "terminal"));
#if 0
rs232b.rxd_handler().set(m_uart8274, FUNC(z80dart_device::rxb_w));
rs232b.dcd_handler().set(m_uart8274, FUNC(z80dart_device::dcdb_w));
rs232b.cts_handler().set(m_uart8274, FUNC(z80dart_device::ctsb_w));
#else
rs232b.rxd_handler().set(m_uart8274, FUNC(i8274_device::rxb_w));
rs232b.dcd_handler().set(m_uart8274, FUNC(i8274_device::dcdb_w));
rs232b.cts_handler().set(m_uart8274, FUNC(i8274_device::ctsb_w));
#endif
rs232b.set_option_device_input_defaults("terminal", DEVICE_INPUT_DEFAULTS_NAME(isbc286_terminal));
ISBX_SLOT(config, m_sbx[0], 0, isbx_cards, nullptr);

2
src/mame/drivers/pulsar.cpp
View File

@ -43,7 +43,7 @@ X - Test off-board memory banks
#include "cpu/z80/z80.h"
#include "imagedev/floppy.h"
#include "machine/z80daisy.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/msm5832.h"
#include "machine/i8255.h"
#include "machine/com8116.h"

2
src/mame/drivers/qvt103.cpp
View File

@ -11,7 +11,7 @@ Skeleton driver for Qume QVT-103 video display terminal.
#include "cpu/mcs48/mcs48.h"
#include "machine/nvram.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "video/crt9007.h"
#include "emupal.h"
#include "screen.h"

2
src/mame/drivers/qvt70.cpp
View File

@ -26,7 +26,7 @@
#include "emu.h"
#include "cpu/z80/z80.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "bus/centronics/ctronics.h"
#include "bus/rs232/rs232.h"
#include "emupal.h"

2
src/mame/drivers/rc702.cpp
View File

@ -32,8 +32,8 @@ Issues:
#include "machine/keyboard.h"
#include "machine/upd765.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80pio.h"
#include "machine/z80sio.h"
#include "sound/beep.h"
#include "video/i8275.h"

2
src/mame/drivers/superslave.cpp
View File

@ -28,8 +28,8 @@ Oxx,yy = Out port
#include "machine/am9519.h"
#include "machine/com8116.h"
#include "machine/ram.h"
#include "machine/z80dart.h"
#include "machine/z80pio.h"
#include "machine/z80sio.h"
#define Z80_TAG "u45"
#define Z80DART_0_TAG "u14"

2
src/mame/drivers/ti931.cpp
View File

@ -11,7 +11,7 @@
//#include "bus/rs232/rs232.h"
#include "machine/nvram.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "video/scn2674.h"
#include "screen.h"

2
src/mame/drivers/ts802.cpp
View File

@ -28,7 +28,7 @@
#include "machine/terminal.h"
#include "machine/z80dma.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/wd_fdc.h"
class ts802_state : public driver_device

2
src/mame/drivers/ts803.cpp
View File

@ -52,7 +52,7 @@ PAGE SEL bit in PORT0 set to 1:
#include "machine/z80daisy.h"
#include "machine/keyboard.h"
#include "machine/timer.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/wd_fdc.h"
#include "machine/z80sti.h"
#include "video/mc6845.h"

2
src/mame/includes/abc1600.h
View File

@ -15,8 +15,8 @@
#include "machine/nmc9306.h"
#include "machine/ram.h"
#include "machine/wd_fdc.h"
#include "machine/z80dart.h"
#include "machine/z80dma.h"
#include "machine/z80sio.h"
#include "machine/z8536.h"
#include "imagedev/floppy.h"
#include "video/abc1600.h"

1
src/mame/includes/abc80x.h
View File

@ -16,7 +16,6 @@
#include "bus/abckb/abc800kb.h"
#include "machine/e0516.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/ram.h"
#include "machine/timer.h"

2
src/mame/includes/bullet.h
View File

@ -13,9 +13,9 @@
#include "machine/timer.h"
#include "machine/wd_fdc.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80dma.h"
#include "machine/z80pio.h"
#include "machine/z80sio.h"
#define Z80_TAG "u20"
#define Z80CTC_TAG "u1"

2
src/mame/includes/mtx.h
View File

@ -17,7 +17,7 @@
#include "bus/mtx/exp.h"
#include "cpu/z80/z80.h"
#include "machine/z80daisy.h"
#include "machine/z80dart.h"
#include "machine/z80sio.h"
#include "machine/z80ctc.h"
#include "sound/sn76496.h"
#include "machine/ram.h"

2
src/mame/includes/super6.h
View File

@ -12,9 +12,9 @@
#include "machine/ram.h"
#include "machine/wd_fdc.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80dma.h"
#include "machine/z80pio.h"
#include "machine/z80sio.h"
#define Z80_TAG "u30"
#define Z80CTC_TAG "u20"

2
src/mame/includes/tiki100.h
View File

@ -16,8 +16,8 @@
#include "machine/ram.h"
#include "machine/timer.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80pio.h"
#include "machine/z80sio.h"
#include "machine/wd_fdc.h"
#include "sound/ay8910.h"
#include "emupal.h"

2
src/mame/includes/tranz330.h
View File

@ -9,8 +9,8 @@
#include "cpu/z80/z80.h"
#include "machine/z80daisy.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "machine/z80pio.h"
#include "machine/z80sio.h"
#include "machine/msm6242.h"
#include "machine/roc10937.h"
#include "bus/rs232/rs232.h"

12
src/mame/machine/mtx.cpp
View File

@ -7,17 +7,9 @@
**************************************************************************/
#include "emu.h"
#include "formats/imageutl.h"
#include "includes/mtx.h"
#include "cpu/z80/z80.h"
#include "imagedev/cassette.h"
#include "machine/ram.h"
#include "imagedev/snapquik.h"
#include "bus/centronics/ctronics.h"
#include "machine/z80ctc.h"
#include "machine/z80dart.h"
#include "video/tms9928a.h"
#include "sound/sn76496.h"
#include "formats/imageutl.h"
/***************************************************************************
READ/WRITE HANDLERS