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More AM_BASE_LEGACY removal.

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This commit is contained in:
Aaron Giles 2012-09-12 09:44:42 +00:00
parent f0fe035026
commit 8fa9cb845e
16 changed files with 301 additions and 258 deletions
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12
src/mame/drivers/konamigx.c
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@ -1190,10 +1190,10 @@ static ADDRESS_MAP_START( gx_type1_map, AS_PROGRAM, 32, konamigx_state )
AM_RANGE(0xdda000, 0xddafff) AM_WRITE_PORT("ADC-WRPORT") AM_RANGE(0xdda000, 0xddafff) AM_WRITE_PORT("ADC-WRPORT")
AM_RANGE(0xddc000, 0xddcfff) AM_READ_PORT("ADC-RDPORT") AM_RANGE(0xddc000, 0xddcfff) AM_READ_PORT("ADC-RDPORT")
AM_RANGE(0xdde000, 0xdde003) AM_WRITE(type1_cablamps_w) AM_RANGE(0xdde000, 0xdde003) AM_WRITE(type1_cablamps_w)
AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_ctrl) AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_SHARE("k053936_0_ctrl")
AM_RANGE(0xe20000, 0xe2000f) AM_WRITENOP AM_RANGE(0xe20000, 0xe2000f) AM_WRITENOP
AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP
AM_RANGE(0xe80000, 0xe81fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl) // chips 21L+19L / S AM_RANGE(0xe80000, 0xe81fff) AM_RAM AM_SHARE("k053936_0_line") // chips 21L+19L / S
AM_RANGE(0xec0000, 0xedffff) AM_RAM_WRITE(konamigx_t1_psacmap_w) AM_SHARE("psacram") // chips 20J+23J+18J / S AM_RANGE(0xec0000, 0xedffff) AM_RAM_WRITE(konamigx_t1_psacmap_w) AM_SHARE("psacram") // chips 20J+23J+18J / S
AM_RANGE(0xf00000, 0xf3ffff) AM_READ(type1_roz_r1) // ROM readback AM_RANGE(0xf00000, 0xf3ffff) AM_READ(type1_roz_r1) // ROM readback
AM_RANGE(0xf40000, 0xf7ffff) AM_READ(type1_roz_r2) // ROM readback AM_RANGE(0xf40000, 0xf7ffff) AM_READ(type1_roz_r2) // ROM readback
@ -1211,10 +1211,10 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( gx_type3_map, AS_PROGRAM, 32, konamigx_state ) static ADDRESS_MAP_START( gx_type3_map, AS_PROGRAM, 32, konamigx_state )
AM_RANGE(0xd90000, 0xd97fff) AM_RAM AM_RANGE(0xd90000, 0xd97fff) AM_RAM
//AM_RANGE(0xcc0000, 0xcc0007) AM_WRITE(type4_prot_w) //AM_RANGE(0xcc0000, 0xcc0007) AM_WRITE(type4_prot_w)
AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_ctrl) AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_SHARE("k053936_0_ctrl")
//AM_RANGE(0xe20000, 0xe20003) AM_WRITENOP //AM_RANGE(0xe20000, 0xe20003) AM_WRITENOP
AM_RANGE(0xe40000, 0xe40003) AM_WRITE(konamigx_type3_psac2_bank_w) AM_BASE_LEGACY(&konamigx_type3_psac2_bank) AM_RANGE(0xe40000, 0xe40003) AM_WRITE(konamigx_type3_psac2_bank_w) AM_BASE_LEGACY(&konamigx_type3_psac2_bank)
AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl) AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_SHARE("k053936_0_line")
AM_RANGE(0xe80000, 0xe83fff) AM_RAM AM_SHARE("paletteram") // main monitor palette AM_RANGE(0xe80000, 0xe83fff) AM_RAM AM_SHARE("paletteram") // main monitor palette
AM_RANGE(0xea0000, 0xea3fff) AM_RAM AM_SHARE("subpaletteram") AM_RANGE(0xea0000, 0xea3fff) AM_RAM AM_SHARE("subpaletteram")
AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r) AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r)
@ -1225,10 +1225,10 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( gx_type4_map, AS_PROGRAM, 32, konamigx_state ) static ADDRESS_MAP_START( gx_type4_map, AS_PROGRAM, 32, konamigx_state )
AM_RANGE(0xcc0000, 0xcc0007) AM_WRITE(type4_prot_w) AM_RANGE(0xcc0000, 0xcc0007) AM_WRITE(type4_prot_w)
AM_RANGE(0xd90000, 0xd97fff) AM_RAM AM_RANGE(0xd90000, 0xd97fff) AM_RAM
AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_ctrl) AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_SHARE("k053936_0_ctrl")
AM_RANGE(0xe20000, 0xe20003) AM_WRITENOP AM_RANGE(0xe20000, 0xe20003) AM_WRITENOP
AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP
AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl) // 29C & 29G (PSAC2 line control) AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_SHARE("k053936_0_line") // 29C & 29G (PSAC2 line control)
AM_RANGE(0xe80000, 0xe87fff) AM_RAM AM_SHARE("paletteram") // 11G/13G/15G (main screen palette RAM) AM_RANGE(0xe80000, 0xe87fff) AM_RAM AM_SHARE("paletteram") // 11G/13G/15G (main screen palette RAM)
AM_RANGE(0xea0000, 0xea7fff) AM_RAM AM_SHARE("subpaletteram") // 5G/7G/9G (sub screen palette RAM) AM_RANGE(0xea0000, 0xea7fff) AM_RAM AM_SHARE("subpaletteram") // 5G/7G/9G (sub screen palette RAM)
AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r) // type 4 polls this too AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r) // type 4 polls this too

16
src/mame/drivers/legionna.c
View File

@ -82,7 +82,7 @@ Preliminary COP MCU memory map
static ADDRESS_MAP_START( legionna_map, AS_PROGRAM, 16, legionna_state ) static ADDRESS_MAP_START( legionna_map, AS_PROGRAM, 16, legionna_state )
AM_RANGE(0x000000, 0x07ffff) AM_ROM AM_RANGE(0x000000, 0x07ffff) AM_ROM
AM_RANGE(0x100000, 0x1003ff) AM_RAM AM_RANGE(0x100000, 0x1003ff) AM_RAM
AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(legionna_mcu_r, legionna_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram) /* COP mcu */ AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(legionna_mcu_r, legionna_mcu_w) AM_SHARE("cop_mcu_ram") /* COP mcu */
AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data") AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data") AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
AM_RANGE(0x102000, 0x1027ff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data") AM_RANGE(0x102000, 0x1027ff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
@ -97,7 +97,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( heatbrl_map, AS_PROGRAM, 16, legionna_state ) static ADDRESS_MAP_START( heatbrl_map, AS_PROGRAM, 16, legionna_state )
AM_RANGE(0x000000, 0x07ffff) AM_ROM AM_RANGE(0x000000, 0x07ffff) AM_ROM
AM_RANGE(0x100000, 0x1003ff) AM_RAM AM_RANGE(0x100000, 0x1003ff) AM_RAM
AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(heatbrl_mcu_r, heatbrl_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram) /* COP mcu */ AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(heatbrl_mcu_r, heatbrl_mcu_w) AM_SHARE("cop_mcu_ram") /* COP mcu */
AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data") AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data") AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data") AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
@ -110,7 +110,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( godzilla_map, AS_PROGRAM, 16, legionna_state ) static ADDRESS_MAP_START( godzilla_map, AS_PROGRAM, 16, legionna_state )
AM_RANGE(0x000000, 0x07ffff) AM_ROM AM_RANGE(0x000000, 0x07ffff) AM_ROM
AM_RANGE(0x100000, 0x1003ff) AM_RAM AM_RANGE(0x100000, 0x1003ff) AM_RAM
AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(godzilla_mcu_r, godzilla_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram) /* COP mcu */ AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(godzilla_mcu_r, godzilla_mcu_w) AM_SHARE("cop_mcu_ram") /* COP mcu */
AM_RANGE(0x100800, 0x100fff) AM_RAM AM_RANGE(0x100800, 0x100fff) AM_RAM
AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data") AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
AM_RANGE(0x102000, 0x1027ff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data") AM_RANGE(0x102000, 0x1027ff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
@ -135,7 +135,7 @@ WRITE16_MEMBER(legionna_state::denjin_paletteram16_xBBBBBGGGGGRRRRR_word_w)
static ADDRESS_MAP_START( denjinmk_map, AS_PROGRAM, 16, legionna_state ) static ADDRESS_MAP_START( denjinmk_map, AS_PROGRAM, 16, legionna_state )
AM_RANGE(0x000000, 0x0fffff) AM_ROM AM_RANGE(0x000000, 0x0fffff) AM_ROM
AM_RANGE(0x100000, 0x1003ff) AM_RAM AM_RANGE(0x100000, 0x1003ff) AM_RAM
AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(denjinmk_mcu_r, denjinmk_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram) /* COP mcu */ AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(denjinmk_mcu_r, denjinmk_mcu_w) AM_SHARE("cop_mcu_ram") /* COP mcu */
AM_RANGE(0x100800, 0x100fff) AM_RAM AM_RANGE(0x100800, 0x100fff) AM_RAM
AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data") AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data") AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
@ -152,7 +152,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( grainbow_map, AS_PROGRAM, 16, legionna_state ) static ADDRESS_MAP_START( grainbow_map, AS_PROGRAM, 16, legionna_state )
AM_RANGE(0x000000, 0x0fffff) AM_ROM AM_RANGE(0x000000, 0x0fffff) AM_ROM
AM_RANGE(0x100000, 0x1003ff) AM_RAM AM_RANGE(0x100000, 0x1003ff) AM_RAM
AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(grainbow_mcu_r, grainbow_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram) /* COP mcu */ AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(grainbow_mcu_r, grainbow_mcu_w) AM_SHARE("cop_mcu_ram") /* COP mcu */
AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data") AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data") AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data") AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
@ -168,7 +168,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( cupsoc_mem, AS_PROGRAM, 16, legionna_state ) static ADDRESS_MAP_START( cupsoc_mem, AS_PROGRAM, 16, legionna_state )
AM_RANGE(0x000000, 0x0fffff) AM_ROM AM_RANGE(0x000000, 0x0fffff) AM_ROM
AM_RANGE(0x100000, 0x1003ff) AM_RAM AM_RANGE(0x100000, 0x1003ff) AM_RAM
AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(cupsoc_mcu_r,cupsoc_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram) AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(cupsoc_mcu_r,cupsoc_mcu_w) AM_SHARE("cop_mcu_ram")
AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data") AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data") AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data") AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
@ -187,7 +187,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( cupsocs_mem, AS_PROGRAM, 16, legionna_state ) static ADDRESS_MAP_START( cupsocs_mem, AS_PROGRAM, 16, legionna_state )
AM_RANGE(0x000000, 0x0fffff) AM_ROM AM_RANGE(0x000000, 0x0fffff) AM_ROM
AM_RANGE(0x100000, 0x1003ff) AM_RAM AM_RANGE(0x100000, 0x1003ff) AM_RAM
AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(cupsocs_mcu_r,cupsocs_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram) AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(cupsocs_mcu_r,cupsocs_mcu_w) AM_SHARE("cop_mcu_ram")
AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data") AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data") AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data") AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
@ -206,7 +206,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( cupsocbl_mem, AS_PROGRAM, 16, legionna_state ) static ADDRESS_MAP_START( cupsocbl_mem, AS_PROGRAM, 16, legionna_state )
AM_RANGE(0x000000, 0x0fffff) AM_ROM AM_RANGE(0x000000, 0x0fffff) AM_ROM
//AM_RANGE(0x100000, 0x1003ff) AM_RAM //AM_RANGE(0x100000, 0x1003ff) AM_RAM
AM_RANGE(0x100000, 0x1007ff) AM_READWRITE_LEGACY(copdxbl_0_r,copdxbl_0_w) AM_BASE_LEGACY(&cop_mcu_ram) AM_RANGE(0x100000, 0x1007ff) AM_READWRITE_LEGACY(copdxbl_0_r,copdxbl_0_w) AM_SHARE("cop_mcu_ram")
AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data") AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data") AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data") AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")

33
src/mame/drivers/midzeus.c
View File

@ -56,16 +56,11 @@ static UINT8 crusnexo_leds_select;
static UINT8 keypad_select; static UINT8 keypad_select;
static UINT8 bitlatch[10]; static UINT8 bitlatch[10];
static UINT32 *ram_base;
static UINT8 cmos_protected; static UINT8 cmos_protected;
static UINT32 *linkram;
static emu_timer *timer[2]; static emu_timer *timer[2];
static UINT32 *tms32031_control;
static TIMER_CALLBACK( invasn_gun_callback ); static TIMER_CALLBACK( invasn_gun_callback );
@ -95,8 +90,10 @@ static MACHINE_START( midzeus )
static MACHINE_RESET( midzeus ) static MACHINE_RESET( midzeus )
{ {
memcpy(ram_base, machine.root_device().memregion("user1")->base(), 0x40000*4); midzeus_state *state = machine.driver_data<midzeus_state>();
*ram_base <<= 1;
memcpy(state->m_ram_base, machine.root_device().memregion("user1")->base(), 0x40000*4);
*state->m_ram_base <<= 1;
machine.device("maincpu")->reset(); machine.device("maincpu")->reset();
cmos_protected = TRUE; cmos_protected = TRUE;
@ -362,13 +359,13 @@ READ32_MEMBER(midzeus_state::linkram_r)
return 0x30313042; return 0x30313042;
else if (offset == 0x3c) else if (offset == 0x3c)
return 0xffffffff; return 0xffffffff;
return linkram[offset]; return m_linkram[offset];
} }
WRITE32_MEMBER(midzeus_state::linkram_w) WRITE32_MEMBER(midzeus_state::linkram_w)
{ {
logerror("%06X:unknown_8a000_w(%02X) = %08X\n", space.device().safe_pc(), offset, data); logerror("%06X:unknown_8a000_w(%02X) = %08X\n", space.device().safe_pc(), offset, data);
COMBINE_DATA(&linkram[offset]); COMBINE_DATA(&m_linkram[offset]);
} }
@ -394,13 +391,13 @@ READ32_MEMBER(midzeus_state::tms32031_control_r)
if (offset != 0x64) if (offset != 0x64)
logerror("%06X:tms32031_control_r(%02X)\n", space.device().safe_pc(), offset); logerror("%06X:tms32031_control_r(%02X)\n", space.device().safe_pc(), offset);
return tms32031_control[offset]; return m_tms32031_control[offset];
} }
WRITE32_MEMBER(midzeus_state::tms32031_control_w) WRITE32_MEMBER(midzeus_state::tms32031_control_w)
{ {
COMBINE_DATA(&tms32031_control[offset]); COMBINE_DATA(&m_tms32031_control[offset]);
/* ignore changes to the memory control register */ /* ignore changes to the memory control register */
if (offset == 0x64) if (offset == 0x64)
@ -567,10 +564,10 @@ READ32_MEMBER(midzeus_state::invasn_gun_r)
static ADDRESS_MAP_START( zeus_map, AS_PROGRAM, 32, midzeus_state ) static ADDRESS_MAP_START( zeus_map, AS_PROGRAM, 32, midzeus_state )
ADDRESS_MAP_UNMAP_HIGH ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x000000, 0x03ffff) AM_RAM AM_BASE_LEGACY(&ram_base) AM_RANGE(0x000000, 0x03ffff) AM_RAM AM_SHARE("ram_base")
AM_RANGE(0x400000, 0x41ffff) AM_RAM AM_RANGE(0x400000, 0x41ffff) AM_RAM
AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_BASE_LEGACY(&tms32031_control) AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_SHARE("tms32031_ctl")
AM_RANGE(0x880000, 0x8803ff) AM_READWRITE(zeus_r, zeus_w) AM_BASE_LEGACY(&zeusbase) AM_RANGE(0x880000, 0x8803ff) AM_READWRITE(zeus_r, zeus_w) AM_SHARE("zeusbase")
AM_RANGE(0x8d0000, 0x8d0004) AM_READWRITE(bitlatches_r, bitlatches_w) AM_RANGE(0x8d0000, 0x8d0004) AM_READWRITE(bitlatches_r, bitlatches_w)
AM_RANGE(0x990000, 0x99000f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w) AM_RANGE(0x990000, 0x99000f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)
AM_RANGE(0x9e0000, 0x9e0000) AM_WRITENOP // watchdog? AM_RANGE(0x9e0000, 0x9e0000) AM_WRITENOP // watchdog?
@ -582,11 +579,11 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( zeus2_map, AS_PROGRAM, 32, midzeus_state ) static ADDRESS_MAP_START( zeus2_map, AS_PROGRAM, 32, midzeus_state )
ADDRESS_MAP_UNMAP_HIGH ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x000000, 0x03ffff) AM_RAM AM_BASE_LEGACY(&ram_base) AM_RANGE(0x000000, 0x03ffff) AM_RAM AM_SHARE("ram_base")
AM_RANGE(0x400000, 0x43ffff) AM_RAM AM_RANGE(0x400000, 0x43ffff) AM_RAM
AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_BASE_LEGACY(&tms32031_control) AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_SHARE("tms32031_ctl")
AM_RANGE(0x880000, 0x88007f) AM_READWRITE_LEGACY(zeus2_r, zeus2_w) AM_BASE_LEGACY(&zeusbase) AM_RANGE(0x880000, 0x88007f) AM_READWRITE_LEGACY(zeus2_r, zeus2_w) AM_SHARE("zeusbase")
AM_RANGE(0x8a0000, 0x8a003f) AM_READWRITE(linkram_r, linkram_w) AM_BASE_LEGACY(&linkram) AM_RANGE(0x8a0000, 0x8a003f) AM_READWRITE(linkram_r, linkram_w) AM_SHARE("linkram")
AM_RANGE(0x8d0000, 0x8d000a) AM_READWRITE(bitlatches_r, bitlatches_w) AM_RANGE(0x8d0000, 0x8d000a) AM_READWRITE(bitlatches_r, bitlatches_w)
AM_RANGE(0x900000, 0x91ffff) AM_READWRITE(zpram_r, zpram_w) AM_SHARE("nvram") AM_MIRROR(0x020000) AM_RANGE(0x900000, 0x91ffff) AM_READWRITE(zpram_r, zpram_w) AM_SHARE("nvram") AM_MIRROR(0x020000)
AM_RANGE(0x990000, 0x99000f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w) AM_RANGE(0x990000, 0x99000f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)

8
src/mame/drivers/mystwarr.c
View File

@ -471,8 +471,8 @@ static ADDRESS_MAP_START( dadandrn_map, AS_PROGRAM, 16, mystwarr_state )
AM_RANGE(0x440000, 0x443fff) AM_READ_LEGACY(K056832_mw_rom_word_r) AM_RANGE(0x440000, 0x443fff) AM_READ_LEGACY(K056832_mw_rom_word_r)
AM_RANGE(0x450000, 0x45000f) AM_READ_LEGACY(K055673_rom_word_r) AM_RANGE(0x450000, 0x45000f) AM_READ_LEGACY(K055673_rom_word_r)
AM_RANGE(0x450010, 0x45001f) AM_WRITE_LEGACY(K053247_reg_word_w) AM_RANGE(0x450010, 0x45001f) AM_WRITE_LEGACY(K053247_reg_word_w)
AM_RANGE(0x460000, 0x46001f) AM_WRITEONLY AM_BASE_LEGACY(&K053936_0_ctrl) AM_RANGE(0x460000, 0x46001f) AM_WRITEONLY AM_SHARE("k053936_0_ctrl")
AM_RANGE(0x470000, 0x470fff) AM_RAM AM_BASE_LEGACY(&K053936_0_linectrl) AM_RANGE(0x470000, 0x470fff) AM_RAM AM_SHARE("k053936_0_line")
AM_RANGE(0x480000, 0x48003f) AM_WRITE_LEGACY(K056832_word_w) // VACSET AM_RANGE(0x480000, 0x48003f) AM_WRITE_LEGACY(K056832_word_w) // VACSET
AM_RANGE(0x482000, 0x482007) AM_WRITE_LEGACY(K056832_b_word_w) // VSCCS AM_RANGE(0x482000, 0x482007) AM_WRITE_LEGACY(K056832_b_word_w) // VSCCS
AM_RANGE(0x484000, 0x484003) AM_WRITE(ddd_053936_clip_w) AM_RANGE(0x484000, 0x484003) AM_WRITE(ddd_053936_clip_w)
@ -518,8 +518,8 @@ static ADDRESS_MAP_START( gaiapols_map, AS_PROGRAM, 16, mystwarr_state )
AM_RANGE(0x440000, 0x441fff) AM_READ_LEGACY(K056832_mw_rom_word_r) AM_RANGE(0x440000, 0x441fff) AM_READ_LEGACY(K056832_mw_rom_word_r)
AM_RANGE(0x450000, 0x45000f) AM_READ_LEGACY(K055673_rom_word_r) AM_RANGE(0x450000, 0x45000f) AM_READ_LEGACY(K055673_rom_word_r)
AM_RANGE(0x450010, 0x45001f) AM_WRITE_LEGACY(K053247_reg_word_w) AM_RANGE(0x450010, 0x45001f) AM_WRITE_LEGACY(K053247_reg_word_w)
AM_RANGE(0x460000, 0x46001f) AM_WRITEONLY AM_BASE_LEGACY(&K053936_0_ctrl) AM_RANGE(0x460000, 0x46001f) AM_WRITEONLY AM_SHARE("k053936_0_ctrl")
AM_RANGE(0x470000, 0x470fff) AM_RAM AM_BASE_LEGACY(&K053936_0_linectrl) AM_RANGE(0x470000, 0x470fff) AM_RAM AM_SHARE("k053936_0_line")
AM_RANGE(0x480000, 0x48003f) AM_WRITE_LEGACY(K056832_word_w) // VACSET AM_RANGE(0x480000, 0x48003f) AM_WRITE_LEGACY(K056832_word_w) // VACSET
AM_RANGE(0x482000, 0x482007) AM_WRITE_LEGACY(K056832_b_word_w) // VSCCS AM_RANGE(0x482000, 0x482007) AM_WRITE_LEGACY(K056832_b_word_w) // VSCCS
AM_RANGE(0x484000, 0x484003) AM_WRITE(ddd_053936_clip_w) AM_RANGE(0x484000, 0x484003) AM_WRITE(ddd_053936_clip_w)

91
src/mame/drivers/r2dx_v33.c
View File

@ -30,7 +30,12 @@ class r2dx_v33_state : public driver_device
public: public:
r2dx_v33_state(const machine_config &mconfig, device_type type, const char *tag) r2dx_v33_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag) , : driver_device(mconfig, type, tag) ,
m_spriteram(*this, "spriteram"){ } m_spriteram(*this, "spriteram"),
m_bg_vram(*this, "bg_vram"),
m_md_vram(*this, "md_vram"),
m_fg_vram(*this, "fg_vram"),
m_tx_vram(*this, "tx_vram")
{ }
required_shared_ptr<UINT16> m_spriteram; required_shared_ptr<UINT16> m_spriteram;
DECLARE_WRITE16_MEMBER(rdx_bg_vram_w); DECLARE_WRITE16_MEMBER(rdx_bg_vram_w);
@ -55,16 +60,21 @@ public:
TILE_GET_INFO_MEMBER(get_md_tile_info); TILE_GET_INFO_MEMBER(get_md_tile_info);
TILE_GET_INFO_MEMBER(get_fg_tile_info); TILE_GET_INFO_MEMBER(get_fg_tile_info);
TILE_GET_INFO_MEMBER(get_tx_tile_info); TILE_GET_INFO_MEMBER(get_tx_tile_info);
required_shared_ptr<UINT16> m_bg_vram;
required_shared_ptr<UINT16> m_md_vram;
required_shared_ptr<UINT16> m_fg_vram;
required_shared_ptr<UINT16> m_tx_vram;
tilemap_t *m_bg_tilemap;
tilemap_t *m_md_tilemap;
tilemap_t *m_fg_tilemap;
tilemap_t *m_tx_tilemap;
}; };
static UINT16 *seibu_crtc_regs;
static UINT16 *bg_vram,*md_vram,*fg_vram,*tx_vram;
static tilemap_t *bg_tilemap,*md_tilemap,*fg_tilemap,*tx_tilemap;
TILE_GET_INFO_MEMBER(r2dx_v33_state::get_bg_tile_info) TILE_GET_INFO_MEMBER(r2dx_v33_state::get_bg_tile_info)
{ {
int tile = bg_vram[tile_index]; int tile = m_bg_vram[tile_index];
int color = (tile>>12)&0xf; int color = (tile>>12)&0xf;
tile &= 0xfff; tile &= 0xfff;
@ -74,7 +84,7 @@ TILE_GET_INFO_MEMBER(r2dx_v33_state::get_bg_tile_info)
TILE_GET_INFO_MEMBER(r2dx_v33_state::get_md_tile_info) TILE_GET_INFO_MEMBER(r2dx_v33_state::get_md_tile_info)
{ {
int tile = md_vram[tile_index]; int tile = m_md_vram[tile_index];
int color = (tile>>12)&0xf; int color = (tile>>12)&0xf;
tile &= 0xfff; tile &= 0xfff;
@ -84,7 +94,7 @@ TILE_GET_INFO_MEMBER(r2dx_v33_state::get_md_tile_info)
TILE_GET_INFO_MEMBER(r2dx_v33_state::get_fg_tile_info) TILE_GET_INFO_MEMBER(r2dx_v33_state::get_fg_tile_info)
{ {
int tile = fg_vram[tile_index]; int tile = m_fg_vram[tile_index];
int color = (tile>>12)&0xf; int color = (tile>>12)&0xf;
tile &= 0xfff; tile &= 0xfff;
@ -94,7 +104,7 @@ TILE_GET_INFO_MEMBER(r2dx_v33_state::get_fg_tile_info)
TILE_GET_INFO_MEMBER(r2dx_v33_state::get_tx_tile_info) TILE_GET_INFO_MEMBER(r2dx_v33_state::get_tx_tile_info)
{ {
int tile = tx_vram[tile_index]; int tile = m_tx_vram[tile_index];
int color = (tile>>12)&0xf; int color = (tile>>12)&0xf;
tile &= 0xfff; tile &= 0xfff;
@ -192,28 +202,29 @@ static void draw_sprites(running_machine &machine, bitmap_ind16 &bitmap,const re
static VIDEO_START( rdx_v33 ) static VIDEO_START( rdx_v33 )
{ {
r2dx_v33_state *state = machine.driver_data<r2dx_v33_state>(); r2dx_v33_state *state = machine.driver_data<r2dx_v33_state>();
bg_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_bg_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32); state->m_bg_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_bg_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32);
md_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_md_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32); state->m_md_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_md_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32);
fg_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_fg_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32); state->m_fg_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_fg_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32);
tx_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_tx_tile_info),state), TILEMAP_SCAN_ROWS,8, 8, 64,32); state->m_tx_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_tx_tile_info),state), TILEMAP_SCAN_ROWS,8, 8, 64,32);
bg_tilemap->set_transparent_pen(15); state->m_bg_tilemap->set_transparent_pen(15);
md_tilemap->set_transparent_pen(15); state->m_md_tilemap->set_transparent_pen(15);
fg_tilemap->set_transparent_pen(15); state->m_fg_tilemap->set_transparent_pen(15);
tx_tilemap->set_transparent_pen(15); state->m_tx_tilemap->set_transparent_pen(15);
} }
static SCREEN_UPDATE_IND16( rdx_v33 ) static SCREEN_UPDATE_IND16( rdx_v33 )
{ {
r2dx_v33_state *state = screen.machine().driver_data<r2dx_v33_state>();
bitmap.fill(get_black_pen(screen.machine()), cliprect); bitmap.fill(get_black_pen(screen.machine()), cliprect);
bg_tilemap->draw(bitmap, cliprect, 0, 0); state->m_bg_tilemap->draw(bitmap, cliprect, 0, 0);
md_tilemap->draw(bitmap, cliprect, 0, 0); state->m_md_tilemap->draw(bitmap, cliprect, 0, 0);
fg_tilemap->draw(bitmap, cliprect, 0, 0); state->m_fg_tilemap->draw(bitmap, cliprect, 0, 0);
draw_sprites(screen.machine(),bitmap,cliprect,0); draw_sprites(screen.machine(),bitmap,cliprect,0);
tx_tilemap->draw(bitmap, cliprect, 0, 0); state->m_tx_tilemap->draw(bitmap, cliprect, 0, 0);
/* debug DMA processing */ /* debug DMA processing */
if(0) if(0)
@ -247,7 +258,7 @@ static SCREEN_UPDATE_IND16( rdx_v33 )
} }
popmessage("%08x 1",src_addr); popmessage("%08x 1",src_addr);
bg_tilemap->mark_all_dirty(); state->m_bg_tilemap->mark_all_dirty();
frame = 0; frame = 0;
src_addr+=0x800; src_addr+=0x800;
} }
@ -312,26 +323,26 @@ WRITE16_MEMBER(r2dx_v33_state::mcu_prog_offs_w)
WRITE16_MEMBER(r2dx_v33_state::rdx_bg_vram_w) WRITE16_MEMBER(r2dx_v33_state::rdx_bg_vram_w)
{ {
COMBINE_DATA(&bg_vram[offset]); COMBINE_DATA(&m_bg_vram[offset]);
bg_tilemap->mark_tile_dirty(offset); m_bg_tilemap->mark_tile_dirty(offset);
} }
WRITE16_MEMBER(r2dx_v33_state::rdx_md_vram_w) WRITE16_MEMBER(r2dx_v33_state::rdx_md_vram_w)
{ {
COMBINE_DATA(&md_vram[offset]); COMBINE_DATA(&m_md_vram[offset]);
md_tilemap->mark_tile_dirty(offset); m_md_tilemap->mark_tile_dirty(offset);
} }
WRITE16_MEMBER(r2dx_v33_state::rdx_fg_vram_w) WRITE16_MEMBER(r2dx_v33_state::rdx_fg_vram_w)
{ {
COMBINE_DATA(&fg_vram[offset]); COMBINE_DATA(&m_fg_vram[offset]);
fg_tilemap->mark_tile_dirty(offset); m_fg_tilemap->mark_tile_dirty(offset);
} }
WRITE16_MEMBER(r2dx_v33_state::rdx_tx_vram_w) WRITE16_MEMBER(r2dx_v33_state::rdx_tx_vram_w)
{ {
COMBINE_DATA(&tx_vram[offset]); COMBINE_DATA(&m_tx_vram[offset]);
tx_tilemap->mark_tile_dirty(offset); m_tx_tilemap->mark_tile_dirty(offset);
} }
READ16_MEMBER(r2dx_v33_state::rdx_v33_unknown_r) READ16_MEMBER(r2dx_v33_state::rdx_v33_unknown_r)
@ -385,7 +396,7 @@ static ADDRESS_MAP_START( rdx_v33_map, AS_PROGRAM, 16, r2dx_v33_state )
AM_RANGE(0x00434, 0x00435) AM_READ(rdx_v33_unknown_r) AM_RANGE(0x00434, 0x00435) AM_READ(rdx_v33_unknown_r)
AM_RANGE(0x00436, 0x00437) AM_READ(rdx_v33_unknown_r) AM_RANGE(0x00436, 0x00437) AM_READ(rdx_v33_unknown_r)
AM_RANGE(0x00600, 0x0064f) AM_RAM AM_BASE_LEGACY(&seibu_crtc_regs) AM_RANGE(0x00600, 0x0064f) AM_RAM AM_SHARE("crtc_regs")
AM_RANGE(0x00650, 0x0068f) AM_RAM //??? AM_RANGE(0x00650, 0x0068f) AM_RAM //???
AM_RANGE(0x0068e, 0x0068f) AM_WRITENOP // synch for the MCU? AM_RANGE(0x0068e, 0x0068f) AM_WRITENOP // synch for the MCU?
@ -413,10 +424,10 @@ static ADDRESS_MAP_START( rdx_v33_map, AS_PROGRAM, 16, r2dx_v33_state )
AM_RANGE(0x0c000, 0x0c7ff) AM_RAM AM_SHARE("spriteram") AM_RANGE(0x0c000, 0x0c7ff) AM_RAM AM_SHARE("spriteram")
AM_RANGE(0x0c800, 0x0cfff) AM_RAM AM_RANGE(0x0c800, 0x0cfff) AM_RAM
AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(rdx_bg_vram_w) AM_BASE_LEGACY(&bg_vram) AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(rdx_bg_vram_w) AM_SHARE("bg_vram")
AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(rdx_md_vram_w) AM_BASE_LEGACY(&md_vram) AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(rdx_md_vram_w) AM_SHARE("md_vram")
AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(rdx_fg_vram_w) AM_BASE_LEGACY(&fg_vram) AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(rdx_fg_vram_w) AM_SHARE("fg_vram")
AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(rdx_tx_vram_w) AM_BASE_LEGACY(&tx_vram) AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(rdx_tx_vram_w) AM_SHARE("tx_vram")
AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */ AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */
AM_RANGE(0x10000, 0x1efff) AM_RAM AM_RANGE(0x10000, 0x1efff) AM_RAM
AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram") AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram")
@ -462,7 +473,7 @@ static ADDRESS_MAP_START( nzerotea_map, AS_PROGRAM, 16, r2dx_v33_state )
AM_RANGE(0x00400, 0x00407) AM_WRITE(mcu_table_w) AM_RANGE(0x00400, 0x00407) AM_WRITE(mcu_table_w)
AM_RANGE(0x00420, 0x00427) AM_WRITE(mcu_table2_w) AM_RANGE(0x00420, 0x00427) AM_WRITE(mcu_table2_w)
AM_RANGE(0x00600, 0x0064f) AM_RAM AM_BASE_LEGACY(&seibu_crtc_regs) AM_RANGE(0x00600, 0x0064f) AM_RAM AM_SHARE("crtc_regs")
AM_RANGE(0x0068e, 0x0068f) AM_WRITENOP // synch for the MCU? AM_RANGE(0x0068e, 0x0068f) AM_WRITENOP // synch for the MCU?
AM_RANGE(0x006b0, 0x006b1) AM_WRITE(mcu_prog_w) AM_RANGE(0x006b0, 0x006b1) AM_WRITE(mcu_prog_w)
@ -486,10 +497,10 @@ static ADDRESS_MAP_START( nzerotea_map, AS_PROGRAM, 16, r2dx_v33_state )
AM_RANGE(0x0c000, 0x0c7ff) AM_RAM AM_SHARE("spriteram") AM_RANGE(0x0c000, 0x0c7ff) AM_RAM AM_SHARE("spriteram")
AM_RANGE(0x0c800, 0x0cfff) AM_RAM AM_RANGE(0x0c800, 0x0cfff) AM_RAM
AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(rdx_bg_vram_w) AM_BASE_LEGACY(&bg_vram) AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(rdx_bg_vram_w) AM_SHARE("bg_vram")
AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(rdx_md_vram_w) AM_BASE_LEGACY(&md_vram) AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(rdx_md_vram_w) AM_SHARE("md_vram")
AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(rdx_fg_vram_w) AM_BASE_LEGACY(&fg_vram) AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(rdx_fg_vram_w) AM_SHARE("fg_vram")
AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(rdx_tx_vram_w) AM_BASE_LEGACY(&tx_vram) AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(rdx_tx_vram_w) AM_SHARE("tx_vram")
AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */ AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */
AM_RANGE(0x10000, 0x1efff) AM_RAM AM_RANGE(0x10000, 0x1efff) AM_RAM
AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram") AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram")

8
src/mame/includes/konamigx.h
View File

@ -6,13 +6,17 @@ public:
m_maincpu(*this,"maincpu"), m_maincpu(*this,"maincpu"),
m_workram(*this,"workram"), m_workram(*this,"workram"),
m_psacram(*this,"psacram"), m_psacram(*this,"psacram"),
m_subpaletteram32(*this,"subpaletteram") m_subpaletteram32(*this,"subpaletteram"),
m_k053936_0_ctrl(*this,"k053936_0_ctrl",32),
m_k053936_0_linectrl(*this,"k053936_0_line",32)
{ } { }
required_device<cpu_device> m_maincpu; required_device<cpu_device> m_maincpu;
required_shared_ptr<UINT32> m_workram; optional_shared_ptr<UINT32> m_workram;
optional_shared_ptr<UINT32> m_psacram; optional_shared_ptr<UINT32> m_psacram;
optional_shared_ptr<UINT32> m_subpaletteram32; optional_shared_ptr<UINT32> m_subpaletteram32;
optional_shared_ptr<UINT16> m_k053936_0_ctrl;
optional_shared_ptr<UINT16> m_k053936_0_linectrl;
DECLARE_WRITE32_MEMBER(esc_w); DECLARE_WRITE32_MEMBER(esc_w);
DECLARE_WRITE32_MEMBER(eeprom_w); DECLARE_WRITE32_MEMBER(eeprom_w);
DECLARE_WRITE32_MEMBER(control_w); DECLARE_WRITE32_MEMBER(control_w);

13
src/mame/includes/midzeus.h
View File

@ -11,9 +11,18 @@ class midzeus_state : public driver_device
public: public:
midzeus_state(const machine_config &mconfig, device_type type, const char *tag) midzeus_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag), : driver_device(mconfig, type, tag),
m_nvram(*this, "nvram") { } m_nvram(*this, "nvram"),
m_ram_base(*this, "ram_base"),
m_linkram(*this, "linkram"),
m_tms32031_control(*this, "tms32031_ctl"),
m_zeusbase(*this, "zeusbase") { }
required_shared_ptr<UINT32> m_nvram; required_shared_ptr<UINT32> m_nvram;
required_shared_ptr<UINT32> m_ram_base;
optional_shared_ptr<UINT32> m_linkram;
required_shared_ptr<UINT32> m_tms32031_control;
required_shared_ptr<UINT32> m_zeusbase;
DECLARE_WRITE32_MEMBER(cmos_w); DECLARE_WRITE32_MEMBER(cmos_w);
DECLARE_READ32_MEMBER(cmos_r); DECLARE_READ32_MEMBER(cmos_r);
DECLARE_WRITE32_MEMBER(cmos_protect_w); DECLARE_WRITE32_MEMBER(cmos_protect_w);
@ -48,8 +57,6 @@ public:
/*----------- defined in video/midzeus.c -----------*/ /*----------- defined in video/midzeus.c -----------*/
extern UINT32 *zeusbase;
VIDEO_START( midzeus ); VIDEO_START( midzeus );
SCREEN_UPDATE_IND16( midzeus ); SCREEN_UPDATE_IND16( midzeus );

19
src/mame/machine/seicop.c
View File

@ -1411,7 +1411,7 @@ Miscellaneous registers:
#define seibu_cop_log logerror #define seibu_cop_log logerror
#define LOG_CMDS 1 #define LOG_CMDS 1
UINT16 *cop_mcu_ram; static UINT16 *cop_mcu_ram;
static UINT16 copd2_table[0x100]; static UINT16 copd2_table[0x100];
static UINT16 copd2_table_2[0x100/8]; static UINT16 copd2_table_2[0x100/8];
@ -1664,8 +1664,15 @@ No known explanation to this so far ...
*******************************************************************************************/ *******************************************************************************************/
// temporary hack until this is a proper device
inline void get_ram(running_machine &machine)
{
if (cop_mcu_ram == NULL) cop_mcu_ram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("cop_mcu_ram")->ptr());
}
READ16_HANDLER( copdxbl_0_r ) READ16_HANDLER( copdxbl_0_r )
{ {
get_ram(space->machine());
UINT16 retvalue = cop_mcu_ram[offset]; UINT16 retvalue = cop_mcu_ram[offset];
switch(offset) switch(offset)
@ -1692,6 +1699,7 @@ READ16_HANDLER( copdxbl_0_r )
WRITE16_HANDLER( copdxbl_0_w ) WRITE16_HANDLER( copdxbl_0_w )
{ {
legionna_state *state = space->machine().driver_data<legionna_state>(); legionna_state *state = space->machine().driver_data<legionna_state>();
get_ram(space->machine());
COMBINE_DATA(&cop_mcu_ram[offset]); COMBINE_DATA(&cop_mcu_ram[offset]);
switch(offset) switch(offset)
@ -1814,6 +1822,7 @@ static UINT8 cop_calculate_collsion_detection(running_machine &machine)
static READ16_HANDLER( generic_cop_r ) static READ16_HANDLER( generic_cop_r )
{ {
UINT16 retvalue; UINT16 retvalue;
get_ram(space->machine());
retvalue = cop_mcu_ram[offset]; retvalue = cop_mcu_ram[offset];
@ -1883,6 +1892,7 @@ static UINT32 cop_sprite_dma_param;
static WRITE16_HANDLER( generic_cop_w ) static WRITE16_HANDLER( generic_cop_w )
{ {
UINT32 temp32; UINT32 temp32;
get_ram(space->machine());
switch (offset) switch (offset)
{ {
@ -2716,6 +2726,7 @@ READ16_HANDLER( heatbrl_mcu_r )
WRITE16_HANDLER( heatbrl_mcu_w ) WRITE16_HANDLER( heatbrl_mcu_w )
{ {
get_ram(space->machine());
COMBINE_DATA(&cop_mcu_ram[offset]); COMBINE_DATA(&cop_mcu_ram[offset]);
/* external pin register, used for banking */ /* external pin register, used for banking */
@ -2771,6 +2782,7 @@ READ16_HANDLER( cupsoc_mcu_r )
WRITE16_HANDLER( cupsoc_mcu_w ) WRITE16_HANDLER( cupsoc_mcu_w )
{ {
get_ram(space->machine());
COMBINE_DATA(&cop_mcu_ram[offset]); COMBINE_DATA(&cop_mcu_ram[offset]);
if(offset == 0x280/2) //irq ack / sprite buffering? if(offset == 0x280/2) //irq ack / sprite buffering?
@ -2813,6 +2825,7 @@ READ16_HANDLER( cupsocs_mcu_r )
WRITE16_HANDLER( cupsocs_mcu_w ) WRITE16_HANDLER( cupsocs_mcu_w )
{ {
get_ram(space->machine());
COMBINE_DATA(&cop_mcu_ram[offset]); COMBINE_DATA(&cop_mcu_ram[offset]);
if(offset == 0x280/2) //irq ack / sprite buffering? if(offset == 0x280/2) //irq ack / sprite buffering?
@ -2860,6 +2873,7 @@ READ16_HANDLER( godzilla_mcu_r )
WRITE16_HANDLER( godzilla_mcu_w ) WRITE16_HANDLER( godzilla_mcu_w )
{ {
get_ram(space->machine());
COMBINE_DATA(&cop_mcu_ram[offset]); COMBINE_DATA(&cop_mcu_ram[offset]);
if(offset == 0x070/2) if(offset == 0x070/2)
@ -2912,6 +2926,7 @@ READ16_HANDLER( denjinmk_mcu_r )
WRITE16_HANDLER( denjinmk_mcu_w ) WRITE16_HANDLER( denjinmk_mcu_w )
{ {
get_ram(space->machine());
COMBINE_DATA(&cop_mcu_ram[offset]); COMBINE_DATA(&cop_mcu_ram[offset]);
if(offset == 0x280/2) //irq ack / sprite buffering? if(offset == 0x280/2) //irq ack / sprite buffering?
@ -2965,6 +2980,7 @@ READ16_HANDLER( grainbow_mcu_r )
WRITE16_HANDLER( grainbow_mcu_w ) WRITE16_HANDLER( grainbow_mcu_w )
{ {
get_ram(space->machine());
COMBINE_DATA(&cop_mcu_ram[offset]); COMBINE_DATA(&cop_mcu_ram[offset]);
if(offset == 0x280/2) //irq ack / sprite buffering? if(offset == 0x280/2) //irq ack / sprite buffering?
@ -3007,6 +3023,7 @@ READ16_HANDLER( legionna_mcu_r )
WRITE16_HANDLER( legionna_mcu_w ) WRITE16_HANDLER( legionna_mcu_w )
{ {
get_ram(space->machine());
COMBINE_DATA(&cop_mcu_ram[offset]); COMBINE_DATA(&cop_mcu_ram[offset]);
if(offset == 0x070/2) //external pin: puts bit 13 high, delay, reads 0x748, writes bit 13 low if(offset == 0x070/2) //external pin: puts bit 13 high, delay, reads 0x748, writes bit 13 low

2
src/mame/machine/seicop.h
View File

@ -1,5 +1,3 @@
extern UINT16* cop_mcu_ram;
READ16_HANDLER( copdxbl_0_r ); READ16_HANDLER( copdxbl_0_r );
WRITE16_HANDLER( copdxbl_0_w ); WRITE16_HANDLER( copdxbl_0_w );

6
src/mame/video/konamigx.c
View File

@ -348,13 +348,15 @@ static void K053936GP_zoom_draw(running_machine &machine,
static void K053936GP_0_zoom_draw(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect, static void K053936GP_0_zoom_draw(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect,
tilemap_t *tmap, int tilebpp, int blend, int alpha, int pixeldouble_output) tilemap_t *tmap, int tilebpp, int blend, int alpha, int pixeldouble_output)
{ {
K053936GP_zoom_draw(machine, 0,K053936_0_ctrl,K053936_0_linectrl,bitmap,cliprect,tmap,tilebpp,blend,alpha, pixeldouble_output); konamigx_state *state = machine.driver_data<konamigx_state>();
K053936GP_zoom_draw(machine, 0,state->m_k053936_0_ctrl,state->m_k053936_0_linectrl,bitmap,cliprect,tmap,tilebpp,blend,alpha, pixeldouble_output);
} }
static void K053936GP_1_zoom_draw(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect, static void K053936GP_1_zoom_draw(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect,
tilemap_t *tmap, int tilebpp, int blend, int alpha, int pixeldouble_output) tilemap_t *tmap, int tilebpp, int blend, int alpha, int pixeldouble_output)
{ {
K053936GP_zoom_draw(machine, 1,K053936_1_ctrl,K053936_1_linectrl,bitmap,cliprect,tmap,tilebpp,blend,alpha, pixeldouble_output); // konamigx_state *state = machine.driver_data<konamigx_state>();
// K053936GP_zoom_draw(machine, 1,K053936_1_ctrl,K053936_1_linectrl,bitmap,cliprect,tmap,tilebpp,blend,alpha, pixeldouble_output);
} }

6
src/mame/video/konamiic.c
View File

@ -1510,8 +1510,6 @@ int K053246_is_IRQ_enabled(void)
#define K053936_MAX_CHIPS 2 #define K053936_MAX_CHIPS 2
UINT16 *K053936_0_ctrl,*K053936_0_linectrl;
UINT16 *K053936_1_ctrl,*K053936_1_linectrl;
static int K053936_offset[K053936_MAX_CHIPS][2]; static int K053936_offset[K053936_MAX_CHIPS][2];
static int K053936_wraparound[K053936_MAX_CHIPS]; static int K053936_wraparound[K053936_MAX_CHIPS];
@ -1641,7 +1639,9 @@ if (machine.input().code_pressed(KEYCODE_D))
void K053936_0_zoom_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,tilemap_t *tmap,int flags,UINT32 priority, int glfgreat_hack) void K053936_0_zoom_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,tilemap_t *tmap,int flags,UINT32 priority, int glfgreat_hack)
{ {
K053936_zoom_draw(0,K053936_0_ctrl,K053936_0_linectrl,bitmap,cliprect,tmap,flags,priority, glfgreat_hack); UINT16 *ctrl = reinterpret_cast<UINT16 *>(tmap->machine().root_device().memshare("k053936_0_ctrl")->ptr());
UINT16 *linectrl = reinterpret_cast<UINT16 *>(tmap->machine().root_device().memshare("k053936_0_line")->ptr());
K053936_zoom_draw(0,ctrl,linectrl,bitmap,cliprect,tmap,flags,priority, glfgreat_hack);
} }
void K053936_wraparound_enable(int chip, int status) void K053936_wraparound_enable(int chip, int status)

2
src/mame/video/konamiic.h
View File

@ -36,7 +36,7 @@ int K053246_is_IRQ_enabled(void);
int K053246_read_register(int regnum); int K053246_read_register(int regnum);
extern UINT16 *K053936_0_ctrl,*K053936_0_linectrl; extern UINT16 *K053936_0_ctrl,*K053936_0_linectrl;
extern UINT16 *K053936_1_ctrl,*K053936_1_linectrl; //extern UINT16 *K053936_1_ctrl,*K053936_1_linectrl;
void K053936_0_zoom_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,tilemap_t *tmap,int flags,UINT32 priority, int glfgreat_hack); void K053936_0_zoom_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,tilemap_t *tmap,int flags,UINT32 priority, int glfgreat_hack);
void K053936_wraparound_enable(int chip, int status); void K053936_wraparound_enable(int chip, int status);
void K053936_set_offset(int chip, int xoffs, int yoffs); void K053936_set_offset(int chip, int xoffs, int yoffs);

179
src/mame/video/midzeus.c
View File

@ -56,8 +56,6 @@ struct _poly_extra_data
* *
*************************************/ *************************************/
UINT32 *zeusbase;
static poly_manager *poly; static poly_manager *poly;
static UINT8 log_fifo; static UINT8 log_fifo;
@ -341,7 +339,8 @@ SCREEN_UPDATE_IND16( midzeus )
/* normal update case */ /* normal update case */
if (!screen.machine().input().code_pressed(KEYCODE_W)) if (!screen.machine().input().code_pressed(KEYCODE_W))
{ {
const void *base = waveram1_ptr_from_expanded_addr(zeusbase[0xcc]); midzeus_state *state = screen.machine().driver_data<midzeus_state>();
const void *base = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0xcc]);
int xoffs = screen.visible_area().min_x; int xoffs = screen.visible_area().min_x;
for (y = cliprect.min_y; y <= cliprect.max_y; y++) for (y = cliprect.min_y; y <= cliprect.max_y; y++)
{ {
@ -390,7 +389,7 @@ SCREEN_UPDATE_IND16( midzeus )
READ32_MEMBER(midzeus_state::zeus_r) READ32_MEMBER(midzeus_state::zeus_r)
{ {
int logit = (offset < 0xb0 || offset > 0xb7); int logit = (offset < 0xb0 || offset > 0xb7);
UINT32 result = zeusbase[offset & ~1]; UINT32 result = m_zeusbase[offset & ~1];
switch (offset & ~1) switch (offset & ~1)
{ {
@ -414,14 +413,14 @@ READ32_MEMBER(midzeus_state::zeus_r)
case 0xf6: // status -- they wait for this & 9 == 0 case 0xf6: // status -- they wait for this & 9 == 0
// value & $9600 must == $9600 to pass Zeus system test // value & $9600 must == $9600 to pass Zeus system test
result = 0x9600; result = 0x9600;
if (zeusbase[0xb6] == 0x80040000) if (m_zeusbase[0xb6] == 0x80040000)
result |= 1; result |= 1;
logit = 0; logit = 0;
break; break;
} }
/* 32-bit mode */ /* 32-bit mode */
if (zeusbase[0x80] & 0x00020000) if (m_zeusbase[0x80] & 0x00020000)
{ {
if (offset & 1) if (offset & 1)
result >>= 16; result >>= 16;
@ -465,7 +464,7 @@ WRITE32_MEMBER(midzeus_state::zeus_w)
logerror("%06X:zeus_w", space.device().safe_pc()); logerror("%06X:zeus_w", space.device().safe_pc());
/* 32-bit mode */ /* 32-bit mode */
if (zeusbase[0x80] & 0x00020000) if (m_zeusbase[0x80] & 0x00020000)
zeus_register32_w(machine(), offset, data, logit); zeus_register32_w(machine(), offset, data, logit);
/* 16-bit mode */ /* 16-bit mode */
@ -546,21 +545,23 @@ static void zeus_pointer_w(UINT32 which, UINT32 data, int logit)
static void zeus_register16_w(running_machine &machine, offs_t offset, UINT16 data, int logit) static void zeus_register16_w(running_machine &machine, offs_t offset, UINT16 data, int logit)
{ {
midzeus_state *state = machine.driver_data<midzeus_state>();
/* writes to register $CC need to force a partial update */ /* writes to register $CC need to force a partial update */
if ((offset & ~1) == 0xcc) if ((offset & ~1) == 0xcc)
machine.primary_screen->update_partial(machine.primary_screen->vpos()); machine.primary_screen->update_partial(machine.primary_screen->vpos());
/* write to high part on odd addresses */ /* write to high part on odd addresses */
if (offset & 1) if (offset & 1)
zeusbase[offset & ~1] = (zeusbase[offset & ~1] & 0x0000ffff) | (data << 16); state->m_zeusbase[offset & ~1] = (state->m_zeusbase[offset & ~1] & 0x0000ffff) | (data << 16);
/* write to low part on event addresses */ /* write to low part on event addresses */
else else
zeusbase[offset & ~1] = (zeusbase[offset & ~1] & 0xffff0000) | (data & 0xffff); state->m_zeusbase[offset & ~1] = (state->m_zeusbase[offset & ~1] & 0xffff0000) | (data & 0xffff);
/* log appropriately */ /* log appropriately */
if (logit) if (logit)
logerror("(%02X) = %04X [%08X]\n", offset, data & 0xffff, zeusbase[offset & ~1]); logerror("(%02X) = %04X [%08X]\n", offset, data & 0xffff, state->m_zeusbase[offset & ~1]);
/* handle the update */ /* handle the update */
if ((offset & 1) == 0) if ((offset & 1) == 0)
@ -570,12 +571,14 @@ static void zeus_register16_w(running_machine &machine, offs_t offset, UINT16 da
static void zeus_register32_w(running_machine &machine, offs_t offset, UINT32 data, int logit) static void zeus_register32_w(running_machine &machine, offs_t offset, UINT32 data, int logit)
{ {
midzeus_state *state = machine.driver_data<midzeus_state>();
/* writes to register $CC need to force a partial update */ /* writes to register $CC need to force a partial update */
if ((offset & ~1) == 0xcc) if ((offset & ~1) == 0xcc)
machine.primary_screen->update_partial(machine.primary_screen->vpos()); machine.primary_screen->update_partial(machine.primary_screen->vpos());
/* always write to low word? */ /* always write to low word? */
zeusbase[offset & ~1] = data; state->m_zeusbase[offset & ~1] = data;
/* log appropriately */ /* log appropriately */
if (logit) if (logit)
@ -603,54 +606,56 @@ static void zeus_register32_w(running_machine &machine, offs_t offset, UINT32 da
static void zeus_register_update(running_machine &machine, offs_t offset) static void zeus_register_update(running_machine &machine, offs_t offset)
{ {
midzeus_state *state = machine.driver_data<midzeus_state>();
/* handle the writes; only trigger on low accesses */ /* handle the writes; only trigger on low accesses */
switch (offset) switch (offset)
{ {
case 0x52: case 0x52:
zeusbase[0xb2] = zeusbase[0x52]; state->m_zeusbase[0xb2] = state->m_zeusbase[0x52];
break; break;
case 0x60: case 0x60:
/* invasn writes here to execute a command (?) */ /* invasn writes here to execute a command (?) */
if (zeusbase[0x60] & 1) if (state->m_zeusbase[0x60] & 1)
{ {
if ((zeusbase[0x80] & 0xffffff) == 0x22FCFF) if ((state->m_zeusbase[0x80] & 0xffffff) == 0x22FCFF)
{ {
// zeusbase[0x00] = color // state->m_zeusbase[0x00] = color
// zeusbase[0x02] = ??? = 0x000C0000 // state->m_zeusbase[0x02] = ??? = 0x000C0000
// zeusbase[0x04] = ??? = 0x00000E01 // state->m_zeusbase[0x04] = ??? = 0x00000E01
// zeusbase[0x06] = ??? = 0xFFFF0030 // state->m_zeusbase[0x06] = ??? = 0xFFFF0030
// zeusbase[0x08] = vert[0] = (y0 << 16) | x0 // state->m_zeusbase[0x08] = vert[0] = (y0 << 16) | x0
// zeusbase[0x0a] = vert[1] = (y1 << 16) | x1 // state->m_zeusbase[0x0a] = vert[1] = (y1 << 16) | x1
// zeusbase[0x0c] = vert[2] = (y2 << 16) | x2 // state->m_zeusbase[0x0c] = vert[2] = (y2 << 16) | x2
// zeusbase[0x0e] = vert[3] = (y3 << 16) | x3 // state->m_zeusbase[0x0e] = vert[3] = (y3 << 16) | x3
// zeusbase[0x18] = ??? = 0xFFFFFFFF // state->m_zeusbase[0x18] = ??? = 0xFFFFFFFF
// zeusbase[0x1a] = ??? = 0xFFFFFFFF // state->m_zeusbase[0x1a] = ??? = 0xFFFFFFFF
// zeusbase[0x1c] = ??? = 0xFFFFFFFF // state->m_zeusbase[0x1c] = ??? = 0xFFFFFFFF
// zeusbase[0x1e] = ??? = 0xFFFFFFFF // state->m_zeusbase[0x1e] = ??? = 0xFFFFFFFF
// zeusbase[0x20] = ??? = 0x00000000 // state->m_zeusbase[0x20] = ??? = 0x00000000
// zeusbase[0x22] = ??? = 0x00000000 // state->m_zeusbase[0x22] = ??? = 0x00000000
// zeusbase[0x24] = ??? = 0x00000000 // state->m_zeusbase[0x24] = ??? = 0x00000000
// zeusbase[0x26] = ??? = 0x00000000 // state->m_zeusbase[0x26] = ??? = 0x00000000
// zeusbase[0x40] = ??? = 0x00000000 // state->m_zeusbase[0x40] = ??? = 0x00000000
// zeusbase[0x42] = ??? = 0x00000000 // state->m_zeusbase[0x42] = ??? = 0x00000000
// zeusbase[0x44] = ??? = 0x00000000 // state->m_zeusbase[0x44] = ??? = 0x00000000
// zeusbase[0x46] = ??? = 0x00000000 // state->m_zeusbase[0x46] = ??? = 0x00000000
// zeusbase[0x4c] = ??? = 0x00808080 (brightness?) // state->m_zeusbase[0x4c] = ??? = 0x00808080 (brightness?)
// zeusbase[0x4e] = ??? = 0x00808080 (brightness?) // state->m_zeusbase[0x4e] = ??? = 0x00808080 (brightness?)
poly_extra_data *extra = (poly_extra_data *)poly_get_extra_data(poly); poly_extra_data *extra = (poly_extra_data *)poly_get_extra_data(poly);
poly_vertex vert[4]; poly_vertex vert[4];
vert[0].x = (INT16)zeusbase[0x08]; vert[0].x = (INT16)state->m_zeusbase[0x08];
vert[0].y = (INT16)(zeusbase[0x08] >> 16); vert[0].y = (INT16)(state->m_zeusbase[0x08] >> 16);
vert[1].x = (INT16)zeusbase[0x0a]; vert[1].x = (INT16)state->m_zeusbase[0x0a];
vert[1].y = (INT16)(zeusbase[0x0a] >> 16); vert[1].y = (INT16)(state->m_zeusbase[0x0a] >> 16);
vert[2].x = (INT16)zeusbase[0x0c]; vert[2].x = (INT16)state->m_zeusbase[0x0c];
vert[2].y = (INT16)(zeusbase[0x0c] >> 16); vert[2].y = (INT16)(state->m_zeusbase[0x0c] >> 16);
vert[3].x = (INT16)zeusbase[0x0e]; vert[3].x = (INT16)state->m_zeusbase[0x0e];
vert[3].y = (INT16)(zeusbase[0x0e] >> 16); vert[3].y = (INT16)(state->m_zeusbase[0x0e] >> 16);
extra->solidcolor = zeusbase[0x00]; extra->solidcolor = state->m_zeusbase[0x00];
extra->zoffset = 0x7fff; extra->zoffset = 0x7fff;
poly_render_quad(poly, NULL, zeus_cliprect, render_poly_solid_fixedz, 0, &vert[0], &vert[1], &vert[2], &vert[3]); poly_render_quad(poly, NULL, zeus_cliprect, render_poly_solid_fixedz, 0, &vert[0], &vert[1], &vert[2], &vert[3]);
@ -662,22 +667,22 @@ static void zeus_register_update(running_machine &machine, offs_t offset)
break; break;
case 0x70: case 0x70:
zeus_point[0] = zeusbase[0x70] << 16; zeus_point[0] = state->m_zeusbase[0x70] << 16;
break; break;
case 0x72: case 0x72:
zeus_point[1] = zeusbase[0x72] << 16; zeus_point[1] = state->m_zeusbase[0x72] << 16;
break; break;
case 0x74: case 0x74:
zeus_point[2] = zeusbase[0x74] << 16; zeus_point[2] = state->m_zeusbase[0x74] << 16;
break; break;
case 0x80: case 0x80:
/* this bit enables the "FIFO empty" IRQ; since our virtual FIFO is always empty, /* this bit enables the "FIFO empty" IRQ; since our virtual FIFO is always empty,
we simply assert immediately if this is enabled. invasn needs this for proper we simply assert immediately if this is enabled. invasn needs this for proper
operations */ operations */
if (zeusbase[0x80] & 0x02000000) if (state->m_zeusbase[0x80] & 0x02000000)
machine.device("maincpu")->execute().set_input_line(2, ASSERT_LINE); machine.device("maincpu")->execute().set_input_line(2, ASSERT_LINE);
else else
machine.device("maincpu")->execute().set_input_line(2, CLEAR_LINE); machine.device("maincpu")->execute().set_input_line(2, CLEAR_LINE);
@ -686,50 +691,50 @@ static void zeus_register_update(running_machine &machine, offs_t offset)
case 0x84: case 0x84:
/* MK4: Written in tandem with 0xcc */ /* MK4: Written in tandem with 0xcc */
/* MK4: Writes either 0x80 (and 0x000000 to 0xcc) or 0x00 (and 0x800000 to 0xcc) */ /* MK4: Writes either 0x80 (and 0x000000 to 0xcc) or 0x00 (and 0x800000 to 0xcc) */
zeus_renderbase = waveram1_ptr_from_expanded_addr(zeusbase[0x84] << 16); zeus_renderbase = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0x84] << 16);
break; break;
case 0xb0: case 0xb0:
case 0xb2: case 0xb2:
if ((zeusbase[0xb6] >> 16) != 0) if ((state->m_zeusbase[0xb6] >> 16) != 0)
{ {
if ((offset == 0xb0 && (zeusbase[0xb6] & 0x02000000) == 0) || if ((offset == 0xb0 && (state->m_zeusbase[0xb6] & 0x02000000) == 0) ||
(offset == 0xb2 && (zeusbase[0xb6] & 0x02000000) != 0)) (offset == 0xb2 && (state->m_zeusbase[0xb6] & 0x02000000) != 0))
{ {
void *dest; void *dest;
if (zeusbase[0xb6] & 0x80000000) if (state->m_zeusbase[0xb6] & 0x80000000)
dest = waveram1_ptr_from_expanded_addr(zeusbase[0xb4]); dest = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0xb4]);
else else
dest = waveram0_ptr_from_expanded_addr(zeusbase[0xb4]); dest = waveram0_ptr_from_expanded_addr(state->m_zeusbase[0xb4]);
if (zeusbase[0xb6] & 0x00100000) if (state->m_zeusbase[0xb6] & 0x00100000)
WAVERAM_WRITE16(dest, 0, zeusbase[0xb0]); WAVERAM_WRITE16(dest, 0, state->m_zeusbase[0xb0]);
if (zeusbase[0xb6] & 0x00200000) if (state->m_zeusbase[0xb6] & 0x00200000)
WAVERAM_WRITE16(dest, 1, zeusbase[0xb0] >> 16); WAVERAM_WRITE16(dest, 1, state->m_zeusbase[0xb0] >> 16);
if (zeusbase[0xb6] & 0x00400000) if (state->m_zeusbase[0xb6] & 0x00400000)
WAVERAM_WRITE16(dest, 2, zeusbase[0xb2]); WAVERAM_WRITE16(dest, 2, state->m_zeusbase[0xb2]);
if (zeusbase[0xb6] & 0x00800000) if (state->m_zeusbase[0xb6] & 0x00800000)
WAVERAM_WRITE16(dest, 3, zeusbase[0xb2] >> 16); WAVERAM_WRITE16(dest, 3, state->m_zeusbase[0xb2] >> 16);
if (zeusbase[0xb6] & 0x00020000) if (state->m_zeusbase[0xb6] & 0x00020000)
zeusbase[0xb4]++; state->m_zeusbase[0xb4]++;
} }
} }
break; break;
case 0xb4: case 0xb4:
if (zeusbase[0xb6] & 0x00010000) if (state->m_zeusbase[0xb6] & 0x00010000)
{ {
const UINT32 *src; const UINT32 *src;
if (zeusbase[0xb6] & 0x80000000) if (state->m_zeusbase[0xb6] & 0x80000000)
src = (const UINT32 *)waveram1_ptr_from_expanded_addr(zeusbase[0xb4]); src = (const UINT32 *)waveram1_ptr_from_expanded_addr(state->m_zeusbase[0xb4]);
else else
src = (const UINT32 *)waveram0_ptr_from_expanded_addr(zeusbase[0xb4]); src = (const UINT32 *)waveram0_ptr_from_expanded_addr(state->m_zeusbase[0xb4]);
poly_wait(poly, "vram_read"); poly_wait(poly, "vram_read");
zeusbase[0xb0] = WAVERAM_READ32(src, 0); state->m_zeusbase[0xb0] = WAVERAM_READ32(src, 0);
zeusbase[0xb2] = WAVERAM_READ32(src, 1); state->m_zeusbase[0xb2] = WAVERAM_READ32(src, 1);
} }
break; break;
@ -741,10 +746,10 @@ static void zeus_register_update(running_machine &machine, offs_t offset)
case 0xca: case 0xca:
machine.primary_screen->update_partial(machine.primary_screen->vpos()); machine.primary_screen->update_partial(machine.primary_screen->vpos());
{ {
int vtotal = zeusbase[0xca] >> 16; int vtotal = state->m_zeusbase[0xca] >> 16;
int htotal = zeusbase[0xc6] >> 16; int htotal = state->m_zeusbase[0xc6] >> 16;
rectangle visarea(zeusbase[0xc6] & 0xffff, htotal - 3, 0, zeusbase[0xc8] & 0xffff); rectangle visarea(state->m_zeusbase[0xc6] & 0xffff, htotal - 3, 0, state->m_zeusbase[0xc8] & 0xffff);
if (htotal > 0 && vtotal > 0 && visarea.min_x < visarea.max_x && visarea.max_y < vtotal) if (htotal > 0 && vtotal > 0 && visarea.min_x < visarea.max_x && visarea.max_y < vtotal)
{ {
machine.primary_screen->configure(htotal, vtotal, visarea, HZ_TO_ATTOSECONDS((double)MIDZEUS_VIDEO_CLOCK / 8.0 / (htotal * vtotal))); machine.primary_screen->configure(htotal, vtotal, visarea, HZ_TO_ATTOSECONDS((double)MIDZEUS_VIDEO_CLOCK / 8.0 / (htotal * vtotal)));
@ -761,7 +766,7 @@ static void zeus_register_update(running_machine &machine, offs_t offset)
break; break;
case 0xe0: case 0xe0:
zeus_fifo[zeus_fifo_words++] = zeusbase[0xe0]; zeus_fifo[zeus_fifo_words++] = state->m_zeusbase[0xe0];
if (zeus_fifo_process(machine, zeus_fifo, zeus_fifo_words)) if (zeus_fifo_process(machine, zeus_fifo, zeus_fifo_words))
zeus_fifo_words = 0; zeus_fifo_words = 0;
break; break;
@ -778,6 +783,8 @@ static void zeus_register_update(running_machine &machine, offs_t offset)
static int zeus_fifo_process(running_machine &machine, const UINT32 *data, int numwords) static int zeus_fifo_process(running_machine &machine, const UINT32 *data, int numwords)
{ {
midzeus_state *state = machine.driver_data<midzeus_state>();
/* handle logging */ /* handle logging */
switch (data[0] >> 24) switch (data[0] >> 24)
{ {
@ -796,7 +803,7 @@ static int zeus_fifo_process(running_machine &machine, const UINT32 *data, int n
case 0x13: /* invasn */ case 0x13: /* invasn */
if (log_fifo) if (log_fifo)
log_fifo_command(data, numwords, ""); log_fifo_command(data, numwords, "");
zeus_draw_model(machine, (zeusbase[0x06] << 16), log_fifo); zeus_draw_model(machine, (state->m_zeusbase[0x06] << 16), log_fifo);
break; break;
/* 0x17: write 16-bit value to low registers */ /* 0x17: write 16-bit value to low registers */
@ -957,7 +964,7 @@ static int zeus_fifo_process(running_machine &machine, const UINT32 *data, int n
} }
else else
{ {
UINT32 texdata = (zeusbase[0x06] << 16) | (zeusbase[0x00] >> 16); UINT32 texdata = (state->m_zeusbase[0x06] << 16) | (state->m_zeusbase[0x00] >> 16);
zeus_draw_quad(machine, FALSE, data, texdata, log_fifo); zeus_draw_quad(machine, FALSE, data, texdata, log_fifo);
} }
break; break;
@ -999,6 +1006,7 @@ static int zeus_fifo_process(running_machine &machine, const UINT32 *data, int n
static void zeus_draw_model(running_machine &machine, UINT32 texdata, int logit) static void zeus_draw_model(running_machine &machine, UINT32 texdata, int logit)
{ {
midzeus_state *state = machine.driver_data<midzeus_state>();
UINT32 databuffer[32]; UINT32 databuffer[32];
int databufcount = 0; int databufcount = 0;
int model_done = FALSE; int model_done = FALSE;
@ -1058,7 +1066,7 @@ static void zeus_draw_model(running_machine &machine, UINT32 texdata, int logit)
logerror("reg16"); logerror("reg16");
zeus_register16_w(machine, (databuffer[0] >> 16) & 0x7f, databuffer[0], logit); zeus_register16_w(machine, (databuffer[0] >> 16) & 0x7f, databuffer[0], logit);
if (((databuffer[0] >> 16) & 0x7f) == 0x06) if (((databuffer[0] >> 16) & 0x7f) == 0x06)
texdata = (texdata & 0xffff) | (zeusbase[0x06] << 16); texdata = (texdata & 0xffff) | (state->m_zeusbase[0x06] << 16);
break; break;
case 0x19: /* invasn */ case 0x19: /* invasn */
@ -1066,7 +1074,7 @@ static void zeus_draw_model(running_machine &machine, UINT32 texdata, int logit)
logerror("reg32"); logerror("reg32");
zeus_register32_w(machine, (databuffer[0] >> 16) & 0x7f, databuffer[1], logit); zeus_register32_w(machine, (databuffer[0] >> 16) & 0x7f, databuffer[1], logit);
if (((databuffer[0] >> 16) & 0x7f) == 0x06) if (((databuffer[0] >> 16) & 0x7f) == 0x06)
texdata = (texdata & 0xffff) | (zeusbase[0x06] << 16); texdata = (texdata & 0xffff) | (state->m_zeusbase[0x06] << 16);
break; break;
case 0x25: /* mk4 */ case 0x25: /* mk4 */
@ -1098,6 +1106,7 @@ static void zeus_draw_model(running_machine &machine, UINT32 texdata, int logit)
static void zeus_draw_quad(running_machine &machine, int long_fmt, const UINT32 *databuffer, UINT32 texdata, int logit) static void zeus_draw_quad(running_machine &machine, int long_fmt, const UINT32 *databuffer, UINT32 texdata, int logit)
{ {
midzeus_state *state = machine.driver_data<midzeus_state>();
poly_draw_scanline_func callback; poly_draw_scanline_func callback;
poly_extra_data *extra; poly_extra_data *extra;
poly_vertex clipvert[8]; poly_vertex clipvert[8];
@ -1148,8 +1157,8 @@ static void zeus_draw_quad(running_machine &machine, int long_fmt, const UINT32
val2 = (texdata >> 16) & 0x3ff; val2 = (texdata >> 16) & 0x3ff;
texwshift = (val2 >> 6) & 7; texwshift = (val2 >> 6) & 7;
uscale = (8 >> ((zeusbase[0x04] >> 4) & 3)) * 0.125f * 256.0f; uscale = (8 >> ((state->m_zeusbase[0x04] >> 4) & 3)) * 0.125f * 256.0f;
vscale = (8 >> ((zeusbase[0x04] >> 6) & 3)) * 0.125f * 256.0f; vscale = (8 >> ((state->m_zeusbase[0x04] >> 6) & 3)) * 0.125f * 256.0f;
int xy_offset = long_fmt ? 2 : 1; int xy_offset = long_fmt ? 2 : 1;
@ -1265,9 +1274,9 @@ static void zeus_draw_quad(running_machine &machine, int long_fmt, const UINT32
printf("Unknown draw mode: %.8x\n", ctrl_word); printf("Unknown draw mode: %.8x\n", ctrl_word);
return; return;
} }
extra->solidcolor = zeusbase[0x00] & 0x7fff; extra->solidcolor = state->m_zeusbase[0x00] & 0x7fff;
extra->zoffset = zeusbase[0x7e] >> 16; extra->zoffset = state->m_zeusbase[0x7e] >> 16;
extra->alpha = zeusbase[0x4e]; extra->alpha = state->m_zeusbase[0x4e];
extra->transcolor = ((ctrl_word >> 16) & 1) ? 0 : 0x100; extra->transcolor = ((ctrl_word >> 16) & 1) ? 0 : 0x100;
extra->palbase = waveram0_ptr_from_block_addr(zeus_palbase); extra->palbase = waveram0_ptr_from_block_addr(zeus_palbase);

141
src/mame/video/midzeus2.c
View File

@ -370,7 +370,8 @@ if (screen.machine().input().code_pressed(KEYCODE_DOWN)) { zbase -= 1.0f; popmes
/* normal update case */ /* normal update case */
if (!screen.machine().input().code_pressed(KEYCODE_W)) if (!screen.machine().input().code_pressed(KEYCODE_W))
{ {
const void *base = waveram1_ptr_from_expanded_addr(zeusbase[0x38]); midzeus_state *state = screen.machine().driver_data<midzeus_state>();
const void *base = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0x38]);
int xoffs = screen.visible_area().min_x; int xoffs = screen.visible_area().min_x;
for (y = cliprect.min_y; y <= cliprect.max_y; y++) for (y = cliprect.min_y; y <= cliprect.max_y; y++)
{ {
@ -419,7 +420,8 @@ if (screen.machine().input().code_pressed(KEYCODE_DOWN)) { zbase -= 1.0f; popmes
READ32_HANDLER( zeus2_r ) READ32_HANDLER( zeus2_r )
{ {
int logit = (offset != 0x00 && offset != 0x01 && offset != 0x54 && offset != 0x48 && offset != 0x49 && offset != 0x58 && offset != 0x59 && offset != 0x5a); int logit = (offset != 0x00 && offset != 0x01 && offset != 0x54 && offset != 0x48 && offset != 0x49 && offset != 0x58 && offset != 0x59 && offset != 0x5a);
UINT32 result = zeusbase[offset]; midzeus_state *state = space->machine().driver_data<midzeus_state>();
UINT32 result = state->m_zeusbase[offset];
#if TRACK_REG_USAGE #if TRACK_REG_USAGE
regread_count[offset]++; regread_count[offset]++;
@ -486,7 +488,8 @@ WRITE32_HANDLER( zeus2_w )
static void zeus_register32_w(running_machine &machine, offs_t offset, UINT32 data, int logit) static void zeus_register32_w(running_machine &machine, offs_t offset, UINT32 data, int logit)
{ {
UINT32 oldval = zeusbase[offset]; midzeus_state *state = machine.driver_data<midzeus_state>();
UINT32 oldval = state->m_zeusbase[offset];
#if TRACK_REG_USAGE #if TRACK_REG_USAGE
regwrite_count[offset]++; regwrite_count[offset]++;
@ -512,7 +515,7 @@ if (regdata_count[offset] < 256)
// machine.primary_screen->update_partial(machine.primary_screen->vpos()); // machine.primary_screen->update_partial(machine.primary_screen->vpos());
/* always write to low word? */ /* always write to low word? */
zeusbase[offset] = data; state->m_zeusbase[offset] = data;
/* log appropriately */ /* log appropriately */
if (logit) if (logit)
@ -533,10 +536,11 @@ if (regdata_count[offset] < 256)
static void zeus_register_update(running_machine &machine, offs_t offset, UINT32 oldval, int logit) static void zeus_register_update(running_machine &machine, offs_t offset, UINT32 oldval, int logit)
{ {
/* handle the writes; only trigger on low accesses */ /* handle the writes; only trigger on low accesses */
midzeus_state *state = machine.driver_data<midzeus_state>();
switch (offset) switch (offset)
{ {
case 0x08: case 0x08:
zeus_fifo[zeus_fifo_words++] = zeusbase[0x08]; zeus_fifo[zeus_fifo_words++] = state->m_zeusbase[0x08];
if (zeus_fifo_process(machine, zeus_fifo, zeus_fifo_words)) if (zeus_fifo_process(machine, zeus_fifo, zeus_fifo_words))
zeus_fifo_words = 0; zeus_fifo_words = 0;
@ -547,12 +551,12 @@ static void zeus_register_update(running_machine &machine, offs_t offset, UINT32
case 0x20: case 0x20:
/* toggles between two values based on the page: /* toggles between two values based on the page:
Page # zeusbase[0x20] zeusbase[0x38] Page # state->m_zeusbase[0x20] state->m_zeusbase[0x38]
------ -------------- -------------- ------ -------------- --------------
0 $04000190 $00000000 0 $04000190 $00000000
1 $04000000 $01900000 1 $04000000 $01900000
*/ */
zeus_pointer_write(zeusbase[0x20] >> 24, zeusbase[0x20]); zeus_pointer_write(state->m_zeusbase[0x20] >> 24, state->m_zeusbase[0x20]);
break; break;
case 0x33: case 0x33:
@ -562,10 +566,10 @@ static void zeus_register_update(running_machine &machine, offs_t offset, UINT32
case 0x37: case 0x37:
machine.primary_screen->update_partial(machine.primary_screen->vpos()); machine.primary_screen->update_partial(machine.primary_screen->vpos());
{ {
int vtotal = zeusbase[0x37] & 0xffff; int vtotal = state->m_zeusbase[0x37] & 0xffff;
int htotal = zeusbase[0x34] >> 16; int htotal = state->m_zeusbase[0x34] >> 16;
rectangle visarea(zeusbase[0x33] >> 16, (zeusbase[0x34] & 0xffff) - 1, 0, zeusbase[0x35] & 0xffff); rectangle visarea(state->m_zeusbase[0x33] >> 16, (state->m_zeusbase[0x34] & 0xffff) - 1, 0, state->m_zeusbase[0x35] & 0xffff);
if (htotal > 0 && vtotal > 0 && visarea.min_x < visarea.max_x && visarea.max_y < vtotal) if (htotal > 0 && vtotal > 0 && visarea.min_x < visarea.max_x && visarea.max_y < vtotal)
{ {
machine.primary_screen->configure(htotal, vtotal, visarea, HZ_TO_ATTOSECONDS((double)MIDZEUS_VIDEO_CLOCK / 4.0 / (htotal * vtotal))); machine.primary_screen->configure(htotal, vtotal, visarea, HZ_TO_ATTOSECONDS((double)MIDZEUS_VIDEO_CLOCK / 4.0 / (htotal * vtotal)));
@ -578,28 +582,28 @@ static void zeus_register_update(running_machine &machine, offs_t offset, UINT32
case 0x38: case 0x38:
{ {
UINT32 temp = zeusbase[0x38]; UINT32 temp = state->m_zeusbase[0x38];
zeusbase[0x38] = oldval; state->m_zeusbase[0x38] = oldval;
machine.primary_screen->update_partial(machine.primary_screen->vpos()); machine.primary_screen->update_partial(machine.primary_screen->vpos());
log_fifo = machine.input().code_pressed(KEYCODE_L); log_fifo = machine.input().code_pressed(KEYCODE_L);
zeusbase[0x38] = temp; state->m_zeusbase[0x38] = temp;
} }
break; break;
case 0x41: case 0x41:
/* this is the address, except in read mode, where it latches values */ /* this is the address, except in read mode, where it latches values */
if (zeusbase[0x4e] & 0x10) if (state->m_zeusbase[0x4e] & 0x10)
{ {
const void *src = waveram0_ptr_from_expanded_addr(oldval); const void *src = waveram0_ptr_from_expanded_addr(oldval);
zeusbase[0x41] = oldval; state->m_zeusbase[0x41] = oldval;
zeusbase[0x48] = WAVERAM_READ32(src, 0); state->m_zeusbase[0x48] = WAVERAM_READ32(src, 0);
zeusbase[0x49] = WAVERAM_READ32(src, 1); state->m_zeusbase[0x49] = WAVERAM_READ32(src, 1);
if (zeusbase[0x4e] & 0x40) if (state->m_zeusbase[0x4e] & 0x40)
{ {
zeusbase[0x41]++; state->m_zeusbase[0x41]++;
zeusbase[0x41] += (zeusbase[0x41] & 0x400) << 6; state->m_zeusbase[0x41] += (state->m_zeusbase[0x41] & 0x400) << 6;
zeusbase[0x41] &= ~0xfc00; state->m_zeusbase[0x41] &= ~0xfc00;
} }
} }
break; break;
@ -607,113 +611,113 @@ static void zeus_register_update(running_machine &machine, offs_t offset, UINT32
case 0x48: case 0x48:
case 0x49: case 0x49:
/* if we're in write mode, process it */ /* if we're in write mode, process it */
if (zeusbase[0x40] == 0x00890000) if (state->m_zeusbase[0x40] == 0x00890000)
{ {
/* /*
zeusbase[0x4e]: state->m_zeusbase[0x4e]:
bit 0-1: which register triggers write through bit 0-1: which register triggers write through
bit 3: enable write through via these registers bit 3: enable write through via these registers
bit 4: seems to be set during reads, when 0x41 is used for latching bit 4: seems to be set during reads, when 0x41 is used for latching
bit 6: enable autoincrement on write through bit 6: enable autoincrement on write through
*/ */
if ((zeusbase[0x4e] & 0x08) && (offset & 3) == (zeusbase[0x4e] & 3)) if ((state->m_zeusbase[0x4e] & 0x08) && (offset & 3) == (state->m_zeusbase[0x4e] & 3))
{ {
void *dest = waveram0_ptr_from_expanded_addr(zeusbase[0x41]); void *dest = waveram0_ptr_from_expanded_addr(state->m_zeusbase[0x41]);
WAVERAM_WRITE32(dest, 0, zeusbase[0x48]); WAVERAM_WRITE32(dest, 0, state->m_zeusbase[0x48]);
WAVERAM_WRITE32(dest, 1, zeusbase[0x49]); WAVERAM_WRITE32(dest, 1, state->m_zeusbase[0x49]);
if (zeusbase[0x4e] & 0x40) if (state->m_zeusbase[0x4e] & 0x40)
{ {
zeusbase[0x41]++; state->m_zeusbase[0x41]++;
zeusbase[0x41] += (zeusbase[0x41] & 0x400) << 6; state->m_zeusbase[0x41] += (state->m_zeusbase[0x41] & 0x400) << 6;
zeusbase[0x41] &= ~0xfc00; state->m_zeusbase[0x41] &= ~0xfc00;
} }
} }
} }
/* make sure we log anything else */ /* make sure we log anything else */
else if (logit) else if (logit)
logerror("\t[40]=%08X [4E]=%08X\n", zeusbase[0x40], zeusbase[0x4e]); logerror("\t[40]=%08X [4E]=%08X\n", state->m_zeusbase[0x40], state->m_zeusbase[0x4e]);
break; break;
case 0x51: case 0x51:
/* in this mode, crusnexo expects the reads to immediately latch */ /* in this mode, crusnexo expects the reads to immediately latch */
if (zeusbase[0x50] == 0x00a20000) if (state->m_zeusbase[0x50] == 0x00a20000)
oldval = zeusbase[0x51]; oldval = state->m_zeusbase[0x51];
/* this is the address, except in read mode, where it latches values */ /* this is the address, except in read mode, where it latches values */
if ((zeusbase[0x5e] & 0x10) || (zeusbase[0x50] == 0x00a20000)) if ((state->m_zeusbase[0x5e] & 0x10) || (state->m_zeusbase[0x50] == 0x00a20000))
{ {
const void *src = waveram1_ptr_from_expanded_addr(oldval); const void *src = waveram1_ptr_from_expanded_addr(oldval);
zeusbase[0x51] = oldval; state->m_zeusbase[0x51] = oldval;
zeusbase[0x58] = WAVERAM_READ32(src, 0); state->m_zeusbase[0x58] = WAVERAM_READ32(src, 0);
zeusbase[0x59] = WAVERAM_READ32(src, 1); state->m_zeusbase[0x59] = WAVERAM_READ32(src, 1);
zeusbase[0x5a] = WAVERAM_READ32(src, 2); state->m_zeusbase[0x5a] = WAVERAM_READ32(src, 2);
if (zeusbase[0x5e] & 0x40) if (state->m_zeusbase[0x5e] & 0x40)
{ {
zeusbase[0x51]++; state->m_zeusbase[0x51]++;
zeusbase[0x51] += (zeusbase[0x51] & 0x200) << 7; state->m_zeusbase[0x51] += (state->m_zeusbase[0x51] & 0x200) << 7;
zeusbase[0x51] &= ~0xfe00; state->m_zeusbase[0x51] &= ~0xfe00;
} }
} }
break; break;
case 0x57: case 0x57:
/* thegrid uses this to write either left or right halves of pixels */ /* thegrid uses this to write either left or right halves of pixels */
if (zeusbase[0x50] == 0x00e90000) if (state->m_zeusbase[0x50] == 0x00e90000)
{ {
void *dest = waveram1_ptr_from_expanded_addr(zeusbase[0x51]); void *dest = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0x51]);
if (zeusbase[0x57] & 1) if (state->m_zeusbase[0x57] & 1)
WAVERAM_WRITE32(dest, 0, zeusbase[0x58]); WAVERAM_WRITE32(dest, 0, state->m_zeusbase[0x58]);
if (zeusbase[0x57] & 4) if (state->m_zeusbase[0x57] & 4)
WAVERAM_WRITE32(dest, 1, zeusbase[0x59]); WAVERAM_WRITE32(dest, 1, state->m_zeusbase[0x59]);
} }
/* make sure we log anything else */ /* make sure we log anything else */
else if (logit) else if (logit)
logerror("\t[50]=%08X [5E]=%08X\n", zeusbase[0x50], zeusbase[0x5e]); logerror("\t[50]=%08X [5E]=%08X\n", state->m_zeusbase[0x50], state->m_zeusbase[0x5e]);
break; break;
case 0x58: case 0x58:
case 0x59: case 0x59:
case 0x5a: case 0x5a:
/* if we're in write mode, process it */ /* if we're in write mode, process it */
if (zeusbase[0x50] == 0x00890000) if (state->m_zeusbase[0x50] == 0x00890000)
{ {
/* /*
zeusbase[0x5e]: state->m_zeusbase[0x5e]:
bit 0-1: which register triggers write through bit 0-1: which register triggers write through
bit 3: enable write through via these registers bit 3: enable write through via these registers
bit 4: seems to be set during reads, when 0x51 is used for latching bit 4: seems to be set during reads, when 0x51 is used for latching
bit 5: unknown, currently used to specify ordering, but this is suspect bit 5: unknown, currently used to specify ordering, but this is suspect
bit 6: enable autoincrement on write through bit 6: enable autoincrement on write through
*/ */
if ((zeusbase[0x5e] & 0x08) && (offset & 3) == (zeusbase[0x5e] & 3)) if ((state->m_zeusbase[0x5e] & 0x08) && (offset & 3) == (state->m_zeusbase[0x5e] & 3))
{ {
void *dest = waveram1_ptr_from_expanded_addr(zeusbase[0x51]); void *dest = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0x51]);
WAVERAM_WRITE32(dest, 0, zeusbase[0x58]); WAVERAM_WRITE32(dest, 0, state->m_zeusbase[0x58]);
if (zeusbase[0x5e] & 0x20) if (state->m_zeusbase[0x5e] & 0x20)
WAVERAM_WRITE32(dest, 1, zeusbase[0x5a]); WAVERAM_WRITE32(dest, 1, state->m_zeusbase[0x5a]);
else else
{ {
WAVERAM_WRITE32(dest, 1, zeusbase[0x59]); WAVERAM_WRITE32(dest, 1, state->m_zeusbase[0x59]);
WAVERAM_WRITE32(dest, 2, zeusbase[0x5a]); WAVERAM_WRITE32(dest, 2, state->m_zeusbase[0x5a]);
} }
if (zeusbase[0x5e] & 0x40) if (state->m_zeusbase[0x5e] & 0x40)
{ {
zeusbase[0x51]++; state->m_zeusbase[0x51]++;
zeusbase[0x51] += (zeusbase[0x51] & 0x200) << 7; state->m_zeusbase[0x51] += (state->m_zeusbase[0x51] & 0x200) << 7;
zeusbase[0x51] &= ~0xfe00; state->m_zeusbase[0x51] &= ~0xfe00;
} }
} }
} }
/* make sure we log anything else */ /* make sure we log anything else */
else if (logit) else if (logit)
logerror("\t[50]=%08X [5E]=%08X\n", zeusbase[0x50], zeusbase[0x5e]); logerror("\t[50]=%08X [5E]=%08X\n", state->m_zeusbase[0x50], state->m_zeusbase[0x5e]);
break; break;
} }
} }
@ -1038,6 +1042,7 @@ static void zeus_draw_model(running_machine &machine, UINT32 baseaddr, UINT16 co
static void zeus_draw_quad(running_machine &machine, const UINT32 *databuffer, UINT32 texoffs, int logit) static void zeus_draw_quad(running_machine &machine, const UINT32 *databuffer, UINT32 texoffs, int logit)
{ {
midzeus_state *state = machine.driver_data<midzeus_state>();
poly_draw_scanline_func callback; poly_draw_scanline_func callback;
poly_extra_data *extra; poly_extra_data *extra;
poly_vertex clipvert[8]; poly_vertex clipvert[8];
@ -1249,12 +1254,12 @@ In memory:
} }
} }
extra->solidcolor = 0;//zeusbase[0x00] & 0x7fff; extra->solidcolor = 0;//state->m_zeusbase[0x00] & 0x7fff;
extra->zoffset = 0;//zeusbase[0x7e] >> 16; extra->zoffset = 0;//state->m_zeusbase[0x7e] >> 16;
extra->alpha = 0;//zeusbase[0x4e]; extra->alpha = 0;//state->m_zeusbase[0x4e];
extra->transcolor = 0x100;//((databuffer[1] >> 16) & 1) ? 0 : 0x100; extra->transcolor = 0x100;//((databuffer[1] >> 16) & 1) ? 0 : 0x100;
extra->texbase = WAVERAM_BLOCK0(zeus_texbase); extra->texbase = WAVERAM_BLOCK0(zeus_texbase);
extra->palbase = waveram0_ptr_from_expanded_addr(zeusbase[0x41]); extra->palbase = waveram0_ptr_from_expanded_addr(state->m_zeusbase[0x41]);
poly_render_quad_fan(poly, NULL, zeus_cliprect, callback, 4, numverts, &clipvert[0]); poly_render_quad_fan(poly, NULL, zeus_cliprect, callback, 4, numverts, &clipvert[0]);
} }

19
src/mess/drivers/mmodular.c
View File

@ -99,9 +99,6 @@ Bit 5+6 LED 1-8 enable
#include "machine/nvram.h" #include "machine/nvram.h"
//static UINT16 unknown2_data = 0; //static UINT16 unknown2_data = 0;
static UINT16 *save_ram;
static UINT32 *save_ram32;
// Berlin Pro 68020 // Berlin Pro 68020
static UINT32 BPL32latch_data = 0; static UINT32 BPL32latch_data = 0;
@ -1005,9 +1002,6 @@ static MACHINE_START( van32 )
rom[0x870] = 0x38; rom[0x870] = 0x38;
} }
} }
machine.device<nvram_device>("nvram")->set_base(save_ram32, 0x8000);
} }
@ -1046,7 +1040,6 @@ static MACHINE_START( van16 )
{ {
mboard_savestate_register(machine); mboard_savestate_register(machine);
machine.device<nvram_device>("nvram")->set_base(save_ram, 0x4000);
} }
@ -1148,7 +1141,7 @@ static ADDRESS_MAP_START(gen32_mem, AS_PROGRAM, 32, polgar_state )
AM_RANGE( 0x40000000, 0x4007ffff ) AM_RAM /* 512KB */ AM_RANGE( 0x40000000, 0x4007ffff ) AM_RAM /* 512KB */
AM_RANGE( 0x80000000, 0x8003ffff ) AM_RAM /* 256KB */ AM_RANGE( 0x80000000, 0x8003ffff ) AM_RAM /* 256KB */
AM_RANGE( 0xe8000000, 0xe8007fff ) AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram") AM_RANGE( 0xe8000000, 0xe8007fff ) AM_RAM AM_SHARE("nvram")
ADDRESS_MAP_END ADDRESS_MAP_END
@ -1161,7 +1154,7 @@ static ADDRESS_MAP_START(bpl32_mem, AS_PROGRAM, 32, polgar_state )
AM_RANGE( 0xc00000 , 0xc00003 ) AM_WRITE(write_LCD_data_32 ) AM_RANGE( 0xc00000 , 0xc00003 ) AM_WRITE(write_LCD_data_32 )
AM_RANGE( 0xb00000 , 0xb00003 ) AM_WRITE(write_IOenables_32 ) AM_RANGE( 0xb00000 , 0xb00003 ) AM_WRITE(write_IOenables_32 )
AM_RANGE( 0x400000 , 0x4fffff ) AM_RAM /* 1024KB */ AM_RANGE( 0x400000 , 0x4fffff ) AM_RAM /* 1024KB */
AM_RANGE( 0xd00000 , 0xd07fff ) AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram") AM_RANGE( 0xd00000 , 0xd07fff ) AM_RAM AM_SHARE("nvram")
ADDRESS_MAP_END ADDRESS_MAP_END
@ -1180,7 +1173,7 @@ static ADDRESS_MAP_START(van32_mem, AS_PROGRAM, 32, polgar_state )
AM_RANGE( 0x9800000c , 0x9800000f ) AM_READ(read_unknown3_32 ) AM_RANGE( 0x9800000c , 0x9800000f ) AM_READ(read_unknown3_32 )
AM_RANGE( 0x40000000, 0x400fffff ) AM_RAM /* 1024KB */ AM_RANGE( 0x40000000, 0x400fffff ) AM_RAM /* 1024KB */
AM_RANGE( 0xa8000000, 0xa8007fff ) AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram") AM_RANGE( 0xa8000000, 0xa8007fff ) AM_RAM AM_SHARE("nvram")
ADDRESS_MAP_END ADDRESS_MAP_END
@ -1200,7 +1193,7 @@ static ADDRESS_MAP_START(alm32_mem, AS_PROGRAM, 32, polgar_state )
AM_RANGE( 0x9800000c , 0x9800000f ) AM_READ(read_unknown3_32 ) AM_RANGE( 0x9800000c , 0x9800000f ) AM_READ(read_unknown3_32 )
AM_RANGE( 0x40000000, 0x400fffff ) AM_RAM AM_RANGE( 0x40000000, 0x400fffff ) AM_RAM
AM_RANGE( 0xa8000000, 0xa8007fff ) AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram") AM_RANGE( 0xa8000000, 0xa8007fff ) AM_RAM AM_SHARE("nvram")
ADDRESS_MAP_END ADDRESS_MAP_END
@ -1228,7 +1221,7 @@ static ADDRESS_MAP_START(van16_mem, AS_PROGRAM, 16, polgar_state )
AM_RANGE( 0xe80006 , 0xe80007 ) AM_READ(read_unknown3 ) AM_RANGE( 0xe80006 , 0xe80007 ) AM_READ(read_unknown3 )
AM_RANGE( 0x400000, 0x47ffff ) AM_RAM /* 512KB */ AM_RANGE( 0x400000, 0x47ffff ) AM_RAM /* 512KB */
AM_RANGE( 0x800000, 0x803fff ) AM_RAM AM_BASE_LEGACY(&save_ram) AM_SHARE("nvram") AM_RANGE( 0x800000, 0x803fff ) AM_RAM AM_SHARE("nvram")
ADDRESS_MAP_END ADDRESS_MAP_END
@ -1248,7 +1241,7 @@ static ADDRESS_MAP_START(alm16_mem, AS_PROGRAM, 16, polgar_state )
AM_RANGE( 0x400000, 0x47ffff ) AM_RAM /* 512KB */ AM_RANGE( 0x400000, 0x47ffff ) AM_RAM /* 512KB */
AM_RANGE( 0x800000, 0x803fff ) AM_RAM AM_BASE_LEGACY(&save_ram) AM_SHARE("nvram") AM_RANGE( 0x800000, 0x803fff ) AM_RAM AM_SHARE("nvram")
ADDRESS_MAP_END ADDRESS_MAP_END

4
src/mess/drivers/ng_aes.c
View File

@ -1303,7 +1303,7 @@ static ADDRESS_MAP_START( main_map, AS_PROGRAM, 16, ng_aes_state )
AM_RANGE(0x400000, 0x401fff) AM_MIRROR(0x3fe000) AM_READWRITE(neogeo_paletteram_r, neogeo_paletteram_w) AM_RANGE(0x400000, 0x401fff) AM_MIRROR(0x3fe000) AM_READWRITE(neogeo_paletteram_r, neogeo_paletteram_w)
AM_RANGE(0x800000, 0x800fff) AM_READWRITE(memcard_r, memcard_w) AM_RANGE(0x800000, 0x800fff) AM_READWRITE(memcard_r, memcard_w)
AM_RANGE(0xc00000, 0xc1ffff) AM_MIRROR(0x0e0000) AM_ROMBANK(NEOGEO_BANK_BIOS) AM_RANGE(0xc00000, 0xc1ffff) AM_MIRROR(0x0e0000) AM_ROMBANK(NEOGEO_BANK_BIOS)
AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE(save_ram_w) AM_BASE_LEGACY(&save_ram) AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE(save_ram_w) AM_SHARE("save_ram")
AM_RANGE(0xe00000, 0xffffff) AM_READ(neogeo_unmapped_r) AM_RANGE(0xe00000, 0xffffff) AM_READ(neogeo_unmapped_r)
ADDRESS_MAP_END ADDRESS_MAP_END
@ -1329,7 +1329,7 @@ static ADDRESS_MAP_START( neocd_main_map, AS_PROGRAM, 16, ng_aes_state )
AM_RANGE(0x400000, 0x401fff) AM_MIRROR(0x3fe000) AM_READWRITE(neogeo_paletteram_r, neogeo_paletteram_w) AM_RANGE(0x400000, 0x401fff) AM_MIRROR(0x3fe000) AM_READWRITE(neogeo_paletteram_r, neogeo_paletteram_w)
AM_RANGE(0x800000, 0x803fff) AM_READWRITE(neocd_memcard_r, neocd_memcard_w) AM_RANGE(0x800000, 0x803fff) AM_READWRITE(neocd_memcard_r, neocd_memcard_w)
AM_RANGE(0xc00000, 0xcfffff) AM_ROMBANK(NEOGEO_BANK_BIOS) AM_RANGE(0xc00000, 0xcfffff) AM_ROMBANK(NEOGEO_BANK_BIOS)
AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE(save_ram_w) AM_BASE_LEGACY(&save_ram) AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE(save_ram_w) AM_SHARE("save_ram")
AM_RANGE(0xe00000, 0xefffff) AM_READWRITE(neocd_transfer_r,neocd_transfer_w) AM_RANGE(0xe00000, 0xefffff) AM_READWRITE(neocd_transfer_r,neocd_transfer_w)
AM_RANGE(0xf00000, 0xfeffff) AM_READ(neogeo_unmapped_r) AM_RANGE(0xf00000, 0xfeffff) AM_READ(neogeo_unmapped_r)
AM_RANGE(0xff0000, 0xff01ff) AM_READWRITE(neocd_control_r, neocd_control_w) // CDROM / DMA AM_RANGE(0xff0000, 0xff01ff) AM_READWRITE(neocd_control_r, neocd_control_w) // CDROM / DMA