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arm: Fix register-counted shifts in disassembly

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This commit is contained in:
AJR 2023-11-08 21:52:49 -05:00
parent 5a3628fa3a
commit 8fba51ccfc
1 changed files with 2 additions and 7 deletions
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9
src/devices/cpu/arm/armdasm.cpp
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@ -81,7 +81,7 @@ void arm_disassembler::WriteRegisterOperand1(std::ostream &stream, uint32_t opco
if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */
{
util::stream_format(stream, ", %s R%d", pRegOp[shiftop], (opcode >> 7) & 0xf);
util::stream_format(stream, ", %s R%d", pRegOp[shiftop], (opcode >> 8) & 0xf);
}
else /* Shift amount immediate 5 bit unsigned integer */
{
@ -104,12 +104,7 @@ void arm_disassembler::WriteRegisterOperand1(std::ostream &stream, uint32_t opco
void arm_disassembler::WriteBranchAddress(std::ostream &stream, uint32_t pc, uint32_t opcode) const
{
opcode &= 0x00ffffff;
if( opcode&0x00800000 )
{
opcode |= 0xff000000; /* sign-extend */
}
pc += 8+4*opcode;
pc += 8+4*util::sext(opcode, 24);
util::stream_format( stream, "&%07X", pc & 0x03ffffff );
} /* WriteBranchAddress */