Cleanups and version bump.

This commit is contained in:
Aaron Giles 2009-09-07 01:34:34 +00:00
parent 10b6e7e106
commit 8fbe10c91f
41 changed files with 514 additions and 514 deletions

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@ -9,15 +9,15 @@
/* /*
TODO: TODO:
- strobed I/O - strobed I/O
- interrupts - interrupts
- expose register file to disassembler - expose register file to disassembler
- decimal adjust instruction - decimal adjust instruction
- timer Tin/Tout modes - timer Tin/Tout modes
- serial - serial
- instruction pipeline - instruction pipeline
*/ */

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@ -208,7 +208,7 @@ INSTRUCTION( ldei_Ir2_Irr1 ) { load_to_memory_autoinc(cpustate, cpustate->data);
static void pop(z8_state *cpustate, UINT8 dst) static void pop(z8_state *cpustate, UINT8 dst)
{ {
/* dst <- @SP /* dst <- @SP
SP <- SP + 1 */ SP <- SP + 1 */
register_write(cpustate, dst, stack_pop_byte(cpustate)); register_write(cpustate, dst, stack_pop_byte(cpustate));
} }
@ -218,7 +218,7 @@ INSTRUCTION( pop_IR1 ) { mode_IR1(pop) }
static void push(z8_state *cpustate, UINT8 src) static void push(z8_state *cpustate, UINT8 src)
{ {
/* SP <- SP - 1 /* SP <- SP - 1
@SP <- src */ @SP <- src */
stack_push_byte(cpustate, read(src)); stack_push_byte(cpustate, read(src));
} }
@ -513,11 +513,11 @@ INSTRUCTION( djnz_r1_RA )
INSTRUCTION( iret ) INSTRUCTION( iret )
{ {
/* FLAGS <- @SP /* FLAGS <- @SP
SP <- SP + 1 */ SP <- SP + 1 */
register_write(cpustate, Z8_REGISTER_FLAGS, stack_pop_byte(cpustate)); register_write(cpustate, Z8_REGISTER_FLAGS, stack_pop_byte(cpustate));
/* PC <- @SP /* PC <- @SP
SP <- SP + 2 */ SP <- SP + 2 */
cpustate->pc = stack_pop_word(cpustate); cpustate->pc = stack_pop_word(cpustate);
/* IMR (7) <- 1 */ /* IMR (7) <- 1 */
@ -527,7 +527,7 @@ INSTRUCTION( iret )
INSTRUCTION( ret ) INSTRUCTION( ret )
{ {
/* PC <- @SP /* PC <- @SP
SP <- SP + 2 */ SP <- SP + 2 */
cpustate->pc = stack_pop_word(cpustate); cpustate->pc = stack_pop_word(cpustate);
} }
@ -727,7 +727,7 @@ static void swap(z8_state *cpustate, UINT8 dst)
set_flag_z(data == 0); set_flag_z(data == 0);
set_flag_s(data & 0x80); set_flag_s(data & 0x80);
// set_flag_v(0); undefined // set_flag_v(0); undefined
} }
INSTRUCTION( swap_R1 ) { mode_R1(swap) } INSTRUCTION( swap_R1 ) { mode_R1(swap) }

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@ -111,20 +111,20 @@ INLINE duart68681_state *get_safe_token(const device_config *device)
static void duart68681_update_interrupts(duart68681_state *duart68681) static void duart68681_update_interrupts(duart68681_state *duart68681)
{ {
/* update SR state and update interrupt ISR state for the following bits: /* update SR state and update interrupt ISR state for the following bits:
SRn: bits 7-4: handled elsewhere. SRn: bits 7-4: handled elsewhere.
SRn: bit 3 (TxEMTn) (we can assume since we're not actually emulating the delay/timing of sending bits, that as long as TxRDYn is set, TxEMTn is also set since the transmit byte has 'already happened', therefore TxEMTn is always 1 assuming tx is enabled on channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined) SRn: bit 3 (TxEMTn) (we can assume since we're not actually emulating the delay/timing of sending bits, that as long as TxRDYn is set, TxEMTn is also set since the transmit byte has 'already happened', therefore TxEMTn is always 1 assuming tx is enabled on channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined)
SRn: bit 2 (TxRDYn) (we COULD assume since we're not emulating delay and timing output, that as long as tx is enabled on channel n, TxRDY is 1 for channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined; however, tx_ready is already nicely handled for us elsewhere, so we can use that instead for now, though we may need to retool that code as well) SRn: bit 2 (TxRDYn) (we COULD assume since we're not emulating delay and timing output, that as long as tx is enabled on channel n, TxRDY is 1 for channel n and the MSR2n mode is 0 or 2; in mode 1 it is explicitly zeroed, and mode 3 is undefined; however, tx_ready is already nicely handled for us elsewhere, so we can use that instead for now, though we may need to retool that code as well)
SRn: bit 1 (FFULLn) (this bit we actually emulate; if the recieve fifo for channel n is full, this bit is 1, otherwise it is 0. the recieve fifo should be three words long.) SRn: bit 1 (FFULLn) (this bit we actually emulate; if the recieve fifo for channel n is full, this bit is 1, otherwise it is 0. the recieve fifo should be three words long.)
SRn: bit 0 (RxRDYn) (this bit we also emulate; the bit is always asserted if the recieve fifo is not empty) SRn: bit 0 (RxRDYn) (this bit we also emulate; the bit is always asserted if the recieve fifo is not empty)
ISR: bit 7: Input Port change; this should be handled elsewhere, on the input port handler ISR: bit 7: Input Port change; this should be handled elsewhere, on the input port handler
ISR: bit 6: Delta Break B; this should be handled elsewhere, on the data recieve handler ISR: bit 6: Delta Break B; this should be handled elsewhere, on the data recieve handler
ISR: bit 5: RxRDYB/FFULLB: this is handled here; depending on whether MSR1B bit 6 is 0 or 1, this bit holds the state of SRB bit 0 or bit 1 respectively ISR: bit 5: RxRDYB/FFULLB: this is handled here; depending on whether MSR1B bit 6 is 0 or 1, this bit holds the state of SRB bit 0 or bit 1 respectively
ISR: bit 4: TxRDYB: this is handled here; it mirrors SRB bit 2 ISR: bit 4: TxRDYB: this is handled here; it mirrors SRB bit 2
ISR: bit 3: Counter ready; this should be handled by the timer generator ISR: bit 3: Counter ready; this should be handled by the timer generator
ISR: bit 2: Delta Break A; this should be handled elsewhere, on the data recieve handler ISR: bit 2: Delta Break A; this should be handled elsewhere, on the data recieve handler
ISR: bit 1: RxRDYA/FFULLA: this is handled here; depending on whether MSR1A bit 6 is 0 or 1, this bit holds the state of SRA bit 0 or bit 1 respectively ISR: bit 1: RxRDYA/FFULLA: this is handled here; depending on whether MSR1A bit 6 is 0 or 1, this bit holds the state of SRA bit 0 or bit 1 respectively
ISR: bit 0: TxRDYA: this is handled here; it mirrors SRA bit 2 ISR: bit 0: TxRDYA: this is handled here; it mirrors SRA bit 2
*/ */
UINT8 ch = 0; UINT8 ch = 0;
//logerror("DEBUG: 68681 int check: upon func call, SRA is %02X, SRB is %02X, ISR is %02X\n", duart68681->channel[0].SR, duart68681->channel[1].SR, duart68681->ISR); //logerror("DEBUG: 68681 int check: upon func call, SRA is %02X, SRB is %02X, ISR is %02X\n", duart68681->channel[0].SR, duart68681->channel[1].SR, duart68681->ISR);
for (ch = 0; ch < 2; ch++) for (ch = 0; ch < 2; ch++)

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@ -44,8 +44,8 @@ static DISCRETE_START( dso_task )
const linked_list_entry *step_entry; const linked_list_entry *step_entry;
/* Determine, which nodes in the task are referenced in the main task /* Determine, which nodes in the task are referenced in the main task
* and add them to the list of nodes to be buffered for further processing * and add them to the list of nodes to be buffered for further processing
*/ */
for (node_entry = task->list; node_entry != NULL; node_entry = node_entry->next) for (node_entry = task->list; node_entry != NULL; node_entry = node_entry->next)
{ {
node_description *node = (node_description *) node_entry->ptr; node_description *node = (node_description *) node_entry->ptr;

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@ -293,18 +293,18 @@ static DISCRETE_SOUND_START(galaxian)
/************************************************/ /************************************************/
/* two cascaded LS164 which are reset to pitch latch value, /* two cascaded LS164 which are reset to pitch latch value,
* thus generating SOUND_CLOCK / (256 - pitch_clock) signal * thus generating SOUND_CLOCK / (256 - pitch_clock) signal
* *
* One possibility to implement this is * One possibility to implement this is
* DISCRETE_TRANSFORM3(NODE_130, SOUND_CLOCK, 256, GAL_INP_PITCH, "012-/") * DISCRETE_TRANSFORM3(NODE_130, SOUND_CLOCK, 256, GAL_INP_PITCH, "012-/")
* DISCRETE_COUNTER(NODE_132, 1, 0, NODE_130, 15, DISC_COUNT_UP, 0, DISC_CLK_IS_FREQ) * DISCRETE_COUNTER(NODE_132, 1, 0, NODE_130, 15, DISC_COUNT_UP, 0, DISC_CLK_IS_FREQ)
* but there is a native choice: * but there is a native choice:
*/ */
DISCRETE_NOTE(NODE_132, 1, SOUND_CLOCK, GAL_INP_PITCH, 255, 15, DISC_CLK_IS_FREQ) DISCRETE_NOTE(NODE_132, 1, SOUND_CLOCK, GAL_INP_PITCH, 255, 15, DISC_CLK_IS_FREQ)
/* from the 74393 (counter 2 above) only QA, QC, QD are used. /* from the 74393 (counter 2 above) only QA, QC, QD are used.
* We decode three here and use SUB_NODE(133,x) below to access. * We decode three here and use SUB_NODE(133,x) below to access.
*/ */
DISCRETE_BITS_DECODE(NODE_133, NODE_132, 0, 3, TTL_OUT) /* QA-QD 74393 */ DISCRETE_BITS_DECODE(NODE_133, NODE_132, 0, 3, TTL_OUT) /* QA-QD 74393 */
/* End of this task */ /* End of this task */
@ -320,15 +320,15 @@ static DISCRETE_SOUND_START(galaxian)
/* NOISE */ /* NOISE */
/* since only a sample of the LFSR is latched @V2 we let the lfsr /* since only a sample of the LFSR is latched @V2 we let the lfsr
* run at a lower speed * run at a lower speed
*/ */
DISCRETE_LFSR_NOISE(NODE_150, 1, 1, RNG_RATE/100, 1.0, 0, 0.5, &galaxian_lfsr) DISCRETE_LFSR_NOISE(NODE_150, 1, 1, RNG_RATE/100, 1.0, 0, 0.5, &galaxian_lfsr)
DISCRETE_SQUAREWFIX(NODE_151,1,60*264/2,1.0,50,0.5,0) /* 2V signal */ DISCRETE_SQUAREWFIX(NODE_151,1,60*264/2,1.0,50,0.5,0) /* 2V signal */
DISCRETE_LOGIC_DFLIPFLOP(NODE_152,1,1,1,NODE_151,NODE_150) DISCRETE_LOGIC_DFLIPFLOP(NODE_152,1,1,1,NODE_151,NODE_150)
/* Not 100% correct - switching causes high impedance input for node_157 /* Not 100% correct - switching causes high impedance input for node_157
* this is not emulated */ * this is not emulated */
DISCRETE_RCDISC5(NODE_155, NODE_152, GAL_INP_HIT, (GAL_R35 + GAL_R36), GAL_C21) DISCRETE_RCDISC5(NODE_155, NODE_152, GAL_INP_HIT, (GAL_R35 + GAL_R36), GAL_C21)
DISCRETE_OP_AMP_FILTER(NODE_157, 1, NODE_155, 0, DISC_OP_AMP_FILTER_IS_BAND_PASS_1M, &galaxian_bandpass_desc) DISCRETE_OP_AMP_FILTER(NODE_157, 1, NODE_155, 0, DISC_OP_AMP_FILTER_IS_BAND_PASS_1M, &galaxian_bandpass_desc)

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@ -949,45 +949,45 @@ Master Ninja
CPUs CPUs
QTY Type position function QTY Type position function
1x MC68000P10 68000 main PCB main 1x MC68000P10 68000 main PCB main
1x Z8400HB1 ic36 main PCB sound 1x Z8400HB1 ic36 main PCB sound
2x YM2203C ic31,ic32 main PCB sound 2x YM2203C ic31,ic32 main PCB sound
2x Y3014B c16,ic17 main PCB sound 2x Y3014B c16,ic17 main PCB sound
2x LM324N ic2,ic6 main PCB sound 2x LM324N ic2,ic6 main PCB sound
1x TDA2002 ic1 main PCB sound 1x TDA2002 ic1 main PCB sound
Oscillators Oscillators
1x oscillator 20.000 (xl2 main PCB) 1x oscillator 20.000 (xl2 main PCB)
1x blu resonator 400K (xl1 main PCB) 1x blu resonator 400K (xl1 main PCB)
ROMs ROMs
QTY Type position status QTY Type position status
6x AM27C512 1-6 main PCB dumped 6x AM27C512 1-6 main PCB dumped
32x AM27C512 8-39 ROMs PCB dumped 32x AM27C512 8-39 ROMs PCB dumped
RAMs RAMs
QTY Type position QTY Type position
4x HY6264LP-10 ic25,ic28,ic61,ic62 main PCB 4x HY6264LP-10 ic25,ic28,ic61,ic62 main PCB
3x HY6116ALP-10 ic33,ic123,ic124 main PCB 3x HY6116ALP-10 ic33,ic123,ic124 main PCB
1x HM6148P ic80 main PCB 1x HM6148P ic80 main PCB
1x MCM2018AN45 ic81 main PCB 1x MCM2018AN45 ic81 main PCB
4x HM6148P ic63-66 ROMs PCB 4x HM6148P ic63-66 ROMs PCB
1x HY6116ALP-10 ic85 ROMs PCB 1x HY6116ALP-10 ic85 ROMs PCB
PLDs PLDs
QTY Type position status QTY Type position status
2x TIBPAL16L8 ic15,ic54 main PCB read protected 2x TIBPAL16L8 ic15,ic54 main PCB read protected
1x GAL16L8 ic42 ROMs PCB read protected 1x GAL16L8 ic42 ROMs PCB read protected
Others Others
1x JAMMA edge connector 1x JAMMA edge connector
1x trimmer (volume) 1x trimmer (volume)
2x 8x2 switches DIP 2x 8x2 switches DIP
*/ */
static ADDRESS_MAP_START( mastninj_sound_map, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( mastninj_sound_map, ADDRESS_SPACE_PROGRAM, 8 )
@ -995,8 +995,8 @@ static ADDRESS_MAP_START( mastninj_sound_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0xf000, 0xf7ff) AM_RAM AM_RANGE(0xf000, 0xf7ff) AM_RAM
AM_RANGE(0xc400, 0xc401) AM_DEVWRITE("ym1", ym2203_w) AM_RANGE(0xc400, 0xc401) AM_DEVWRITE("ym1", ym2203_w)
AM_RANGE(0xc800, 0xc801) AM_DEVWRITE("ym2", ym2203_w) AM_RANGE(0xc800, 0xc801) AM_DEVWRITE("ym2", ym2203_w)
// AM_RANGE(0xfc00, 0xfc00) AM_NOP /* ?? */ // AM_RANGE(0xfc00, 0xfc00) AM_NOP /* ?? */
// AM_RANGE(0xfc20, 0xfc20) AM_READ(soundlatch_r) // AM_RANGE(0xfc20, 0xfc20) AM_READ(soundlatch_r)
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( mastninj_map, ADDRESS_SPACE_PROGRAM, 16 ) static ADDRESS_MAP_START( mastninj_map, ADDRESS_SPACE_PROGRAM, 16 )
@ -1007,20 +1007,20 @@ static ADDRESS_MAP_START( mastninj_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x074000, 0x075fff) AM_READWRITE(gaiden_videoram3_r, gaiden_videoram3_w) AM_BASE(&gaiden_videoram3) AM_RANGE(0x074000, 0x075fff) AM_READWRITE(gaiden_videoram3_r, gaiden_videoram3_w) AM_BASE(&gaiden_videoram3)
AM_RANGE(0x076000, 0x077fff) AM_RAM AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) AM_RANGE(0x076000, 0x077fff) AM_RAM AM_BASE(&spriteram16) AM_SIZE(&spriteram_size)
AM_RANGE(0x078000, 0x079fff) AM_RAM_WRITE(paletteram16_xxxxBBBBGGGGRRRR_word_w) AM_BASE(&paletteram16) AM_RANGE(0x078000, 0x079fff) AM_RAM_WRITE(paletteram16_xxxxBBBBGGGGRRRR_word_w) AM_BASE(&paletteram16)
// AM_RANGE(0x078800, 0x079fff) AM_RAM // AM_RANGE(0x078800, 0x079fff) AM_RAM
AM_RANGE(0x07a000, 0x07a001) AM_READ_PORT("SYSTEM") AM_RANGE(0x07a000, 0x07a001) AM_READ_PORT("SYSTEM")
AM_RANGE(0x07a002, 0x07a003) AM_READ_PORT("P1_P2") AM_RANGE(0x07a002, 0x07a003) AM_READ_PORT("P1_P2")
AM_RANGE(0x07a004, 0x07a005) AM_READ_PORT("DSW") AM_RANGE(0x07a004, 0x07a005) AM_READ_PORT("DSW")
// AM_RANGE(0x07a104, 0x07a105) AM_WRITE(gaiden_txscrolly_w) // AM_RANGE(0x07a104, 0x07a105) AM_WRITE(gaiden_txscrolly_w)
// AM_RANGE(0x07a10c, 0x07a10d) AM_WRITE(gaiden_txscrollx_w) // AM_RANGE(0x07a10c, 0x07a10d) AM_WRITE(gaiden_txscrollx_w)
AM_RANGE(0x07f000, 0x07f001) AM_WRITE(gaiden_bgscrolly_w) AM_RANGE(0x07f000, 0x07f001) AM_WRITE(gaiden_bgscrolly_w)
AM_RANGE(0x07f002, 0x07f003) AM_WRITE(gaiden_bgscrollx_w) AM_RANGE(0x07f002, 0x07f003) AM_WRITE(gaiden_bgscrollx_w)
AM_RANGE(0x07f004, 0x07f005) AM_WRITE(gaiden_fgscrolly_w) AM_RANGE(0x07f004, 0x07f005) AM_WRITE(gaiden_fgscrolly_w)
AM_RANGE(0x07f006, 0x07f007) AM_WRITE(gaiden_fgscrollx_w) AM_RANGE(0x07f006, 0x07f007) AM_WRITE(gaiden_fgscrollx_w)
AM_RANGE(0x07a800, 0x07a801) AM_WRITE(watchdog_reset16_w) AM_RANGE(0x07a800, 0x07a801) AM_WRITE(watchdog_reset16_w)
AM_RANGE(0x07e000, 0x07e001) AM_WRITE(gaiden_sound_command_w) AM_RANGE(0x07e000, 0x07e001) AM_WRITE(gaiden_sound_command_w)
// AM_RANGE(0x07a806, 0x07a807) AM_WRITENOP // AM_RANGE(0x07a806, 0x07a807) AM_WRITENOP
// AM_RANGE(0x07a808, 0x07a809) AM_WRITE(gaiden_flip_w) // AM_RANGE(0x07a808, 0x07a809) AM_WRITE(gaiden_flip_w)
ADDRESS_MAP_END ADDRESS_MAP_END
static MACHINE_DRIVER_START( mastninj ) static MACHINE_DRIVER_START( mastninj )
@ -1067,9 +1067,9 @@ static MACHINE_DRIVER_START( mastninj )
MDRV_SOUND_ROUTE(3, "mono", 0.60) MDRV_SOUND_ROUTE(3, "mono", 0.60)
/* no OKI on the bootleg */ /* no OKI on the bootleg */
// MDRV_SOUND_ADD("oki", OKIM6295, 1000000) // MDRV_SOUND_ADD("oki", OKIM6295, 1000000)
// MDRV_SOUND_CONFIG(okim6295_interface_pin7high) // MDRV_SOUND_CONFIG(okim6295_interface_pin7high)
// MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.20) // MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.20)
MACHINE_DRIVER_END MACHINE_DRIVER_END
/*************************************************************************** /***************************************************************************

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@ -1531,7 +1531,7 @@ static INPUT_PORTS_START( witchcdd )
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
/* even when the following one is forced to OFF, /* even when the following one is forced to OFF,
turned ON behaves like "Jacks and Better" */ turned ON behaves like "Jacks and Better" */
PORT_DIPNAME( 0x10, 0x10, "SW 1 (always to OFF)") PORT_DIPNAME( 0x10, 0x10, "SW 1 (always to OFF)")
PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@ -1620,14 +1620,14 @@ static INPUT_PORTS_START( witchcde )
/* DIP Switches (as shown in the epoxy block) /* DIP Switches (as shown in the epoxy block)
Schalter 1 2 3 4 5 6 7 8 Schalter 1 2 3 4 5 6 7 8
-------------------------------------------- --------------------------------------------
Bet > 10 OFF OFF Bet > 10 OFF OFF
Bet > 20 ON OFF Bet > 20 ON OFF
Bet > 50 OFF ON Bet > 50 OFF ON
Bet > 100 ON ON Bet > 100 ON ON
-------------------------------------------- --------------------------------------------
Jolli-Witch OFF Jolli-Witch OFF
Witch-Card ON Witch-Card ON
-------------------------------------------- --------------------------------------------
6 Taster ON 6 Taster ON
12 Taster OFF 12 Taster OFF
@ -1635,8 +1635,8 @@ static INPUT_PORTS_START( witchcde )
Hohes Paar ON Hohes Paar ON
2 Paar OFF 2 Paar OFF
-------------------------------------------- --------------------------------------------
1 DM - 1 PKT OFF OFF 1 DM - 1 PKT OFF OFF
1 DM - 10 PKT OFF ON 1 DM - 10 PKT OFF ON
-------------------------------------------- --------------------------------------------
RF ON RF ON
RF NO OFF RF NO OFF
@ -2658,7 +2658,7 @@ ROM_END
Code jumps into a zero-filled zone. Code jumps into a zero-filled zone.
Addressing seems to be scrambled in some way Addressing seems to be scrambled in some way
maybe through a PLD. maybe through a PLD.
*/ */
ROM_START( witchcde ) ROM_START( witchcde )
ROM_REGION( 0x10000, "maincpu", 0 ) /* inside epoxy block with the CPU */ ROM_REGION( 0x10000, "maincpu", 0 ) /* inside epoxy block with the CPU */

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@ -301,14 +301,14 @@ static DRIVER_INIT(hshavoc)
} }
/* Uncommented until actively worked on /* Uncommented until actively worked on
{ {
FILE*FP; FILE*FP;
FP=fopen("hshavoc.dump","wb"); FP=fopen("hshavoc.dump","wb");
fwrite(src, rom_size/2, 2, FP); fwrite(src, rom_size/2, 2, FP);
fclose(FP); fclose(FP);
} }
*/ */

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@ -3849,12 +3849,12 @@ static void expand_shogwarr_samples(running_machine* machine)
static void expand_brapboys_music(running_machine* machine) static void expand_brapboys_music(running_machine* machine)
{ {
/* /*
Expand the OKI sample data Expand the OKI sample data
OKI 2: OKI 2:
Address space 0x00000-0x1ffff is fixed Address space 0x00000-0x1ffff is fixed
Address space 0x20000-0x3ffff is banked (15 banks) Address space 0x20000-0x3ffff is banked (15 banks)
*/ */
int bank; int bank;
UINT8 *src = memory_region(machine, "samples"); UINT8 *src = memory_region(machine, "samples");

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@ -392,7 +392,7 @@
- norautjp: - norautjp:
At the first start-up, the game will give you a very clever At the first start-up, the game will give you a very clever
"FU" screen. Press the following buttons *together* on different times "FU" screen. Press the following buttons *together* on different times
to get rid of it (and actually initialize the machine): to get rid of it (and actually initialize the machine):
@ -687,7 +687,7 @@ static READ8_DEVICE_HANDLER( ppi2_portc_r )
UINT8 ppi2_pcmix = 0; UINT8 ppi2_pcmix = 0;
UINT8 hndshk = 0x80; /* simulating the handshake lines (bits 3-7) */ UINT8 hndshk = 0x80; /* simulating the handshake lines (bits 3-7) */
ppi2_pcmix = (hndshk | (input_port_read(device->machine, "IN2") & 0x07)); ppi2_pcmix = (hndshk | (input_port_read(device->machine, "IN2") & 0x07));
// popmessage("portc read: %02x", ppi2_pcmix); // popmessage("portc read: %02x", ppi2_pcmix);
return ppi2_pcmix; return ppi2_pcmix;
} }
@ -695,7 +695,7 @@ static READ8_DEVICE_HANDLER( ppi2_portc_r )
static WRITE8_DEVICE_HANDLER( ppi2_portc_w ) static WRITE8_DEVICE_HANDLER( ppi2_portc_w )
{ {
/* PC0-PC2 don't seems to be connected to any output */ /* PC0-PC2 don't seems to be connected to any output */
// popmessage("portc write: %02x", data); // popmessage("portc write: %02x", data);
} }
static READ8_DEVICE_HANDLER( vram_data_r ) static READ8_DEVICE_HANDLER( vram_data_r )
@ -753,9 +753,9 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( norautxp_portmap, ADDRESS_SPACE_IO, 8 ) static ADDRESS_MAP_START( norautxp_portmap, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff) ADDRESS_MAP_GLOBAL_MASK(0xff)
// AM_RANGE(0x60, 0x63) AM_DEVREADWRITE("ppi8255_0", ppi8255_r, ppi8255_w) // AM_RANGE(0x60, 0x63) AM_DEVREADWRITE("ppi8255_0", ppi8255_r, ppi8255_w)
// AM_RANGE(0xa0, 0xa3) AM_DEVREADWRITE("ppi8255_1", ppi8255_r, ppi8255_w) // AM_RANGE(0xa0, 0xa3) AM_DEVREADWRITE("ppi8255_1", ppi8255_r, ppi8255_w)
// AM_RANGE(0xc0, 0xc3) AM_DEVREADWRITE("ppi8255_2", ppi8255_r, ppi8255_w) // AM_RANGE(0xc0, 0xc3) AM_DEVREADWRITE("ppi8255_2", ppi8255_r, ppi8255_w)
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( gtipoker_map, ADDRESS_SPACE_PROGRAM, 8 ) static ADDRESS_MAP_START( gtipoker_map, ADDRESS_SPACE_PROGRAM, 8 )
@ -1008,7 +1008,7 @@ static const ppi8255_interface ppi8255_intf[3] =
DEVCB_HANDLER(soundlamps_w) /* Port C write */ DEVCB_HANDLER(soundlamps_w) /* Port C write */
}, },
{ /* (c0-c3) Group A Mode 2 (5-handshacked bidirectional port) { /* (c0-c3) Group A Mode 2 (5-handshacked bidirectional port)
Group B Mode 0, output; (see below for lines PC0-PC2) */ Group B Mode 0, output; (see below for lines PC0-PC2) */
DEVCB_HANDLER(vram_data_r), /* Port A read */ DEVCB_HANDLER(vram_data_r), /* Port A read */
DEVCB_NULL, /* Port B read */ DEVCB_NULL, /* Port B read */
DEVCB_HANDLER(ppi2_portc_r), /* Port C read */ DEVCB_HANDLER(ppi2_portc_r), /* Port C read */
@ -1017,9 +1017,9 @@ static const ppi8255_interface ppi8255_intf[3] =
DEVCB_HANDLER(ppi2_portc_w) /* Port C write */ DEVCB_HANDLER(ppi2_portc_w) /* Port C write */
} }
/* PPI-2 is configured as mixed mode2 and mode0 output. /* PPI-2 is configured as mixed mode2 and mode0 output.
It means that port A should be bidirectional and port B just as output. It means that port A should be bidirectional and port B just as output.
Port C as hshk regs, and P0-P2 as output (noraut11) or input (noraut12). Port C as hshk regs, and P0-P2 as output (noraut11) or input (noraut12).
*/ */
}; };
@ -1305,9 +1305,9 @@ static DRIVER_INIT( norautpn )
static DRIVER_INIT( gtipoker ) static DRIVER_INIT( gtipoker )
{ {
// UINT8 *ROM = memory_region(machine, "maincpu"); // UINT8 *ROM = memory_region(machine, "maincpu");
// ROM[0x0cc6] = 0x00; // ROM[0x0cc6] = 0x00;
// ROM[0x0cc7] = 0x00; // ROM[0x0cc7] = 0x00;
} }

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@ -198,7 +198,7 @@ static WRITE8_HANDLER( playmark_oki_w )
static WRITE8_DEVICE_HANDLER( playmark_snd_control_w ) static WRITE8_DEVICE_HANDLER( playmark_snd_control_w )
{ {
// const address_space *space = cputag_get_address_space(device->machine, "audiocpu", ADDRESS_SPACE_PROGRAM); // const address_space *space = cputag_get_address_space(device->machine, "audiocpu", ADDRESS_SPACE_PROGRAM);
/* This port controls communications to and from the 68K, and the OKI /* This port controls communications to and from the 68K, and the OKI
device. device.
@ -395,7 +395,7 @@ static INPUT_PORTS_START( bigtwin )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x30, 0x00, DEF_STR( Difficulty ) ) PORT_DIPNAME( 0x30, 0x00, DEF_STR( Difficulty ) )
// PORT_DIPSETTING( 0x20, DEF_STR( Easy ) ) /* Seems same as Medium */ // PORT_DIPSETTING( 0x20, DEF_STR( Easy ) ) /* Seems same as Medium */
PORT_DIPSETTING( 0x30, DEF_STR( Medium ) ) PORT_DIPSETTING( 0x30, DEF_STR( Medium ) )
PORT_DIPSETTING( 0x10, DEF_STR( Hard ) ) PORT_DIPSETTING( 0x10, DEF_STR( Hard ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) ) PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) )

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@ -2003,15 +2003,15 @@ static WRITE16_HANDLER( mcu_prog_w2 )
mcu_prog[mcu_prog_offs*2+1] = data; mcu_prog[mcu_prog_offs*2+1] = data;
/* Uncommented until actively worked on /* Uncommented until actively worked on
{ {
FILE *fp; FILE *fp;
fp=fopen("rdx_v33.dmp", "w+b"); fp=fopen("rdx_v33.dmp", "w+b");
if (fp) if (fp)
{ {
fwrite(mcu_prog, 0x400, 2, fp); fwrite(mcu_prog, 0x400, 2, fp);
fclose(fp); fclose(fp);
} }
} }
*/ */
} }

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@ -263,8 +263,8 @@ READ16_HANDLER(bloodwar_calc_r)
} }
/* /*
B Rap Boys B Rap Boys
Shogun Warriors Shogun Warriors
*/ */
@ -616,7 +616,7 @@ OFFSET 1 - a 'mode' register of some sort, usually 0,1,2 or 3 for used data, sho
OFFSET 2 - unknown, might be some kind of 'step' register OFFSET 2 - unknown, might be some kind of 'step' register
- 4 bits are 'shift' used in the decryption - 4 bits are 'shift' used in the decryption
- the other 4 bits probably control if the odd/even bytes are inverted, and if an alt shift is applied every other byte - the other 4 bits probably control if the odd/even bytes are inverted, and if an alt shift is applied every other byte
OFFSET 3 - decryption key - specifies which decryption table to use (ignored for inline tables, see offset 0), key 00 is blank OFFSET 3 - decryption key - specifies which decryption table to use (ignored for inline tables, see offset 0), key 00 is blank
@ -2156,16 +2156,16 @@ void calc3_mcu_run(running_machine *machine)
printf("Calc 3 Init Command - %04x ROM Checksum Address\n", cakc3_checkumaddress); printf("Calc 3 Init Command - %04x ROM Checksum Address\n", cakc3_checkumaddress);
printf("Calc 3 Init Command - %08x Data Write Address\n", calc3_writeaddress); printf("Calc 3 Init Command - %08x Data Write Address\n", calc3_writeaddress);
#endif #endif
// memory_write_byte(space, calc3_dsw_addr+0x200000, ( ~input_port_read(machine, "DSW1"))&0xff); // // DSW // dsw actually updates in realtime - mcu reads+writes it every frame // memory_write_byte(space, calc3_dsw_addr+0x200000, ( ~input_port_read(machine, "DSW1"))&0xff); // // DSW // dsw actually updates in realtime - mcu reads+writes it every frame
kaneko16_mcu_ram[cakc3_checkumaddress / 2] = calc3_mcu_crc; // MCU Rom Checksum! kaneko16_mcu_ram[cakc3_checkumaddress / 2] = calc3_mcu_crc; // MCU Rom Checksum!
/* /*
for (i=0;i<0x40;i++) for (i=0;i<0x40;i++)
{ {
kaneko16_mcu_ram[(calc3_eeprom_addr / 2)+i] = kaneko16_eeprom_data[i];//((eepromData[i]&0xff00)>>8) | ((eepromData[i]&0x00ff)<<8); kaneko16_mcu_ram[(calc3_eeprom_addr / 2)+i] = kaneko16_eeprom_data[i];//((eepromData[i]&0xff00)>>8) | ((eepromData[i]&0x00ff)<<8);
} }
*/ */
{ {
UINT32 length, size; UINT32 length, size;

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@ -87,39 +87,39 @@ static void copd2_set_tableoffset(running_machine *machine, UINT16 data)
copd2_table_4[copd2_offs/8] = cop_43c; copd2_table_4[copd2_offs/8] = cop_43c;
/* Uncommented until actively worked on /* Uncommented until actively worked on
{ {
FILE *fp; FILE *fp;
char filename[256]; char filename[256];
sprintf(filename,"copdat_%s.table2", machine->gamedrv->name); sprintf(filename,"copdat_%s.table2", machine->gamedrv->name);
fp=fopen(filename, "w+b"); fp=fopen(filename, "w+b");
if (fp) if (fp)
{ {
fwrite(copd2_table_2, 0x200/8, 1, fp); fwrite(copd2_table_2, 0x200/8, 1, fp);
fclose(fp); fclose(fp);
} }
} }
{ {
FILE *fp; FILE *fp;
char filename[256]; char filename[256];
sprintf(filename,"copdat_%s.table3", machine->gamedrv->name); sprintf(filename,"copdat_%s.table3", machine->gamedrv->name);
fp=fopen(filename, "w+b"); fp=fopen(filename, "w+b");
if (fp) if (fp)
{ {
fwrite(copd2_table_3, 0x200/8, 1, fp); fwrite(copd2_table_3, 0x200/8, 1, fp);
fclose(fp); fclose(fp);
} }
} }
{ {
FILE *fp; FILE *fp;
char filename[256]; char filename[256];
sprintf(filename,"copdat_%s.table4", machine->gamedrv->name); sprintf(filename,"copdat_%s.table4", machine->gamedrv->name);
fp=fopen(filename, "w+b"); fp=fopen(filename, "w+b");
if (fp) if (fp)
{ {
fwrite(copd2_table_4, 0x200/8, 1, fp); fwrite(copd2_table_4, 0x200/8, 1, fp);
fclose(fp); fclose(fp);
} }
} }
*/ */
} }
@ -130,17 +130,17 @@ static void copd2_set_tabledata(running_machine *machine, UINT16 data)
logerror("mcu_data %04x\n", data); logerror("mcu_data %04x\n", data);
/* Uncommented until actively worked on /* Uncommented until actively worked on
{ {
FILE *fp; FILE *fp;
char filename[256]; char filename[256];
sprintf(filename,"copdat_%s.data", machine->gamedrv->name); sprintf(filename,"copdat_%s.data", machine->gamedrv->name);
fp=fopen(filename, "w+b"); fp=fopen(filename, "w+b");
if (fp) if (fp)
{ {
fwrite(copd2_table, 0x200, 1, fp); fwrite(copd2_table, 0x200, 1, fp);
fclose(fp); fclose(fp);
} }
} }
*/ */
} }

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@ -2240,8 +2240,8 @@ VIDEO_UPDATE(dc)
******************/ ******************/
// static int useframebuffer=1; // static int useframebuffer=1;
// const rectangle *visarea = video_screen_get_visible_area(screen); // const rectangle *visarea = video_screen_get_visible_area(screen);
// int y,x; // int y,x;
//printf("videoupdate\n"); //printf("videoupdate\n");
#if DEBUG_PALRAM #if DEBUG_PALRAM

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@ -93,7 +93,7 @@ VIDEO_START( mastninj )
foreground = tilemap_create(machine, get_fg_tile_info, tilemap_scan_rows, 16, 16, 64, 32); foreground = tilemap_create(machine, get_fg_tile_info, tilemap_scan_rows, 16, 16, 64, 32);
text_layer = tilemap_create(machine, get_tx_tile_info, tilemap_scan_rows, 8, 8, 32, 32); text_layer = tilemap_create(machine, get_tx_tile_info, tilemap_scan_rows, 8, 8, 32, 32);
// tilemap_set_transparent_pen(background, 15); // tilemap_set_transparent_pen(background, 15);
tilemap_set_transparent_pen(foreground, 15); tilemap_set_transparent_pen(foreground, 15);
tilemap_set_transparent_pen(text_layer, 15); tilemap_set_transparent_pen(text_layer, 15);

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@ -656,7 +656,7 @@ static TIMER_CALLBACK( jaguar_pit )
if (gpu_regs[PIT0]) if (gpu_regs[PIT0])
{ {
sample_period = ATTOTIME_IN_NSEC(cpu_get_clock(cputag_get_cpu(machine,"gpu")) / (1+gpu_regs[PIT0]) / (1+gpu_regs[PIT1])); sample_period = ATTOTIME_IN_NSEC(cpu_get_clock(cputag_get_cpu(machine,"gpu")) / (1+gpu_regs[PIT0]) / (1+gpu_regs[PIT1]));
// timer_set(machine, sample_period, NULL, 0, jaguar_pit); // timer_set(machine, sample_period, NULL, 0, jaguar_pit);
} }
} }
#endif #endif
@ -664,7 +664,7 @@ static TIMER_CALLBACK( jaguar_pit )
WRITE16_HANDLER( jaguar_tom_regs_w ) WRITE16_HANDLER( jaguar_tom_regs_w )
{ {
UINT32 reg_store = gpu_regs[offset]; UINT32 reg_store = gpu_regs[offset];
// attotime sample_period; // attotime sample_period;
if (offset < GPU_REGS) if (offset < GPU_REGS)
{ {
COMBINE_DATA(&gpu_regs[offset]); COMBINE_DATA(&gpu_regs[offset]);

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@ -10,4 +10,4 @@
***************************************************************************/ ***************************************************************************/
extern const char build_version[]; extern const char build_version[];
const char build_version[] = "0.133u4 ("__DATE__")"; const char build_version[] = "0.133u5 ("__DATE__")";