mirror of
https://github.com/holub/mame
synced 2025-05-28 08:33:05 +03:00
Refactored i8237 DMA to use devcb.
This commit is contained in:
Curt Coder
parent
ff9e79ecea
commit
9186e3c549
@ -23,7 +23,7 @@
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#include "8237dma.h"
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/* States that the dma8237 device can be in */
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/* States that the i8237 device can be in */
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typedef enum {
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DMA8237_SI, /* Idle state */
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DMA8237_S0, /* HRQ has been triggered, waiting to receive HLDA */
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@ -47,15 +47,21 @@ typedef enum {
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} dma8237_state;
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typedef struct dma8237 dma8237_t;
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struct dma8237
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typedef struct _i8237_t i8237_t;
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struct _i8237_t
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{
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const struct dma8237_interface *intf;
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devcb_resolved_write_line out_hrq_func;
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devcb_resolved_write_line out_eop_func;
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devcb_resolved_read8 in_memr_func;
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devcb_resolved_write8 out_memw_func;
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emu_timer *timer;
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struct
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{
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devcb_resolved_read8 in_ior_func;
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devcb_resolved_write8 out_iow_func;
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devcb_resolved_write_line out_dack_func;
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UINT16 base_address;
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UINT16 base_count;
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UINT16 address;
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@ -103,11 +109,11 @@ struct dma8237
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/* ----------------------------------------------------------------------- */
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INLINE dma8237_t *get_safe_token(const device_config *device) {
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INLINE i8237_t *get_safe_token(const device_config *device) {
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assert( device != NULL );
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assert( device->token != NULL );
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assert( device->type == DEVICE_GET_INFO_NAME(dma8237) );
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return ( dma8237_t *) device->token;
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assert( device->type == I8237 );
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return ( i8237_t *) device->token;
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}
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@ -116,16 +122,16 @@ INLINE dma8237_t *get_safe_token(const device_config *device) {
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INLINE void dma8237_do_read( const device_config *device )
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{
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dma8237_t *dma8237 = get_safe_token( device );
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int channel = dma8237->service_channel;
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i8237_t *i8237 = get_safe_token( device );
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int channel = i8237->service_channel;
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switch( DMA_MODE_OPERATION( dma8237->chan[ channel ].mode ) )
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switch( DMA_MODE_OPERATION( i8237->chan[ channel ].mode ) )
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{
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case DMA8237_WRITE_TRANSFER:
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dma8237->temporary_data = dma8237->intf->channel_read_func[ channel ]( device );
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i8237->temporary_data = devcb_call_read8(&i8237->chan[channel].in_ior_func, 0);
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break;
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case DMA8237_READ_TRANSFER:
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dma8237->temporary_data = dma8237->intf->memory_read_func( device, channel, dma8237->chan[ channel ].address );
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i8237->temporary_data = devcb_call_read8(&i8237->in_memr_func, i8237->chan[ channel ].address);
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break;
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case DMA8237_VERIFY_TRANSFER:
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case DMA8237_ILLEGAL_TRANSFER:
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@ -136,16 +142,16 @@ INLINE void dma8237_do_read( const device_config *device )
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INLINE void dma8237_do_write( const device_config *device )
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{
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dma8237_t *dma8237 = get_safe_token( device );
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int channel = dma8237->service_channel;
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i8237_t *i8237 = get_safe_token( device );
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int channel = i8237->service_channel;
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switch( DMA_MODE_OPERATION( dma8237->chan[ channel ].mode ) )
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switch( DMA_MODE_OPERATION( i8237->chan[ channel ].mode ) )
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{
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case DMA8237_WRITE_TRANSFER:
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dma8237->intf->memory_write_func( device, channel, dma8237->chan[ channel ].address, dma8237->temporary_data );
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devcb_call_write8(&i8237->out_memw_func, i8237->chan[ channel ].address, i8237->temporary_data);
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break;
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case DMA8237_READ_TRANSFER:
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dma8237->intf->channel_write_func[channel]( device, dma8237->temporary_data );
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devcb_call_write8(&i8237->chan[channel].out_iow_func, 0, i8237->temporary_data);
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break;
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case DMA8237_VERIFY_TRANSFER:
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case DMA8237_ILLEGAL_TRANSFER:
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@ -156,46 +162,46 @@ INLINE void dma8237_do_write( const device_config *device )
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INLINE void dma8237_advance( const device_config *device )
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{
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dma8237_t *dma8237 = get_safe_token( device );
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int channel = dma8237->service_channel;
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int mode = dma8237->chan[channel].mode;
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i8237_t *i8237 = get_safe_token( device );
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int channel = i8237->service_channel;
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int mode = i8237->chan[channel].mode;
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switch ( DMA_MODE_OPERATION( mode ) )
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{
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case DMA8237_VERIFY_TRANSFER:
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case DMA8237_WRITE_TRANSFER:
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case DMA8237_READ_TRANSFER:
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dma8237->chan[channel].high_address_changed = 0;
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i8237->chan[channel].high_address_changed = 0;
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if ( DMA_MODE_DIRECTION( mode ) )
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{
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dma8237->chan[channel].address -= 1;
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if ( ( dma8237->chan[channel].address & 0xFF ) == 0xFF )
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dma8237->chan[channel].high_address_changed = 1;
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i8237->chan[channel].address -= 1;
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if ( ( i8237->chan[channel].address & 0xFF ) == 0xFF )
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i8237->chan[channel].high_address_changed = 1;
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}
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else
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{
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dma8237->chan[channel].address += 1;
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if ( ( dma8237->chan[channel].address & 0xFF ) == 0x00 )
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dma8237->chan[channel].high_address_changed = 1;
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i8237->chan[channel].address += 1;
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if ( ( i8237->chan[channel].address & 0xFF ) == 0x00 )
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i8237->chan[channel].high_address_changed = 1;
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}
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dma8237->chan[channel].count--;
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i8237->chan[channel].count--;
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if ( dma8237->chan[channel].count == 0xFFFF )
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if ( i8237->chan[channel].count == 0xFFFF )
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{
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/* Set TC bit for this channel */
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dma8237->status |= ( 0x01 << channel );
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i8237->status |= ( 0x01 << channel );
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if ( DMA_MODE_AUTO_INIT( mode ) )
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{
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dma8237->chan[channel].address = dma8237->chan[channel].base_address;
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dma8237->chan[channel].count = dma8237->chan[channel].base_count;
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dma8237->chan[channel].high_address_changed = 1;
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i8237->chan[channel].address = i8237->chan[channel].base_address;
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i8237->chan[channel].count = i8237->chan[channel].base_count;
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i8237->chan[channel].high_address_changed = 1;
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}
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else
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{
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dma8237->mask |= ( 0x01 << channel );
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i8237->mask |= ( 0x01 << channel );
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}
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}
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break;
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@ -205,39 +211,49 @@ INLINE void dma8237_advance( const device_config *device )
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}
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static void set_dack(i8237_t *i8237, int channel)
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{
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int i;
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for (i = 0; i < 4; i++)
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{
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int state = (i == channel) ^ BIT(i8237->command, 7);
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devcb_call_write_line(&i8237->chan[i].out_dack_func, state);
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}
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}
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static TIMER_CALLBACK( dma8237_timerproc )
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{
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const device_config *device = (const device_config *)ptr;
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dma8237_t *dma8237 = get_safe_token(device);
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i8237_t *i8237 = get_safe_token(device);
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/* Check if operation is disabled */
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if ( dma8237->command & 0x04 )
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if ( i8237->command & 0x04 )
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return;
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switch ( dma8237->state ) {
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switch ( i8237->state ) {
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case DMA8237_SI:
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/* Make sure EOP is high */
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if ( ! dma8237->eop )
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if ( ! i8237->eop )
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{
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dma8237->eop = 1;
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if ( dma8237->intf->out_eop_func )
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dma8237->intf->out_eop_func( device, 0, dma8237->eop ? ASSERT_LINE : CLEAR_LINE );
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i8237->eop = 1;
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devcb_call_write_line(&i8237->out_eop_func, i8237->eop ? ASSERT_LINE : CLEAR_LINE);
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}
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/* Check if a new DMA request has been received. */
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{
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/* Bit 6 of the command register determines whether the DREQ signals are active
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high or active low. */
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UINT16 pending_request = ( ( dma8237->command & 0x40 ) ? ~dma8237->drq : dma8237->drq ) & ~dma8237->mask;
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UINT16 pending_request = ( ( i8237->command & 0x40 ) ? ~i8237->drq : i8237->drq ) & ~i8237->mask;
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if ( pending_request & 0x0f )
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{
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int i, channel, prio_channel = 0;
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/* Determine the channel that should be serviced */
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channel = ( dma8237->command & 0x10 ) ? dma8237->last_service_channel : 3;
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channel = ( i8237->command & 0x10 ) ? i8237->last_service_channel : 3;
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for ( i = 0; i < 4; i++ )
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{
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if ( pending_request & ( 1 << channel ) )
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@ -246,17 +262,17 @@ static TIMER_CALLBACK( dma8237_timerproc )
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}
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/* Store the channel we will be servicing and go to the next state */
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dma8237->service_channel = prio_channel;
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dma8237->last_service_channel = prio_channel;
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dma8237->hrq = 1;
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dma8237->intf->hrq_changed( device, dma8237->hrq );
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dma8237->state = DMA8237_S0;
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i8237->service_channel = prio_channel;
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i8237->last_service_channel = prio_channel;
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i8237->hrq = 1;
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devcb_call_write_line(&i8237->out_hrq_func, i8237->hrq);
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i8237->state = DMA8237_S0;
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timer_enable( dma8237->timer, 1 );
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timer_enable( i8237->timer, 1 );
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}
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else
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{
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timer_enable( dma8237->timer, 0 );
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timer_enable( i8237->timer, 0 );
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}
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}
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break;
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@ -264,41 +280,44 @@ static TIMER_CALLBACK( dma8237_timerproc )
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case DMA8237_S0:
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/* S0 is the first of the DMA service. We have requested a hold but are waiting
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for confirmation. */
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if ( dma8237->hlda )
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if ( i8237->hlda )
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{
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if ( dma8237->command & 0x01 )
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if ( i8237->command & 0x01 )
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{
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/* Memory-to-memory transfers */
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dma8237->state = DMA8237_S11;
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i8237->state = DMA8237_S11;
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}
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else
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{
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/* Regular transfers */
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dma8237->state = DMA8237_S1;
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i8237->state = DMA8237_S1;
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}
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}
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break;
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case DMA8237_S1: /* Output A8-A15 */
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dma8237->state = DMA8237_S2;
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i8237->state = DMA8237_S2;
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break;
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case DMA8237_S2: /* Output A7-A0 */
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/* set DACK */
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set_dack(i8237, i8237->service_channel);
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/* Check for compressed timing */
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if ( dma8237->command & 0x08 )
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dma8237->state = DMA8237_S4;
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if ( i8237->command & 0x08 )
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i8237->state = DMA8237_S4;
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else
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dma8237->state = DMA8237_S3;
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i8237->state = DMA8237_S3;
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break;
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case DMA8237_S3: /* Initiate read */
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dma8237_do_read( device );
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dma8237->state = DMA8237_S4;
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i8237->state = DMA8237_S4;
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break;
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case DMA8237_S4: /* Perform read/write */
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/* Perform read when in compressed timing mode */
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if ( dma8237->command & 0x08 )
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if ( i8237->command & 0x08 )
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dma8237_do_read( device );
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/* Perform write */
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@ -308,66 +327,68 @@ static TIMER_CALLBACK( dma8237_timerproc )
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dma8237_advance( device );
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{
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int channel = dma8237->service_channel;
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int channel = i8237->service_channel;
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switch( DMA_MODE_TRANSFERMODE( dma8237->chan[channel].mode ) )
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switch( DMA_MODE_TRANSFERMODE( i8237->chan[channel].mode ) )
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{
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case DMA8237_DEMAND_MODE:
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/* Check for terminal count or EOP signal or DREQ begin de-asserted */
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if ( ( dma8237->status & ( 0x01 << channel ) ) || ! dma8237->eop || ! ( dma8237->drq & ( 0x01 << channel ) ) )
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if ( ( i8237->status & ( 0x01 << channel ) ) || ! i8237->eop || ! ( i8237->drq & ( 0x01 << channel ) ) )
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{
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dma8237->hrq = 0;
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dma8237->hlda = 0;
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dma8237->intf->hrq_changed( device, dma8237->hrq );
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dma8237->state = DMA8237_SI;
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i8237->hrq = 0;
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i8237->hlda = 0;
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devcb_call_write_line(&i8237->out_hrq_func, i8237->hrq);
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i8237->state = DMA8237_SI;
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}
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else
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{
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dma8237->state = dma8237->chan[channel].high_address_changed ? DMA8237_S1 : DMA8237_S2;
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i8237->state = i8237->chan[channel].high_address_changed ? DMA8237_S1 : DMA8237_S2;
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}
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break;
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case DMA8237_SINGLE_MODE:
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dma8237->hrq = 0;
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dma8237->hlda = 0;
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dma8237->intf->hrq_changed( device, dma8237->hrq );
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dma8237->state = DMA8237_SI;
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i8237->hrq = 0;
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i8237->hlda = 0;
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devcb_call_write_line(&i8237->out_hrq_func, i8237->hrq);
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i8237->state = DMA8237_SI;
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break;
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case DMA8237_BLOCK_MODE:
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/* Check for terminal count or EOP signal */
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if ( ( dma8237->status & ( 0x01 << channel ) ) || ! dma8237->eop )
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if ( ( i8237->status & ( 0x01 << channel ) ) || ! i8237->eop )
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{
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dma8237->hrq = 0;
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dma8237->hlda = 0;
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dma8237->intf->hrq_changed( device, dma8237->hrq );
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dma8237->state = DMA8237_SI;
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i8237->hrq = 0;
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i8237->hlda = 0;
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devcb_call_write_line(&i8237->out_hrq_func, i8237->hrq);
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i8237->state = DMA8237_SI;
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}
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else
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{
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dma8237->state = dma8237->chan[channel].high_address_changed ? DMA8237_S1 : DMA8237_S2;
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i8237->state = i8237->chan[channel].high_address_changed ? DMA8237_S1 : DMA8237_S2;
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}
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break;
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case DMA8237_CASCADE_MODE:
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if ( ! ( dma8237->drq & ( 0x01 << channel ) ) )
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if ( ! ( i8237->drq & ( 0x01 << channel ) ) )
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{
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dma8237->hrq = 0;
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dma8237->hlda = 0;
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dma8237->intf->hrq_changed( device, dma8237->hrq );
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dma8237->state = DMA8237_SI;
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i8237->hrq = 0;
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i8237->hlda = 0;
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devcb_call_write_line(&i8237->out_hrq_func, i8237->hrq);
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i8237->state = DMA8237_SI;
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}
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break;
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}
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/* Check if EOP output needs to be asserted */
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if ( dma8237->status & ( 0x01 << channel ) )
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if ( i8237->status & ( 0x01 << channel ) )
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{
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dma8237->eop = 0;
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if ( dma8237->intf->out_eop_func )
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dma8237->intf->out_eop_func( device, channel, dma8237->eop ? ASSERT_LINE : CLEAR_LINE );
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i8237->eop = 0;
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devcb_call_write_line(&i8237->out_eop_func, i8237->eop ? ASSERT_LINE : CLEAR_LINE);
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}
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}
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/* clear DACK */
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set_dack(i8237, -1);
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break;
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case DMA8237_S11: /* Output A8-A15 */
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@ -381,9 +402,9 @@ static TIMER_CALLBACK( dma8237_timerproc )
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/* ----------------------------------------------------------------------- */
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READ8_DEVICE_HANDLER( dma8237_r )
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READ8_DEVICE_HANDLER( i8237_r )
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{
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dma8237_t *dma8237 = get_safe_token(device);
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i8237_t *i8237 = get_safe_token(device);
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UINT8 data = 0xFF;
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offset &= 0x0F;
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@ -394,8 +415,8 @@ READ8_DEVICE_HANDLER( dma8237_r )
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case 4:
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case 6:
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/* DMA address register */
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data = dma8237->chan[offset / 2].address >> (dma8237->msb ? 8 : 0);
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dma8237->msb ^= 1;
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data = i8237->chan[offset / 2].address >> (i8237->msb ? 8 : 0);
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i8237->msb ^= 1;
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break;
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case 1:
|
||||
@ -403,26 +424,26 @@ READ8_DEVICE_HANDLER( dma8237_r )
|
||||
case 5:
|
||||
case 7:
|
||||
/* DMA count register */
|
||||
data = dma8237->chan[offset / 2].count >> (dma8237->msb ? 8 : 0);
|
||||
dma8237->msb ^= 1;
|
||||
data = i8237->chan[offset / 2].count >> (i8237->msb ? 8 : 0);
|
||||
i8237->msb ^= 1;
|
||||
break;
|
||||
|
||||
case 8:
|
||||
/* DMA status register */
|
||||
data = (UINT8) dma8237->status;
|
||||
data = (UINT8) i8237->status;
|
||||
|
||||
/* TC bits are cleared on a status read */
|
||||
dma8237->status &= 0xF0;
|
||||
i8237->status &= 0xF0;
|
||||
break;
|
||||
|
||||
case 10:
|
||||
/* DMA mask register */
|
||||
data = dma8237->mask;
|
||||
data = i8237->mask;
|
||||
break;
|
||||
|
||||
case 13:
|
||||
/* DMA master clear */
|
||||
data = dma8237->temp;
|
||||
data = i8237->temp;
|
||||
break;
|
||||
|
||||
case 9: /* DMA write request register */
|
||||
@ -439,14 +460,14 @@ READ8_DEVICE_HANDLER( dma8237_r )
|
||||
|
||||
|
||||
|
||||
WRITE8_DEVICE_HANDLER( dma8237_w )
|
||||
WRITE8_DEVICE_HANDLER( i8237_w )
|
||||
{
|
||||
dma8237_t *dma8237 = get_safe_token(device);
|
||||
i8237_t *i8237 = get_safe_token(device);
|
||||
int channel;
|
||||
|
||||
offset &= 0x0F;
|
||||
|
||||
logerror("dma8237_w: offset = %02x, data = %02x\n", offset, data );
|
||||
logerror("i8237_w: offset = %02x, data = %02x\n", offset, data );
|
||||
|
||||
switch(offset) {
|
||||
case 0:
|
||||
@ -455,17 +476,17 @@ WRITE8_DEVICE_HANDLER( dma8237_w )
|
||||
case 6:
|
||||
/* DMA address register */
|
||||
channel = offset / 2;
|
||||
if (dma8237->msb)
|
||||
if (i8237->msb)
|
||||
{
|
||||
dma8237->chan[channel].base_address = ( dma8237->chan[channel].base_address & 0x00FF ) | ( data << 8 );
|
||||
dma8237->chan[channel].address = ( dma8237->chan[channel].address & 0x00FF ) | ( data << 8 );
|
||||
i8237->chan[channel].base_address = ( i8237->chan[channel].base_address & 0x00FF ) | ( data << 8 );
|
||||
i8237->chan[channel].address = ( i8237->chan[channel].address & 0x00FF ) | ( data << 8 );
|
||||
}
|
||||
else
|
||||
{
|
||||
dma8237->chan[channel].base_address = ( dma8237->chan[channel].base_address & 0xFF00 ) | data;
|
||||
dma8237->chan[channel].address = ( dma8237->chan[channel].address & 0xFF00 ) | data;
|
||||
i8237->chan[channel].base_address = ( i8237->chan[channel].base_address & 0xFF00 ) | data;
|
||||
i8237->chan[channel].address = ( i8237->chan[channel].address & 0xFF00 ) | data;
|
||||
}
|
||||
dma8237->msb ^= 1;
|
||||
i8237->msb ^= 1;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
@ -474,23 +495,23 @@ WRITE8_DEVICE_HANDLER( dma8237_w )
|
||||
case 7:
|
||||
/* DMA count register */
|
||||
channel = offset / 2;
|
||||
if (dma8237->msb)
|
||||
if (i8237->msb)
|
||||
{
|
||||
dma8237->chan[channel].base_count = ( dma8237->chan[channel].base_count & 0x00FF ) | ( data << 8 );
|
||||
dma8237->chan[channel].count = ( dma8237->chan[channel].count & 0x00FF ) | ( data << 8 );
|
||||
i8237->chan[channel].base_count = ( i8237->chan[channel].base_count & 0x00FF ) | ( data << 8 );
|
||||
i8237->chan[channel].count = ( i8237->chan[channel].count & 0x00FF ) | ( data << 8 );
|
||||
}
|
||||
else
|
||||
{
|
||||
dma8237->chan[channel].base_count = ( dma8237->chan[channel].base_count & 0xFF00 ) | data;
|
||||
dma8237->chan[channel].count = ( dma8237->chan[channel].count & 0xFF00 ) | data;
|
||||
i8237->chan[channel].base_count = ( i8237->chan[channel].base_count & 0xFF00 ) | data;
|
||||
i8237->chan[channel].count = ( i8237->chan[channel].count & 0xFF00 ) | data;
|
||||
}
|
||||
dma8237->msb ^= 1;
|
||||
i8237->msb ^= 1;
|
||||
break;
|
||||
|
||||
case 8:
|
||||
/* DMA command register */
|
||||
dma8237->command = data;
|
||||
timer_enable( dma8237->timer, ( dma8237->command & 0x04 ) ? 0 : 1 );
|
||||
i8237->command = data;
|
||||
timer_enable( i8237->timer, ( i8237->command & 0x04 ) ? 0 : 1 );
|
||||
break;
|
||||
|
||||
case 9:
|
||||
@ -498,13 +519,13 @@ WRITE8_DEVICE_HANDLER( dma8237_w )
|
||||
channel = DMA_MODE_CHANNEL(data);
|
||||
if ( data & 0x04 )
|
||||
{
|
||||
dma8237->drq |= 0x01 << channel;
|
||||
timer_enable( dma8237->timer, ( dma8237->command & 0x04 ) ? 0 : 1 );
|
||||
i8237->drq |= 0x01 << channel;
|
||||
timer_enable( i8237->timer, ( i8237->command & 0x04 ) ? 0 : 1 );
|
||||
}
|
||||
else
|
||||
{
|
||||
dma8237->status &= ~ ( 0x10 << channel );
|
||||
dma8237->drq &= ~ ( 0x01 << channel );
|
||||
i8237->status &= ~ ( 0x10 << channel );
|
||||
i8237->drq &= ~ ( 0x01 << channel );
|
||||
}
|
||||
break;
|
||||
|
||||
@ -512,132 +533,157 @@ WRITE8_DEVICE_HANDLER( dma8237_w )
|
||||
/* DMA mask register */
|
||||
channel = DMA_MODE_CHANNEL(data);
|
||||
if (data & 0x04)
|
||||
dma8237->mask |= 0x11 << channel;
|
||||
i8237->mask |= 0x11 << channel;
|
||||
else
|
||||
dma8237->mask &= ~(0x11 << channel);
|
||||
i8237->mask &= ~(0x11 << channel);
|
||||
break;
|
||||
|
||||
case 11:
|
||||
/* DMA mode register */
|
||||
channel = DMA_MODE_CHANNEL(data);
|
||||
dma8237->chan[channel].mode = data;
|
||||
i8237->chan[channel].mode = data;
|
||||
/* Apparently mode writes also clear the TC bit(?) */
|
||||
dma8237->status &= ~ ( 1 << channel );
|
||||
i8237->status &= ~ ( 1 << channel );
|
||||
break;
|
||||
|
||||
case 12:
|
||||
/* DMA clear byte pointer flip-flop */
|
||||
dma8237->temp = data;
|
||||
dma8237->msb = 0;
|
||||
i8237->temp = data;
|
||||
i8237->msb = 0;
|
||||
break;
|
||||
|
||||
case 13:
|
||||
/* DMA master clear */
|
||||
dma8237->msb = 0;
|
||||
dma8237->mask = 0x0f;
|
||||
dma8237->state = DMA8237_SI;
|
||||
dma8237->status &= 0xF0;
|
||||
i8237->msb = 0;
|
||||
i8237->mask = 0x0f;
|
||||
i8237->state = DMA8237_SI;
|
||||
i8237->status &= 0xF0;
|
||||
break;
|
||||
|
||||
case 14:
|
||||
/* DMA clear mask register */
|
||||
dma8237->mask &= ~data;
|
||||
dma8237->mask = 0;
|
||||
i8237->mask &= ~data;
|
||||
i8237->mask = 0;
|
||||
break;
|
||||
|
||||
case 15:
|
||||
/* DMA write mask register */
|
||||
dma8237->mask = data & 0x0f;
|
||||
i8237->mask = data & 0x0f;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
void dma8237_drq_write(const device_config *device, int channel, int state)
|
||||
static void dma8237_drq_write(const device_config *device, int channel, int state)
|
||||
{
|
||||
dma8237_t *dma8237 = get_safe_token( device );
|
||||
i8237_t *i8237 = get_safe_token( device );
|
||||
|
||||
if (state)
|
||||
dma8237->drq |= ( 0x01 << channel );
|
||||
i8237->drq |= ( 0x01 << channel );
|
||||
else
|
||||
dma8237->drq &= ~( 0x01 << channel );
|
||||
i8237->drq &= ~( 0x01 << channel );
|
||||
|
||||
timer_enable( dma8237->timer, ( dma8237->command & 0x04 ) ? 0 : 1 );
|
||||
timer_enable( i8237->timer, ( i8237->command & 0x04 ) ? 0 : 1 );
|
||||
}
|
||||
|
||||
|
||||
void dma8237_set_hlda(const device_config *device, int state)
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_hlda_w )
|
||||
{
|
||||
dma8237_t *dma8237 = get_safe_token( device );
|
||||
i8237_t *i8237 = get_safe_token( device );
|
||||
|
||||
dma8237->hlda = state;
|
||||
i8237->hlda = state;
|
||||
}
|
||||
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_ready_w )
|
||||
{
|
||||
}
|
||||
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_dreq0_w ) { dma8237_drq_write(device, 0, state); }
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_dreq1_w ) { dma8237_drq_write(device, 1, state); }
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_dreq2_w ) { dma8237_drq_write(device, 2, state); }
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_dreq3_w ) { dma8237_drq_write(device, 3, state); }
|
||||
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_eop_w )
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
/******************* Unfortunate hacks *******************/
|
||||
|
||||
void dma8237_run_transfer(const device_config *device, int channel)
|
||||
void i8237_run_transfer(const device_config *device, int channel)
|
||||
{
|
||||
dma8237_t *dma8237 = get_safe_token(device);
|
||||
i8237_t *i8237 = get_safe_token(device);
|
||||
|
||||
dma8237->status |= 0x10 << channel; /* reset DMA running flag */
|
||||
i8237->status |= 0x10 << channel; /* reset DMA running flag */
|
||||
|
||||
popmessage("dma8237_run_transfer(): please do not use me anymore\n");
|
||||
|
||||
dma8237->status &= ~(0x10 << channel);
|
||||
dma8237->status |= (0x01 << channel);
|
||||
i8237->status &= ~(0x10 << channel);
|
||||
i8237->status |= (0x01 << channel);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static DEVICE_START( dma8237 ) {
|
||||
dma8237_t *dma8237 = get_safe_token(device);
|
||||
static DEVICE_START( i8237 ) {
|
||||
i8237_t *i8237 = get_safe_token(device);
|
||||
i8237_interface *intf = (i8237_interface *)device->static_config;
|
||||
int i;
|
||||
|
||||
dma8237->intf = (struct dma8237_interface *)device->static_config;
|
||||
/* resolve callbacks */
|
||||
devcb_resolve_write_line(&i8237->out_hrq_func, &intf->out_hrq_func, device);
|
||||
devcb_resolve_write_line(&i8237->out_eop_func, &intf->out_eop_func, device);
|
||||
devcb_resolve_read8(&i8237->in_memr_func, &intf->in_memr_func, device);
|
||||
devcb_resolve_write8(&i8237->out_memw_func, &intf->out_memw_func, device);
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
devcb_resolve_read8(&i8237->chan[i].in_ior_func, &intf->in_ior_func[i], device);
|
||||
devcb_resolve_write8(&i8237->chan[i].out_iow_func, &intf->out_iow_func[i], device);
|
||||
devcb_resolve_write_line(&i8237->chan[i].out_dack_func, &intf->out_dack_func[i], device);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static DEVICE_RESET( dma8237 ) {
|
||||
dma8237_t *dma8237 = get_safe_token(device);
|
||||
static DEVICE_RESET( i8237 ) {
|
||||
i8237_t *i8237 = get_safe_token(device);
|
||||
|
||||
dma8237->status = 0x0F;
|
||||
dma8237->timer = timer_alloc(device->machine, dma8237_timerproc, (void *)device);
|
||||
dma8237->eop = 1;
|
||||
dma8237->state = DMA8237_SI;
|
||||
dma8237->last_service_channel = 3;
|
||||
i8237->status = 0x0F;
|
||||
i8237->timer = timer_alloc(device->machine, dma8237_timerproc, (void *)device);
|
||||
i8237->eop = 1;
|
||||
i8237->state = DMA8237_SI;
|
||||
i8237->last_service_channel = 3;
|
||||
|
||||
dma8237->mask = 0x00;
|
||||
dma8237->status = 0x0F;
|
||||
dma8237->hrq = 0;
|
||||
dma8237->hlda = 0;
|
||||
dma8237->chan[0].mode = 0;
|
||||
dma8237->chan[1].mode = 0;
|
||||
dma8237->chan[2].mode = 0;
|
||||
dma8237->chan[3].mode = 0;
|
||||
i8237->mask = 0x00;
|
||||
i8237->status = 0x0F;
|
||||
i8237->hrq = 0;
|
||||
i8237->hlda = 0;
|
||||
i8237->chan[0].mode = 0;
|
||||
i8237->chan[1].mode = 0;
|
||||
i8237->chan[2].mode = 0;
|
||||
i8237->chan[3].mode = 0;
|
||||
|
||||
timer_adjust_periodic(dma8237->timer,
|
||||
ATTOTIME_IN_HZ(dma8237->intf->bus_speed),
|
||||
timer_adjust_periodic(i8237->timer,
|
||||
ATTOTIME_IN_HZ(device->clock),
|
||||
0,
|
||||
ATTOTIME_IN_HZ(dma8237->intf->bus_speed));
|
||||
ATTOTIME_IN_HZ(device->clock));
|
||||
}
|
||||
|
||||
|
||||
DEVICE_GET_INFO( dma8237 ) {
|
||||
DEVICE_GET_INFO( i8237 ) {
|
||||
switch ( state ) {
|
||||
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
||||
case DEVINFO_INT_TOKEN_BYTES: info->i = sizeof(dma8237_t); break;
|
||||
case DEVINFO_INT_TOKEN_BYTES: info->i = sizeof(i8237_t); break;
|
||||
case DEVINFO_INT_INLINE_CONFIG_BYTES: info->i = 0; break;
|
||||
case DEVINFO_INT_CLASS: info->i = DEVICE_CLASS_PERIPHERAL; break;
|
||||
|
||||
/* --- the following bits of info are returned as pointers to data or functions --- */
|
||||
case DEVINFO_FCT_START: info->start = DEVICE_START_NAME(dma8237); break;
|
||||
case DEVINFO_FCT_START: info->start = DEVICE_START_NAME(i8237); break;
|
||||
case DEVINFO_FCT_STOP: /* nothing */ break;
|
||||
case DEVINFO_FCT_RESET: info->reset = DEVICE_RESET_NAME(dma8237); break;
|
||||
case DEVINFO_FCT_RESET: info->reset = DEVICE_RESET_NAME(i8237); break;
|
||||
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
case DEVINFO_STR_NAME: strcpy(info->s, "Intel DMA8237"); break;
|
||||
case DEVINFO_STR_FAMILY: strcpy(info->s, "DMA8237"); break;
|
||||
case DEVINFO_STR_NAME: strcpy(info->s, "Intel 8237"); break;
|
||||
case DEVINFO_STR_FAMILY: strcpy(info->s, "Intel 8080"); break;
|
||||
case DEVINFO_STR_VERSION: strcpy(info->s, "1.01"); break;
|
||||
case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
|
||||
case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright the MAME and MESS Teams"); break;
|
||||
|
||||
@ -1,66 +1,99 @@
|
||||
/**********************************************************************
|
||||
|
||||
8237 DMA interface and emulation
|
||||
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __DMA8237_H_
|
||||
#define __DMA8237_H_
|
||||
|
||||
#define DMA8237 DEVICE_GET_INFO_NAME(dma8237)
|
||||
|
||||
typedef void (*dma8237_hrq_func)(const device_config *device, int state);
|
||||
typedef UINT8 (*dma8237_mem_read_func)(const device_config *device, int channel, offs_t offset);
|
||||
typedef void (*dma8237_mem_write_func)(const device_config *device, int channel, offs_t offset, UINT8 data);
|
||||
typedef int (*dma8237_channel_read_func)(const device_config *device);
|
||||
typedef void (*dma8237_channel_write_func)(const device_config *device, int data);
|
||||
typedef void (*dma8237_out_eop_func)(const device_config *device, int channel, int state);
|
||||
|
||||
#define DMA8237_HRQ_CHANGED(name) void name(const device_config *device, int state)
|
||||
#define DMA8237_MEM_READ(name) UINT8 name(const device_config *device, int channel, offs_t offset)
|
||||
#define DMA8237_MEM_WRITE(name) void name(const device_config *device, int channel, offs_t offset, UINT8 data)
|
||||
#define DMA8237_CHANNEL_READ(name) int name(const device_config *device)
|
||||
#define DMA8237_CHANNEL_WRITE(name) void name(const device_config *device, int data)
|
||||
#define DMA8237_OUT_EOP(name) void name(const device_config *device, int channel, int state)
|
||||
|
||||
struct dma8237_interface
|
||||
{
|
||||
/* speed of DMA accesses (per byte) */
|
||||
double bus_speed;
|
||||
|
||||
/* function that will be called when HRQ may have changed */
|
||||
dma8237_hrq_func hrq_changed;
|
||||
|
||||
/* accessors to main memory */
|
||||
dma8237_mem_read_func memory_read_func;
|
||||
dma8237_mem_write_func memory_write_func;
|
||||
|
||||
/* channel accesors */
|
||||
dma8237_channel_read_func channel_read_func[4];
|
||||
dma8237_channel_write_func channel_write_func[4];
|
||||
|
||||
/* function to call when DMA completes */
|
||||
dma8237_out_eop_func out_eop_func;
|
||||
};
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
DEVICE CONFIGURATION MACROS
|
||||
|
||||
Intel 8237 Programmable DMA Controller emulation
|
||||
|
||||
Copyright Nicola Salmoria and the MAME Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
****************************************************************************
|
||||
_____ _____
|
||||
_I/OR 1 |* \_/ | 40 A7
|
||||
_I/OW 2 | | 39 A6
|
||||
_MEMR 3 | | 38 A5
|
||||
_MEMW 4 | | 37 A4
|
||||
5 | | 36 _EOP
|
||||
READY 6 | | 35 A3
|
||||
HLDA 7 | | 34 A2
|
||||
ADSTB 8 | | 33 A1
|
||||
AEN 9 | | 32 A0
|
||||
HRQ 10 | 8237 | 31 Vcc
|
||||
_CS 11 | | 30 DB0
|
||||
CLK 12 | | 29 DB1
|
||||
RESET 13 | | 28 DB2
|
||||
DACK2 14 | | 27 DB3
|
||||
DACK3 15 | | 26 DB4
|
||||
DREQ3 16 | | 25 DACK0
|
||||
DREQ2 17 | | 24 DACK1
|
||||
DREQ1 18 | | 23 DB5
|
||||
DREQ0 19 | | 22 DB6
|
||||
GND 20 |_____________| 21 DB7
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#define MDRV_DMA8237_ADD(_tag, _intrf) \
|
||||
MDRV_DEVICE_ADD(_tag, DMA8237, 0) \
|
||||
MDRV_DEVICE_CONFIG(_intrf)
|
||||
#ifndef __I8237__
|
||||
#define __I8237__
|
||||
|
||||
#include "devcb.h"
|
||||
|
||||
/* device interface */
|
||||
DEVICE_GET_INFO( dma8237 );
|
||||
READ8_DEVICE_HANDLER( dma8237_r );
|
||||
WRITE8_DEVICE_HANDLER( dma8237_w );
|
||||
void dma8237_drq_write(const device_config *device, int channel, int state);
|
||||
void dma8237_set_hlda(const device_config *device, int state);
|
||||
/***************************************************************************
|
||||
MACROS / CONSTANTS
|
||||
***************************************************************************/
|
||||
|
||||
#define I8237 DEVICE_GET_INFO_NAME(i8237)
|
||||
|
||||
#define MDRV_I8237_ADD(_tag, _clock, _config) \
|
||||
MDRV_DEVICE_ADD(_tag, I8237, _clock) \
|
||||
MDRV_DEVICE_CONFIG(_config)
|
||||
|
||||
#define I8237_INTERFACE(_name) \
|
||||
const i8237_interface (_name) =
|
||||
|
||||
/***************************************************************************
|
||||
TYPE DEFINITIONS
|
||||
***************************************************************************/
|
||||
|
||||
typedef struct _i8237_interface i8237_interface;
|
||||
struct _i8237_interface
|
||||
{
|
||||
devcb_write_line out_hrq_func;
|
||||
devcb_write_line out_eop_func;
|
||||
|
||||
/* accessors to main memory */
|
||||
devcb_read8 in_memr_func;
|
||||
devcb_write8 out_memw_func;
|
||||
|
||||
/* channel accessors */
|
||||
devcb_read8 in_ior_func[4];
|
||||
devcb_write8 out_iow_func[4];
|
||||
devcb_write_line out_dack_func[4];
|
||||
};
|
||||
|
||||
/***************************************************************************
|
||||
PROTOTYPES
|
||||
***************************************************************************/
|
||||
|
||||
/* register access */
|
||||
READ8_DEVICE_HANDLER( i8237_r );
|
||||
WRITE8_DEVICE_HANDLER( i8237_w );
|
||||
|
||||
/* hold acknowledge */
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_hlda_w );
|
||||
|
||||
/* ready */
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_ready_w );
|
||||
|
||||
/* data request */
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_dreq0_w );
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_dreq1_w );
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_dreq2_w );
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_dreq3_w );
|
||||
|
||||
/* end of process */
|
||||
WRITE_LINE_DEVICE_HANDLER( i8237_eop_w );
|
||||
|
||||
DEVICE_GET_INFO( i8237 );
|
||||
|
||||
/* unfortunate hack for the interim for PC HDC */
|
||||
void dma8237_run_transfer(const device_config *device, int channel);
|
||||
void i8237_run_transfer(const device_config *device, int channel);
|
||||
|
||||
#endif /* __DMA8237_H_ */
|
||||
#endif
|
||||
|
||||
@ -148,12 +148,12 @@ static VIDEO_UPDATE(calchase)
|
||||
|
||||
static READ8_DEVICE_HANDLER(at_dma8237_2_r)
|
||||
{
|
||||
return dma8237_r(device, offset / 2);
|
||||
return i8237_r(device, offset / 2);
|
||||
}
|
||||
|
||||
static WRITE8_DEVICE_HANDLER(at_dma8237_2_w)
|
||||
{
|
||||
dma8237_w(device, offset / 2, data);
|
||||
i8237_w(device, offset / 2, data);
|
||||
}
|
||||
|
||||
static READ32_DEVICE_HANDLER(at32_dma8237_2_r)
|
||||
@ -166,6 +166,7 @@ static WRITE32_DEVICE_HANDLER(at32_dma8237_2_w)
|
||||
write32le_with_write8_device_handler(at_dma8237_2_w, device, offset, data, mem_mask);
|
||||
}
|
||||
|
||||
static int dma_channel;
|
||||
static UINT8 dma_offset[2][4];
|
||||
static UINT8 at_pages[0x10];
|
||||
|
||||
@ -213,60 +214,58 @@ static WRITE8_HANDLER(at_page8_w)
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_HRQ_CHANGED( pc_dma_hrq_changed )
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
|
||||
{
|
||||
cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
dma8237_set_hlda( device, state );
|
||||
i8237_hlda_w( device, state );
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_READ( pc_dma_read_byte )
|
||||
static READ8_HANDLER( pc_dma_read_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
return memory_read_byte(space, page_offset + offset);
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_WRITE( pc_dma_write_byte )
|
||||
static WRITE8_HANDLER( pc_dma_write_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
memory_write_byte(space, page_offset + offset, data);
|
||||
}
|
||||
|
||||
|
||||
static const struct dma8237_interface dma8237_1_config =
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { if (state) dma_channel = 0; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { if (state) dma_channel = 1; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { if (state) dma_channel = 2; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { if (state) dma_channel = 3; }
|
||||
|
||||
static I8237_INTERFACE( dma8237_1_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
pc_dma_hrq_changed,
|
||||
pc_dma_read_byte,
|
||||
pc_dma_write_byte,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_LINE(pc_dma_hrq_changed),
|
||||
DEVCB_NULL,
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
|
||||
};
|
||||
|
||||
|
||||
static const struct dma8237_interface dma8237_2_config =
|
||||
static I8237_INTERFACE( dma8237_2_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
|
||||
};
|
||||
|
||||
static READ32_HANDLER(at_page32_r)
|
||||
@ -471,7 +470,7 @@ static ADDRESS_MAP_START( calchase_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( calchase_io, ADDRESS_SPACE_IO, 32)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", dma8237_r, dma8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", i8237_r, i8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_1", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
AM_RANGE(0x0060, 0x006f) AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
@ -660,8 +659,8 @@ static MACHINE_DRIVER_START( calchase )
|
||||
MDRV_MACHINE_RESET(calchase)
|
||||
|
||||
MDRV_PIT8254_ADD( "pit8254", calchase_pit8254_config )
|
||||
MDRV_DMA8237_ADD( "dma8237_1", dma8237_1_config )
|
||||
MDRV_DMA8237_ADD( "dma8237_2", dma8237_2_config )
|
||||
MDRV_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
|
||||
MDRV_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
|
||||
MDRV_PIC8259_ADD( "pic8259_1", calchase_pic8259_1_config )
|
||||
MDRV_PIC8259_ADD( "pic8259_2", calchase_pic8259_2_config )
|
||||
MDRV_IDE_CONTROLLER_ADD("ide", ide_interrupt)
|
||||
|
||||
@ -152,12 +152,12 @@ static VIDEO_UPDATE(gamecstl)
|
||||
|
||||
static READ8_DEVICE_HANDLER(at_dma8237_2_r)
|
||||
{
|
||||
return dma8237_r(device, offset / 2);
|
||||
return i8237_r(device, offset / 2);
|
||||
}
|
||||
|
||||
static WRITE8_DEVICE_HANDLER(at_dma8237_2_w)
|
||||
{
|
||||
dma8237_w(device, offset / 2, data);
|
||||
i8237_w(device, offset / 2, data);
|
||||
}
|
||||
|
||||
static READ32_DEVICE_HANDLER(at32_dma8237_2_r)
|
||||
@ -371,6 +371,7 @@ static WRITE32_HANDLER(bios_ram_w)
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
static int dma_channel;
|
||||
static UINT8 dma_offset[2][4];
|
||||
static UINT8 at_pages[0x10];
|
||||
|
||||
@ -420,60 +421,58 @@ static WRITE8_HANDLER(at_page8_w)
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_HRQ_CHANGED( pc_dma_hrq_changed )
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
|
||||
{
|
||||
cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
dma8237_set_hlda( device, state );
|
||||
i8237_hlda_w( device, state );
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_READ( pc_dma_read_byte )
|
||||
static READ8_HANDLER( pc_dma_read_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
return memory_read_byte(space, page_offset + offset);
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_WRITE( pc_dma_write_byte )
|
||||
static WRITE8_HANDLER( pc_dma_write_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
memory_write_byte(space, page_offset + offset, data);
|
||||
}
|
||||
|
||||
|
||||
static const struct dma8237_interface dma8237_1_config =
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { if (state) dma_channel = 0; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { if (state) dma_channel = 1; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { if (state) dma_channel = 2; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { if (state) dma_channel = 3; }
|
||||
|
||||
static I8237_INTERFACE( dma8237_1_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
pc_dma_hrq_changed,
|
||||
pc_dma_read_byte,
|
||||
pc_dma_write_byte,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_LINE(pc_dma_hrq_changed),
|
||||
DEVCB_NULL,
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
|
||||
};
|
||||
|
||||
|
||||
static const struct dma8237_interface dma8237_2_config =
|
||||
static I8237_INTERFACE( dma8237_2_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
|
||||
};
|
||||
|
||||
static READ32_HANDLER(at_page32_r)
|
||||
@ -502,7 +501,7 @@ static ADDRESS_MAP_START( gamecstl_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(gamecstl_io, ADDRESS_SPACE_IO, 32)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", dma8237_r, dma8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", i8237_r, i8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_1", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
AM_RANGE(0x0060, 0x006f) AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
@ -677,9 +676,9 @@ static MACHINE_DRIVER_START(gamecstl)
|
||||
|
||||
MDRV_PIT8254_ADD( "pit8254", gamecstl_pit8254_config )
|
||||
|
||||
MDRV_DMA8237_ADD( "dma8237_1", dma8237_1_config )
|
||||
MDRV_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
|
||||
|
||||
MDRV_DMA8237_ADD( "dma8237_2", dma8237_2_config )
|
||||
MDRV_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
|
||||
|
||||
MDRV_PIC8259_ADD( "pic8259_1", gamecstl_pic8259_1_config )
|
||||
|
||||
|
||||
@ -363,12 +363,12 @@ static WRITE32_HANDLER( disp_ctrl_w )
|
||||
|
||||
static READ8_DEVICE_HANDLER(at_dma8237_2_r)
|
||||
{
|
||||
return dma8237_r(device, offset / 2);
|
||||
return i8237_r(device, offset / 2);
|
||||
}
|
||||
|
||||
static WRITE8_DEVICE_HANDLER(at_dma8237_2_w)
|
||||
{
|
||||
dma8237_w(device, offset / 2, data);
|
||||
i8237_w(device, offset / 2, data);
|
||||
}
|
||||
|
||||
|
||||
@ -726,6 +726,7 @@ static WRITE32_HANDLER( ad1847_w )
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
static int dma_channel;
|
||||
static UINT8 dma_offset[2][4];
|
||||
static UINT8 at_pages[0x10];
|
||||
|
||||
@ -775,60 +776,58 @@ static WRITE8_HANDLER(at_page8_w)
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_HRQ_CHANGED( pc_dma_hrq_changed )
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
|
||||
{
|
||||
cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
dma8237_set_hlda( device, state );
|
||||
i8237_hlda_w( device, state );
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_READ( pc_dma_read_byte )
|
||||
static READ8_HANDLER( pc_dma_read_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
return memory_read_byte(space, page_offset + offset);
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_WRITE( pc_dma_write_byte )
|
||||
static WRITE8_HANDLER( pc_dma_write_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
memory_write_byte(space, page_offset + offset, data);
|
||||
}
|
||||
|
||||
|
||||
static const struct dma8237_interface dma8237_1_config =
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { if (state) dma_channel = 0; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { if (state) dma_channel = 1; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { if (state) dma_channel = 2; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { if (state) dma_channel = 3; }
|
||||
|
||||
static I8237_INTERFACE( dma8237_1_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
pc_dma_hrq_changed,
|
||||
pc_dma_read_byte,
|
||||
pc_dma_write_byte,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_LINE(pc_dma_hrq_changed),
|
||||
DEVCB_NULL,
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
|
||||
};
|
||||
|
||||
|
||||
static const struct dma8237_interface dma8237_2_config =
|
||||
static I8237_INTERFACE( dma8237_2_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
|
||||
};
|
||||
|
||||
|
||||
@ -848,7 +847,7 @@ static ADDRESS_MAP_START( mediagx_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(mediagx_io, ADDRESS_SPACE_IO, 32)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", dma8237_r, dma8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", i8237_r, i8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_master", io20_r, io20_w, 0xffffffff)
|
||||
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
AM_RANGE(0x0060, 0x006f) AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
@ -1057,9 +1056,9 @@ static MACHINE_DRIVER_START(mediagx)
|
||||
|
||||
MDRV_PIT8254_ADD( "pit8254", mediagx_pit8254_config )
|
||||
|
||||
MDRV_DMA8237_ADD( "dma8237_1", dma8237_1_config )
|
||||
MDRV_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
|
||||
|
||||
MDRV_DMA8237_ADD( "dma8237_2", dma8237_2_config )
|
||||
MDRV_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
|
||||
|
||||
MDRV_PIC8259_ADD( "pic8259_master", mediagx_pic8259_1_config )
|
||||
|
||||
|
||||
@ -111,36 +111,10 @@ static struct {
|
||||
DMA8237 Controller
|
||||
******************/
|
||||
|
||||
static int dma_channel;
|
||||
static UINT8 dma_offset[2][4];
|
||||
static UINT8 at_pages[0x10];
|
||||
|
||||
static DMA8237_HRQ_CHANGED( pc_dma_hrq_changed )
|
||||
{
|
||||
cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
dma8237_set_hlda( device, state );
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_READ( pc_dma_read_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
return memory_read_byte(space, page_offset + offset);
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_WRITE( pc_dma_write_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
memory_write_byte(space, page_offset + offset, data);
|
||||
}
|
||||
|
||||
static READ8_HANDLER(dma_page_select_r)
|
||||
{
|
||||
@ -187,30 +161,58 @@ static WRITE8_HANDLER(dma_page_select_w)
|
||||
}
|
||||
|
||||
|
||||
static const struct dma8237_interface dma8237_1_config =
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
pc_dma_hrq_changed,
|
||||
pc_dma_read_byte,
|
||||
pc_dma_write_byte,
|
||||
/* Assert HLDA */
|
||||
i8237_hlda_w( device, state );
|
||||
}
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
|
||||
static READ8_HANDLER( pc_dma_read_byte )
|
||||
{
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
return memory_read_byte(space, page_offset + offset);
|
||||
}
|
||||
|
||||
|
||||
static WRITE8_HANDLER( pc_dma_write_byte )
|
||||
{
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
memory_write_byte(space, page_offset + offset, data);
|
||||
}
|
||||
|
||||
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { if (state) dma_channel = 0; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { if (state) dma_channel = 1; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { if (state) dma_channel = 2; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { if (state) dma_channel = 3; }
|
||||
|
||||
static I8237_INTERFACE( dma8237_1_config )
|
||||
{
|
||||
DEVCB_LINE(pc_dma_hrq_changed),
|
||||
DEVCB_NULL,
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
|
||||
};
|
||||
|
||||
static const struct dma8237_interface dma8237_2_config =
|
||||
static I8237_INTERFACE( dma8237_2_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
|
||||
};
|
||||
|
||||
|
||||
@ -352,14 +354,14 @@ static WRITE32_HANDLER( vga_regs_w )
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( pcat_io, ADDRESS_SPACE_IO, 32 )
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", dma8237_r, dma8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", i8237_r, i8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_1", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
AM_RANGE(0x0060, 0x006f) AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
AM_RANGE(0x0070, 0x007f) AM_RAM//READWRITE(mc146818_port32le_r, mc146818_port32le_w)
|
||||
AM_RANGE(0x0080, 0x009f) AM_READWRITE8(dma_page_select_r,dma_page_select_w, 0xffffffff)//TODO
|
||||
AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8("pic8259_2", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE8("dma8237_2", dma8237_r, dma8237_w, 0xffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE8("dma8237_2", i8237_r, i8237_w, 0xffff)
|
||||
AM_RANGE(0x0278, 0x027f) AM_RAM //parallel port 2
|
||||
AM_RANGE(0x0378, 0x037f) AM_RAM //parallel port
|
||||
AM_RANGE(0x03c0, 0x03c3) AM_RAM
|
||||
@ -513,8 +515,8 @@ static MACHINE_DRIVER_START( pcat_dyn )
|
||||
// MDRV_IMPORT_FROM( at_kbdc8042 )
|
||||
MDRV_PIC8259_ADD( "pic8259_1", pic8259_1_config )
|
||||
MDRV_PIC8259_ADD( "pic8259_2", pic8259_2_config )
|
||||
MDRV_DMA8237_ADD( "dma8237_1", dma8237_1_config )
|
||||
MDRV_DMA8237_ADD( "dma8237_2", dma8237_2_config )
|
||||
MDRV_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
|
||||
MDRV_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
|
||||
MDRV_PIT8254_ADD( "pit8254", at_pit8254_config )
|
||||
|
||||
MDRV_PALETTE_INIT(pcat_286)
|
||||
|
||||
@ -183,32 +183,31 @@ static struct {
|
||||
DMA8237 Controller
|
||||
******************/
|
||||
|
||||
static int dma_channel;
|
||||
static UINT8 dma_offset[2][4];
|
||||
static UINT8 at_pages[0x10];
|
||||
|
||||
static DMA8237_HRQ_CHANGED( pc_dma_hrq_changed )
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
|
||||
{
|
||||
cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
dma8237_set_hlda( device, state );
|
||||
i8237_hlda_w( device, state );
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_READ( pc_dma_read_byte )
|
||||
static READ8_HANDLER( pc_dma_read_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
return memory_read_byte(space, page_offset + offset);
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_WRITE( pc_dma_write_byte )
|
||||
static WRITE8_HANDLER( pc_dma_write_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
memory_write_byte(space, page_offset + offset, data);
|
||||
@ -258,31 +257,31 @@ static WRITE8_HANDLER(dma_page_select_w)
|
||||
}
|
||||
}
|
||||
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { if (state) dma_channel = 0; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { if (state) dma_channel = 1; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { if (state) dma_channel = 2; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { if (state) dma_channel = 3; }
|
||||
|
||||
static const struct dma8237_interface dma8237_1_config =
|
||||
static I8237_INTERFACE( dma8237_1_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
pc_dma_hrq_changed,
|
||||
pc_dma_read_byte,
|
||||
pc_dma_write_byte,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_LINE(pc_dma_hrq_changed),
|
||||
DEVCB_NULL,
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
|
||||
};
|
||||
|
||||
static const struct dma8237_interface dma8237_2_config =
|
||||
static I8237_INTERFACE( dma8237_2_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
|
||||
};
|
||||
|
||||
|
||||
@ -424,14 +423,14 @@ static WRITE32_HANDLER( vga_regs_w )
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( pcat_io, ADDRESS_SPACE_IO, 32 )
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", dma8237_r, dma8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", i8237_r, i8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_1", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
AM_RANGE(0x0060, 0x006f) AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
AM_RANGE(0x0070, 0x007f) AM_RAM//READWRITE(mc146818_port32le_r, mc146818_port32le_w)
|
||||
AM_RANGE(0x0080, 0x009f) AM_READWRITE8(dma_page_select_r,dma_page_select_w, 0xffffffff)//TODO
|
||||
AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8("pic8259_2", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE8("dma8237_2", dma8237_r, dma8237_w, 0xffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE8("dma8237_2", i8237_r, i8237_w, 0xffff)
|
||||
AM_RANGE(0x0278, 0x027f) AM_RAM //parallel port 2
|
||||
AM_RANGE(0x0378, 0x037f) AM_RAM //parallel port
|
||||
AM_RANGE(0x03c0, 0x03c3) AM_RAM
|
||||
@ -590,8 +589,8 @@ static MACHINE_DRIVER_START( pcat_nit )
|
||||
// MDRV_IMPORT_FROM( at_kbdc8042 )
|
||||
MDRV_PIC8259_ADD( "pic8259_1", pic8259_1_config )
|
||||
MDRV_PIC8259_ADD( "pic8259_2", pic8259_2_config )
|
||||
MDRV_DMA8237_ADD( "dma8237_1", dma8237_1_config )
|
||||
MDRV_DMA8237_ADD( "dma8237_2", dma8237_2_config )
|
||||
MDRV_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
|
||||
MDRV_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
|
||||
MDRV_PIT8254_ADD( "pit8254", at_pit8254_config )
|
||||
|
||||
MDRV_PALETTE_INIT(pcat_286)
|
||||
|
||||
@ -548,32 +548,31 @@ static WRITE8_HANDLER( drive_selection_w )
|
||||
DMA8237 Controller
|
||||
******************/
|
||||
|
||||
static int dma_channel;
|
||||
static UINT8 dma_offset[2][4];
|
||||
static UINT8 at_pages[0x10];
|
||||
|
||||
static DMA8237_HRQ_CHANGED( pc_dma_hrq_changed )
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
|
||||
{
|
||||
cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
dma8237_set_hlda( device, state );
|
||||
i8237_hlda_w( device, state );
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_READ( pc_dma_read_byte )
|
||||
static READ8_HANDLER( pc_dma_read_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
return memory_read_byte(space, page_offset + offset);
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_WRITE( pc_dma_write_byte )
|
||||
static WRITE8_HANDLER( pc_dma_write_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
memory_write_byte(space, page_offset + offset, data);
|
||||
@ -621,18 +620,20 @@ static WRITE8_HANDLER(dma_page_select_w)
|
||||
}
|
||||
}
|
||||
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { if (state) dma_channel = 0; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { if (state) dma_channel = 1; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { if (state) dma_channel = 2; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { if (state) dma_channel = 3; }
|
||||
|
||||
static const struct dma8237_interface dma8237_1_config =
|
||||
static I8237_INTERFACE( dma8237_1_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
pc_dma_hrq_changed,
|
||||
pc_dma_read_byte,
|
||||
pc_dma_write_byte,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_LINE(pc_dma_hrq_changed),
|
||||
DEVCB_NULL,
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
|
||||
};
|
||||
|
||||
/******************
|
||||
@ -677,7 +678,7 @@ ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( filetto_io, ADDRESS_SPACE_IO, 8 )
|
||||
ADDRESS_MAP_GLOBAL_MASK(0x3ff)
|
||||
AM_RANGE(0x0000, 0x000f) AM_DEVREADWRITE("dma8237_1", dma8237_r, dma8237_w ) //8237 DMA Controller
|
||||
AM_RANGE(0x0000, 0x000f) AM_DEVREADWRITE("dma8237_1", i8237_r, i8237_w ) //8237 DMA Controller
|
||||
AM_RANGE(0x0020, 0x002f) AM_DEVREADWRITE("pic8259_1", pic8259_r, pic8259_w ) //8259 Interrupt control
|
||||
AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE("pit8253", pit8253_r, pit8253_w) //8253 PIT
|
||||
AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE("ppi8255_0", ppi8255_r, ppi8255_w) //PPI 8255
|
||||
@ -706,7 +707,7 @@ ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( tetriskr_io, ADDRESS_SPACE_IO, 8 )
|
||||
ADDRESS_MAP_GLOBAL_MASK(0x3ff)
|
||||
AM_RANGE(0x0000, 0x000f) AM_DEVREADWRITE("dma8237_1", dma8237_r, dma8237_w ) //8237 DMA Controller
|
||||
AM_RANGE(0x0000, 0x000f) AM_DEVREADWRITE("dma8237_1", i8237_r, i8237_w ) //8237 DMA Controller
|
||||
AM_RANGE(0x0020, 0x002f) AM_DEVREADWRITE("pic8259_1", pic8259_r, pic8259_w ) //8259 Interrupt control
|
||||
AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE("pit8253", pit8253_r, pit8253_w) //8253 PIT
|
||||
AM_RANGE(0x0060, 0x0063) AM_DEVREADWRITE("ppi8255_0", ppi8255_r, ppi8255_w) //PPI 8255
|
||||
@ -927,7 +928,7 @@ static MACHINE_DRIVER_START( filetto )
|
||||
MDRV_PPI8255_ADD( "ppi8255_0", filetto_ppi8255_intf[0] )
|
||||
MDRV_PPI8255_ADD( "ppi8255_1", filetto_ppi8255_intf[1] )
|
||||
|
||||
MDRV_DMA8237_ADD( "dma8237_1", dma8237_1_config )
|
||||
MDRV_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
|
||||
|
||||
MDRV_PIC8259_ADD( "pic8259_1", pic8259_1_config )
|
||||
|
||||
@ -972,7 +973,7 @@ static MACHINE_DRIVER_START( tetriskr )
|
||||
MDRV_PPI8255_ADD( "ppi8255_0", filetto_ppi8255_intf[0] )
|
||||
MDRV_PPI8255_ADD( "ppi8255_1", filetto_ppi8255_intf[1] )
|
||||
|
||||
MDRV_DMA8237_ADD( "dma8237_1", dma8237_1_config )
|
||||
MDRV_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
|
||||
|
||||
MDRV_PIC8259_ADD( "pic8259_1", pic8259_1_config )
|
||||
|
||||
|
||||
@ -114,32 +114,31 @@ static struct {
|
||||
DMA8237 Controller
|
||||
******************/
|
||||
|
||||
static int dma_channel;
|
||||
static UINT8 dma_offset[2][4];
|
||||
static UINT8 at_pages[0x10];
|
||||
|
||||
static DMA8237_HRQ_CHANGED( pc_dma_hrq_changed )
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
|
||||
{
|
||||
cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
dma8237_set_hlda( device, state );
|
||||
i8237_hlda_w( device, state );
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_READ( pc_dma_read_byte )
|
||||
static READ8_HANDLER( pc_dma_read_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
return memory_read_byte(space, page_offset + offset);
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_WRITE( pc_dma_write_byte )
|
||||
static WRITE8_HANDLER( pc_dma_write_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
memory_write_byte(space, page_offset + offset, data);
|
||||
@ -189,31 +188,31 @@ static WRITE8_HANDLER(dma_page_select_w)
|
||||
}
|
||||
}
|
||||
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { if (state) dma_channel = 0; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { if (state) dma_channel = 1; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { if (state) dma_channel = 2; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { if (state) dma_channel = 3; }
|
||||
|
||||
static const struct dma8237_interface dma8237_1_config =
|
||||
static I8237_INTERFACE( dma8237_1_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
pc_dma_hrq_changed,
|
||||
pc_dma_read_byte,
|
||||
pc_dma_write_byte,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_LINE(pc_dma_hrq_changed),
|
||||
DEVCB_NULL,
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
|
||||
};
|
||||
|
||||
static const struct dma8237_interface dma8237_2_config =
|
||||
static I8237_INTERFACE( dma8237_2_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
|
||||
};
|
||||
|
||||
|
||||
@ -349,14 +348,14 @@ static WRITE32_HANDLER( vga_regs_w )
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( photoply_io, ADDRESS_SPACE_IO, 32 )
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", dma8237_r, dma8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", i8237_r, i8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_1", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
AM_RANGE(0x0060, 0x006f) AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
AM_RANGE(0x0070, 0x007f) AM_RAM//READWRITE(mc146818_port32le_r, mc146818_port32le_w)
|
||||
AM_RANGE(0x0080, 0x009f) AM_READWRITE8(dma_page_select_r,dma_page_select_w, 0xffffffff)//TODO
|
||||
AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8("pic8259_2", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE8("dma8237_2", dma8237_r, dma8237_w, 0xffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE8("dma8237_2", i8237_r, i8237_w, 0xffff)
|
||||
AM_RANGE(0x0278, 0x027f) AM_RAM //parallel port 2
|
||||
AM_RANGE(0x0378, 0x037f) AM_RAM //parallel port
|
||||
AM_RANGE(0x03c0, 0x03c3) AM_RAM
|
||||
@ -513,8 +512,8 @@ static MACHINE_DRIVER_START( photoply )
|
||||
// MDRV_IMPORT_FROM( at_kbdc8042 )
|
||||
MDRV_PIC8259_ADD( "pic8259_1", pic8259_1_config )
|
||||
MDRV_PIC8259_ADD( "pic8259_2", pic8259_2_config )
|
||||
MDRV_DMA8237_ADD( "dma8237_1", dma8237_1_config )
|
||||
MDRV_DMA8237_ADD( "dma8237_2", dma8237_2_config )
|
||||
MDRV_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
|
||||
MDRV_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
|
||||
MDRV_PIT8254_ADD( "pit8254", at_pit8254_config )
|
||||
|
||||
MDRV_PALETTE_INIT(pcat_286)
|
||||
|
||||
@ -97,12 +97,12 @@ static VIDEO_UPDATE(taitowlf)
|
||||
|
||||
static READ8_DEVICE_HANDLER(at_dma8237_2_r)
|
||||
{
|
||||
return dma8237_r(device, offset / 2);
|
||||
return i8237_r(device, offset / 2);
|
||||
}
|
||||
|
||||
static WRITE8_DEVICE_HANDLER(at_dma8237_2_w)
|
||||
{
|
||||
dma8237_w(device, offset / 2, data);
|
||||
i8237_w(device, offset / 2, data);
|
||||
}
|
||||
|
||||
static READ32_DEVICE_HANDLER(at32_dma8237_2_r)
|
||||
@ -316,6 +316,7 @@ static WRITE32_HANDLER(bios_ram_w)
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
static int dma_channel;
|
||||
static UINT8 dma_offset[2][4];
|
||||
static UINT8 at_pages[0x10];
|
||||
|
||||
@ -365,60 +366,58 @@ static WRITE8_HANDLER(at_page8_w)
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_HRQ_CHANGED( pc_dma_hrq_changed )
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
|
||||
{
|
||||
cputag_set_input_line(device->machine, "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
dma8237_set_hlda( device, state );
|
||||
i8237_hlda_w( device, state );
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_READ( pc_dma_read_byte )
|
||||
static READ8_HANDLER( pc_dma_read_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
return memory_read_byte(space, page_offset + offset);
|
||||
}
|
||||
|
||||
|
||||
static DMA8237_MEM_WRITE( pc_dma_write_byte )
|
||||
static WRITE8_HANDLER( pc_dma_write_byte )
|
||||
{
|
||||
const address_space *space = cputag_get_address_space(device->machine, "maincpu", ADDRESS_SPACE_PROGRAM);
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][channel]) << 16)
|
||||
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
memory_write_byte(space, page_offset + offset, data);
|
||||
}
|
||||
|
||||
|
||||
static const struct dma8237_interface dma8237_1_config =
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { if (state) dma_channel = 0; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { if (state) dma_channel = 1; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { if (state) dma_channel = 2; }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { if (state) dma_channel = 3; }
|
||||
|
||||
static I8237_INTERFACE( dma8237_1_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
pc_dma_hrq_changed,
|
||||
pc_dma_read_byte,
|
||||
pc_dma_write_byte,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_LINE(pc_dma_hrq_changed),
|
||||
DEVCB_NULL,
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
|
||||
};
|
||||
|
||||
|
||||
static const struct dma8237_interface dma8237_2_config =
|
||||
static I8237_INTERFACE( dma8237_2_config )
|
||||
{
|
||||
XTAL_14_31818MHz/3,
|
||||
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
{ NULL, NULL, NULL, NULL },
|
||||
NULL
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
|
||||
};
|
||||
|
||||
static READ32_HANDLER(at_page32_r)
|
||||
@ -447,7 +446,7 @@ static ADDRESS_MAP_START( taitowlf_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(taitowlf_io, ADDRESS_SPACE_IO, 32)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", dma8237_r, dma8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", i8237_r, i8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_1", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
AM_RANGE(0x0060, 0x006f) AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
@ -622,9 +621,9 @@ static MACHINE_DRIVER_START(taitowlf)
|
||||
|
||||
MDRV_PIT8254_ADD( "pit8254", taitowlf_pit8254_config )
|
||||
|
||||
MDRV_DMA8237_ADD( "dma8237_1", dma8237_1_config )
|
||||
MDRV_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
|
||||
|
||||
MDRV_DMA8237_ADD( "dma8237_2", dma8237_2_config )
|
||||
MDRV_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
|
||||
|
||||
MDRV_PIC8259_ADD( "pic8259_1", taitowlf_pic8259_1_config )
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user