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maciifx: Add preliminary PIC (Peripheral Interface Controller) devices and OSS interrupt control

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* machine/applefdintf.*: Correct permissions
This commit is contained in:
AJR 2021-07-29 23:40:16 -04:00
parent 946ad8b339
commit 918da8411d
8 changed files with 102 additions and 29 deletions
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12
scripts/src/machine.lua
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@ -824,6 +824,18 @@ if (MACHINES["AMIGAFDC"]~=null) then
}
end
---------------------------------------------------
--
--@src/devices/machine/applepic.h,MACHINES["APPLEPIC"] = true
---------------------------------------------------
if (MACHINES["APPLEPIC"]~=null) then
files {
MAME_DIR .. "src/devices/machine/applepic.cpp",
MAME_DIR .. "src/devices/machine/applepic.h",
}
end
---------------------------------------------------
--
--@src/devices/machine/at28c16.h,MACHINES["AT28C16"] = true

1
scripts/target/mame/arcade.lua
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@ -457,6 +457,7 @@ MACHINES["AM79C90"] = true
--MACHINES["AM9513"] = true
MACHINES["AM9517A"] = true
MACHINES["AMIGAFDC"] = true
--MACHINES["APPLEPIC"] = true
MACHINES["AT_KEYBC"] = true
MACHINES["AT28C16"] = true
--MACHINES["AT28C64B"] = true

1
scripts/target/mame/mess.lua
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@ -479,6 +479,7 @@ MACHINES["AM9513"] = true
MACHINES["AM9517A"] = true
MACHINES["AM9519"] = true
MACHINES["AMIGAFDC"] = true
MACHINES["APPLEPIC"] = true
MACHINES["ARM_IOMD"] = true
MACHINES["AT_KEYBC"] = true
MACHINES["AT28C16"] = true

0
src/devices/machine/applefdintf.cpp Executable file → Normal file
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0
src/devices/machine/applefdintf.h Executable file → Normal file
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99
src/mame/drivers/mac.cpp
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@ -17,6 +17,7 @@
#include "cpu/m68000/m68000.h"
#include "cpu/m6805/m6805.h"
#include "formats/ap_dsk35.h"
#include "machine/applepic.h"
#include "machine/iwm.h"
#include "machine/swim1.h"
#include "machine/swim2.h"
@ -394,6 +395,44 @@ void mac_state::biu_w(offs_t offset, uint32_t data, uint32_t mem_mask)
// printf("biu_w %x @ %x, mask %08x\n", data, offset, mem_mask);
}
template <int N> WRITE_LINE_MEMBER(mac_state::oss_interrupt)
{
if (state == ASSERT_LINE)
m_oss_regs[N >= 8 ? 0x202 : 0x203] |= 1 << (N & 7);
else
m_oss_regs[N >= 8 ? 0x202 : 0x203] &= ~(1 << (N & 7));
int take_interrupt = 0;
for (int n = 0; n < 8; n++)
{
if (BIT(m_oss_regs[0x203], n) && take_interrupt < m_oss_regs[n])
take_interrupt = m_oss_regs[n];
if (BIT(m_oss_regs[0x202], n) && take_interrupt < m_oss_regs[8 + n])
take_interrupt = m_oss_regs[8 + n];
}
if (m_last_taken_interrupt > -1)
{
m_maincpu->set_input_line(m_last_taken_interrupt, CLEAR_LINE);
m_last_taken_interrupt = -1;
m_oss_regs[0x200] &= 0x7f;
}
if (take_interrupt > 0)
{
m_maincpu->set_input_line(take_interrupt, ASSERT_LINE);
m_last_taken_interrupt = take_interrupt;
m_oss_regs[0x200] |= 0x80;
}
}
TIMER_CALLBACK_MEMBER(mac_state::oss_6015_tick)
{
m_via1->write_ca1(0);
m_via1->write_ca1(1);
oss_interrupt<10>(ASSERT_LINE);
}
uint8_t mac_state::oss_r(offs_t offset)
{
// printf("oss_r @ %x\n", offset);
@ -402,12 +441,18 @@ uint8_t mac_state::oss_r(offs_t offset)
// return m_oss_regs[offset]<<4;
// }
if (offset < std::size(m_oss_regs))
return m_oss_regs[offset];
else
return 0;
}
void mac_state::oss_w(offs_t offset, uint8_t data)
{
// printf("oss_w %x @ %x\n", data, offset);
if (offset == 0x207)
oss_interrupt<10>(CLEAR_LINE);
else if (offset < std::size(m_oss_regs))
m_oss_regs[offset] = data;
}
@ -418,28 +463,11 @@ uint32_t mac_state::buserror_r()
return 0;
}
uint8_t mac_state::scciop_r(offs_t offset)
uint8_t mac_state::maciifx_unknown_r()
{
// printf("scciop_r @ %x (PC=%x)\n", offset, m_maincpu->pc());
return 0;
}
void mac_state::scciop_w(offs_t offset, uint8_t data)
{
// printf("scciop_w %x @ %x (PC=%x)\n", data, offset, m_maincpu->pc());
}
uint8_t mac_state::swimiop_r(offs_t offset)
{
// printf("swimiop_r @ %x (PC=%x)\n", offset, m_maincpu->pc());
return 0;
}
void mac_state::swimiop_w(offs_t offset, uint8_t data)
{
// printf("swimiop_w %x @ %x (PC=%x)\n", data, offset, m_maincpu->pc());
}
/***************************************************************************
ADDRESS MAPS
***************************************************************************/
@ -539,13 +567,16 @@ void mac_state::maciifx_map(address_map &map)
map(0x40000000, 0x4007ffff).rom().region("bootrom", 0).mirror(0x0ff80000);
map(0x50000000, 0x50001fff).rw(FUNC(mac_state::mac_via_r), FUNC(mac_state::mac_via_w)).mirror(0x00f00000);
map(0x50004000, 0x50005fff).rw(FUNC(mac_state::scciop_r), FUNC(mac_state::scciop_w)).mirror(0x00f00000);
map(0x50004000, 0x50005fff).rw("sccpic", FUNC(applepic_device::host_r), FUNC(applepic_device::host_w)).mirror(0x00f00000).umask32(0xff00ff00);
map(0x50004000, 0x50005fff).rw("sccpic", FUNC(applepic_device::host_r), FUNC(applepic_device::host_w)).mirror(0x00f00000).umask32(0x00ff00ff);
map(0x50008040, 0x50008040).r(FUNC(mac_state::maciifx_unknown_r)).mirror(0x00f00000);
map(0x5000a000, 0x5000bfff).rw(FUNC(mac_state::macplus_scsi_r), FUNC(mac_state::macii_scsi_w)).mirror(0x00f00000);
map(0x5000c060, 0x5000c063).r(FUNC(mac_state::macii_scsi_drq_r)).mirror(0x00f00000);
map(0x5000d000, 0x5000d003).w(FUNC(mac_state::macii_scsi_drq_w)).mirror(0x00f00000);
map(0x5000d060, 0x5000d063).r(FUNC(mac_state::macii_scsi_drq_r)).mirror(0x00f00000);
map(0x50010000, 0x50011fff).rw(m_asc, FUNC(asc_device::read), FUNC(asc_device::write)).mirror(0x00f00000);
map(0x50012000, 0x50013fff).rw(FUNC(mac_state::swimiop_r), FUNC(mac_state::swimiop_w)).mirror(0x00f00000);
map(0x50012000, 0x50013fff).rw("swimpic", FUNC(applepic_device::host_r), FUNC(applepic_device::host_w)).mirror(0x00f00000).umask32(0xff00ff00);
map(0x50012000, 0x50013fff).rw("swimpic", FUNC(applepic_device::host_r), FUNC(applepic_device::host_w)).mirror(0x00f00000).umask32(0x00ff00ff);
map(0x50018000, 0x50019fff).rw(FUNC(mac_state::biu_r), FUNC(mac_state::biu_w)).mirror(0x00f00000);
map(0x5001a000, 0x5001bfff).rw(FUNC(mac_state::oss_r), FUNC(mac_state::oss_w)).mirror(0x00f00000);
map(0x50024000, 0x50027fff).r(FUNC(mac_state::buserror_r)).mirror(0x00f00000); // must bus error on access here so ROM can determine we're an FMC
@ -824,13 +855,32 @@ void mac_state::maciifx(machine_config &config)
add_base_devices(config, true, 1);
add_scsi(config);
m_asc->irqf_callback().set(FUNC(mac_state::oss_interrupt<8>));
subdevice<nscsi_connector>("scsi:7")->set_option_machine_config("ncr5380", [this](device_t *device) {
ncr53c80_device &adapter = downcast<ncr53c80_device &>(*device);
adapter.irq_handler().set(*this, FUNC(mac_state::oss_interrupt<9>));
adapter.drq_handler().set(m_scsihelp, FUNC(mac_scsi_helper_device::drq_w));
});
R65NC22(config, m_via1, C7M/10);
m_via1->readpa_handler().set(FUNC(mac_state::mac_via_in_a));
m_via1->readpb_handler().set(FUNC(mac_state::mac_via_in_b_ii));
m_via1->writepa_handler().set(FUNC(mac_state::mac_via_out_a));
m_via1->writepb_handler().set(FUNC(mac_state::mac_via_out_b));
m_via1->cb2_handler().set(FUNC(mac_state::mac_adb_via_out_cb2));
m_via1->irq_handler().set(FUNC(mac_state::mac_via_irq));
m_via1->irq_handler().set(FUNC(mac_state::oss_interrupt<11>));
applepic_device &sccpic(APPLEPIC(config, "sccpic", C15M));
sccpic.prd_callback().set(m_scc, FUNC(scc8530_legacy_device::reg_r));
sccpic.pwr_callback().set(m_scc, FUNC(scc8530_legacy_device::reg_w));
sccpic.hint_callback().set(FUNC(mac_state::oss_interrupt<7>));
m_scc->intrq_callback().set("sccpic", FUNC(applepic_device::pint_w));
applepic_device &swimpic(APPLEPIC(config, "swimpic", C15M));
swimpic.prd_callback().set(m_fdc, FUNC(applefdintf_device::read));
swimpic.pwr_callback().set(m_fdc, FUNC(applefdintf_device::write));
swimpic.hint_callback().set(FUNC(mac_state::oss_interrupt<6>));
RAM(config, m_ram);
m_ram->set_default_size("4M");
@ -839,6 +889,13 @@ void mac_state::maciifx(machine_config &config)
SOFTWARE_LIST(config, "flop35_list").set_original("mac_flop");
add_nubus(config);
nubus_device &nubus(*subdevice<nubus_device>("nubus"));
nubus.out_irq9_callback().set(FUNC(mac_state::oss_interrupt<0>));
nubus.out_irqa_callback().set(FUNC(mac_state::oss_interrupt<1>));
nubus.out_irqb_callback().set(FUNC(mac_state::oss_interrupt<2>));
nubus.out_irqc_callback().set(FUNC(mac_state::oss_interrupt<3>));
nubus.out_irqd_callback().set(FUNC(mac_state::oss_interrupt<4>));
nubus.out_irqe_callback().set(FUNC(mac_state::oss_interrupt<5>));
}
void mac_state::maclc(machine_config &config, bool cpu, bool egret, asc_device::asc_type asc_type, int woz_version)

7
src/mame/includes/mac.h
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@ -306,13 +306,12 @@ private:
uint32_t biu_r(offs_t offset, uint32_t mem_mask = ~0);
void biu_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
template <int N> DECLARE_WRITE_LINE_MEMBER(oss_interrupt);
TIMER_CALLBACK_MEMBER(oss_6015_tick);
uint8_t oss_r(offs_t offset);
void oss_w(offs_t offset, uint8_t data);
uint32_t buserror_r();
uint8_t swimiop_r(offs_t offset);
void swimiop_w(offs_t offset, uint8_t data);
uint8_t scciop_r(offs_t offset);
void scciop_w(offs_t offset, uint8_t data);
uint8_t maciifx_unknown_r();
DECLARE_WRITE_LINE_MEMBER(nubus_irq_9_w);
DECLARE_WRITE_LINE_MEMBER(nubus_irq_a_w);

5
src/mame/machine/mac.cpp
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@ -1029,7 +1029,10 @@ void mac_state::machine_start()
m_adbupdate_timer->adjust(attotime::from_hz(70));
}
if (m_model != MODEL_MAC_IIFX)
m_6015_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mac_state::mac_6015_tick),this));
else
m_6015_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mac_state::oss_6015_tick),this));
m_6015_timer->adjust(attotime::never);
}
@ -1046,7 +1049,7 @@ void mac_state::machine_reset()
m_rbv_vbltime = 0;
// start 60.15 Hz timer for most systems
if (((m_model >= MODEL_MAC_IICI) && (m_model <= MODEL_MAC_IIVI)) || (m_model >= MODEL_MAC_LC))
if (((m_model >= MODEL_MAC_IICI) && (m_model <= MODEL_MAC_IIFX)) || (m_model >= MODEL_MAC_LC))
{
m_6015_timer->adjust(attotime::from_hz(60.15), 0, attotime::from_hz(60.15));
}