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Fixed Cause register for bad COP instructions. Verified with
mtetrisc and starsldr that they both throw and handle these exceptions.
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parent
c1a1cab523
commit
91f55454e4
@ -1454,6 +1454,13 @@ static void static_generate_exception(drcuml_state *drcuml, UINT8 exception, int
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UML_MOVc(block, IF_Z, CPR032(COP0_EPC), IREG(0)); // mov [EPC],i0,Z
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UML_OR(block, CPR032(COP0_Cause), IREG(2), IMM(exception << 2)); // or [Cause],i2,exception << 2
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/* for BADCOP exceptions, we use the exception parameter to know which COP */
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if (exception == EXCEPTION_BADCOP)
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{
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UML_GETEXP(block, IREG(0)); // getexp i0
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UML_INSERT(block, CPR032(COP0_Cause), IREG(0), IMM(28), IMM(0x30000000)); // insert [Cause],i0,28,0x30000000
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}
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/* set EXL in the SR */
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UML_OR(block, IREG(0), CPR032(COP0_Status), IMM(SR_EXL)); // or i0,[Status],SR_EXL
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UML_MOV(block, CPR032(COP0_Status), IREG(0)); // mov [Status],i0
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@ -3240,7 +3247,7 @@ static int generate_cop1(drcuml_block *block, compiler_state *compiler, const op
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if (mips3->impstate->drcoptions & MIPS3DRC_STRICT_COP1)
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{
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UML_TEST(block, CPR032(COP0_Status), IMM(SR_COP1)); // test [Status],SR_COP1
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UML_EXHc(block, IF_Z, mips3->impstate->exception[EXCEPTION_BADCOP], IMM(0));// exh cop,0,Z
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UML_EXHc(block, IF_Z, mips3->impstate->exception[EXCEPTION_BADCOP], IMM(1));// exh cop,1,Z
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}
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switch (RSREG)
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@ -3595,7 +3602,7 @@ static int generate_cop1x(drcuml_block *block, compiler_state *compiler, const o
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if (mips3->impstate->drcoptions & MIPS3DRC_STRICT_COP1)
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{
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UML_TEST(block, CPR032(COP0_Status), IMM(SR_COP1)); // test [Status],SR_COP1
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UML_EXHc(block, IF_Z, mips3->impstate->exception[EXCEPTION_BADCOP], IMM(0));// exh cop,0,Z
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UML_EXHc(block, IF_Z, mips3->impstate->exception[EXCEPTION_BADCOP], IMM(1));// exh cop,1,Z
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}
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switch (op & 0x3f)
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