mirror of
https://github.com/holub/mame
synced 2025-04-25 17:56:43 +03:00
dbox: New driver NOT_WORKING, Nokia Dbox 1 satellite digital receiver
This commit is contained in:
Joakim Larsson Edstrom
parent
a6e7aa977c
commit
925b244ced
@ -2434,6 +2434,7 @@ files {
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createMESSProjects(_target, _subtarget, "nokia")
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files {
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MAME_DIR .. "src/mame/drivers/dbox.cpp",
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MAME_DIR .. "src/mame/drivers/mikromik.cpp",
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MAME_DIR .. "src/mame/includes/mikromik.h",
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MAME_DIR .. "src/mame/machine/mm1kb.cpp",
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453
src/devices/video/sda5708.cpp
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453
src/devices/video/sda5708.cpp
Normal file
@ -0,0 +1,453 @@
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// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edstrom
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/**********************************************************************
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Siemens SDA5708 8 character 7x5 dot matrix LED display
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**********************************************************************/
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#include "sda5708.h"
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/* Misc info
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* ---------
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* http://www.sbprojects.com/knowledge/footprints/sda5708/index.php
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* http://arduinotehniq.blogspot.se/2015/07/sda5708-display-8-character-7x5-dot.html
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*
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* Display front - LEDs
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* --------------------
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* xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx
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* xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx
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* xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx
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* xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx
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* xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx
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* xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx
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* xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx
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* Dig0 Dig1 Dig2 Dig3 Dig4 Dig5 Dig6 Dig7
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*
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* Display rear - Pinout
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* ---------------------
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* +--------------------------------------------------------+
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* | O O |
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* | +----------------------------------------------+ |
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* | | o o o o o o | |
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* | | Pin:6 5 4 3 2 1 | |
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* | | | |
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* | +----------------------------------------------+ |
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* +--------------------------------------------------------+
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* 6:GND 5:_RESET 4:SDCLK 3:Data 2:_Load 1:Vcc
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*
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*/
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//**************************************************************************
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// MACROS / CONSTANTS
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//**************************************************************************
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#define LOG 0
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#define SDA5708_REG_MASK 0xE0
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#define SDA5708_CNTR_COMMAND 0xE0
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#define SDA5708_CNTR_BRIGHT_MASK 0x1F
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#define SDA5708_CNTR_BRIGHT_100 0x00
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#define SDA5708_CNTR_BRIGHT_53 0x01
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#define SDA5708_CNTR_BRIGHT_40 0x02
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#define SDA5708_CNTR_BRIGHT_27 0x03
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#define SDA5708_CNTR_BRIGHT_20 0x04
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#define SDA5708_CNTR_BRIGHT_13 0x05
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#define SDA5708_CNTR_BRIGHT_6_6 0x06
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#define SDA5708_CNTR_BRIGHT_0 0x07
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#define SDA5708_CNTR_PKCUR_12_5 0x08
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#define SDA5708_CLEAR_COMMAND 0xC0
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#define SDA5708_ADDR_COMMAND 0xA0
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#define SDA5708_ADDR_LED_MASK 0x07
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#define SDA5708_ADDR_LED0 0x00
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#define SDA5708_ADDR_LED1 0x01
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#define SDA5708_ADDR_LED2 0x02
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#define SDA5708_ADDR_LED3 0x03
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#define SDA5708_ADDR_LED4 0x04
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#define SDA5708_ADDR_LED5 0x05
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#define SDA5708_ADDR_LED6 0x06
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#define SDA5708_ADDR_LED7 0x07
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#define SDA5708_DATA_COMMAND 0x00
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//**************************************************************************
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// DEVICE DEFINITIONS
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//**************************************************************************
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// device type definition
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const device_type SDA5708 = &device_creator<sda5708_device>;
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#if 0
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// I/O map
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DEVICE_ADDRESS_MAP_START( map, 8, sda5708_device )
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AM_RANGE(0x00, 0x00) AM_READWRITE(dr_r, dr_w)
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AM_RANGE(0x01, 0x01) AM_READWRITE(ir_r, ir_w)
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ADDRESS_MAP_END
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// default address map
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static ADDRESS_MAP_START( sda5708, AS_0, 8, sda5708_device )
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AM_RANGE(0x00000, 0xfffff) AM_RAM
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ADDRESS_MAP_END
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#endif
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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//-------------------------------------------------
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// sda5708_device - constructor
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//-------------------------------------------------
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sda5708_device::sda5708_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, SDA5708, "SDA5708", tag, owner, clock, "sda5708", __FILE__),
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device_memory_interface(mconfig, *this),
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device_video_interface(mconfig, *this),
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m_space_config("videoram", ENDIANNESS_LITTLE, 8, 20, 0, NULL, *ADDRESS_MAP_NAME(sda5708)),
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m_cursor(0)
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void sda5708_device::device_start()
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{
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// register for state saving
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save_item(NAME(m_frame));
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void sda5708_device::device_reset()
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{
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m_frame = 0;
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}
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//-------------------------------------------------
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// memory_space_config - return a description of
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// any address spaces owned by this device
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//-------------------------------------------------
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const address_space_config *sda5708_device::memory_space_config(address_spacenum spacenum) const
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{
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return (spacenum == AS_0) ? &m_space_config : NULL;
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}
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//-------------------------------------------------
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// ir_r -
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//-------------------------------------------------
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READ8_MEMBER( sda5708_device::ir_r )
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{
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return m_ir;
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}
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//-------------------------------------------------
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// ir_w -
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//-------------------------------------------------
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WRITE8_MEMBER( sda5708_device::ir_w )
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{
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m_ir = data & 0x0f;
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}
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//-------------------------------------------------
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// dr_r -
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//-------------------------------------------------
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READ8_MEMBER( sda5708_device::dr_r )
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{
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UINT8 data = 0;
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switch (m_ir)
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{
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case REGISTER_MOR:
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break; // write-only
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case REGISTER_PR:
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data = m_pr;
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break;
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case REGISTER_HNR:
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data = m_hnr;
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break;
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case REGISTER_DVR:
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break; // write-only
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case REGISTER_CPR:
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data = m_cpr;
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break;
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case REGISTER_SLR:
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data = m_slr;
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break;
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case REGISTER_SUR:
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data = m_sur;
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break;
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case REGISTER_CLR:
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data = m_clr;
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break;
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case REGISTER_CUR:
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data = m_cur;
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break;
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}
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return data;
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}
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//-------------------------------------------------
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// dr_w -
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//-------------------------------------------------
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WRITE8_MEMBER( sda5708_device::dr_w )
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{
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switch (m_ir)
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{
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case REGISTER_MOR:
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m_mor = data & 0x7f;
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break;
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case REGISTER_PR:
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m_pr = data & 0xf7;
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break;
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case REGISTER_HNR:
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m_hnr = data & 0x7f;
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break;
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case REGISTER_DVR:
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m_dvr = data;
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break;
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case REGISTER_CPR:
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m_cpr = data;
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break;
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case REGISTER_SLR:
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m_slr = data;
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break;
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case REGISTER_SUR:
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m_sur = data;
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break;
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case REGISTER_CLR:
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m_clr = data;
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break;
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case REGISTER_CUR:
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m_cur = data;
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break;
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}
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}
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//-------------------------------------------------
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// read_byte -
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//-------------------------------------------------
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UINT8 sda5708_device::read_byte(UINT16 ma, UINT8 ra)
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{
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offs_t offset;
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if (m_mor & MOR_GRAPHICS)
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{
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offset = ma;
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}
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else
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{
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offset = ((offs_t)ma << 4) | ra;
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}
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return space().read_byte(offset);
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}
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//-------------------------------------------------
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// update_cursor -
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//-------------------------------------------------
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void sda5708_device::update_cursor()
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{
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if (m_mor & MOR_CURSOR_ON)
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{
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if (m_mor & MOR_CURSOR_BLINK)
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{
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if (m_mor & MOR_BLINK_TIME_16)
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{
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if (m_frame == 16)
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{
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m_cursor = !m_cursor;
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m_frame = 0;
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}
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else
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{
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m_frame++;
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}
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}
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else
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{
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if (m_frame == 32)
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{
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m_cursor = !m_cursor;
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m_frame = 0;
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}
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else
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{
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m_frame++;
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}
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}
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}
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else
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{
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m_cursor = 1;
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}
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}
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else
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{
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m_cursor = 0;
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}
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}
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//-------------------------------------------------
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// draw_scanline -
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//-------------------------------------------------
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void sda5708_device::draw_scanline(bitmap_ind16 &bitmap, const rectangle &cliprect, int y, UINT16 ma, UINT8 ra)
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{
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UINT8 hp = (m_pr & PR_HP_MASK) + 1;
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UINT8 hn = (m_hnr & HNR_HN_MASK) + 1;
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UINT8 cpu = m_cpr & CPR_CPU_MASK;
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UINT8 cpd = m_cpr & CPR_CPD_MASK;
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UINT16 car = (m_cur << 8) | m_clr;
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int sx, x;
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for (sx = 0; sx < hn; sx++)
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{
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UINT8 data = read_byte(ma, ra);
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if (m_cursor)
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{
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if (ma == car)
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{
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if (ra >= cpu && ra <= cpd)
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{
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data ^= 0xff;
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}
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}
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}
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for (x = 0; x < hp; x++)
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{
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bitmap.pix16(y, (sx * hp) + x) = BIT(data, 7);
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data <<= 1;
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}
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ma++;
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}
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}
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//-------------------------------------------------
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// update_graphics -
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//-------------------------------------------------
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void sda5708_device::update_graphics(bitmap_ind16 &bitmap, const rectangle &cliprect)
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{
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UINT8 hn = (m_hnr & HNR_HN_MASK) + 1;
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UINT8 nx = (m_dvr & DVR_DN_MASK) + 1;
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UINT16 sar = (m_sur << 8) | m_slr;
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int y;
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m_cursor = 0;
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m_frame = 0;
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for (y = 0; y < nx; y++)
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{
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// draw upper half scanline
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UINT16 ma = sar + (y * hn);
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draw_scanline(bitmap, cliprect, y, ma);
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// draw lower half scanline
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ma = sar + ((y + nx) * hn);
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draw_scanline(bitmap, cliprect, y + nx, ma);
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}
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}
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//-------------------------------------------------
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// update_text -
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//-------------------------------------------------
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void sda5708_device::update_text(bitmap_ind16 &bitmap, const rectangle &cliprect)
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{
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UINT8 hn = (m_hnr & HNR_HN_MASK) + 1;
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UINT8 vp = (m_pr & PR_VP_MASK) + 1;
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UINT8 nx = (m_dvr & DVR_DN_MASK) + 1;
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UINT16 sar = (m_sur << 8) | m_slr;
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int sy, y;
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update_cursor();
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for (sy = 0; sy < nx; sy++)
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{
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for (y = 0; y < vp; y++)
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{
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// draw upper half scanline
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UINT16 ma = sar + ((sy * vp) + y) * hn;
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draw_scanline(bitmap, cliprect, (sy * vp) + y, ma, y);
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// draw lower half scanline
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ma = sar + (((sy + nx) * vp) + y) * hn;
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draw_scanline(bitmap, cliprect, (sy * vp) + y, ma, y);
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}
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}
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}
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//-------------------------------------------------
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// update_screen - update screen
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//-------------------------------------------------
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UINT32 sda5708_device::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
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{
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if (m_mor & MOR_DISPLAY_ON)
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{
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if (m_mor & MOR_GRAPHICS)
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{
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update_graphics(bitmap, cliprect);
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}
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else
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{
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update_text(bitmap, cliprect);
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}
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}
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else
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{
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bitmap.fill(0, cliprect);
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}
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return 0;
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}
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67
src/devices/video/sda5708.h
Normal file
67
src/devices/video/sda5708.h
Normal file
@ -0,0 +1,67 @@
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// license:BSD-3-Clause
|
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// copyright-holders:Joakim Larsson Edstrom
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/**********************************************************************
|
||||
|
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Siemens SDA5708 8 character 7x5 dot matrix LED display
|
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|
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**********************************************************************/
|
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|
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#pragma once
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#ifndef __SDA5708__
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#define __SDA5708__
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#include "emu.h"
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///*************************************************************************
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// TYPE DEFINITIONS
|
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///*************************************************************************
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// ======================> sda5708_device
|
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class sda5708_device : public device_t,
|
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public device_memory_interface,
|
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public device_video_interface
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{
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public:
|
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// construction/destruction
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sda5708_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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virtual DECLARE_ADDRESS_MAP(map, 8);
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DECLARE_READ8_MEMBER( ir_r );
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DECLARE_WRITE8_MEMBER( ir_w );
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DECLARE_READ8_MEMBER( dr_r );
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DECLARE_WRITE8_MEMBER( dr_w );
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|
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UINT32 screen_update(screen_device &device, bitmap_ind16 &bitmap, const rectangle &cliprect);
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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// device_memory_interface overrides
|
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
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|
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private:
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void update_cursor();
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void draw_scanline(bitmap_ind16 &bitmap, const rectangle &cliprect, int y, UINT16 ma, UINT8 ra = 0);
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void update_graphics(bitmap_ind16 &bitmap, const rectangle &cliprect);
|
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void update_text(bitmap_ind16 &bitmap, const rectangle &cliprect);
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const address_space_config m_space_config;
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int m_frame; // frame counter
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};
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|
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|
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// device type definition
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||||
extern const device_type SDA5708;
|
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|
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|
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|
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#endif
|
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347
src/mame/drivers/dbox.cpp
Normal file
347
src/mame/drivers/dbox.cpp
Normal file
@ -0,0 +1,347 @@
|
||||
/*
|
||||
* The Dbox-1 CPU board.
|
||||
*__________________________________________________________________________________________________________
|
||||
* |
|
||||
* |
|
||||
* _______________ |
|
||||
* ___ | | ________ ________ |
|
||||
* | | |_______________| | | | | |
|
||||
* | | | FLASH | | FLASH | |
|
||||
* | | | 29F800 | | 29F800 | |
|
||||
* | | | | | | |
|
||||
* | | ____________ | 1Mb | | 1Mb | |
|
||||
* | | | | | | | | |
|
||||
* |___| | CPU32 | | | | | |
|
||||
* | 68340PV16E | |________| |________| |
|
||||
* | | |
|
||||
* | | |
|
||||
* _______________ |____________| _____ |
|
||||
* | | | | |
|
||||
* | SCSI | |_____| _____ _____ |
|
||||
* | CONTROLLER | +-+ _____ | | | | |
|
||||
* | LSI 53CF54-2 | |X| | | |DRAM | |DRAM | |
|
||||
* | | |T| |_____| |42460| |42460| |
|
||||
* | | |A| | | | | |
|
||||
* | | |L| ---------------- |512Kb| |512Kb| |
|
||||
* |_______________| +-+ | | | | | | |
|
||||
* 3.6864 ---------------- |_____| |_____| |
|
||||
* |
|
||||
*__________________________________________________________________________________________________________|
|
||||
*
|
||||
* History of Nokia Multimedia Division
|
||||
*-------------------------------------
|
||||
* Luxor AB was a swedish home electronics and computer manufacturer located in Motala from 1923 and aquired
|
||||
* by Nokia 1985. Luxor designed among other things TV setsm Radios and the famous ABC-80. The Nokia Multimedia
|
||||
* Division was formed in Linköping as a result of the Luxor aquesition. Their main design was a satellite
|
||||
* receiver, the first satellite in Europee was launched in 1988 and market was growing fast however it took
|
||||
* a long time, almost 10 years before the breakthrough came for Nokia, a deal with the Kirsch Gruppe was struck and
|
||||
* in 1996 the 68340 based Dbox-1 was released in Germany. The original design was expensive, so soon a cost reduced
|
||||
* version based on PPC, the Dbox-2, was released. The boxes sold in millions but the margins were negative or very
|
||||
* low at best and the Kirsch Gruppe went bankrupt in 2002 and Nokia decided to shutdown the facility in Linköping.
|
||||
*
|
||||
* The heavily subsidiced Dbox was very popular in Holland since Kirsch Gruppe didn't lock use to themselfs. This was
|
||||
* corrected in a forced firmware upgrade leaving the "customers" in Holland without a working box. Pretty soon a
|
||||
* shareware software developed by Uli Hermann appeared called DVB98 and later DVB2000 reenabling the boxes in Holland
|
||||
* and blocking upgrades. Uli's software was by many considered better than the original software.
|
||||
*
|
||||
* Misc links about Nokia Multimedia Division and this board:
|
||||
* http://www.siliconinvestor.com/readmsg.aspx?msgid=5097482
|
||||
* http://www.telecompaper.com/news/beta-research-publishes-dbox-specifications--163443
|
||||
* https://de.wikipedia.org/wiki/D-box
|
||||
* http://dvb2000.org/dvb2000/
|
||||
*
|
||||
* Misc findings
|
||||
*--------------
|
||||
* - Serial port on the back runs at 19200 at issues modem commands when attached to terminal
|
||||
* - It is possible to attach a BDM emulator and retrieve the ROM through it.
|
||||
* - It is possible to flash new firmware by adding jumper XP06 (under the modem board)
|
||||
* - The bootstrap is based on RTXC 3.2g RTOS
|
||||
* - The bootstrap jumps to firmware from 0xb82 to RAM at 0x800000
|
||||
*
|
||||
* Identified chips/devices
|
||||
*-----------------
|
||||
* Motorola 68340 CPU
|
||||
* Philips SAA7124 Digital Video Encoder
|
||||
* LSI 53CF54-2 SCSI controller
|
||||
* Crystal CL4922-CL Mpeg Audio Decoder System
|
||||
* Rockwell R6653-16 Single Device Data/Fax Modem Data Pump
|
||||
* Philips 8020401TM100 <modem related, unknown purpose>
|
||||
* C-cube CL9100 MPEG2 decoder
|
||||
* Lucent AV6220A MPEG2 demultiplexer w. crypto interface
|
||||
* CI Common Interface module
|
||||
* LSI L2A0371 Tuner
|
||||
* 2 x 29F800-90 (2Mb FLASH)
|
||||
* 2 x 42260-60 (1Mb DRAM)
|
||||
* Siemens SDA5708 dot matrix display, SPI like connection
|
||||
* - http://arduinotehniq.blogspot.se/2015/07/sda5708-display-8-character-7x5-dot.html
|
||||
* - charset stored at 0x808404 to 0x808780, 7 bytes per character
|
||||
*
|
||||
*
|
||||
* Address Map
|
||||
* --------------------------------------------------------------------------
|
||||
* Address Range Memory Space (physical) Notes
|
||||
* --------------------------------------------------------------------------
|
||||
* 0xffffffff (top of memory)
|
||||
* 0x00FFF780-0x00FFF7BF DMA offset to SIM40
|
||||
* 0x00FFF700-0x00FFF721 Serial devices offset to SIM40
|
||||
* 0x00FFF600-0x00FFF67F Timers offset to SIM40
|
||||
* 0x00FFF000-0x00FFF07F SIM40 programmed base adress (MCR)
|
||||
* 0x00700000-0x008fffff RAM
|
||||
* 0x00000000-0x0001ffff bootstrap
|
||||
* --------------------------------------------------------------------------
|
||||
*
|
||||
* Init sequence
|
||||
* -------------
|
||||
* MCR : 0x6301 Timer/wd disabled, show cycles, ext arbit,
|
||||
* user access to SIM40, IARB = 1
|
||||
* MBAR : 0x00FFF101 SIM40 base = 0x00fff000
|
||||
* VBR : 0x008096F8 VBR - Vector Base Register
|
||||
* SIM40 + 0x0006: 0xE8 AVR - Auto Vector Register
|
||||
* SIM40 + 0x0021: 0x0C SWIV_SYPCR
|
||||
* SIM40 + 0x001F: 0x00 PPARB - Port B pin assignment
|
||||
* SIM40 + 0x0011: 0xFF PORTA - Port A Data
|
||||
* SIM40 + 0x0013: 0x16 DDRA - Port A Data direction
|
||||
* SIM40 + 0x0700: 0x00 Serial port
|
||||
* SIM40 + 0x071F: 0xFF Serial port
|
||||
* SIM40 + 0x0004: 0x7F03 SYNCR
|
||||
* SIM40 + 0x0040: 0x003FFFF5 CS0 mask 1
|
||||
* SIM40 + 0x0044: 0x00000003 CS0 base 1
|
||||
* SIM40 + 0x0048: 0x003FFFF5 CS1 mask 1
|
||||
* SIM40 + 0x004C: 0x00800003 CS1 base 1
|
||||
* SIM40 + 0x0050: 0x00007FFF CS2 mask 1
|
||||
* SIM40 + 0x0054: 0x00700003 CS2 base 1
|
||||
* SIM40 + 0x0058: 0x000007F2 CS3 mask 1
|
||||
* SIM40 + 0x005C: 0x00700003 CS3 base 1
|
||||
* SIM40 + 0x001F: 0x40 PBARB Port B Pin Assignment
|
||||
*
|
||||
* -------------------------------------------------------------
|
||||
* The bootstrap copies the firmware to RAM and jumps to it
|
||||
* -------------------------------------------------------------
|
||||
*
|
||||
* --- PC > 0x700000 so probably init of the RTXC tick timer setup?!
|
||||
* SIM40 + 0x0022: 0x0140 PICR Periodic Interrupt Control Register
|
||||
* SIM40 + 0x0024: 0x0029 PICR Periodic Interrupt Timer Register
|
||||
*
|
||||
* Serial port setup
|
||||
* ------------------
|
||||
* --- PC < 0x1FFFF so bootstrap code
|
||||
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
|
||||
* - The serial module is enabled
|
||||
* - ignore FREEZE
|
||||
* - The crystal clock is the clear-to-send input capture clock for both channels
|
||||
* SIM40 + 0x071F: 0xFF Serial Module - OUTPUT PORT (OP)4 BIT RESET - all cleared
|
||||
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
|
||||
* - The serial module is enabled
|
||||
* - ignore FREEZE
|
||||
* - The crystal clock is the clear-to-send input capture clock for both channels
|
||||
* SIM40 + 0x0701: 0x8A Serial Module - MCR Low Byte
|
||||
* - The serial control regosters are only accessable from supervisor mode
|
||||
* - IARB = 0x0A - serial module has priority level 10d
|
||||
* SIM40 + 0x0704: 0x01 Serial Module - ILR Interrupt Level
|
||||
* SIM40 + 0x0705: 0x44 Serial Module - IVR Interrupt Vector
|
||||
* SIM40 + 0x0714: 0x80 Serial Module - ACR Auxiliary Control
|
||||
* - Set 2 of the available baud rates is selected.
|
||||
* - CTS state change has no effect
|
||||
* --- setup Channel A
|
||||
* SIM40 + 0x0712: 0x20 Serial Module - CRA Command Register A
|
||||
* - Reset the receiver
|
||||
* SIM40 + 0x0712: 0x30 Serial Module - CRA Command Register A
|
||||
* - Reset the transmitter
|
||||
* SIM40 + 0x0710: 0x93 Serial Module - MR1A Mode Register 1A
|
||||
* - Upon receipt of a valid start bit, RTS≈ is negated if the channel's FIFO is full.
|
||||
* RTS≈ is reasserted when the FIFO has an empty position available.
|
||||
* - No Parity
|
||||
* - Eight bits
|
||||
* SIM40 + 0x0720: 0x07 Serial Module - MR2A Mode Register 2A
|
||||
* - No CTS or RTS controll
|
||||
* - 1 STOP bit
|
||||
* SIM40 + 0x0711: 0xCC Serial Module - CSRA Clock Select Register A
|
||||
* - 19200 baud TXc
|
||||
* - 19200 baud Rxc
|
||||
* SIM40 + 0x0712: 0x41 Serial Module - CRA Command Register A
|
||||
* - Reset Error status
|
||||
* - Enable Receiver
|
||||
* - Check for charcters in channel A
|
||||
* SIM40 + 0x0711: btst #0 Serial Module - SRA Status Register A
|
||||
* --- if there is
|
||||
* store all characters in buffer at (A6) 0x88FFD0
|
||||
* --- setup Channel B (See details as for channel A above)
|
||||
* SIM40 + 0x071A: 0x20 Serial Module - CRB Command Register B
|
||||
* SIM40 + 0x071A: 0x30 Serial Module - CRB Command Register B
|
||||
* SIM40 + 0x0718: 0x93 Serial Module - MR1B Mode Register 1B
|
||||
* SIM40 + 0x0721: 0x07 Serial Module - MR2B Mode Register 2B
|
||||
* SIM40 + 0x0719: 0xCC Serial Module - CSRB Clock Select Register B
|
||||
* SIM40 + 0x071A: 0x41 Serial Module - CRB Command Register B
|
||||
* - Check for characters in channel B
|
||||
* SIM40 + 0x0719: btst #0 Serial Module - SRB Status Register B
|
||||
* --- if there is
|
||||
* store all characters in buffer at (A6) 0x88FFD0
|
||||
* ---
|
||||
* - Check bit 0 set on Input Port
|
||||
* SIM40 + 0x071D: btst #0 Input Port - IP
|
||||
* --- if bit 0 is set
|
||||
* 0x00801208: 0x80
|
||||
* SIM40 + 0x071A: 0x81 Serial Module - CRB Command Register B
|
||||
* ---
|
||||
* SIM40 + 0x0720: 0x41 Serial Module - MR2A Mode register 2A
|
||||
* SIM40 + 0x071D: 0x03 OPCR Output Port Control Register
|
||||
* SIM40 + 0x0715: 0x03 IER Interrupt Enable Register
|
||||
*
|
||||
* Timer setup
|
||||
* ------------
|
||||
* SIM40 + 0x0640: 0x03 MCR Timer 2
|
||||
* tbc...
|
||||
*
|
||||
* -------------------------------------------------------------
|
||||
* The bootstrap copies the firmware to RAM and jumps to it
|
||||
* -------------------------------------------------------------
|
||||
*
|
||||
* --- PC > 0x700000 so probably init of the RTXC tick timer setup?!
|
||||
* SIM40 + 0x0022: 0x0140 PICR Periodic Interrupt Control Register
|
||||
* SIM40 + 0x0024: 0x0029 PICR Periodic Interrupt Timer Register
|
||||
*
|
||||
* Serial port setup
|
||||
* ------------------
|
||||
* --- PC < 0x1FFFF so bootstrap code
|
||||
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
|
||||
* - The serial module is enabled
|
||||
* - ignore FREEZE
|
||||
* - The crystal clock is the clear-to-send input capture clock for both channels
|
||||
* SIM40 + 0x071F: 0xFF Serial Module - OUTPUT PORT (OP)4 BIT RESET - all cleared
|
||||
* SIM40 + 0x0700: 0x00 Serial Module - MCR High Byte
|
||||
* - The serial module is enabled
|
||||
* - ignore FREEZE
|
||||
* - The crystal clock is the clear-to-send input capture clock for both channels
|
||||
* SIM40 + 0x0701: 0x8A Serial Module - MCR Low Byte
|
||||
* - The serial control regosters are only accessable from supervisor mode
|
||||
* - IARB = 0x0A - serial module has priority level 10d
|
||||
* SIM40 + 0x0704: 0x01 Serial Module - ILR Interrupt Level
|
||||
* SIM40 + 0x0705: 0x44 Serial Module - IVR Interrupt Vector
|
||||
* SIM40 + 0x0714: 0x80 Serial Module - ACR Auxiliary Control
|
||||
* - Set 2 of the available baud rates is selected.
|
||||
* - CTS state change has no effect
|
||||
* --- setup Channel A
|
||||
* SIM40 + 0x0712: 0x20 Serial Module - CRA Command Register A
|
||||
* - Reset the receiver
|
||||
* SIM40 + 0x0712: 0x30 Serial Module - CRA Command Register A
|
||||
* - Reset the transmitter
|
||||
* SIM40 + 0x0710: 0x93 Serial Module - MR1A Mode Register 1A
|
||||
* - Upon receipt of a valid start bit, RTS≈ is negated if the channel's FIFO is full.
|
||||
* RTS≈ is reasserted when the FIFO has an empty position available.
|
||||
* - No Parity
|
||||
* - Eight bits
|
||||
* SIM40 + 0x0720: 0x07 Serial Module - MR2A Mode Register 2A
|
||||
* - No CTS or RTS controll
|
||||
* - 1 STOP bit
|
||||
* SIM40 + 0x0711: 0xCC Serial Module - CSRA Clock Select Register A
|
||||
* - 19200 baud TXc
|
||||
* - 19200 baud Rxc
|
||||
* SIM40 + 0x0712: 0x41 Serial Module - CRA Command Register A
|
||||
* - Reset Error status
|
||||
* - Enable Receiver
|
||||
* - Check for charcters in channel A
|
||||
* SIM40 + 0x0711: btst #0 Serial Module - SRA Status Register A
|
||||
* --- if there is
|
||||
* store all characters in buffer at (A6) 0x88FFD0
|
||||
* --- setup Channel B (See details as for channel A above)
|
||||
* SIM40 + 0x071A: 0x20 Serial Module - CRB Command Register B
|
||||
* SIM40 + 0x071A: 0x30 Serial Module - CRB Command Register B
|
||||
* SIM40 + 0x0718: 0x93 Serial Module - MR1B Mode Register 1B
|
||||
* SIM40 + 0x0721: 0x07 Serial Module - MR2B Mode Register 2B
|
||||
* SIM40 + 0x0719: 0xCC Serial Module - CSRB Clock Select Register B
|
||||
* SIM40 + 0x071A: 0x41 Serial Module - CRB Command Register B
|
||||
* - Check for characters in channel B
|
||||
* SIM40 + 0x0719: btst #0 Serial Module - SRB Status Register B
|
||||
* --- if there is
|
||||
* store all characters in buffer at (A6) 0x88FFD0
|
||||
* ---
|
||||
* - Check bit 0 set on Input Port
|
||||
* SIM40 + 0x071D: btst #0 Input Port - IP
|
||||
* --- if bit 0 is set
|
||||
* 0x00801208: 0x80
|
||||
* SIM40 + 0x071A: 0x81 Serial Module - CRB Command Register B
|
||||
* ---
|
||||
* SIM40 + 0x0720: 0x41 Serial Module - MR2A Mode register 2A
|
||||
* SIM40 + 0x071D: 0x03 OPCR Output Port Control Register
|
||||
* SIM40 + 0x0715: 0x03 IER Interrupt Enable Register
|
||||
*
|
||||
* Timer setup
|
||||
* ------------
|
||||
* SIM40 + 0x0640: 0x03 MCR Timer 2
|
||||
* tbc...
|
||||
*
|
||||
* Identified low level drivers in firmware
|
||||
* ----------------------------------------
|
||||
* 800420..80046C : Some PORT A serialisation routine for the
|
||||
* Siemens SDA5708 dot matrix display
|
||||
*
|
||||
* Interrupt sources
|
||||
* ----------------------------------------------------------
|
||||
* Description Device Lvl IRQ
|
||||
* /Board Vector
|
||||
* ----------------------------------------------------------
|
||||
* On board Sources
|
||||
*
|
||||
* Off board Sources (other boards)
|
||||
* ----------------------------------------------------------
|
||||
*
|
||||
* DMAC Channel Assignments
|
||||
* ----------------------------------------------------------
|
||||
* Channel Device
|
||||
* ----------------------------------------------------------
|
||||
* ----------------------------------------------------------
|
||||
*
|
||||
* TODO:
|
||||
* - Dump the ROMs
|
||||
* - Dump/Find bootable software
|
||||
* - Setup a working address map
|
||||
* - Fix debug terminal
|
||||
* - TBC
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "machine/68340.h"
|
||||
|
||||
class dbox_state : public driver_device
|
||||
{
|
||||
public:
|
||||
dbox_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_maincpu(*this, "maincpu"){ }
|
||||
required_device<m68340_cpu_device> m_maincpu;
|
||||
|
||||
virtual void machine_reset();
|
||||
DECLARE_DRIVER_INIT(dbox);
|
||||
};
|
||||
|
||||
void dbox_state::machine_reset()
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
static ADDRESS_MAP_START( dbox_map, AS_PROGRAM, 32, dbox_state )
|
||||
AM_RANGE(0x000000, 0x01ffff) AM_ROM AM_REGION("maincpu", 0)
|
||||
AM_RANGE(0x700000, 0x8fffff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
/* Input ports */
|
||||
static INPUT_PORTS_START( dbox )
|
||||
INPUT_PORTS_END
|
||||
|
||||
static MACHINE_CONFIG_START( dbox )
|
||||
MCFG_CPU_ADD("maincpu", M68340, XTAL_16MHz)
|
||||
MCFG_CPU_PROGRAM_MAP(dbox_map)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
DRIVER_INIT_MEMBER(dbox_state, dbox)
|
||||
{
|
||||
}
|
||||
|
||||
ROM_START( dbox )
|
||||
ROM_REGION(0x1000000, "maincpu", 0)
|
||||
// ROM_LOAD16_WORD( "dvb2000.bin", 0x000000, 0x8b742, CRC(5b21c455) SHA1(1e7654c37dfa65d1b8ac2469cdda82f91b47b3c7) )
|
||||
ROM_LOAD16_WORD( "nokboot.bin", 0x000000, 0x20000, CRC(0ff53e1f) SHA1(52002ee22c032775dac383d408c44abe9244724f) )
|
||||
ROM_END
|
||||
|
||||
COMP( 1996, dbox, 0, 0, dbox, dbox, dbox_state, dbox, "Nokia Multimedia", "D-box 1, Kirsch gruppe", MACHINE_IS_SKELETON )
|
||||
@ -10691,6 +10691,9 @@ dblcrown // (c) 1994 Excellent System
|
||||
@source:dblewing.cpp
|
||||
dblewing // MBE (c) 1993 Mitchell
|
||||
|
||||
@source:dbox.cpp
|
||||
dbox // (c) 1996 Nokia Multimedia
|
||||
|
||||
@source:dbz.cpp
|
||||
dbz // (c) 1993 Banpresto
|
||||
dbz2 // (c) 1994 Banpresto
|
||||
|
||||
Loading…
Reference in New Issue
Block a user